KR19990079604A - Symbol deinterleaving device - Google Patents

Abstract

The present invention relates to a device for deinterleaving data interleaved and received in a DVB-T system back to an original state. In particular, a symbol index signal transmitted from a transmitter is used to determine whether an OFDM symbol input is an even symbol or an odd symbol. An even / odd detector for outputting an address flag signal according to the present invention, a signal controller for outputting an R / W flag signal according to a state of an input symbol, an address flag signal for the even / odd detector, and an R / W flag signal of a signal controller An address generator for generating a read / write address for each symbol and a data of the first demapped symbol are written to the write address generated by the address generator, and then the next symbol is input. The data stored at the read address generated by the program is read first and output. It consists of a symbol memory that repeats the process of writing the data of the symbol input to the address where the data is read, for each symbol, and performs interleaving / deinterleaving without data loss while reducing the amount of memory when implementing symbol interleaver / deinterleaver. can do.

Description

Symbol deinterleaving device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital TV transmission in Europe, and more particularly, to a deinterleaving apparatus for deinterleaving data that is interleaved and received in a digital video broadcasting-terrestrial (DVB-T) system back to its original state. .

Digital TV transmission methods can be roughly divided into a single carrier modulation method using a single carrier and a multi-carrier transmission method for transmitting desired data using a plurality of multiple carriers. That is, it is classified into a VSB scheme using one single carrier and a Coded Orthogonal Frequency Division Multiplexing (COFDM) modulation scheme using multiple carriers.

The DVB-T system is a terrestrial digital TV transmission system in Europe and is currently being broadcast in several countries in Europe. The DVB-T system uses a COFDM method. The COFDM scheme is further divided into a 2K mode with 1705 carriers and an 8K mode with 6817 carriers according to the number of carriers in one symbol to be transmitted.

Unlike the conventional DVB-C (Cable) or DVB-S (Satellite), the COFDM method uses an Inverse Fast Fourier Transform (IFFT) at the transmitting end and an FFT at the receiving end. Demodulation is different, but the FEC part has a feature of sharing with other DVB-C or DVB-S. In addition to the shared part with other standards, the newly added part may be called an inner interleaver. In other words, when data is transmitted by performing internal interleaving at the transmitter side, frequency null generated in a specific portion of the transmission frequency band is divided into all the frequency bands, which is generated in a multipath channel environment. The performance degradation by this can be improved.

The internal interleaver for this purpose is composed of a bit interleaver and a symbol interleaver. The bit interleaver interleaves digital data to be transmitted in units of bits of a predetermined size, and the symbol interleaver refers to interleaving the interleaved data in units of bits again in units of symbols. Here, the symbol interleaver performs interleaving at the transmitting end and deinterleaving at the receiving end in units of constant COFDM symbols. In the symbol interleaver / deinterleaver, the main operation is to write data input to the memory by a predetermined address and to read the data again. And, the interleaved data is transmitted by mapping in a method called quadrature amplitude modulation (QAM), and a modulation scheme mainly used is quadrature phase shift keying (QPSK), 16-QAM, and 64-QAM.

Therefore, the operation of the deinterleaver on the receiving side can be referred to as the amount of memory required to deinterleave data. In the related art, the memory size of the OFDM symbol size × 2 to be deinterleaved was required. This is because, in order to change the order of data to a desired rule, first, the equalized OFDM signal must be stored in a memory of a certain size every symbol, and then data is output again in a different order generated by a predetermined rule.

In other words, when transmitted in 16-QAM, 16-QAM consists of 4 bits of one QAM symbol, and when the soft decision is performed again for non-tubbing decoding, the size of the memory increases by the number of soft decision numbers. . For example, in the case of 3 bit soft decision in 2K transmission mode, one OFDM symbol has 1512 active carriers, one QAM symbol consists of 4 bits, and each bit of the QAM symbol is 3 bit soft decision. * 4 * 3 size of memory is required.

This memory size is a major obstacle in ICing DVB-T receiving systems.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to write the data of one OFDM symbol to be interleaved and received in the memory, and then read and write the data. It is to provide a deinterleaving device to reduce.

1 is an overall block diagram of a DVB-T receiving system according to the present invention.

FIG. 2 is a detailed block diagram of the symbol deinterleaver of FIG. 1. FIG.

(A) to (k) is an input / output waveform diagram of each part of the symbol deinterleaver of FIG.

4 is a detailed block diagram of the address generator of FIG. 2.

5A to 5D are each input / output waveform diagram of the address generator of FIG. 4.

Explanation of symbols for main parts of the drawings

11 control unit 12 demapper

13 symbol deinterleaver 14 bit interleaver

21: Even / odd detector 22: Signal controller

23: address generator 24: symbol memory

A feature of the deinterleaving apparatus according to the present invention for achieving the above object is that if the first symbol is an even symbol, the data is written according to the q address, and if the odd symbol is input after the even symbol is finished, the Hq address is input. According to the stored data, the data of the odd symbols inputted to the address to which the data is read is written, and if the odd symbols are inputted after the writing of the odd symbols is completed, the stored data is read again according to the q address and the data is read. The process of writing data of even symbols in is repeated for each OFDM symbol.

Another feature of the symbol deinterleaving apparatus according to the present invention is that if the first symbol is an odd symbol, the data is written according to the Hq address, and if the even symbol is input after the writing of the odd symbol is finished, the stored data is read according to the q address. While writing the data of the even symbol inputted to the address where the data was read, and writing the even symbol after the writing of the even symbol is completed, the data of the odd symbol is read to the address where the data is read while reading the stored data according to the Hq address. The process of writing is repeated for each OFDM symbol.

The q address is an sequentially increasing address, and the Hq address is an address according to the deinterleaving rule of even symbols, and is generated alternately for each OFDM symbol.

According to the symbol deinterleaving apparatus, the present invention can perform symbol deinterleaving only with a memory size corresponding to a symbol size of COFDM, and may perform symbol interleaving on a transmitting side.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a DVB-T receiving system according to the present invention, a demapper 12 for demapping data output from an equalizer, and a symbol deinterleaver for symbol deinterleaving on demapped data ( 13), a bit deinterleaver 14 for deinterleaving the deinterleaved data in units of symbols again, and a TPS control unit 11 for controlling demapping and deinterleaving using received TPS information.

In the present invention configured as described above, the demapper 12 demaps data output from the equalizer. At this time, the demapping method is usually performed using a 3-bit or 4-bit soft decision. The COFDM standard is defined to accommodate various modes, and the information of these various modes is transmitted by TPS (Transmission Parameter Signaling), and the receiving end uses the TPS information to demapper 12, symbols, and bit deinterleaver. (13,14), Viterbi decoder and many other parts.

That is, the TPS control unit 11 receives TPS information from a digital signal processor (DSP) and provides the TPS information to various blocks, and among them, the tps_const information about the constellation is demapper 12 and the bit decode. The interleaver 14 is provided and information symbol_index for each OFDM symbol is provided to the symbol deinterleaver 13.

The data de-mapped into the necessary bits by using the output of the equalizer and channel state information (CSI) in the demapper 12 is input to the symbol deinterleaver 13 to be deinterleaved in symbols. The data input to the bit interleaver 14 which performs deinterleaving on a bit-by-bit basis, deinterleaving is performed, and finally input to the FEC stage and transmitted data is demodulated.

FIG. 2 is a detailed block diagram of the symbol deinterleaver 13. The pair determines whether an input symbol is an even symbol or an odd symbol according to symbol_index input from the TPS controller 11 and outputs an address flag signal address_flag accordingly. Of the odd / odd detector 21, the signal controller 22 which outputs the read / write flag signal R / W_flag according to the state of the inputted OFDM symbol, and the address_flag signal of the even / odd detector 21 and the signal controller 22. The address generator 23 generates a read / write address that meets the deinterleaving rule by using the R / W_flag signal, and the data output through the signal controller 22 to the address generated by the address generator 23. It consists of a symbol memory 24 that reads or writes to perform deinterleaving.

At this time, the 7-bit symbol_index as shown in FIG. 3 (g) input from the TPS control unit 11 to the even / odd detection unit 21 represents an index of OFDM symbols from 0 to 67, and the frame is 68 OFDM symbols. It consists of. That is, since the DVB-T system uses a COFDM transmission scheme, data is transmitted in one OFDM symbol on 1512 carriers in the 2K transmission mode. The data is divided into even and odd symbols according to the index value of the OFDM symbol. That is, since the interleaving / deinterleaving rule of the DVB-T system differs according to even and odd symbols, the even / odd detector 21 determines whether the input OFDM symbol is an even symbol or an odd symbol by looking at symbol_index and accordingly An address_flag signal is generated and output to the address generator 23. Here, the information about the symbol_index is included in the transmitted pilot signal.

Then, the output from the demapper 12, that is, the reset signal rst as shown in FIG. 3 (b) and the signal sym_flag indicating the enable of the symbol as shown in FIG. The signal (sym_sync) indicating the start of every symbol as shown in FIG. 3 and the signal (sym_dvald) indicating only the active carrier portion in each symbol as shown in FIG. 3 (e) and the soft decision as 3 bits as shown in FIG. The received signals from sd0 to sd5 are input to the signal controller 22. The signal controller 22 analyzes the various signals thus input and generates R / W_flag, which is a read / write flag signal representing reads and writes of the memory 24, and outputs the generated R / W_flag to the address generator 23.

The address generator 23 receiving the R / W_flag and the address_flag outputs the write address and read address, which are necessary for the OFDM symbol, to the symbol memory 24. The symbol memory 24 writes the data d0 to d5 output from the signal controller 22 to the write address output from the address generator 23 and to the read address output from the address generator 23. Read and output the stored data. Also, data bd0 to bd5 output as shown in FIG. 3 (k) is also required at this time since data of an active carrier, a non-active carrier, and a guard interval must also be appropriately output in one OFDM symbol. For example, a bit_flag signal as shown in (h) of FIG. 3, a bit_sync signal as shown in (i) of FIG. 3, and a bit_dvalid signal as shown in (j) of FIG. 3 are also output from the signal controller 22 to obtain final symbol deinterleaving. Is performed to sort the data.

At this time, after the sym_sync indicating the start of one symbol is input, the start of the output symbol is output after the input symbol is delayed by one symbol interval.

Fig. 4 is a diagram showing an address output process when reading and writing such input data into the symbol memory 24, respectively, which is known in the transmission standard. That is, according to the R / W_flag output from the signal control unit 22 of FIG. 2 and the address_flag of the even / odd detection unit 21, the control unit 41 determines which address of q address and Hq address, respectively, and outputs the corresponding address. Output Here, q addresses are addresses (0,1,2, ..., 1511) which are sequentially increased, and Hq addresses are addresses (0,1024,16, ..., 1023) generated by the deinterleaving rule of even symbols. )to be. In the case of the Hq address output, first, data is calculated from the shift register 44 and converted again by the bit replacement unit 45, and the address check unit 43 checks whether the address is larger than or smaller than 1511 (in the 2K mode). If the address is larger than 1511, the shift control signal is output from the controller 41 again, the shift register 44 is shifted, and the address is calculated again. In addition, the address_flag signal output from the even / odd detector 21 of FIG. 2 is input to the controller 41, and the most significant bit is added to the data output from the bit substituter 45 to perform calculation. At this time, if the q address is selected by R / W_flag, the address corresponding to each active carrier is sequentially increased by the counter 46 and output.

FIG. 5 is a waveform diagram showing a process of effectively writing and reading data into the symbol memory 24. As shown in FIG.

First, suppose that sym_sync, which is a signal indicating the start point of each OFDM symbol input from the demapper 12, is input as shown in FIG. 5 (a), between the first sym_sync signal and the next sym_sync signal. It is time, and this time is a period where the guard interval for retransmitting part of the period Tu of the actual symbol including the carrier and the Tu period again is combined. First, after the sym_sync signal input after the first power-on-reset or IC reset, as shown in (b) of FIG. 5, when the sym_dvald signal, which is a signal representing a valid active carrier, is high, the input of the OFDM symbol is started. Since the interval in which the sym_dvald signal is low is a signal indicating a non-active carrier interval, the write_vald signal becomes low as shown in FIG.

After only writing the data of the active carrier during the first inputted symbol period, the read_vald signal goes high again as shown in (d) of FIG. 5 in the next inputted OFDM symbol to read the data written to the memory 24 first. The data input again to the read address is written.

This writes only the data for one symbol first, and then writes back to the address that reads the data. Therefore, the memory required for the deinterleaver requires only one symbol of memory. At this time, if the address generated when the first input data is written to the memory is q, the address of the next symbol becomes Hq, and then q and Hq are repeated. Similarly, the write address of the first symbol becomes Hq, the address of the next symbol becomes q, and then Hq and q are repeated. At this time, the address of q indicates that the input symbol is an even symbol and Hq indicates an odd symbol.

That is, the symbol memory 24 writes data according to the q address generated by the address generator 23 when the first OFDM symbol is an even symbol. When the odd symbol is input after the writing of one symbol is completed, the symbol memory 24 writes to the Hq address. Therefore, the process of writing the data of the odd symbols inputted to the address to which the data is read while reading the stored data is repeated for one symbol period. When the writing of the odd symbols is completed and the even symbols are input again, the stored data is returned according to the q address. The process of reading and writing data of even symbols at an address to which data is read is repeated for each OFDM symbol.

Similarly, if the first symbol is an odd symbol, data is written according to the Hq address, and if an even symbol is input after all of the odd symbols have been written, an even number is inputted at the position where the data is read while reading the stored data according to the q address. The process of writing the data of the symbol is repeated for one symbol period. When the writing of the even symbol is completed and the odd symbol is input, the stored data is read again according to the Hq address and the odd symbol data is written to the address where the data is read. The process is repeated for each OFDM symbol.

When the deinterleaving is performed in this manner, the amount of memory required is only one symbol in size, and the output time is output by one symbol delay.

Meanwhile, the present invention can be equally applied not only to the deinterleaver but also to the interleaver on the transmitting side, thereby reducing the amount of memory when performing interleaving on the transmitting side.

As described above, according to the symbol deinterleaving apparatus according to the present invention, after writing only the data of the active carrier during the first inputted symbol period, the data written to the memory is first read and then read in the next input OFDM symbol. By repeating the process of writing data inputted back to the address, when the symbol interleaver / deinterleaver is implemented, interleaving / deinterleaving can be performed without data loss with the amount of memory corresponding to one OFDM symbol. In other words, since the amount of internal memory required to IC the present system is reduced, IC is facilitated.

Claims (6)

A deinterleaving apparatus for deinterleaving demapped data on a symbol basis, An even / odd detection unit for determining whether an OFDM symbol to be input is an even symbol or an odd symbol using a symbol index signal transmitted from a transmitting side, and outputting an address flag signal according thereto; A signal controller for outputting a read / write flag signal according to a state of an input symbol; An address generator for generating read / write addresses in accordance with the deinterleaving rule of each symbol by using the address flag signal of the even / odd detector and the read / write flag signal of the signal controller; When the data of the first demapped symbol is all written according to the write address generated by the address generator, and the next symbol is input, the stored data is first read and output according to the read address generated by the address generator. And a symbol memory for repeating a process of writing data of a symbol input to an address to which data is read. The method of claim 1, wherein the address generator And a first address and a second address are generated alternately for each symbol according to the address flag signal of the even / odd detector and the read / write flag signal of the signal controller. 3. The symbol deinterleaving apparatus according to claim 2, wherein the first address is an address sequentially increasing, and the second address is an address according to a deinterleaving rule of even symbols. The method of claim 1 or 3, wherein the address generator The symbol deinterleaving apparatus of claim 1, wherein the first input symbol is an even symbol, and a first address is generated as a write address and output to the symbol memory. If the odd symbol is an odd symbol, a second address is generated and output to the symbol memory. 4. The symbol memory of claim 1 or 3, wherein the symbol memory If the first input symbol is an even symbol, data is written according to the first address generated by the address generator. If odd symbols are input after all of the even symbols have been written, the second address is generated from the address generator. The process of reading the stored data first and writing the data of the odd symbols inputted to the address to which the data is read is repeated for one symbol period. When the writing of the odd symbols is completed and the even symbols are input again, the address generator generates the data again. And rewriting the stored data according to the first address first, and writing the data of the even symbol inputted to the address to which the data is read, for each symbol. 4. The symbol memory of claim 1 or 3, wherein the symbol memory If the first input symbol is an odd symbol, data is written according to the second address generated by the address generator. If even symbols are input after all of the odd symbols have been written, the first address is generated from the address generator. The process of reading the stored data first and writing the data of the even symbol inputted to the address to which the data is read is repeated for one symbol period, and when the writing of the even symbol is completed and the odd symbol is input again, the address generator is generated again. And rewriting the stored data according to the second address first and writing the data of the odd symbols inputted to the read address for each symbol.