KR19990075407A - Method of manufacturing thin film transistor substrate - Google Patents

Abstract

In the method for manufacturing a thin film transistor substrate according to the present invention, a three-layer film of a hydrogenated amorphous silicon layer, a doped hydrogenated amorphous silicon layer, and a metal film formed on the gate insulating layer is continuously dry-etched. At this time, the gas is a chlorine-based gas having an excellent etching selectivity between the gate insulating layer and the amorphous silicon layer. Cl ₂ + O ₂ is used, and isotropic in order to form a smooth profile of the three-layer film. SF ₆ + O ₂ gas may be additionally used for etching. In addition, a three-layer film of an ITO film, a metal film, and a doped amorphous silicon layer is continuously dry-etched to form a channel portion. In this case, the transparent conductive layer and the metal layer are etched in two steps by using HBr + Cl ₂ + O ₂ gas and the doped amorphous silicon layer by using SF ₆ + Cl ₂ gas, so as to uniformly form the channel part. The metal layer may be etched by using SF ₆ + O ₂ gas having an etching selectivity between the amorphous silicon layers, and may be etched in three steps. In addition, in order to secure the uniformity of the doped amorphous silicon layer to 95% or more with an etch selectivity between the metal film and the doped amorphous silicon layer of 10: 1 or more, the etch stop between the metal film and the doped amorphous silicon layer. An additional layer can be formed and divided into four steps to perform dry etching continuously. Here, the etch stop layer uses chromium silicide, and the gas further used for etching chromium silicide is Cl ₂ + O ₂ .

Description

Method of manufacturing thin film transistor substrate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor substrate, and more particularly, to a method for manufacturing a thin film transistor substrate, which is one of two substrates of a liquid crystal display device and in which a thin film transistor is formed as an active element.

In general, a liquid crystal display device is a display device in which a liquid crystal technology using optical properties of a liquid crystal in which an arrangement of liquid crystal molecules is changed by an electric field and a semiconductor technology forming a fine pattern are fused. Among the liquid crystal display devices, the thin film transistor liquid crystal display device using a thin film transistor as a switching element has various advantages such as low power consumption, low voltage driving force, thickness, and quantity.

In the thin film transistor liquid crystal display, a thin film transistor substrate in which a plurality of pixel units in which a thin film transistor and a pixel electrode are formed are formed in a matrix form, and a gate line and a data line are formed along a pixel row and a pixel column, respectively. And a color filter substrate on which a common electrode is formed, and a liquid crystal material enclosed therebetween.

On the other hand, since the thin film transistor is much thinner than a general transistor, its manufacturing process is more complicated than that of a general transistor, resulting in low productivity and high manufacturing cost. Therefore, various methods have been studied to increase the productivity of the thin film transistor and reduce the manufacturing cost, and in particular, a method for reducing the number of masks used in the manufacturing process has been widely studied.

In this case, a method of manufacturing a thin film transistor using a four-sheet mask requires etching a metal film at the same time when etching an amorphous silicon layer used as a semiconductor layer, and etching a doped amorphous silicon layer to form a channel portion of the semiconductor layer. At the same time, a step of forming a source / drain electrode by simultaneously etching a central portion of the metal film is required.

However, when the metal layer and the amorphous silicon layer are simultaneously etched in the process of forming the semiconductor layer and the channel portion of the semiconductor layer, when the two layers having different physical properties are etched at the same time, an under cut occurs so that the wet etching is performed. There is the hassle of having to perform dry etching in order.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a thin film transistor substrate which reduces a complicated process in applying a four-sheet mask process.

1 is a plan view showing the structure of a thin film transistor substrate according to a first embodiment of the present invention,

FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1,

3A to 3C are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to a first embodiment of the present invention.

4A through 4D are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to a second exemplary embodiment of the present invention.

In the method of manufacturing a thin film transistor substrate according to the present invention for solving this problem, when etching a three-layer film of a metal film, a doped amorphous silicon layer and an undoped amorphous silicon layer to form a semiconductor layer, continuous dry etching In addition, as a chlorine-based gas having an excellent etching selectivity with respect to the gate insulating film and the amorphous silicon layer, Cl ₂ + O ₂ gas is used.

In addition, when etching the three-layer film, it is possible to dry etching in succession by dividing into two steps to form a gentle oblique etching. First, as a fluorine-based gas, dry etching is performed using SF ₆ + O ₂ gas whose etching proceeds isotropically, followed by Cl ₂ + O ₂ having excellent etching selectivity with respect to the gate insulating film and the amorphous silicon layer. Dry etch using gas.

Here, the metal film is preferably formed of molybdenum, tungsten or an alloy thereof which can be dry etched with a fluorine-based gas.

Next, an indium tin oxide (ITO) film, which is a transparent conductive material, is stacked, and the source / drain electrodes are formed by etching the ITO film, the metal film, and the doped amorphous silicon layer, and the undoped amorphous silicon layer is exposed by exposing the undoped amorphous silicon layer. When the channel portion is formed in the silicon layer, dry etching is performed continuously.

Here, the ITO film and the metal film are etched using HBr + Cl ₂ + O ₂ gas, and the doped amorphous silicon layer is a gas mixed with a fluorine-based gas and a chlorine-based gas by using SF ₆ + Cl ₂ gas. Etch it.

In this case, since there is no etch selectivity between the undoped amorphous silicon layer and the doped amorphous silicon layer, the undoped amorphous silicon layer is partially etched when the doped amorphous silicon layer is etched. Therefore, in order to more uniformly etch the channel portion, it is required to uniformly etch the doped amorphous silicon layer while the metal film is uniformly etched. In order to solve this problem, SF having an etching selectivity between the metal film and the amorphous silicon layer is required. _The metal film may be separately etched using a fluorine-based gas such as ₆ + O ₂ gas.

Of course, dry etching is also performed continuously.

In addition, in order to secure the uniformity of the doped amorphous silicon layer to 95% or more by setting the etching selectivity between the metal film and the doped amorphous silicon layer to 10: 1 or more, an etch stop layer is formed between the metal film and the amorphous silicon layer. The channel part may be formed by continuously performing dry etching in four stages by adding a dry etching process for further forming and etching the same.

Here, the etch stop layer uses chromium silicide, and Cl ₂ + O ₂ is used as a gas for etching chromium silicide.

In this case, the dry etching is continuously performed.

An embodiment of a method of manufacturing a thin film transistor substrate according to the present invention will now be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present invention pertains can easily practice the present invention.

1 is a plan view illustrating a structure of a thin film transistor substrate according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1.

A gate pattern including a gate line 200, a branch of the gate electrode 210, and a gate pad 220 formed at an end of the gate line 200 is formed on the substrate 100. The gate pattern is formed of a single layer of molybdenum-tungsten alloy, and the gate pad 220 transmits a scan signal from the outside to the gate line 200.

A gate insulating layer 300 is formed on the gate patterns 200, 210, and 220, and the gate insulating layer 300 has a contact hole 720 exposing an upper portion of the gate pad 220. A hydrogenated amorphous silicon layer 400 is formed on the gate insulating layer 300. The amorphous silicon layer 400 is formed at a position corresponding to the gate electrode 210 to function as an active layer of the thin film transistor, and is formed to be elongated vertically.

Hydrogenated amorphous silicon layers 510 and 520 doped with a high concentration of n-type impurities are formed on the amorphous silicon layer 400. The data patterns 610 and 620 formed of a molybdenum-tungsten alloy film are formed thereon, and the doped amorphous silicon layers 510 and 520 and the data patterns 610 and 620 are formed in the same shape. These two layers are divided into two parts 510, 610; 520, and 620 with respect to the gate electrode 210, respectively, and are formed along the shape of the amorphous silicon layer 400.

Transparent conductive layers 830 and 840 made of a transparent conductive material such as ITO are formed on the data patterns 610 and 620, and some of them 830 are the data pattern 610 and the doped amorphous silicon layer 510. The other portion 840 covers the data pattern 620 and extends to the center portion of the pixel to become the pixel electrode.

Finally, a passivation layer 700 is formed on the ITO patterns 830 and 840 and the gate insulating layer 300 that is not covered by the ITO pattern, and the passivation layer 700 has a gate pad 220 and a transparent conductive layer 830. Contact holes 720 and 730 exposing the ends of the < RTI ID = 0.0 >) < / RTI >

Next, a method of manufacturing the thin film transistor substrate having the structure shown in FIGS. 1 and 2 will be described with reference to FIGS. 3A to 3C.

As shown in FIG. 3A, an aluminum or aluminum alloy layer is stacked on the transparent insulating substrate 100 and photo-etched using a first mask to include a gate line 200, a gate electrode 210, and a gate pad 220. A gate pattern is formed.

Here, a protective metal such as chromium (Cr), molybdenum (Mo), tungsten (W), titanium (Ti), tantalum (Ta), or an alloy thereof to protect the damage thereof on top of the aluminum or aluminum alloy film. It can also form further.

Next, a gate insulating layer 300 made of silicon nitride, a hydrogenated amorphous silicon layer 400, a hydrogenated amorphous silicon layer 500 and a metal film 600 doped with a high concentration of N-type impurities are sequentially stacked. As shown in FIG. 3B, the metal film 600, the doped amorphous silicon layer 500, and the amorphous silicon layer 400 are sequentially dry-etched and patterned using the second mask.

In this case, a gas for dry etching the three-layer film of the metal film 600, the doped amorphous silicon layer 500, and the undoped amorphous silicon layer 400 may be formed between the gate insulating layer 300 and the amorphous silicon layer 400. Cl ₂ + O ₂ is used as the chlorine-based gas having an excellent etching selectivity.

Here, when etching the three-layer film (400, 500, 600) using Cl ₂ + O ₂ gas, the most geographic portion can be formed steeply.

At this time, when the inclination of the edge of the three-layer film 400, 500, 600 is formed steeply, since the step coverage of another film formed later becomes worse, the most of the three-layer film 400, 500, 600 It is desirable to form the geographic portion with gentle oblique etching. Therefore, in order to form the edges of the three-layer films 400, 500, and 600 by gentle oblique etching, dry etching may be performed in two steps. First, as a fluorine-based gas, dry etching is performed using SF ₆ + O ₂ gas which isotropically etched, and is successively superior to the gate insulating layer 300 and the amorphous silicon layer 400. Dry etching is performed using Cl ₂ + O ₂ gas having an etching selectivity.

In this case, the metal film 600 may be formed of molybdenum, tungsten, titanium, tantalum, or an alloy thereof, which may be dry-etched with a fluorine-based gas.

Next, as shown in FIG. 3C, an ITO (indium tin oxide) film, which is a transparent conductive material, is stacked, and the ITO film, the metal film, and the doped amorphous silicon layer are continuously dry-etched using a third mask, thereby providing a transparent conductive layer 830. 840, data patterns 610 and 620, and doped amorphous silicon layers 510 and 520 are formed.

Here, the transparent conductive layers 830 and 840 and the data patterns 610 and 620 are patterned using HBr + Cl ₂ + O ₂ gas, and the doped amorphous silicon layers 510 and 520 are formed of fluorine-based gas and chlorine. Patterning is performed using SF ₆ + Cl ₂ gas as a gas mixed with a series of gases.

In this case, since there is no etching selectivity between the undoped amorphous silicon layer 400 and the doped amorphous silicon layers 510 and 520, the undoped amorphous silicon layer 400 may be etched using SF ₆ + Cl ₂ gas. The undoped amorphous silicon layer 400 is also partially etched. Therefore, when the transparent conductive layers 830 and 840 and the data patterns 610 and 620 are etched using HBr + Cl ₂ + O ₂ gas, the data patterns 610 and 620 must be uniformly etched to form a later doped amorphous layer. The silicon 510 and 520 may be uniformly etched, and the channel portion 40 of the undoped amorphous silicon layer 400 may be uniformly formed. However, since the SF ₆ + Cl ₂ gas has poor etching selectivity between the metal layers of the data patterns 610 and 620 and the amorphous silicon layers 510 and 520, the metal layer may be unevenly etched. Therefore, in order to etch the channel portion 40 more uniformly, it is preferable to etch the doped amorphous silicon layer while the metal films of the date patterns 610 and 620 are uniformly etched. Accordingly, the data patterns 610 and 620 are patterned by using a fluorine-based gas having an excellent etching selectivity between the data patterns 610 and 620 and the amorphous silicon layer, for example, an SF ₆ + O ₂ gas. That is, the channel portion 40 is formed in three steps.

First, only transparent conductive layers 830 and 840 are patterned using HBr + Cl ₂ + O ₂ gas, and then data patterns 610 and 620 are patterned using SF ₆ + O ₂ gas, and finally, The doped amorphous silicon layers 510 and 520 are patterned using SF ₆ + Cl ₂ gas. At this time, dry etching is performed continuously in an in-situ state.

In addition, the etch selectivity between the data patterns 610 and 620 and the doped amorphous silicon layers 510 and 520 is 10: 1 or more, so that the uniformity of the doped amorphous silicon layers 510 and 520 is 95% or more. In order to secure, an etch stop layer may be further formed between the date patterns 610 and 620 and the doped amorphous silicon layers 510 and 520, and dry etching may be continuously performed by dividing into four steps. Here, the etch stop layer uses chromium silicide, and Cl ₂ + O ₂ is used as a gas for etching chromium silicide. In detail, it will be described in the second embodiment according to the present invention.

Finally, as shown in FIG. 2, after the protective film 700 is stacked with silicon nitride, the gate pad 220 and the data pattern 610 are photo-etched with the gate insulating layer 300 using a fourth mask. Contact holes 720 and 730 exposing an upper portion of the transparent conductive film 830 corresponding to the ends of the upper and lower portions.

At this time, in order to smooth the edge inclination of the contact holes 720 and 730, the silicon nitride films 700 and 300 are formed using fluorine-based and chlorine-based gases, such as SF ₆ + HCl or SF ₆ + Cl ₂ gas. Etch in turn.

Next, a method of dividing the channel portion 40 into four stages will be described in detail with reference to FIGS. 4A to 4D.

As shown in FIG. 4A, in the same manner as in the first embodiment of the present invention, an aluminum or aluminum alloy film is laminated on a transparent insulating substrate 100 and photo-etched using a first mask to form a gate line 200 and a gate. A gate pattern including the electrode 210 and the gate pad 220 is formed.

Here, a protective metal such as chromium (Cr), molybdenum (Mo), tungsten (W), titanium (Ti), tantalum (Ta), or an alloy thereof is disposed on the aluminum or aluminum alloy film to prevent them from being damaged. It can also form further.

Next, as shown in FIG. 4B, a gate insulating layer 300 made of silicon nitride, a hydrogenated amorphous silicon layer 400, a hydrogenated amorphous silicon layer 500 heavily doped with N-type impurities, and chromium are formed. The chromium film is laminated. Subsequently, the chromium silicide 900 is formed on the chromium film and the doped amorphous silicon layer 500 by applying heat, and the chromium film is removed.

Subsequently, a metal film 600 made of molybdenum, tungsten, titanium, tantalum, or an alloy thereof is laminated, and the metal film 600, chromium silicide 900, and doping are doped as shown in FIG. 4C using a second mask. The amorphous silicon layer 500 and the undoped amorphous silicon layer 400 are subsequently dry-etched and patterned,

At this time, the four-layer film of the metal film 600, the chromium silicide 900, the doped amorphous silicon layer 500 and the undoped amorphous silicon layer 400 is separated into two steps to perform dry etching continuously.

First, as a fluorine-based gas, dry etching is performed using SF ₆ + O ₂ gas which isotropically etched to give a four-layered film 600, 900, 500, and 400 with a tapered shape having a gentle inclination angle. To form. In this case, a portion of the doped amorphous silicon layer 500 or the undoped amorphous silicon layer 400 is left. Subsequently, the gate insulating layer 300 is exposed using Cl ₂ + O ₂ gas having an excellent etching selectivity between the gate insulating layer 300 and the amorphous silicon layers 500 and 400.

Of course, as in the first embodiment, it is also possible to continuously etch at once using Cl ₂ + O ₂ gas.

Next, as shown in FIG. 4D, an indium tin oxide (ITO) film, which is a transparent conductive material, is stacked, and the ITO film, the metal film, the chromium silicide, and the doped amorphous silicon layer are separated in four steps using a third mask. Dry etching forms the transparent conductive layers 830 and 840, the data patterns 610 and 620, the chrome silicides 910 and 920, and the doped amorphous silicon layers 510 and 520.

First, the transparent conductive layers 830 and 840 are formed by etching the ITO film using a third mask and using HBr + Cl ₂ + O ₂ gas. Next, the data patterns 610 and 620 are formed by etching the metal film using the transparent conductive layers 830 and 840 as a mask and using SF ₆ + O ₂ gas.

In this case, since the chromium silicide 910 is not etched by the fluorine-based gas, the etch process may be excessively formed to uniformly form the data patterns 610 and 620. Therefore, the chromium silicide 910 serves as an etch stop layer to prevent the doped amorphous silicon layer 500 from being etched when etching the data patterns 610 and 620.

Next, Cl ₂ + O ₂ gas, using a removing chromium silicide 910 that is exposed, and a mixed gas of the fluorine series, and chlorine series such as SF ₆ + Cl ₂ gas, for example SF ₆ + Cl ₂ gas The doped amorphous silicon layers 510 and 520 are patterned by using a method.

At this time, the dry etching to form the channel portion 40 in the undoped amorphous silicon layer 400 by separating in four steps is carried out continuously in an in-situ state.

The subsequent process is the same as in the first embodiment.

Therefore, in the method of manufacturing the thin film transistor substrate according to the present invention, a complicated process can be reduced by simultaneously etching the metal film and the amorphous silicon layer simultaneously using a dry etching method. In addition, the profile of the metal layer and the amorphous silicon layer may be gently formed by using an SF ₆ + O ₂ gas that is etched isotropically. In addition, by using a gas having an etch selectivity between the metal film and the amorphous silicon layer, or forming an etch stop layer therebetween, it is possible to form a uniform channel portion to improve the device characteristics.

(If there is a difference between the expression "continuously" and "in-situ" in the description, please point out.)

Claims (40)

Stacking an aluminum film or an aluminum alloy film on a substrate, and patterning the aluminum or aluminum alloy using a first mask to form a gate line, a gate pad, and a gate electrode; Sequentially depositing a gate insulating film, an amorphous silicon layer, an amorphous silicon layer doped with a high concentration impurity, and a metal film on the substrate; Continuously etching a portion of the metal layer, the doped amorphous silicon layer, and the amorphous silicon layer using a second mask, A transparent conductive film was deposited on the substrate, and the transparent conductive film, the metal film, and the doped amorphous silicon layer were continuously formed by using a mixture gas of HBr + Cl ₂ + O ₂ and a chlorine series and a fluorine series using a third mask. Etching into, And forming a passivation layer on the substrate, and etching the gate insulating layer and the passivation layer on the gate pad using a fourth mask. In claim 1, The gas in which the chlorine-based and fluorine-based gas is mixed is SF ₆ + Cl ₂ . In claim 2, The HBr + Cl ₂ + O ₂ gas continuously etches the transparent conductive layer and the metal layer, and the SF ₆ + Cl ₂ gas etches the doped amorphous silicon layer. In claim 3, The metal film is formed of molybdenum, titanium, tantalum, tungsten or an alloy thereof. In claim 4, Dry etching the portions of the second metal film, the doped amorphous silicon layer and the amorphous silicon layer in a continuous method using a chlorine-based gas. In claim 5, The chlorine-based gas is Cl ₂ + O ₂ Method for manufacturing a thin film transistor substrate. In claim 6, And dry etching with a fluorine-based gas prior to dry etching with the chlorine-based gas. In claim 7, The method of manufacturing a thin film transistor substrate using the fluorine-based gas is SF ₆ + O ₂ . In claim 8, The etching of the gate insulating film and the protective film is a method of manufacturing a thin film transistor substrate using HCl + Cl ₂ or SF ₆ + Cl ₂ gas as a mixture of the chlorine series and fluorine series. In claim 9, Fabrication of a thin film transistor substrate further comprising a protective metal film such as chromium (Cr), molybdenum (Mo), tungsten (W), titanium (Ti), tantalum (Ta), or an alloy thereof on top of the aluminum film or aluminum alloy film Way. Stacking an aluminum film or an aluminum alloy film on a substrate and patterning the aluminum film or aluminum alloy film using a first mask to form a gate line, a gate pad, and a gate electrode; Sequentially depositing a gate insulating film, an amorphous silicon layer, an amorphous silicon layer doped with a high concentration impurity, and a metal film on the substrate; Continuously etching a portion of the metal layer, the doped amorphous silicon layer, and the amorphous silicon layer using a second mask, A transparent conductive film was deposited on the substrate, and the transparent conductive film, the metal film, and the doped amorphous silicon layer were subjected to HBr + Cl ₂ + O ₂ , a fluorine series, a fluorine series, and a chlorine series mixed gas using a third mask. Etching continuously, And etching the gate insulating film and the protective film on the gate pad by using a fourth mask after forming the protective film on the substrate. 4. In claim 11, The gas in which the chlorine-based and fluorine-based gas is mixed is SF ₆ + Cl ₂ . In claim 11, The fluorine-based gas is SF ₆ + O _{2 A} method of manufacturing a thin film transistor substrate. In claim 13, The HBr + Cl ₂ + O ₂ gas etches the transparent conductive film, the fluorine-based gas etches the metal film, and the mixed fluorine-based and chlorine-based gas etches the doped amorphous silicon layer. Method of manufacturing a substrate. In claim 13, The metal film is formed of molybdenum, titanium, tantalum, tungsten or an alloy thereof. The method of claim 14, The continuous dry etching of the metal layer, the doped amorphous silicon layer and the amorphous silicon layer may be performed by using a chlorine-based gas. The method of claim 16, The chlorine-based gas is Cl ₂ + O ₂ Method for manufacturing a thin film transistor substrate. The method of claim 17, And dry etching with a fluorine-based gas prior to dry etching with the chlorine-based gas. The method of claim 17, The etching of the gate insulating film and the protective film is a method of manufacturing a thin film transistor substrate using HCl + Cl ₂ or SF ₆ + Cl ₂ gas as a mixture of chlorine series and fluorine series. The method of claim 19, Fabrication of a thin film transistor substrate further comprising a protective metal film such as chromium (Cr), molybdenum (Mo), tungsten (W), titanium (Ti), tantalum (Ta), or an alloy thereof on top of the aluminum film or aluminum alloy film Way. Stacking an aluminum film or an aluminum film on a substrate and patterning the aluminum film or an aluminum alloy film using a first mask to form a gate line, a gate pad, and a gate electrode; Sequentially depositing a gate insulating film, an amorphous silicon layer, and an amorphous silicon layer doped with a high concentration impurity on the substrate; Forming an etch stop layer on top of the doped amorphous silicon layer, Stacking a metal layer on top of the etch stop layer using a second mask, and sequentially dry etching a portion of the metal film, the etch stop layer, the doped amorphous silicon layer, and the amorphous silicon layer, A transparent conductive film was deposited on the substrate, and the transparent conductive film, the metal film, the etch stop layer, and the doped amorphous silicon layer were formed using HBr + Cl ₂ + O ₂ , fluorine series, chlorine series, and fluorine series using a third mask. Continuously etching using a chlorine-based mixed gas, And forming a passivation layer on the substrate, and etching the gate insulating layer and the passivation layer on the gate pad using a fourth mask. The method of claim 21, The etch stop layer is a silicide manufacturing method of a thin film transistor substrate. The method of claim 22, wherein forming the etch stop layer, Laminating a metal film, Applying heat to form the silicide between the metal film and the doped amorphous silicon layer, And removing the metal film. The method of claim 23, The metal film is a method of manufacturing a thin film transistor substrate made of chromium. The method of claim 24, The gas in which the chlorine-based and fluorine-based gas is mixed is SF ₆ + Cl ₂ . The method of claim 25, The fluorine-based gas is SF ₆ + O _{2 A} method of manufacturing a thin film transistor substrate. The method of claim 26, The chlorine-based gas is Cl ₂ + O ₂ Method for manufacturing a thin film transistor substrate. The method of claim 27, The HBr + Cl ₂ + O ₂ gas etches the transparent conductive film, the SF ₆ + O ₂ gas etches the metal film, the Cl ₂ + O ₂ gas etches the etch stop layer, and the SF ₆ + Cl ₂ gas is a method of manufacturing a thin film transistor substrate for etching the doped amorphous silicon layer. The method of claim 28, And the metal film is formed of molybdenum, molybdenum alloy, titanium, tantalum, tungsten or an alloy thereof. The method of claim 29, The continuous dry etching of the metal layer, the etch stop layer, the doped amorphous silicon layer and the amorphous silicon layer may be performed using the chlorine-based gas. The method of claim 30, And dry etching with a fluorine-based gas prior to dry etching with the chlorine-based gas. The method of claim 31, The etching of the gate insulating film and the protective film is a method of manufacturing a thin film transistor substrate using HCl + Cl ₂ or SF ₆ + Cl ₂ gas as a mixture of the fluorine series and chlorine series. 33. The method of claim 32, Fabrication of a thin film transistor substrate further comprising a protective metal film such as chromium (Cr), molybdenum (Mo), tungsten (W), titanium (Ti), tantalum (Ta), or an alloy thereof on top of the aluminum film or aluminum alloy film Way. A gate pattern formed on the transparent insulating substrate and including a gate line, a gate electrode, and a gate pad made of a first metal film, A gate insulating film covering the gate pattern, An amorphous silicon layer formed over the gate insulating film, A doped amorphous silicon layer formed on the amorphous silicon layer, An etch stop layer formed on the doped amorphous silicon layer, A data pattern formed on the etch stop layer and including a data line, a source / drain electrode, and a data pad formed of a second metal layer; A thin film transistor substrate for a display device comprising a pixel electrode connected to the drain electrode. The method of claim 34, The first metal film is a thin film transistor substrate for a display device made of aluminum or an aluminum alloy. 36. The method of claim 35 wherein The first metal film is a thin film transistor substrate for a display device made of aluminum or an aluminum alloy. The method of claim 36, A thin film transistor substrate further comprising a protective metal film such as chromium (Cr), molybdenum (Mo), tungsten (W), titanium (Ti), tantalum (Ta), or an alloy thereof on the aluminum film or the aluminum alloy film. The method of claim 37, The second metal film is made of molybdenum, molybdenum alloy, titanium, tantalum, tungsten or an alloy thereof. The method of claim 38 wherein The etch stop layer is a thin film transistor substrate made of silicide. The method of claim 39, The silicide is a thin film transistor substrate made of chromium silicide.