KR19990061454A - Communication device between processor and devices - Google Patents

Abstract

The present invention relates to a communication device between a processor and devices suitable for connecting between a control system processor and corresponding devices controlled by the control system processor using a processor that provides time division multiplexed (TDM) matching in the TDX-100 electronic switchgear. In general, when a high-performance subprocessor controls a plurality of subordinate devices, the subprocessor processes the device for processing a plurality of messages processed by the device and transmits the device to the upper processor to process the message. Although a bottleneck between the lower processor processors has occurred, in the present invention, by providing a communication device between the processor and the devices in the electronic exchange, the present invention provides a time division multiple serial communication between one high performance processor and a plurality of low performance devices. By using the channel efficiently and changing the value of the internal register of the HIT communication processor (130, 136, 138, 140), it is possible to change the communication bandwidth with the device even during communication, according to the characteristics of each device. By changing the fluid communication bandwidth, the above-mentioned drawbacks can be ameliorated.

Description

Communication device between processor and devices

The present invention relates to a method of communication between a processor and devices, and more particularly, using a processor that provides time division multiplexing (TDM) matching in a TDX-100 electronic switch. It relates to a communication method for connecting.

As is well known in the art, a lower processor (Telephony Processor) and a corresponding device controlled by the lower processor described above are connected via a link to communicate data with another subscriber matching subsystem (ASS). This is possible.

In addition, when a high-performance subprocessor controls a plurality of subordinate devices, the bottleneck is caused by the subprocessor processing the device for processing a plurality of messages processed by the device and transmitting the device to the upper processor to process the message. ) Occurred.

The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object thereof is to provide a communication device between a processor and devices in an electronic exchange.

Another object of the present invention is to provide a multi-serial communication matching device between one high performance processor and a plurality of low performance devices.

The present invention can change the communication bandwidth with the dynamic device even during communication by changing the value of the internal register of the MC68MH360, and the communication device between the processor and the device that changes the fluid communication bandwidth according to the characteristics of each device There is another purpose to provide.

In order to achieve the above object, the present invention provides a plurality of first, second, ..., n-th devices, and a plurality of first, second, ... A subprocessor connected to the nth device to control the plurality of devices, an upper processor connected to the plurality of subprocessors, and controlling a plurality of preset subprocessors, and a main processor to control the subprocessor within the subprocessor. A processor, a communication processor for controlling communication with the upper processor and the device, a first ROM having mounting information and other system information for loading a program in the lower processor, and the lower processor being loaded normally; A first RAM capable of writing and reading data required by a processor and a main processor; It is responsible for the transfer of data between the upper and lower processors, the main processor, the communication processor, the first ROM, the first RAM, the DPRAM, and the DPRAM. Communication between the master communication processor and the first, second, and third slave communication processors and the corresponding device, each HIT communication processor generating a memory and a buffer so as to receive communication information and read and write data to and from the DPRAM. And a second RAM for temporarily storing the transmitted message, and a second ROM for communicating between the DPRAM and the master HIT communication processor and between each HIT communication processor and the respective device. It provides a communication device between the two.

1 is a schematic block diagram of an electronic switchboard for explaining a communication apparatus between a processor and devices according to the present invention;

2 is a block diagram of a master processor in a lower processor board in the electronic switchboard configured according to FIG. 1;

3 is a block diagram suitable for communicating by means of a logical channel formed by a processor in accordance with FIG.

<Description of the code | symbol about the principal part of drawing>

10: upper processor 12: lower processor

13: HIT bus communication unit

14-1 to 20-16: 1st, 2nd agent, ..., nth device

120: main processor 121: bus

122: communication processor 124: first ROM

126: first RAM 128: DPRAM

130: master HIT communication bus 132: second ROM

134: second RAM

136, 138, 140: first, second, third slave HIT communication processor

202: serial matching

204-210: 1st, ..., 4th SCC 212: CPU

300, 340, ..., 380: first, second, ..., n-channel

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the invention described below with reference to the accompanying drawings.

Referring to the configuration of the present invention with reference to Figure 1, a plurality of first, second, ..., n-th device (14-1 to 20-16) for transmitting a message and a control signal and the like, A lower processor 12 connected to a plurality of first, second, ..., n-th devices 14-1 to 20-16 to control the plurality of devices 14-1 to 20-16; Connected to the plurality of sub-processors 12, the upper processor 10 for controlling a plurality of predetermined sub-processor 12, and the main processor (in charge of the control of the lower processor 12 in the lower processor 12) 120, the host processor 10, the main processor 120, the communication processor 122, the first ROM 124, the first RAM 126, DPRAM 128, such as address, data, system data In the bus 121 responsible for transmission, the communication processor 122 controlling to communicate with the upper processor 10 and the devices 14-1 to 20-16 described above, and the lower processor 12. The first ROM 124 having the mounting information and other system information so that the program is loaded and the lower processor 12 is normally loaded, and the data required by the above-described communication processor 122 and the main processor 120 Read and write data between the upper processor 10 and the predetermined HIT communication processors 130, 136, 138, and 140 through the first RAM 126 capable of writing and reading, and the above-described communication processor 122. Communication with the DPRAM 128 through a master HIT communication processor 130 capable of reading and writing data to and from the DPRAM 128, and receiving the DPRAM 128. First, second, and third slave communication processors 136, 138, and 140 for communicating with the corresponding devices 14-1 to 20-16, and the master communication processor 130 and the first. And second and third slave communication processors 136, 138 and 140 and corresponding devices 14-1 to 20-16. Communication between the second RAM 134 and the DPRAM 128 and the master HIT communication processor 130 and each of the HIT communication processors 130, 136, 138, and 140, respectively. And a second ROM 132 to communicate between each of the devices 14-1 to 20-16.

Referring to Figure 1 in detail with respect to the schematic block diagram of the electronic switchboard for explaining the communication device between the processor and the devices (14-1 to 20-16) according to the present invention, the upper processor 10 is maintained And a plurality of sub-processors 12 connected to a plurality of preset sub-processors 12 to re-collect the data collected in the sub-processors 12 to determine the state of the exchange. 12).

The lower processor 12 controls the plurality of devices 14-1 to 20-16, collects data collected by each of the devices 14-1 to 20-16, and collects the collected data as a higher processor. Transfer to (10).

The lower processor 12 is connected to a plurality of first, second, ..., n-th devices 14-1 to 20-16 to display the above-described messages and control signals. The second, ..., n-th devices 14-1 to 20-16 control the input and output of the data.

The main processor 120 is a processor responsible for the overall control of the lower processor 12 in the lower processor 12. For example, in the TDX-100 switch, the main processor 120 uses the MC68060, which is a high-performance processor of 32 bits. Implemented

Each communication processor (130, 1376, 138, 140) consisting of four MC68MH360 in the lower processor 12 takes one form independent from the MC68060, which is the main processor 120, and takes the DPRAM 128. In addition, it is referred to as the HIT bus communication unit 13 in the lower processor 12.

The HIT bus communication unit 13 in the lower processor 12 has a structure of a master slave for HIT bus communication, and is connected to each device 14-1 to 20-16 in an E1 / CEPT (Committee for Europe Postal Telecommunication) method. To support four MC68MH360 processors, which support the time division multiplexed (TDM) 201 matching, which provides the ability to distribute one physical channel to 32 logical channels. 134) are connected to each other by a HIT bus.

The HIT bus communication unit 13 communicates with the operating system mounted on the main processor 120 of the MC68060 with the DPRAM 128 interposed therebetween, and is dedicated to transmitting and receiving HIT bus messages from the lower processor 12, and using one independent firmware ( firmware) is loaded into the second ROM 132 to control the DPRAM 128 and the second RAM 134 according to the size of the cell of the input message, and each of the master communication processor 130 composed of MC68MH360 and Communication between the slave communication processors 136, 138, and 140 and the respective devices 14-1 to 20-16.

In addition, the HIT bus communication unit 13 includes a master HIT communication processor 130 and each slave HIT communication processor 136, 138, and 140 configured with the MC68MH360 and a high-level data link control (HDLC) interface time-slot. Control communication between the communication processor 122 and the main processor 120 through the DPRAM 128 and the bus 121.

One subprocessor has a total of 2.048x4 = 8.192Mbps (64Kbpsx128 time slots) for HIT bus communication. A total of 64 channels can be accommodated using 2 time slots (128Kbps) as the basic 1 channel.

One channel is a concept in which physical channels are divided to communicate with the devices 14-1 to 20-16. Two time slots are grouped into one channel, and one MC68MH360 supports up to 32 time slots. In order to communicate with one device 14-1 to 20-16, a program in MC68MH360 may be set to set a communication bandwidth of 128 Kbps to 2.048 Mbps according to the characteristics of the devices 14-1 to 20-16. Can be.

That is, each HIT communication bus 130, 136, 138, 140 has 16 channels, and one subprocessor 12 having four HIT communication buses 130, 136, 138, 140 has 128 Kbps. It can have a variable communication bandwidth of 2.048Mbps.

In addition, one of each MC68MH360 is set to the master HIT communication processor 130, the other three MC68MH360 is set to the slave HIT communication bus (136, 138, 140) and the processor of the MC68MH360 set as the master 2 RAM (134) ) As well as the second ROM 132 and the DPRAM 128 are connected.

DPRAM 128 is connected to the data, system data, address bus 121 and stores the message input from the HIT bus communication unit 13, and at the same time the main processor 120 or communication processor 122 via the bus 121 Reads the message, and transmits the message to the upper processor 10 through the communication processor 122.

When the message is transmitted from the upper processor 10 or the main processor 120 through the communication processor 122, the DPRAM 128 stores the message and reads it from the master HIT communication processor 130.

The second ROM 132 is between the DPRAM 128 and the master HIT communication processor 130 and the master HIT communication processor 130, each of the first, second, and third slave HIT communication processors 136, 138, 140. And a firmware for communicating between the respective devices 14-1 to 20-16, and the master communication processor 130 and the first, second, and third slave communication processors 136, 138, and 140 In order to communicate with each other, hardware and mounting information of the hardware such as the DPRAM 128 and the second RAM 134 may be included for the most appropriate communication.

In addition, the master communication processor 130 and each slave communication processor 136, 138, 140 may communicate independently, and each HIT communication process 130, 136, 138, 140 of the E1 / CEPT method. The communication bandwidth of one physical channel has 2.048 Mbps.

The lowest communication bandwidth between each of the HIT communication processors 130, 136, 138, and 140 and each of the devices 14-1 to 20-16 is 64, that is, a value obtained by dividing 2.048 Mbps into 32 time slots. 64 Kbps is one time slot.

Since only one time slot can transmit or receive, two channels consist of 64Kbps and 128Kbps.

In the lower processor 12, one MC68MH360 supports 32 time slots, and these four HIT communication processors 130, 136, 138, and 140 operate as master slaves and support a total of 128 time slots.

Referring to FIG. 2, a block diagram of a master processor 120 in a lower processor 12 board in an electronic switch configured according to FIG. 1 is provided. Each HIT communication processor 130, 136, in the lower processor 12 board, 138, 140, MC68MH360 has four SCC (Serial Communication Control) (204, 206, 208, 210), one of the SCC and the SCC through the TDM (201) through the serial matching unit 202 Communication is possible by dividing the serial channel into 32 time slots.

It is the software's job to distribute these 16 logical channels into physical serial transmission lines.

In this case, each logical channel should have a buffer descriptor that reads the message length, transmission / reception and message information from the header of the message, and selects the number of buffer descriptors. It is determined by the communication protocol and the available memory size and can have 128 buffer descriptors per logical channel.

The four MC68MH360s must have a total of 64 logical channels, which requires considerable memory resources. Therefore, it is necessary to obtain and optimize the maximum number of bus descriptors required by the communication protocol.

In the case of HIT bus communication, the sliding window protocol is used. Each sliding window protocol is a management system for transmitting / receiving synchronization information, and all information is synchronized even when errors such as data and data address occur after matching sliding window information of each other. Synchronize so that the address does not change.

At this time, Modulo_8 is used in the sliding window. Modulo_8 means that 8 messages can be sent unconditionally without the other party's authentication.

Therefore, since the CPU 212 is connected to the second ROM 132 and the second RAM 134 to process data input in a total of 16 channels with the second RAM 134, the maximum required by the communication protocol is required. In order to obtain and optimize the number of buffer descriptors, we set the number of buffer descriptors to 10 per channel.

10 buffer descriptors generated for each channel are generated to generate buffers 312 to 318, 332 to 338, 352 to 358, 372 to 378, ..., 392 to 398, and 412 to 418 per corresponding buffer descriptor. The data transmitted and received by the respective devices 14-1 through 20-16 and the HIT communication processors 130, 136, 138, and 140 are buffered.

The CPU 212 receives a communication program from the second ROM 132.

Referring to FIG. 3, a block diagram suitable for communicating by a logical channel formed by a processor according to FIG. 1 will be described. Each 16 logical channels set by one processor are generated in the second RAM 134. Show the configuration of memory and buffer.

At this time, the buffer descriptors 302 to 308, 342 to 348, 382 to 388 on the receiving side and the buffer descriptors 322 to 328, 362 to 368, 402 to 408 on the sending side are reduced. If you run the last Buffer Descriptor 9 with a structure, it initializes itself so that Buffer Depth 0 can be executed next.

Each of the 160 buffer descriptors (302 to 308, 342 to 348, ..., 382 to 388) and the buffer descriptors (322 to 328, 362 to 368, etc.) on the receiving side, respectively, are made. 402 through 408 each contain 320 message buffers (312-318, 332-338, 352-358, 372-378, ..., 392-398, 412-418) of maximum message size. 2 will be made in RAM (134).

The HIT bus communication unit 13 initialized as described above receives a message from the DPRAM 128 through the bus 121 at the master HIT communication processor 130 and corresponding master communication processor 130 or each slave communication processor 136. 138, 140 checks the device ID in the contents of the message, transfers the message to the buffer set by the buffer descriptor of the sender through the logical channel, and then sends the message to the corresponding device 14-1 to 20-16. .

When the reception operation receives a message transmission request through the logical channel to the corresponding HIT communication processor 130, 136, 138, and 140, a reception interrupt is generated by the master HIT communication processor 130, MC68MH360, and the reception interrupt service routing is performed. Moves the message of the corresponding reception buffer to the DPRAM 128 and informs the corresponding HIT communication processors 130, 136, 138, and 140 of the received message through the bus 121.

The previous examples all assume that the logical channels have a bandwidth of two time slots and assume that the devices 14-1 through 20-16 connected to a particular logical channel have a large amount of message transmission and reception so that a communication bandwidth of 1 Mbps is required. If the channel is 0, logical channels 1 to 7 are destroyed. In other words, channels 1 to 7 cannot be used because the bandwidth allocated for channels 1 to 7 has been eroded by channel 0.

That is, if the communication bandwidth of channel 0-7 is 1Mbps and the communication bandwidth of the remaining channel 8-15 is 64Kbps, there are 16 channels, but 90 buffer descriptors of the receiving side and buffer descriptors of the transmitting side are formed.

In actual HIT bus communication, devices 14-1 to 20-16 using two time slots, four time slots, sixteen time slots, and the like communicate with one lower processor 12.

And, these logical channel assignments should be made in consideration of the characteristics of each device (14-1 to 20-16).

For example, a device 14-1 to 20-16 using a communication bandwidth of 2 Mbps must have 0, 16, 32, and 48 logical channels.

This communication bandwidth can be changed dynamically during communication by changing the value of the internal register of the MC68MH360, and can be flexible depending on the characteristics of the devices 14-1 to 20-16, thereby providing excellent variability.

The principles of the invention have been described above in connection with specific devices, which are described by way of example only, and are not limited to the spirit of the invention as described in the appended claims.

As described above, the present invention provides a communication apparatus between the processor and the devices 14-1 to 20-16 in an electronic exchange, so that the present invention provides one high performance processor and a plurality of low performance devices 14-1 to 20. By using time-division multiple serial communication between the -16 devices, the channel is efficiently used, and by changing the value of the internal register of the HIT communication processor 130, 136, 138, 140, the device 14-1 to 20-16), it is possible to change the communication bandwidth, it is effective to change the fluid communication bandwidth according to the characteristics of each device.

Claims (2)

A plurality of first, second, ..., n-th devices 14-1 to 20-16 for transmitting messages and control signals, etc .; A lower processor 12 connected to the plurality of first, second, ..., n-th devices 14-1 to 20-16 to control the plurality of devices; An upper processor 10 connected to the plurality of lower processors 12 and controlling the plurality of preset lower processors 12; A main processor 120 in charge of controlling the lower processor 12 in the lower processor 12; A communication processor (122) which controls to communicate with the upper processor (10) and the device; A first ROM 124 having mounting information and other system information for loading a program in the lower processor 12 so that the lower processor 12 is normally loaded; A first RAM 126 capable of writing and reading data required by the communication processor 122 and the main processor 120; A DPRAM 128 capable of reading and writing data between an upper processor 10 and a predetermined HIT communication processor 130, 136, 138, 140 through the communication processor 122; Upper processor 10, main processor 120, communication processor 122, first ROM 124, first RAM 126, dual dual RAM (hereinafter referred to as DPRAM) (128) A bus 121 that is responsible for transferring addresses, data, system connectors, etc .; A master HIT communication processor 130 capable of receiving communication information and reading and writing data to the DPRAM 128; First, second, and third slaves that communicate with DPRAM 128 through the master HIT communication processor 130 and configure a memory and a buffer to communicate with respective corresponding devices 14-1 through 20-16. (slave) communication processors 136, 138, 140; Temporarily storing a message transmitted when communicating between the master communication processor 130 and the first, second, and third slave communication processors 136, 138, and 140 and the corresponding devices 14-1 to 20-16. A second RAM 134 to allow; Between the DPRAM 128 and the master HIT communication processor 130 and the master HIT communication processor 130, each of the first, second and third slave HIT communication processors 136, 138, 140 and their respective devices ( And a second ROM (132) for communicating between 14-1 through 20-16. The method of claim 1, The memory and buffer are: Buffer Descriptors (302 to 308, 342 to 348, ..., 382 to 388) and Transmit Buffer Descriptors (322 to 328, 362 to 368, ..., 402 to 408) on the receiving side Means for initializing each of the first buffer descriptors to be performed next when performing the last respective buffer descriptors to have a reducing structure; The initialized HIT bus communication unit 13 receives the device ID from the contents of the message in each of the slave communication processors 136, 138, and 140 received from the master HIT communication processor 130 through the DPRAM 128. Means for moving a message through a logical channel to a buffer set by the corresponding transmission buffer descriptor and then transmitting the message to the corresponding devices 14-1 to 20-16; In the receiving operation, when a message transmission request is inputted to the corresponding HIT communication processor 130, 136, 138, or 140 through the corresponding logical channel, a receiving interrupt is generated by the master communication processor 130, and the receiving reception is performed in the receiving interrupt routing. Means for displacing a message in a buffer to the DPRAM (128) and informing the corresponding HIT communication processor (130, 136, 138, 140) that there is a received message; Means for dynamically changing this communication bandwidth during communication by changing the value of an internal register.