KR19990060798A - The inverse discrete cosine transformer of the digital video receiving decoder apparatus - Google Patents

Abstract

In an image decoder of a digital TV receiver that compresses and transmits a video signal and decodes the transmitted compressed video signal at a decoder of a receiver and displays the ID, To an inverse discrete cosine transformer of a digital-TV receiving decoder apparatus that performs arithmetic operations through filtering and decimation (downsampling).

Conventionally, a decoding apparatus (decoder) for receiving an HDTV-class image in an SDTV receiver may or may not use a down-sampler according to a mode (SD / HD) after configuring a down-sampler.

In the present invention, ROM data having IDCT transform coefficient information corresponding to each mode (SD / HD) is selectively used according to characteristics of an input image, and IDCT / downsampling is integrated So that even if the coefficient values input to the IDCT have different points, they can be integratedly processed through only the IDCT without having a separate down sampler. .

Description

The inverse discrete cosine transformer of the digital video receiving decoder apparatus

The present invention relates to an Inverse Discreet Cosine Transform (IDCT) method in a video decoder apparatus of a digital TV receiver that compresses and transmits a video signal, decodes the transmitted compressed video signal in a decoder of a receiver, ).

As an embodiment, the present invention provides a digital TV decoder for receiving an MPEG video signal and decoding the received video signal, wherein a downsampling size is different in a decoder device for receiving an HD video using an SDTV receiver The present invention relates to an inverse discrete cosine transformer of a digital video receiving decoder apparatus capable of performing two-system IDCTs integrally.

The digital TV receiver decodes a video signal compressed and transmitted in MPEG2 in a decoder and displays it on the screen.

Generally, digital TV receivers are divided into HDTV class and SDTV class depending on the number of pixels (pel = picture element) considering factors influencing sharpness / image reproduction performance (picture quality). In the case of HDTV, It has a maximum performance of 1920pels / 1080lines, and for SDTV it has 640pels / 480lines, for example.

FIG. 1 shows an example of a decoder in a digital TV receiver. In FIG. 1, one pixel is represented by 8 bits, one macro block has a data structure of 16 * 16 pixels, Level bit stream.

1, a Variable Length Decoder (VLD) 1 performs variable length decoding on input bitstream data, an IDCT 2 performs Inverse Discrete Cosine Transform on variable length decoded data, The adder 3 stores the reconstructed image in the decoded data by using the motion compensated information of the motion weight information 4 in the frame memory 5 and outputs the reconstructed original image signal to the display means Video out).

FIG. 2A shows a 2D 8 * 8 IDCT process, in which an IDCT 202 is performed in a horizontal direction with respect to an 8 * 8 DCT block 201, and then an IDCT 203 is performed in a vertical direction to obtain an image block 204 .

Since the HDTV receiver receives and decodes HD-level data, it does not suffer from any problem in receiving and decoding SD-level data.

Since the SDTV receiver receives and decodes the SD-level data, it does not suffer from any problem in receiving and decoding the SD-level data, but it must be able to receive (process) (decode / display) the HD-level data from the viewpoint of compatibility.

For this purpose, the decoder device of the SD class TV receiver performs 'data processing' for SD class reception of HD class data.

This data processing is achieved through downsampling, filtering, and decimation.

FIG. 2B shows a simple example of a down-sampling method of a decoder device for receiving, decoding, and displaying HD-level data in an SD class TV receiver.

The method involves subsampling (206) the image block (205) in the horizontal direction to reduce it in the horizontal direction by half, and again vertically to the image block (207) ) To obtain a downsampled image block 209 by halving in the vertical direction.

Conventionally, in a decoder device for receiving an HD-level image in an SDTV receiver, IDCTs for receiving (decoding) down-sampled HDTV images and IDCTs for receiving (SDTV) video are separately provided. (ROM) having respective IDCT coefficient information corresponding to each mode.

The present invention provides an integrated IDCT in a digital TV receiving decoder device that affects the image quality of a reproduced image and downsamples each of the I, P, and B pictures in consideration of both color signals and luminance signals.

The present invention provides an integrated IDCT that performs all operations in a single integrated IDCT without a plurality of IDCTs even when the decoder processes both an HD bitstream and an SD bitstream.

In particular, the present invention provides an integrated IDCT that performs operations through one IDCT and processes both filtering and decimation operations (downsampling), even when outputting different points through downsampling in an SDTV receiver to provide.

In the present invention, a plurality of coefficient values are stored in a ROM by using the symmetry of the IDCT operation, and an integrated IDCT is realized by selectively using the coefficient values according to characteristics of the input image.

1 is a block diagram of a digital TV receiver decoder

2A shows a 2D 8 * 8 IDCT process;

2B is a view showing a sub-sampling process of a 2D image

3 is a block diagram of a decoder device to which the present invention is applied.

4 shows an IDCT / decoding process of progressive data;

5 is a diagram illustrating an IDCT / decoding process of interlaced scanning data;

6 is a block diagram showing a conventional IDCT concept

7 is a block diagram showing the IDCT concept of the present invention

8 is a block diagram of the IDCT block of the present invention

FIG. 3 is an embodiment of a digital TV receiving decoder apparatus to which the integrated IDCT of the present invention is applied. In FIG. 3, the luminance signal I and P pictures are down-sampled to 8 * 4, and the luminance signal B picture and color signals are down- Fig.

Hereinafter, the present invention will be described by way of examples.

First of all,

A first IDCT / downsampling means 31 for performing an IDCT and an 8 * 4 downsampling in the horizontal direction with respect to the IY and PY 32 with the DCT coefficient 30 as an input, A first coder 34 for performing bit reduction encoding of 8 * 4 data output from the first adding means 33, and a second coder 34 for outputting the first coder output A first decoder 36 for decoding the output of the first frame memory 35 and a second decoder 36 for decoding the output of the first decoder 36 into motion vector information 40 A first upsampling means 37 for upsampling in a horizontal direction in consideration of the motion vector information 40 and outputting it as 8 * 8 data; A first motion compensator 38 for processing the output of the first motion compensator 38, First downsampling means (39) for inputting motion compensation information to the motion compensation processing unit (33);

Second IDCT / down-sampling means 41 for performing IDCT and 4 * 4 down-sampling in the vertical and horizontal directions with respect to the BY, IC, PC, BC 42 with the DCT coefficient 30 as input, A second encoder 44 for performing bit reduction encoding of 4 * 4 data output from the second addition means 43, and a second encoder 44 for performing bit reduction encoding of 4 * 4 data output from the second addition means 43, A second decoder 46 for decoding the output of the second frame memory 45; a second decoder 46 for decoding the output of the second decoder 46; A second upsampling means 47 for horizontally / vertically upsampling in consideration of the motion vector information 40 and outputting the resultant as 8 * 8 data, and a second upsampling means 47 for outputting the output of the second upsampling means 47 as motion vector information A second motion compensator 48 for performing motion compensation prediction processing in consideration of the motion vector of the second motion compensator 48, Operating sampled by the second down sampling means (49) for inputting a motion compensation processing information to said adder (43) and;

A third downsampling means 50 for vertically downsampling the 8x4 output of the first decoder 36 to 4x4 and a second downsampling means 50 for outputting the output of the second downsampling means 50 to the second decoder A multiplexer 51 for outputting an output of the video decoder 46 as a final decoded video signal;

.

The first IDCT / downsampling means 31 performs inverse discrete cosine transform on the input DCT coefficients 30 and downsamples in the horizontal direction to reduce the size of 8 * 8 to 8 * 4.

Here, downsampling is performed on the luminance I picture IY and the luminance P picture PY, and the 8 * 4 data is input to the first adder 33.

The method of IDCT / downsampling to M * N (8 * 4) is presented in various ways and will be described later.

The result of performing 8 * 4 horizontal down-sampling on the 8 * 8 IY, PY macroblocks as described above is applied to the first adder 33. [

The output of the first adder 33 is input to the first encoder 34 that performs bit reduction encoding to reduce the amount of bits using the correlation of adjacent pixels in consideration of the capacity limitation of the first frame memory 35.

The amount of bits is reduced to 14 bits by removing 2 samples in consideration of the correlation of adjacent pixels in a horizontal (or vertical) direction on the basis of 8 * 4.

One example of a method for reducing the number of bits is DPCM.

The downsampling data is coded by values of x1 and x2-x1 for horizontal (or vertical) pixels x1 and x2. X1 is an 8-bit value and x2-x1 is a 6 bit value. With an 8-bit value, x2-x1 is encoded with a 6-bit non-uniformly quantized value.

This process is also performed for the second encoder 44.

The data reduced by the DPCM technique is stored in the first frame memory 35 and is decoded by the first decoder 36 through the inverse process of the decoding for image reconstruction (reproduction).

The decoded 8x4 data is upsampled in the horizontal direction by the first sampling means 37 that receives the motion vector information 40 for motion compensation and is output as 8x8 data.

The upsampled 8x8 data is input to the first motion compensator 38 and motion compensated by the motion vector information 40 and the motion compensated information is supplied to the first downsampling means 39 in the size of 8x8 .

The first downsampling means 39 horizontally downsamples the input 8x8 motion compensation information to 8x4 and supplies the resultant to the first adder 33 so that the first IDCT / 4, and outputs the motion compensated I and P picture luminance signals corresponding to the IY and PY data (size) down-sampled by 4.

The 8 × 4 data bit-decoded from the first frame memory 35 is subjected to vertical downsampling to a 4 × 4 size while passing through the third downsampling means 50, (To match BY, IC, PC, and BC down sampled to 4 * 4).

The second IDCT / downsampling means 41 performs inverse discrete cosine transform of the input DCT coefficient 40 and downsamples in the horizontal / vertical direction to reduce the size of 8 * 8 to 4 * 4.

The downsampling is performed on the luminance B picture BY and the color signals IC, PC and BC, and the 4 * 4 data is input to the second adder 43.

A method of IDCT down-sampling with K * L (4 * 4) will also be described later.

The result of performing 4 * 4 horizontal and vertical downsampling on the 8 * 8 BY, IC, PC, and BC macroblocks is applied to the second adder 43 as described above.

The output of the second adder 43 is input to a second encoder 44 that performs bit-reduction encoding by the DPCM technique and takes into account the capacity limitation of the second frame memory 45, Reduce.

The bit reduced data by the DPCM technique is stored in the second frame memory 45 and is decoded by the second decoder 46 through the inverse process of the decoding for image reconstruction (reproduction).

The decoded 4 * 4 data is upsampled in the horizontal / vertical direction by the second sampling means 47 which receives the motion vector information 40 for motion compensation and is output as 8 * 8 data.

The upsampled 8x8 data is input to the second motion compensator 48 and motion compensated by the motion vector information 40 and the motion compensated information is supplied to the second downsampling means 49 in the size of 8x8 .

The second downsampling means 49 horizontally / vertically downsamples the input 8 * 8 motion compensation information to 4 * 4 and supplies it to the second adder 43 so that the second IDCT / downsampling means 41 IC, PC, and BC data corresponding to the data (size) down-sampled by 4 * 4.

The 4 * 4 data bit-decoded from the second frame memory 45 is input to the multiplexer 51, and the third downsampling means 50, and outputs the video signal as a 4 * 4 video signal which is finally downsampled (video out).

In the SDTV receiver using MPEG2, when receiving and processing an HD-class image, downsampling can be performed so as to include a larger amount of information than a non-significant picture, which affects the quality of the reproduced image, Can be reproduced.

FIG. 4 is a view for explaining progressive scanning video signal source decoding, showing the concept of 1D-IDCT / downsampling.

The IDCT and the downsampled image block 403 are obtained by performing 1D-IDCT / filtering and decimation 402 in the horizontal direction with respect to the image data of one block unit 401 to obtain the 1D-IDCT / 404) to obtain an IDCT-processed image block 405. [

IDCT / filtering and decimation 406 in the vertical direction are performed on the 1D-IDCT in the horizontal direction and the downsampled image block 403 to obtain the IDCT and the downsampled image block 407. [

5 is a diagram for explaining interlaced source decoding with a top field and a bottom field. The concept of 1D-IDCT / downsampling is shown in FIG. 5. And black pixels and white pixels were used to distinguish the pixels of the top field and the bottom field).

1D-IDCT / filtering and decimation 502 in the horizontal direction are performed on the image data of one block unit 501 having the top field and the bottom field so that the image block having the IDCT and the downsampled top field and bottom field 503), and performs a 1D-IDCT 504 in the vertical direction with respect to the 1D-IDCT 504 to obtain an image block 505 of the top field and bottom field IDCT.

In addition, vertical direction 1D-IDCT / filtering and decimation 506 are performed on the 1D-IDCT in the horizontal direction and the downsampled top field and the bottom field image block 503 to generate IDCT and downsampled top field and bottom field Field image block 507 is obtained.

6 is an IDCT circuit in a conventional HDTV / SDTV shared decoder.

As described above, in order to receive an HD-level image from an SD-class TV receiver, an SDTV mode for decoding an SD-level image and an HDTV mode for decoding an HD-level image (downsampling) are provided.

Therefore, in HDTV mode, filtering / decimation with IDCT is performed to reduce the size of the HD-class image and display it on the SD class TV receiver.

That is, a 1D-IDCT 602 that receives 8 DCT coefficients and outputs 8 pels and a 1D-IDCT / filter and decimation 604 that receives 8 DCT coefficients and outputs 4 pels are respectively implemented. (The IDCT coefficient value is given to receive an appropriate IDCT coefficient according to each mode).

Horizontal and vertical directions, that is, 2D-IDCT and downsampling are as described in FIGS. 2A and 2B.

FIG. 7 is a block diagram showing the concept of the integrated IDCT of the present invention, in which an operation circuit 702 using four multipliers multiplies the IDCT coefficients corresponding to the SDTV mode and the HDTV mode IDCT coefficients of the HDTV or SDTV are inputted by referring to the value of the ROM 701 having the HDTV-level video data, and the IDCT / downsampled image data is output in the case of the HDTV-level video decoding by 4 pixels, In case of decoding, the image data which is IDCT is outputted in 8 pixels.

For this purpose, a HD / SD selection control signal, a picture selection signal, and a field / frame selection signal are inputted, and an address signal of ROM (ROM) is outputted and an addition or subtraction selection signal +/- do.

8 shows an inverse discrete cosine transformer of the digital video receiving decoder apparatus of the present invention.

A ROM 801-804 for performing an integrated IDCT on an input HDTV or SDTV bitstream 800 and four multiplication operators 805-804 for multiplying an input bitstream by IDCT transform coefficient information provided from the ROM, 808).

A subtracter 809-816 for performing addition or subtraction with the multiplied value as input and a register 817-824 for storing the subtraction or addition result and a signal 825 for controlling the subtraction or addition operation of the subtractor ).

It also has a first multiplexer 826 that selects an 8-point IDCT value 827 in SDTV mode and a second multiplexer 828 which in the HDTV mode has 4 points The IDCT value 829 is selected (filtering and decimation).

Figure 8 is a 1D-IDCT / downsampler circuit, which is cascaded in two stages to implement a 2D-IDCT / downsampler.

The integrated IDCT circuit thus constructed performs IDCT / downsampling for three cases.

That is, in the case of normal reception (SDTV class image reception) in FIG. 3, 8 * 8 IDCT is performed for 8 * 8 blocks, and 8 * 8 blocks for IY, PY, 4 IDCT / down-sampling (filtering / decimation), and performs 4 * 4 IDCT / down-sampling on 8 * 8 blocks of BY, IC, PC and BC.

This is accomplished simply by switching control of the multiplexers 826 and 828 according to the IDCT conversion information written and recorded in the ROM 801-804 corresponding to each case.

That is, in the case of SDTV video reception, the first multiplexer 826 performs 8-point output. In the case of HDTV video reception, the second multiplexer 828 outputs 4-point downsampled data in the vertical direction to the IY and PY data (1D-IDCT / downsampling), and BY, IC, PC and BC data are subjected to 4-point downsampling in the horizontal / vertical direction (2D-IDCT / downsampling, 1D- Gt; IDCT < / RTI > circuit).

According to the present invention, when an HDTV image is received and processed in an SDTV receiver using MPEG2, if downsampling is performed so as to include more information than a non-significant picture that affects the quality of a reproduced image, IDCT / downsampler of each system that performs IDCT / downsampling in different sizes can be integrated and shared as one.

Claims (3)

The data of the first group is divided into the size of M * N and the data of the second group is sized of K * L (M * NK * L) by dividing the data processed in block units. A digital image decoder for performing IDCT and downsampling (filtering and decimation) Computing means for down-sampling IDCT or IDCT / block unit data; Storage means for storing an IDCT transform coefficient value corresponding to a control signal and outputting the stored information in correspondence with the input signal, using an input such as a picture size, a frame rate, a scanning method, a receiving mode, and the like as a control signal; Control means for controlling the operation of said computing means by said control signal to select IDCT or IDCT / downsampling and to selectively output the stored value of said storage means; Point IDCT mode and an n-point IDCT / downsampling mode, including an n-point IDCT mode and an n-point IDCT / downsampling mode. The picture data is processed in a block unit (8x8), and the data processed in block units are divided into a first group of data having a size of 8 * 4 and a second group of data having a size of 4 * 4. A digital image decoder for performing downsampling (filtering and decimation) A ROM for storing IDCT coefficient values for each of the above cases, an operation for performing an IDCT or an IDCT / downsampling operation with an 8-DCT coefficient as input and a ROM (ROM) Circuit 805-824 and switching means 826 and 828 for selecting the output value of the arithmetic circuit corresponding to the picture, the frame rate, the scanning method, and the reception mode to perform 1D-IDCT / downsampling An inverse discrete cosine transformer of a digital video receiving decoder device. 3. The inverse discrete cosine transformer of claim 2, wherein the 1D-IDCT / downsampler performs 2-stage cascade connection to perform 2D-IDCT / downsampling on the second group of data.