KR19990060510A - Digital residual sideband demodulation device - Google Patents

Abstract

The present invention relates to a digital VSB demodulation apparatus for processing a residual side band (VSB) demodulation in a digital domain in a digital TV. Specifically, a low pass filter having a roll-off factor of 0.1152 and a bandwidth of 2.69 MHz is designed, The obtained coefficient is cos (? F ( By multiplying the passband of the SRC filter by the center frequency of the input signal by multiplying the passband of the SRC filter by the coefficient of the passband matching SRC filter and then feeding it back to the matching SRC filter, The interference of the adjacent channel is eliminated and there is no distortion of the received signal. As a result, the reduction of the pilot signal due to the frequency shift and the reduction of the gain, the problem of losing one edge component of the signal band, The inflow problem is solved and the restoration of the data becomes correct. In addition, a SAW filter whose characteristics are not precise can be used, so that it is competitive in cost.

Description

Digital residual sideband demodulation device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital television (TV), and more particularly, to a digital VSB demodulation apparatus that performs a VSB demodulation in a digital domain.

Digital TV has a much higher screen resolution (for example, 1080 × 1920) and wider in the horizontal direction (compared to analog TVs, which can accommodate as much as 4: 3.5: 3.1: 1.85: 1.2.4: 16: 9). CD-level sound is provided on multiple channels (up to 5.1 channels).

In the digital TV, the United States, Europe, and Japan are establishing standard broadcasting standards and standardization. In the United States, the transmission format adopts the residual sideband (VSB) scheme proposed by Zenith in the United States. The compression format adopts MPEG (MPEG) as the video compression and Dolby AC-3 as the audio compression. The display format has to be compatible with existing display methods.

At this time, the VSB modulation is a method of modulating only the remaining part when one of the two side bands, which occur up and down with respect to the carrier, is significantly attenuated when the signal is amplitude-modulated.

In other words, SSB (Single Side Band) using one side band has emerged because DSB (Double Side Band) which uses both upper and lower wave bands has a lower band efficiency, and developed into VSB of filter.

In addition, the Grand Alliance (GA), an organization that unifies the methods of digital TV, adopted 8 VSBs as a transmission method for broadcasting using terrestrial waves. Thereafter, Advisory Committee on Advanced Television Service (ACATS) We decided to adopt 8VSB for broadcasting.

The 8VSB has 8 levels of signals to be transmitted. In the 8VSB, four data levels are present on the positive side with respect to '0' and four data levels exist on the negative side.

Therefore, at the central office, the digital data is modulated to 8VSB and sent to the air through the antenna, so that the digital TV in each household can receive and demodulate it.

FIG. 1 is a block diagram of a VSB demodulation device of a conventional digital TV. FIG. 1 is a block diagram of a VSB demodulation device of a conventional digital TV. The VSB demodulation device of FIG. 1 multiplies a channel tuning of a signal transmitted through an antenna, a delay AGC and a frequency signal output from a local oscillator, A SAW (Surface Acoustic Wave) filter 12 for removing only a band in which information exists in the IF signal output from the tuner 11, and a remaining interval, A variable gain IF amplifier 13 for amplifying a signal output from the filter 12, a frequency-phase locked loop (FPLL) unit 14 for demodulating the amplified IF signal and converting the amplified IF signal into an I and Q signal of a baseband A voltage controlled oscillator (VCO) 15 for generating a center frequency using the feedback voltage of the FPLL unit 14, and a VCO 15 for converting the I signal demodulated by the FPLL unit 14 into a digital signal The analog / And an analog / digital (A / D) conversion section 16.

1, a broadcast signal in the air is input to a tuner 11 of a receiver through an antenna, and the tuner 11 multiplies a frequency signal output from a channel tuning, a delay AGC, and a local oscillator, To an intermediate frequency of 46.69 MHz.

At this time, since the digital TV broadcast signal has all the information in the 6 MHz band from the intermediate frequency of 46.69 MHz, the SAW filter 12 removes all the remaining sections leaving only the 6 MHz band in which information exists from the output of the tuner 11 .

The output of the SAW filter 12 is subjected to automatic gain control by receiving an AGC signal from the IF amplifier 13, demodulated into a baseband I and Q signals in a demodulation and FPLL unit 14, and the frequency and phase are locked.

That is, the output of the VCO 15 whose center frequency is fixed at 46.69 MHz is input to the second mixer 14-5 of the demodulation and FPLL unit 14 and multiplied by the output of the IF amplifier 13, Demodulates the Q channel signal.

The output of the VCO 15 is delayed by 90 DEG from the phase delay of the phase delay 14-6 and input to the first mixer 14-1 to be multiplied by the output signal of the IF amplifier 13, Demodulates the I-channel signal of the I-channel.

On the other hand, the frequency of the pilot inserted in the broadcasting station must be exactly 46.69 MHz at the output of the IF amplifier 13, so that the other receiver normally operates normally. However, in many cases, the frequency is not exactly 46.69 MHz.

Since the output frequency of the VCO 15 is fixed at 46.69 MHz, when the output frequency of the pilot in the IF amplifier 13 is not 46.69 MHz, the output from the first and second mixers 14-1 and 14-5 There is a beat corresponding to the difference between the two frequencies.

The FPLL is used to remove the beat frequency.

That is, by changing the oscillation frequency of the VCO 15, the frequency and phase of the IF signal carrier are changed to remove the bit frequency.

The purpose of the FPLL is to find the direction and magnitude of the oscillation frequency of the VCO 15.

That is, the I channel signal output from the first mixer 14-1 is cos (ω _i -ω _o ) t = cos Δω when the output frequency is ω ₀ and the pilot output frequency of the IF amplifier 13 is ω _{i t} .

Here,? W =? _O -? _I (bit frequency).

On the other hand, the Q channel signal output from the second mixer 14-5 has the form of sin DELTA _t .

At this time, the AFC filter 14-2 is constituted by a secondary passive filter capable of locking a bit frequency of ± 100 KHz, and has a characteristic of changing a frequency to a phase in addition to the characteristics of a low pass filter (LPF) And outputs a phase value for each bit frequency of the I signal of the first mixer 14-1.

The output of the AFC filter 14-2 is input to the limiter 14-3, amplified and limited, multiplied by the Q channel signal in the third mixer 14-4, and then fed back to the VCO 15. [

When the output of the limiter 14-3 is changed due to the existence of a bit frequency, the PLL process is performed to correct the phase when the FLL ends and the output of the limiter 14-3 no longer changes Lt; / RTI >

The I-channel signal demodulated by the demodulation and FPLL unit 14 is converted into a digital signal through an A / D conversion unit 16. The sampling frequency at this time is a symbol rate of 10.76 MHz.

As described above, the VSB demodulation apparatus of FIG. 1 performs carrier recovery and demodulation to the baseband in the analog domain. That is, as shown in FIG. 3, the frequency is directly shifted down to the baseband in the analog domain and then input to the A / D converter 16.

Therefore, it is difficult to adjust the phase difference between the I and Q channels exactly 90 degrees, resulting in deterioration of the demodulation performance. Since various devices are analog devices, there are various disadvantages such as deterioration due to temperature and difficulty in integration.

To solve these problems, the technique of demodulating to the baseband in the digital domain is disclosed in U.S. Patent No. 5,570,136, and is shown in Figs. 2A and 2B. That is, the I and Q channel signals are separated from the analog domain and then sampled using two A / D converters, and then converted into a baseband signal using an SRC filter.

Referring to FIG. 2A, a signal transmitted through an antenna is first and second demodulated by the tuner 21 according to a channel tuning, a delay AGC, and a frequency signal of 876 MHz output from the local oscillator 24, and is converted into an IF signal. Here, the local oscillator 24 is a fixed oscillator that outputs a frequency signal of 876 MHz to the tuner 21.

The IF signal demodulated by the tuner 21 is band-reject filtered through the SAW filter 22 and is subjected to automatic gain control by receiving an AGC signal from the IF amplifier 23 and then demodulated by the demodulator and FPLL unit 26 into I and Q signals Separately, the frequency and phase are locked.

At this time, the local oscillator 25 receives the AFC signal from the demodulator and the FPLL unit 26, and generates a frequency signal that can vary up to 300 KHz with 46.69 MHz as a reference frequency according to the voltage of the AFC signal to generate a demodulator and FPLL unit 26, .

Accordingly, the pilot position of the intermediate frequency signal inputted to the demodulator and the FPLL unit 26 is changed to 46.69 MHz ± 300 KHz, so that the SAW filter 22 should also have a guard band of ± 300 KHz at 6 MHz.

The I channel signal and the Q channel signal separated by the demodulator and the FPLL unit 26 are converted into digital signals and output to the VSB filter 27 in order to be demodulated into a baseband.

As shown in FIG. 2B, the VSB filter 27 includes two A / D converters 27a and 27b for converting an I channel signal and a Q channel signal into digital signals, two SRCs (Square Root Raied Cosine) Filters 27c and 27d, and a subtractor 27e.

That is, the I-channel signal whose frequency and phase are locked by the demodulator and FPLL unit 26 is digitized by the A / D converter 27a to a symbol rate of 10.76 MHz, and then is output from the SRC filter 27c SRC filtered.

The Q channel signal whose frequency and phase are locked by the demodulator and the FPLL unit 26 is digitized by the A / D converter 27b at a symbol rate of 10.76 MHz, and SRC filtered by the SRC filter 27d.

The subtracter 27e subtracts the filtered Q-channel signal from the SRC filter 27d from the I-channel signal filtered by the SRC filter 27c to generate a VSB filtered signal ( ).

2A and 2B, the I and Q signals are separated in the analog domain and then converted into the baseband in the digital domain. Since the frequency of the IF signal output from the tuner 21 is high, it is directly A / D-converted The frequency of the I and Q channel signals of FIG. 4A may be slightly lowered by the demodulator and the FPLL unit 26 as shown in FIG. 4B, and then output to the VSB filter 27 and the VSB filter 27 27 are digitized by the A / D converters 27a and 27b, respectively, and then converted into baseband in the digital domain as shown in FIG. 4C. That is, when A / D sampling is performed at A / D converters 27a and 27b at 46.69 MHz as it is, the frequency of the clock signal, which is required in consideration of various factors, must be 186.76 MHz (46.69 MHz * 4) Because the burden is too large.

However, since the VSB demodulation apparatus of FIG. 2 requires two A / D converters 27a and 27b and two SRC filters 27c and 27d, the VSB demodulator of FIG. 2 is required to design an application specific integrated circuit (ASIC) Integration is difficult, and even if it is integrated, its volume becomes large. Since the separation of the I and Q channel signals is performed in the analog domain, the problem caused by the analog processing also occurs.

In the VSB transmission scheme, the carrier wave is located at the edge of the signal band. Therefore, it can be seen that the signal of the adjacent channel rides like noise on the edge of the original signal due to the pass band characteristic of the SAW filter, as shown in FIG. 5A. Also, even if the signal is transited to a low frequency as shown in FIG. 5B for A / D conversion, the signal remains as an adjacent channel component.

Therefore, if the adjacent channel components are not completely removed by the SAW filter and are changed to the baseband as shown in FIG. 5C, the VSB scheme overlaps the desired signal band. In other words, it can not be removed by the filter.

In order to solve such a problem, the characteristics of the SAW filter must be precise and the change of the filter characteristics depending on the temperature must be small. It is not easy to fabricate the SAW filter satisfying these conditions. This is because the SAW filter serves as a matched filter. Even if such a filter can be manufactured, if the price is high and the frequency of the signal inputted to the filter is wrong, the above problems are inevitably generated.

That is, even if the band of the SAW filter is slightly larger than the original signal band and the signal is demodulated into the baseband in the digital domain, in the case of the VSB scheme, the position of the carrier wave is not located at the center of the signal band, So that the adjacent channel component enters the original signal band after demodulation. Once an interference or noise signal arrives at the signal band, it is difficult to remove it because it is indistinguishable from the original signal.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide an SRC filter capable of adjusting a coefficient according to a recovered carrier wave in a digital domain, So as to coincide with the bandwidth of the signal so that only the signal band is correctly passed.

It is another object of the present invention to provide a digital VSB demodulating device that performs VSB demodulation in a digital domain using one A / D converter and one SRC filter to improve the integration degree and performance of a digital circuit.

It is still another object of the present invention to provide a digital VSB demodulating device capable of removing adjacent channel interference even by using a non-compliant SAW filter.

In order to achieve the above object, a digital VSB demodulation apparatus according to the present invention comprises a low pass filter having a roll-off factor of 0.1152 and a bandwidth of 2.69 MHz, ) To obtain a coefficient of an SRC filter having a passband of 5.38 MHz, and provides the obtained SRC filter to the SRC filter. The SRC filter outputs only a signal in a passband shifted according to the provided coefficient among input signals converted into a digital signal, And the like.

here, , Π is the circumference, and n is an integer.

The SRC filter coefficient corresponding to each frequency deviation stored in the ROM is obtained by using the output value of the loop filter of the carrier recovery unit as a selection signal, The SRC filter coefficient of the corresponding frequency deviation is searched and output to the SRC filter.

The SRC filter of the present invention is a (2n-1) -stap FIR filter comprising a register for delaying a digital signal output from the A / D converter by the number of taps of an FIR filter, an adder and a multiplier, The output of the register Reg-n and the register Reg n are added first because the filter coefficient multiplied by the output of the register Reg-n is symmetric and the filter coefficient of the filter multiplied by the register Reg n is the same And the final output of the filter is calculated by adding all of the outputs of the remaining registers after applying the same to the remaining registers.

In the present invention, the IF signal converted by the tuner is multiplied by a sinusoidal wave to a frequency of 5.38 MHz, sampled at a frequency twice as high as a symbol frequency, and then passed through a coefficient-adjustable SRC filter to demultiplex I and Q channel signals, Is performed.

1 is a block diagram of a conventional analog VSB demodulating device

2 is a block diagram of a conventional digital VSB demodulating device

3 is a frequency spectrum diagram illustrating a frequency transition process in an analog VSB demodulation device

4A to 4C are frequency spectrum diagrams illustrating a frequency transition process in a digital VSB demodulation device

5A to 5C are frequency spectrum diagrams illustrating a frequency transition process when an adjacent channel intrusion occurs in a desired signal band in a digital VSB demodulation device

6 is a block diagram of a digital VSB demodulator according to the present invention

7A is a diagram showing the frequency response of an SRC low-pass filter having a bandwidth of 2.69 MHz and a roll-off factor of 0.1152

7B is a diagram showing the shock wave response of the SRC low-pass filter of FIG. 7A; FIG.

FIG. 7C is a diagram showing the frequency spectrum of FIG.

FIG. 8 is a detailed block diagram of the coefficient selection unit of FIG.

FIG. 9 is a detailed block diagram of the SRC filter of FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

61: tuner 62: frequency synthesizer

63: SAW filter 64: IF amplifier

65: mixer 66: low-pass filter

67: A / D converter 68: SRC filter

69: retarder 70: Hilbert filter

71: complex multiplier 72: carrier recovery unit

72-1, 72-2: IIR filter 72-3: retarder

72-4: Limiter 72-5: Multiplier

72-6: loop filter 72-7: NCO

72-8: coefficient selection unit 81: ROM

82: coefficient slicer

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 6 is a block diagram of a digital VSB demodulator according to the present invention, which includes an analog processor for converting a first IF signal to a second IF signal that is lower than the first IF signal, And a digital processing section for demodulating the signal into a baseband.

The analog processor includes a frequency synthesizer 62 for receiving a channel tuning signal and generating and outputting a first local hop (LO), and a multiplier 62 for multiplying a broadcast signal input through the antenna by a first local frequency (1st LO) (SAW) filter 63 for filtering the first intermediate frequency outputted through the tuner 61. The SAW filter 63 filters the first intermediate frequency outputted from the tuner 61, An IF amplifier 64 for amplifying the first intermediate frequency filtered by the SAW filter 63 and a second intermediate frequency lower than the first intermediate frequency by multiplying the amplified first intermediate frequency by a predetermined frequency, And a LPF 66 for low-pass filtering the second intermediate frequency outputted from the mixer 65. The mixer 65 mixes the low-pass filtered low-

The digital processing unit includes an A / D converter 67 for A / D sampling the output of the LPF 66 at a frequency twice the symbol frequency, a coefficient adjustable matching SRC filter 67 for filtering the output of the A / A delay 69 for delaying the output of the SRC filter 68 for a predetermined time, a Hilbert filter 70 for Hilbert transforming the output of the SRC filter 68, A complex multiplier 71 for multiplying outputs of the Hilbert filter 70 by cos and sin functions to demodulate them into baseband I and Q channel digital signals, And a decimator 73 for performing 2: 1 decimation so as to sample only one signal per symbol for the I-channel digital signal.

In the present invention configured as described above, the VSB signal received from the antenna is input to the tuner 61.

The frequency synthesizer 62 receives the channel tuning signal selected by the user and generates a first local frequency (1st L.O.) having a frequency difference of 920 MHz from the desired broadcast signal.

Therefore, the tuner 61 multiplies a plurality of broadcast signals output from the antenna by a first local frequency (1st L.O.) output from the frequency synthesizer 62 to make the desired broadcast signal frequency 920 MHz. At this time, the tuner 61 is automatically controlled by the feedback of the AGC.

Then, the frequency of the desired broadcast signal is multiplied by the second local frequency to lower the frequency of the desired broadcast signal to the center of 44 + - 3 MHz, which is the first intermediate frequency, and then output to the SAW filter 63 to remove the adjacent channel prepayments. Since the digital TV broadcast signal has all the information in the 6 MHz band from the intermediate frequency of 44 ± 3 MHz, the SAW filter 63 leaves only the 6 MHz band in which the information exists from the output of the tuner 61, Remove.

At this time, the characteristics of the SAW filter 63 need not be precise. That is, the bandwidth of the SAW filter 63 may be a general-purpose SAW filter having a bandwidth slightly larger than the original signal bandwidth, for example, a bandwidth of rough. This means that any kind of bandpass filter can be used. This is because the digital processing section has a matching SRC filter 68 that can be adjusted in coefficients.

The output of the SAW filter 63 is adjusted by the IF amplifier 64 and then multiplied by a sine wave in the mixer 65 to be converted to a frequency lower than the first intermediate frequency. That is, in order to perform VSB demodulation in the digital domain, it is necessary to convert to a second intermediate frequency lower than the first intermediate frequency converted by the tuner 61.

For example, the output of the mixer 65 is converted to be? / 2, that is, the difference (= center frequency) between the two frequencies is 5.38 MHz. This is because the coefficient of the matching SRC filter 68 becomes simpler when the sampling frequency of the A / D converter 67 is 21.52 MHz (= 2 fs and fs is the symbol rate), which is advantageous in implementation as a circuit. The sampling frequency of the A / D converter 67 and an integer multiple (for example, 0, 1, 0, -) of the center frequency and the sampling frequency of the A / D conversion unit 67 are independent of the center frequency converted by the mixer 65, 1) is used, the coefficient of the SRC filter 68 becomes simpler.

At this time, since the sum component of the output of the mixer 65 occurs together with the difference component of the desired frequency, the sum component is removed by using the LPF 66 and then input to the A / D converter 68. The operation of the analog processing unit has been described so far.

The A / D converter 67 converts the second analog IF signal output from the LPF 66 into a digital IF signal at a frequency twice the symbol frequency.

In this case, the signal digitized by the A / D converter 67 is subjected to SRC filtering in the same manner as that used in the transmitter. Conventionally, the SAW filter of the baseband or analog processor performs the digitalization of the signal. And performs SRC filtering using a digital filter 68 in a passband.

That is, if the center frequency of the signal input to the A / D converter 67 does not match the center of the bandwidth of the matching SRC filter 68, the signal is distorted by filtering, It will have a serious impact. In order to solve this problem, the present invention shifts the pass band of the SRC filter 68 that adjusts the coefficient according to the carrier difference signal fed back from the carrier recovery unit 72, using a matching SRC filter 68 capable of adjusting the coefficient.

The output of the matching SRC filter 68 is simultaneously input to the delay 69 and the Hilbert filter 70. The Hilbert transformed signal from the Hilbert filter 70 is input to the complex multiplier 71 do.

Here, when the output of the matching SRC filter 68 passes through the Hilbert filter 70, the output is 90 degrees out of phase.

The delay 69 delays the output of the matching SRC filter 68 by the processing time of the Hilbert filter 70 and is output to the complex multiplier 71.

As a result, the output of the delay 69 input to the complex multiplier 71 and the output of the Hilbert filter 70 have a phase difference of 90 °.

Therefore, when the output of the delay unit 69 and the output of the Hilbert filter 70 are multiplied by sine waves of cos and sin in the complex multiplier 71, they are demodulated into baseband I and Q channel digital signals, 71 and the demodulated I and Q channel digital signals are outputted to the carrier recovery unit 72. [

The carrier recovery unit 72 is applied by the present applicant and further includes a coefficient selection unit 72-8 for adjusting the coefficient of the matching SRC filter 68. [

That is, the I-channel digital signal and the Q-channel digital signal are input to the first and second infinite impulse response filters (IIR filters) 72-1 and 72-2, respectively, The effect is removed and the effect due to the influence on the self-phase characteristic is eliminated.

The output of the first IIR filter 72-1 is input to the delay 72-2 to linearly change the frequency band phase characteristics of the output of the first IIR filter 72-1. Then, it is limited by the limiter 72-3 and input to the multiplier 72-5. That is, the output of the limiter 72-3 becomes a sign.

Therefore, if the multiplier 72-5 multiplies the IIR-filtered Q-channel digital signal, the IIR-filtered Q-channel digital signal is inverted in sign by the multiplier 72-5, (72-6). That is, the output of the multiplier 72-5 becomes an error value.

The digital loop filter 72-6 accumulates an error value input through the multiplier 72-5, that is, a frequency deviation, and an NCO (Numerically Controlled Oscillator) 72-7 accumulates the error value input from the loop filter 72-6 And controls the frequency and phase of the digital signal according to the output to generate a recovered carrier wave having a frequency and a phase, and outputs the generated carrier wave to the complex multiplier 71. [ Therefore, the frequency deviation decreases with time.

Then, the decimator 73 decimates the I-channel digital signal output from the complex multiplier 71 so that only one signal is sampled per symbol, and outputs the decimated VSB baseband signal to a timing recovery, synchronization recovery, and equalization Lt; / RTI >

A detailed description of the matching SRC filter 68 for shifting the pass band by the outputs of the coefficient selecting unit 72-8 and the coefficient selecting unit 72-8 according to the present invention is as follows.

7A shows the frequency response of an SRC low-pass filter having a bandwidth of 2.69 MHz and a roll-off factor value of 0.1152, which is represented by a ratio of a transmission band to a pass band. The impulse response of this filter is shown in Fig.

At this time, the coefficient of the low-pass filter having the roll-off factor of 0.1152 and the bandwidth of 2.69 MHz is obtained, and cos (? F ) To obtain the coefficient of the band-pass SRC filter 68 having a center frequency of 5.38 MHz and a pass band of 5.38 MHz. here, , And Π is the circumference.

That is, as shown in FIG. 7B, the SRC low-pass filter having a bandwidth of 2.69 MHz and a roll-off factor of 0.1152 is called a (2n + 1) -tap FIR filter, = -n, -n + 1, ..., 0, 1, ..., n-1, n; n is an integer), the method of obtaining the coefficients of the passband SRC filter is as follows.

For example, as shown in Fig. 7C, in order to obtain the coefficient of the band-pass SRC filter 68 whose center frequency is 5.38 MHz and the passband of the signal is 5.38 MHz, the above-mentioned bandwidth is 2.69 MHz and the roll- (N) is added to the coefficients a (j) (j = -n, -n + 1, ..., 0, 1, ..., n-1, n; n are integers) of the SRC low- ). ≪ / RTI >

At this time, if the carrier wave of the input signal is exactly 5.38 MHz,? F = 1 and cos (? F ) Is cos ( ), So that one of the two values has a zero value, which can increase the degree of integration in circuit implementation.

That is, if the coefficient of the bandpass SRC filter having the center frequency of 5.38 MHz and the signal passband of 5.38 MHz is a_pass (j), the coefficients for all the taps can be obtained as shown in the following equation (1).

[Equation 1]

As described above, the coefficient of the SRC filter 68 can be adjusted according to the carrier wave of the input signal to move the pass band.

8 is a detailed block diagram of the coefficient selection unit 72-8. The coefficient calculator 72-8 stores in advance the coefficients calculated by the above-mentioned method in the ROM 81 and then outputs it to the loop filter 72-6 of the carrier recovery unit 72 The coefficients to be provided to the SRC filter 68 are searched in the ROM 81 by the outputted coefficient selection signal and the searched coefficients are sliced by the coefficient slicer 82 and then output to the SRC filter 68.

8, m is a coefficient selection signal output from the loop filter 72-6 of the carrier recovery unit 72, and determines the number of frequency bands to be shifted.

For example, when the locking range of the carrier recovery unit 72 is -100 KHz to +100 KHz, the band of the passband matching SRC filter 68 should be shifted in the same manner, 4 bits are required for m, and the coefficients of the SRC filter having the deviations of 5.38 MHz and 20 KHz in the ROM 81 must be calculated and stored in advance. That is, the value of m becomes the address of the ROM 81, and if m is 0001, the coefficients stored in the address 0001 of the ROM 81 are selected and output. P represents a bit stream of coefficients.

n = ( ) -1. This is because when the number of taps of the SRC FIR filter is designed to be odd-numbered, the coefficients are symmetrical, so that the coefficients are stored in the half-ROM 81.

At this time, the coefficient selection signal is determined by slicing the output value of the loop filter 72-6 of the carrier recovery unit 72. [

For convenience of explanation, the loop filter 72-6 changes the center frequency of the input signal to 5.38 KHz when the locking range of the carrier recovery unit 72 is -100 KHz to +100 KHz and varies from -100 to +100 according to the frequency difference Let's assume that you want to output a value. Assuming that the coefficient of the SRC filter 68 having a deviation of 20 KHz is stored in the ROM 81 and the output value of the loop filter 72-6 is -10 KHz to +10 KHz, The coefficient of the SRC filter whose center frequency is 5.38 MHz is selected and when the frequency is -10 KHz to +30 KHz, the coefficient of the SRC filter whose center frequency of the pass band is 5.40 MHz is sliced to be selected.

In this way, the slices are selected to select the remaining coefficients.

Also, the coefficient slicer 82 plays the role of cutting the coefficient of each tap by p bits since the value output from the ROM 81 is p x n bits and input in a row without counting the coefficients for each tap.

9 shows an SRC FIR filter 68 according to the present invention. The SRC FIR filter 68 comprises a register, an adder, and a multiplier that can delay an input signal input from the A / D converter 67 by the number of taps of the FIR filter .

In this case, since the coefficient of the filter has symmetry, that is, the coefficient of the filter multiplied with the output of Reg-n is the same as the coefficient of the filter multiplied by Reg n, the output of Reg-n and Reg n are added first, Is multiplied by the coefficient output from the coefficient selection unit 72-8.

In this way, the outputs of the remaining registers are computed and added together to compute the final output of the filter.

Therefore, since the passband of the matching SRC filter 68 also changes as the center frequency of the input signal changes, a passband is always set with reference to the center frequency of the input signal, and even if the center frequency of the input signal changes, You can prevent the signal from coming in like noise.

As described above, the digital VSB demodulator according to the present invention solves the problem caused by the carrier wave deviation of the transmitter / receiver.

That is, a low-pass filter having a roll-off factor of 0.1152 and a bandwidth of 2.69 MHz is designed to obtain a coefficient, and cos (? F ) ( By multiplying the frequency of the passband of the SRC filter by a predetermined frequency deviation by multiplying the frequency of the passband of the SRC filter by the frequency of the passband of the SRC filter, Since there is no interference between neighboring channels due to coincidence of the frequencies, there is no distortion of the received signal. As a result, the decrease and gain reduction of the pilot signal due to the frequency transition, the problem of losing one edge component of the signal band, Etc. are solved and the restoration of the data is correct.

After the SRC filter coefficient according to the determined angular frequency deviation is obtained by the above method and stored in the ROM, the output value of the loop filter of the carrier recovery unit is used as the selection signal, and the SRC filter coefficient corresponding to each frequency deviation stored in the ROM The SRC filter coefficient of the corresponding frequency deviation is searched and outputted to the SRC filter, so that it is not necessary to calculate the coefficient of the new SRC filter every time the center frequency of the input signal changes, so that the processing speed and hardware complexity can be reduced.

In addition, since SAW filters having unequal characteristics can be used, they are also cost-competitive.

Further, the intermediate frequency converted by the tuner is again lowered to 5.38 MHz, and the clock frequency of the A / D converter is doubled as the symbol frequency so that the demultiplexing of the I and Q channel signals and the demodulation into the baseband are all performed in the digital domain, It is possible to maintain the phase difference of the carrier wave precisely at 90 degrees, thereby improving demodulation performance and facilitating integration and ASIC design. At this time, since only one A / D converter and one SRC filter are used, the degree of integration can be increased.

Claims (11)

A tuner for performing channel tuning on the broadcast signal received from the antenna and then converting the broadcast signal into an intermediate frequency (IF) signal; A low frequency IF signal output unit for multiplying the IF signal output from the tuner by a sinusoidal wave to convert the IF signal to a lower frequency than the IF signal of the tuner; An analog / digital converter for sampling the signal output from the low frequency IF signal output unit at a frequency twice the symbol frequency and converting the sampled signal into a digital signal; A coefficient adjustable digital filter for shifting the pass band of the digital signal converted by the analog / digital converter, A channel signal output unit for demodulating a signal passing through the digital filter into a baseband I-channel digital signal and a Q-channel digital signal, and then decimating the I-channel digital signal so that only one signal is sampled per symbol; A carrier recovery unit for recovering a carrier wave by calculating a frequency deviation from I, Q channel digital signals demodulated in baseband in the channel signal output unit; And a coefficient selecting unit for obtaining coefficients of the digital filter different from the frequency deviation of the carrier recovery unit and providing the coefficient to the digital filter. 2. The apparatus of claim 1, wherein the coefficient selector A low-pass filter having a predetermined roll-off factor value and bandwidth is designed to obtain the coefficient of the low-pass filter, and cos (? F ) To obtain a coefficient of the dichroic filter. here, , Π is the circumference, and n is an integer. 3. The receiver of claim 2, wherein the low pass filter A roll-off factor value of 0.1152, and a bandwidth of 2.69 MHz. 2. The apparatus of claim 1, wherein the coefficient selector Pass filter with a roll-off factor of 0.1152 and a bandwidth of 2.69 MHz is designed to obtain a coefficient, and cos (? F ), The coefficient of the digital filter having the pass band of 5.38 MHz is calculated in advance by a predetermined frequency deviation and stored in the ROM, and the coefficient selection signal corresponding to the frequency deviation outputted from the carrier recovery unit is stored in the ROM And outputs the read digital modulated signal to the digital filter. here, , Π is the circumference, and n is an integer. 5. The method of claim 4, Wherein the coefficient selection signal output from the carrier recovery unit determines the number of frequency bands to be shifted in the digital filter. 5. The method of claim 4, Wherein the coefficient selection signal is determined by slicing the output value of the loop filter of the carrier recovery unit. The digital filter according to claim 4, wherein the digital filter Wherein half of the coefficients are stored in the ROM of the coefficient selection unit by symmetrically designing the coefficients by designing the number of taps as an odd-numbered difference. 8. The method of claim 7, The output of the ROM of the coefficient calculation unit is P x n bits, and P is a bit stream of coefficients Wherein the digital residual-side demodulation unit demodulates the digital residual-side demodulated signal. The digital filter according to claim 1, wherein the digital filter And a coefficient-adjustable matching SRC filter. 10. The apparatus of claim 9, wherein the SRC filter is a (2n + 1) (positive integer) tap FIR filter. 11. The method of claim 10, wherein the SRC FIR filter A filter for delaying the digital signal output from the A / D conversion unit by the number of taps of the FIR filter, an adder and a multiplier, wherein the coefficient of the filter is symmetric and multiplied by the output of the register (Reg -n) The output of the register Reg-n is first added to the register Reg n and then multiplied by the coefficient output from the coefficient selector and the remaining registers are multiplied by the coefficient of the filter multiplied by the register Reg n, And the final output of the filter is calculated by adding all of the outputs to the output of the remaining registers.