KR19990057856A - Low power cache memory device - Google Patents

Abstract

The present invention provides a low-power cache memory device that eliminates unnecessary power waste when all the cache lines of the way are invalid. To this end, the present invention provides an n-way tag address entry block for storing a tag address. A cache memory device comprising: a state block storing a cache line valid bit indicating an entry's validity; an LU block storing recent minimum usage information of each cache line; and a data RAM storing data; First logic means for outputting a cache enable signal by ORing the corresponding cache line valid bits of the state block indexed by an index address among physical addresses inputted for the; Second logic means for outputting a first control signal for reading the Rl block by logically multiplying the cache enable signal and an Ll control signal; Third logic means for outputting a second control signal for reading the tag address entry block by ANDing the cache enable signal and the tag address entry block read signal; And fourth logic means for outputting a third control signal for reading the data RAM by ANDing the cache enable signal and the data RAM read signal.

Description

Low power cache memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly, to a low power cache memory device that limits the read operation of a cache when all the ways are invalid in a way structure cache.

High-performance microprocessors include a large amount of cache memory inside the processor to improve processor performance. As is well known, a cache stores frequently used data in a slow access storage medium (ie, main memory) in cache memory, which is a faster access medium, and stores necessary data faster. It delivers to the microprocessor to improve the performance of the system.

In general, when data is accessed in the cache memory and the data is available without access to the main memory, this is called a cache hit, and the data is taken directly from the cache. In the case of a cache miss (if no data is in the cache), the main memory is accessed to get the data. In addition, in order to increase the cache hit rate, a cache memory structure including a plurality of ways (hereinafter, referred to as “n-way”) of increasing data storage locations by n is recently used.

Although most of the applications show statistically high cache hit ratios due to the local nature of data access, all the ways are invalid when performing low-local program execution or system reset such as multimedia related applications. ), The cache hit ratio decreases considerably.

The read operation of the conventional cache memory device in this case will be described.

FIG. 1 illustrates a configuration of a physical address input from an address generation unit to read data stored in a cache memory. The physical address is field-specific, that is, a tag address and an index address. It consists of (index address) and byte pointer.

2 is a block diagram conceptually illustrating a conventional cache memory device. Referring to the cache memory read operation, first, an n-way tag address entry 200 is accessed in response to an index address and a tag read signal, and then the tag addresses are compared to output a tag hit / miss signal 201. Also, a read recently used block (Least recently used, LRU) is also performed. In the final hit / miss determination unit 220, the tag hit / miss signal 201 is logically multiplied by the cache line valid bit indexed by the index address of the state block 210 and the tag hit / miss signal 201. a hitway signal 221 is generated and the tag hitway signal 221 is output to a dataRAM. Then, in response to the tag heat way signal 221, the n-way output of the data RAM, which has been read to the index address in advance, is selected and sent to the execution unit.

The read operation of the conventional cache memory device has a problem in that unnecessary power is wasted by unnecessarily performing an LRU read, a tag address entry read, and a data RAM read operation when the cache lines of all the ways are invalid.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a low power cache memory device which eliminates unnecessary power waste when all the cache lines of the way are invalid.

1 is a configuration diagram for each field of a physical address.

2 is a block diagram conceptually illustrating a conventional cache memory device;

3 is a block diagram conceptually illustrating a cache memory device of the present invention;

4 is a timing diagram for a valid index address of each block in accordance with the present invention.

* Description of the main parts of the drawing

300: tag address entry block 310: status block

320: LRU block 340: data RAM

330: final hit / miss determination unit

In order to achieve the above object, the present invention provides an n-way tag address entry block for storing a tag address, a status block for storing a cache line valid bit indicating validity of each entry, and a recent minimum usage information of each cache line. A cache memory device including an LU block for storing data and a data RAM for actually storing data, the cache memory device comprising: performing a logical OR of corresponding cache line valid bits of the state block indexed by an index address among physical addresses input for data access; First logic means for outputting an enable signal; Second logic means for outputting a first control signal for reading the Rl block by logically multiplying the cache enable signal and an Ll control signal; Third logic means for outputting a second control signal for reading the tag address entry block by ANDing the cache enable signal and the tag address entry block read signal; And a fourth logic means for performing an AND operation on the cache enable signal and the data RAM read signal to output a third control signal for reading the data RAM.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram conceptually illustrating a cache memory device of the present invention, wherein an n-way tag address entry block 300 storing a tag address and a state block storing a cache line valid bit indicating validity of each entry are shown in FIG. (310), the LRU block 320 to store LRU information of each cache line, the data RAM 340 to actually store the data, the corresponding cache line valid bit 311 of the state block 310 indexed by the index address A logical OR gate 311 that outputs a cache enable signal by OR, a first AND gate 331 that outputs a control signal for reading the LRU block by ANDing the cache enable signal and the LRU read signal, and a cache enable signal. And the second AND gate 301 which outputs a control signal for reading the tag address entry block 300 by ANDing the tag read signal with the AND, and the cache enable signal and the data RAM read signal are ANDed. A third logical AND gate 341 outputting a control signal for reading the tram 340, and a tag hit / miss output from the corresponding cache line valid bit 311 and the tag address entry 300 of the status block 310. The final hit / miss determination unit 330 generates a final tag heat way signal in response to the signal 302 and outputs the final tag heat way signal to the data RAM 340.

In general, the state block 310 allocates 1 bit of valid bits to each way when supporting only a single processor mode, and in case of an x86-structured MESI protocol supporting a multiprocessor mode Assigns 2 bits to each way. Thus, in a typical four-way set associative cache structure, the row pitch of the state block 210 is 4 or 8 bits, the row pitch is short, and the number of cache line entries is 128 with an address address of 7 bits. Because of the entry, the access time of the state block 210 can be processed at a high speed of 2-3ns in a 0.35μm process.

In view of this, the present invention inputs an index address to the falling edge of the cache clock (400 in FIG. 4) as the state block 310, and corresponds to the state block 310 indexed by the index address. The cache line valid bit 311 is first read and ORed to generate a cache enable signal. At this time, if all the corresponding cache lines of all the ways are invalid, the cache enable signal outputs a logic level "0", and is logically multiplied with each read control signal of the LRU / tag address entry / dataram block to raise the edge of the cache clock. Disable operation of the LRU / tag address entry / dataram operated at the (rising edge) 401 of FIG. 4.

4 is a timing diagram of a valid index address of each block according to the present invention, in which an address generating unit must supply an index address sufficiently before the rising edge of the cache clock for an accurate read operation of the state block 310. In other words, the index address is changed on the falling edge of the cache clock to give a half clock time margin.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

According to the present invention as described above, the state block is read first to check the validity of the cache line entries of all the ways, and then the operation of the LRU / tag address entry / dataram block is enabled, thereby eliminating unnecessary power consumption and thus low power cache. It was possible to perform the operation.

In addition, since the weight of the additional circuit is small, it is possible to apply it to the cache memory of all chips because there is no difference from the conventional cache memory device in terms of area.

Claims (4)

An n-way tag address entry block for storing tag addresses, a status block for storing a cache line valid bit indicating validity of each entry, an L block for storing recent minimum usage information of each cache line, and data A cache memory device including a data RAM for storing, First logic means for outputting a cache enable signal by ORing corresponding cache line valid bits of the state block indexed by an index address among physical addresses input for data access; Second logic means for outputting a first control signal for reading the Rl block by logically multiplying the cache enable signal and an Ll control signal; Third logic means for outputting a second control signal for reading the tag address entry block by ANDing the cache enable signal and the tag address entry block read signal; And Fourth logic means for outputting a third control signal for reading the data RAM by ANDing the cache enable signal and the data RAM read signal; Cache memory device comprising a. The method of claim 1, The cache enable signal is And when all cache line entries indexed by the index address are invalid, disable the read operation of the AL block, the tag address entry block, and the data RAM. The method of claim 1, The index address input to the status block is And a memory block which is valid on a falling edge of the cache clock and is input to the state block. The method of claim 3, wherein The index address input to the RB block, the tag address entry block, and the data RAM is And a valid data at the rising edge after the falling edge and input to the RDL block, the tag address entry block, and the data RAM.