KR19990049147A - Error correction method - Google Patents

Abstract

The present invention relates to an error correction method of data, and more particularly, to an error correction method for correcting reproduction data erroneously reproduced from a disc to original data.

The error correction method of the present invention comprises the steps of: performing a syndrome operation on the demodulated data; Constructing and storing a frame with main data and syndrome values; Error correcting in a first manner based on the syndrome value and simultaneously correcting the syndrome; Error correcting the data corrected in the first manner in a second manner and simultaneously correcting the syndromes; And repeating the error correction of the first method again using the syndrome corrected by the second method.

Description

Error correction method

The present invention relates to an error correction method of data, and more particularly, to an error correction method for correcting data which is erroneously read from a disc to original data.

The digital signal transmits and records data in a combination of two pieces of information, 1 and 0, specifically, a binary number with or without voltage (HIGH) or low (LOW). Therefore, even if there is distortion or noise in the transmission system and the recording system, there is no signal deterioration as long as a state capable of correctly discriminating 1 or 0 is ensured. As such, digital signals are more reliable than analog signals.

However, pure digital signals encoded in binary numbers, themselves, are not flexible at all, so if one of the many bits changes from one to zero and zero to one, the original information content will be completely different, causing large distortion or noise. have. Even when the error occurs severely, the content of the information cannot be interpreted at all.

Therefore, it is no exaggeration to say that the quality of a product in a recording medium using a digital signal and a system for reproducing the recording medium depends on how many errors occur.

Compact Discs that record these digital signals (hereinafter referred to as CDs) are reproduced data errors by CIRC (Cross Interleaved Reed-Solomon Code), a very powerful error correction method combining Reed-Solomon codes and interleaving techniques. Correction is being performed.

The CIRC is very powerful in error correction, and is widely used in digital audio equipment including CDs. Furthermore, the CIRC used directly on the CD is a two-stage CIRC treatment called C1 and C2. If the CD surface is scratched and the data between them cannot be read at all, the original sound is completely reproduced. It has strong error correction capability.

The Reed-Solomon code used for CIRC has the minimum unit of data as 8 bits instead of 1 bit. The 8-bit symbol is called a code word. Therefore, the C1 code of CIRC has 28 symbols of data and 4 symbols of parity for correction. In the CIRC C2 code, data has 24 symbols, correction parity has 4 symbols, and 28 symbols.

CIRC error correction independently applies the correcting codes to the cross interleaving of C1 and C2 and their respective sequences. Therefore, error correction of two words is possible independently. In particular, since error correction of C2 is performed using the error flag detected by C1, error correction of up to four words is possible. If error correction of C1 is repeated after error correction of C2, four error corrections are possible by the error flag detected in error correction of C1 and C2.

As described above, when decoding is performed by the C1 → C2 → C1 process, since the decoding is performed using the error flag detected in the previous decoding, the accuracy of error correction is very high. However, it takes longer than necessary to access RAM until C1 → C2 → C1. Therefore, most CDs in C1 → C2 complete the error correction process.

The following describes the error correction method in the conventional CD in detail.

1 is a flowchart showing an operation according to an error correction method used in a conventional compact disc. In this flowchart, a CIRC error correction process according to C1 → C2 → C1 is shown.

The data read from the disk is subjected to EFM demodulation after synchronization detection. The EFM demodulated data is stored in RAM on a frame basis. At this time, since data is stored in one symbol unit, a total of 32 data writing processes are performed.

In this process, the 32 symbols stored in the RAM are read back from the RAM in order to perform C1 error correction. At this time, the read data is data of the C1 system for one frame (step 101). Data reading from the RAM is performed in symbol units. Therefore, in order to read all 32 symbols including 28 data symbols and 4 parity symbols from the RAM in step 101, 32 RAM accesses are required.

Then, decoding of the C1 system is performed (step 103). In the decoding process of C1, an error of two words can be corrected. Therefore, if two errors are detected in the C1 decoding process, the C1 data of the position where the error occurred is read through two reading processes, and the operation of correcting the error value and rewriting the error at the position where the error occurred is performed twice. It is through the process. Therefore, a total of four RAM accesses are required in the decoding process of C1. After C1 decoding in step 103, the data stored in the RAM is in a state including four symbols that are parity data of C1. If one error is detected in the C1 decoding process, one reading and one writing operation will be performed in the C1 decoding process.

After performing C1 decoding by performing step 103, the RAM stores corrected data up to two errors detected in the C1 decoding process. As described above, in order to perform C2 decoding on the data on which the decoding of C1 is performed, 28 symbols of the C2 system are read from the RAM (step 105). Therefore, in step 105, all RAM accesses are required 28 times.

28 symbols of the C2 system read in step 105 are decoded in the C2 system in step 107. The decoding of the C2 system is a process of decoding the data which has already been decoded by the C1 system again. In this case, the decoding is performed by referring to the error flag detected in the decoding process of the C1 system. Thus, in the C2 decoding process, error correction of up to 4 words is possible.

If an error of 4 words is detected in the decoding process of C2, the process of loading from RAM is performed four times to remove the error value of the position where the error occurred, and similarly, the corrected error value is the position where the error occurred. It is written four times. Accordingly, up to eight RAM access operations are performed in the decoding process of C2 in step 107.

In the decoding of C1 and C2 by the above process, since correction codes are independently applied to the cross-interleaves of C1 and C2 and their respective sequences, error correction of two words in C1 decoding and four words in C2 decoding is possible.

In the above process, ECC by C1 → C2 process was completed. However, after the process of C1 → C2, the error correction process by C1 is further performed in ECC by the process C1 → C2 → C1.

That is, in step 109, the 32 symbol data of the C1 system is read from the RAM (step 109). The data read at this time includes four symbols, which are parity data. Accordingly, 32 steps of RAM access are required in step 109 as well. Up to four RAM accesses are performed while C1 decoding the 32 symbols read. (Step 111).

The error correction data according to C1 → C2 → C1 is stored in the RAM. After that, 24 symbols minus parity symbols are read from the RAM and output as a block for digital signal processing (step 113).

In the conventional error correction process performed by the above process, up to 128 RAM accesses are performed in ECC by C1 → C2 and up to 164 RAM accesses are performed in ECC by C1 → C2 → C1. The RAM access time performed in the process C1 → C2 is shown in the attached table Table 1, and the RAM access time in the process C1 → C2 → C1 is shown in the attached table Table2.

However, in the disc reproducing apparatus which is gradually increasing the reproduction speed as in CD and DVD, the RAM access time is the most problematic part in digital signal processing. So even if you want to perform strong ECC by C1 → C2 → C1 process, there is a problem due to RAM access time. Thus, most CD ECCs have been terminated by C1 → C2 process.

This point is not necessarily limited to the case of CD. For example, in the case of digital video discs, PO decoding is performed after PI decoding. Therefore, it is good to repeat PI decoding for better error correction, but it is not possible to perform repeated error correction because the RAM access time by ECC process could not solve this problem.

Accordingly, an object of the present invention is to provide a more accurate error correction method by repeating the decoding process.

Another object of the present invention is to provide an error correction method that can minimize the RAM access time required in the error correction process.

1 is a flowchart showing an operation according to an error correction method used in a conventional compact disc, FIG. 2 is a block diagram showing a general compact disc reproducing apparatus, and FIG. 3 is a detailed configuration diagram of the CIRC decoder 25 according to the present invention. 4 is an internal configuration diagram of the syndrome calculator 56 shown in FIG. 3, FIG. 5 is an operation flowchart according to an error correction process according to the present invention, and FIG. 6 is a diagram of a syndrome operator for syndrome calculation after C2 error correction in the present invention. Internal diagram, Table 1 shows the RAM access time performed in the conventional C1 → C2 process, Table 2 shows the RAM access time according to the conventional C1 → C2 → C1 process.

An error correction method according to the present invention for achieving the above object comprises the steps of: syndrome calculation of the demodulated data; Constructing and storing a frame with main data and syndrome values; Error correcting in a first manner based on the syndrome value and simultaneously correcting the syndrome; Error correcting the data corrected in the first manner in a second manner and simultaneously correcting the syndromes; And repeating the error correction of the first method again using the syndrome corrected by the second method.

The error correction method of the present invention is characterized by repeating the error correction on the basis of the point detected in the previous decoding process in the method C1 → C2 → C1.

In the error correction method of the present invention, C1 decoding is characterized by using a syndrome value.

That is, the error correction method of the present invention brings the effect of improving the error correction capability by performing C1 error correction once more while reducing the RAM access time.

Hereinafter, an error correction method according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram showing a general compact disc reproducing apparatus.

In the disc reproducing operation, first, data is read from the disc 40 using the optical pickup device 5, and the read data is input to the high frequency amplifier 10 so as to be sufficiently signaled at the next stage. After amplifying to a level and shaping the waveform, the waveform is output to the digital signal processing unit 45. Therefore, the EFM signal output from the high frequency amplification unit 10 is greatly improved and the interference or distortion of the adjacent signal is output.

The data strobe 15 accurately reproduces the synchronous clock from the EFM signal output from the high frequency amplifier 10, and demodulates the digital signal into an analog signal without affecting jitter or error. In general, the EFM output of the high frequency amplifier 10 includes a large number of time axis errors due to disc eccentricity, rotation speed change, and the like. Based on this signal, a PLL circuit is generally used to reproduce an accurate sync pulse and to remove an error pulse.

The EFM demodulator 20 is a component for converting an 14-bit channel coded EFM signal into original 8-bit data. The serial EFM signal is converted in parallel in the converter and latched every 14 bits. The 14-bit EFM signal is demodulated in a total of 258 patterns by combining 256 data patterns and two subcode sync patterns representing the head of the subcode.

The CIRC decoder 25 inputs data after the 14-bit EFM signal is converted into an 8-bit data string after synchronous reproduction. The CIRC decoder 25 stores the data once input into the RAM 35 and then simultaneously performs deinterleave and jitter absorption.

That is, symbol data composed of 8-bit units are recorded by being distributed (interleaved) in units of frames at the time of recording in order to randomize the burst error that occurs when the disk is largely damaged. Therefore, the deinterleave is an operation of returning the interleaved data to the original array when data is input to the error correction circuit, and controls the write address and the read address by using an external RAM called a deinterleave RAM.

3 is a detailed block diagram of the CIRC decoder 25 according to the present invention. That is, FIG. 3 shows a configuration in which a syndrome value is calculated in order to perform C1 error correction according to the syndrome value required by the present invention, and the calculated syndrome is stored in the RAM 35 including a symbol.

The CIRC decoder 25 of the present invention inputs a symbol output from the EFM demodulator 20, registers 50 for storing symbols for one frame, a symbol output from the register 50, or is currently input. The multiplexer 52 outputs the alternating symbols R (x), the syndrome operator 56 for inputting the output of the multiplexer 52 and calculating the syndrome, and the output of the multiplexer 52, and parity is removed. And a parity removal unit 54 for outputting only the data.

In addition, the CIRC decoder 25 of the present invention includes a symbol generator 58 constituting a new symbol by including a syndrome value output from the syndrome operator 56 in the data output from the parity remover 54. In the symbol generator 58, a symbol including a syndrome is configured to be stored in the RAM 35.

Next, a process of calculating the syndrome value of the demodulated data by the above configuration will be described.

The demodulated symbol R (x) is inputted by the EFM demodulator 20 to store one frame of data in the register 50. Thereafter, the syndrome operator 56 alternately reads the symbol currently input through the multiplexer 52 and the symbol output from the register 50, and then performs a syndrome operation of the input symbol R '(x).

On the other hand, the parity remover 54 outputs the data D (x) value obtained by subtracting the parity value from the input symbol R '(x). The parity removed by the parity removal unit 54 is four symbols and four symbols.

In this way, the syndrome Sj generated by the syndrome operator 56 and the data D (x) obtained by subtracting the parity value from the input symbol R '(x) are input to the symbol generator 58. The symbol generator 58 forms a symbol R " (x) by using the data D (x) output from the parity removing unit 54 and the syndrome value output from the syndrome operator 56 to the RAM 35. That is, the syndrome output from the syndrome operator 56 is recorded at the parity position of the original data, so that the written syndrome is 4 bytes equal to the amount of parity removed.

Therefore, a total of 32 write processes are performed until 32 symbols for one frame are stored in the RAM 35. 28 bytes of data and 4 bytes of syndrome are stored.

Next, FIG. 4 is an internal configuration diagram of the syndrome calculator 56 shown in FIG.

The syndrome operator 56 once stores the input symbol R (x) in the register 60 through the adder 64. The symbol stored in the register 60 is output as a syndrome value and simultaneously multiplied by the root a ^{jr of the} polynomial generated by the multiplier 62. The value R (x) a ^jr obtained at this time is added to the next input symbol and the adder 64, stored in the register 60, and output as a syndrome value. The process is repeated repeatedly until 32 symbols are input based on one frame.

In other words, the configuration shown in Fig. 4 is a configuration in which a syndrome value is continuously accumulated and added to a symbol input for one frame. 4 illustrates a syndrome operator 56 that outputs one syndrome value. Yet, all of Sind by operator 56 of the present invention outputs the four syndrome value, but the configuration is the same as Figure 4, only the roots of the generator polynomial a ^0, a ^1, a ^2, a calculated according to the ^third applied Losing syndrome values vary.

Therefore, the syndrome operator 56 outputs four syndrome values S0, S1, S2, and S3 for each frame. At this time, generation of the output syndrome value is generated by the following equation.

S0 = r ₃₁ + r ₃₀ + r ₂₉ + r ₂₈ + r ₂₇ + .... r ₀

S1 = r ₃₁ (a) ³¹ + r ₃₀ (a) ³⁰ + r ₂₉ (a) ²⁹ + .... r ₀ a

S2 = r ₃₁ (a ² ) ³¹ + r ₃₀ (a ² ) ³⁰ + r ₂₉ (a ² ) ²⁹ + .... r ₀ a ²

S3 = r ₃₁ (a ³ ) ³¹ + r ₃₀ (a ³ ) ³⁰ + r ₂₉ (a ³ ) ²⁹ + .... r ₀ a ³

Where r _n is the code word and a represents the root of the generator polynomial.

5 is a flowchart showing an error correction method according to the present invention.

Data reproduced from the disc is demodulated by the EFM demodulator 20 (step 201).

The data R (x) demodulated in step 201 stores one frame (32 symbols) in the register 50. Thereafter, the syndrome operator 56 reads the currently input symbol R (x) and the output of the register 50 alternately by one symbol through the multiplexer 52, and then a syndrome operation is performed (step 203). .

At this time, the symbol generator 58 forms a new symbol R "(x) with the syndrome Sj calculated in step 203 and the data d (x) value obtained by subtracting the parity value from the input symbol R (x). The newly constructed symbol R "(x) = d (x) X _nk + Sj.

The symbol R ″ (x) configured as described above is stored in the RAM 35. Therefore, since the data write operation is performed in the unit of the symbol 35, 32 RAM accesses are performed until one frame is stored. In other words, 28 bytes of data and 4 bytes of syndrome are stored (step 205).

In this process, 32 symbols stored in the RAM are read back from the RAM to perform C1 error correction. At this time, the read data is 4 bytes of syndrome data (step 207). Data reading from the RAM is performed in symbol units. Therefore, in step 207, all four RAM accesses are required for the four-byte syndrome to read from the RAM.

In step 207, the syndrome data read for C1 error correction may be omitted. This is because, when the syndrome operation according to step 203 is performed, the syndrome can be stored after error correction.

Then, decoding of the C1 system using the syndrome value is performed (step 209). In the decoding process of C1, an error of mode 2 words can be corrected. Therefore, if two errors are detected in the C1 decoding process, the C1 data of the position where the error occurred is read through two reading processes, and the operation of correcting the error value and rewriting the error at the position where the error occurred is performed twice. It is through the process. Therefore, a total of four RAM accesses are required in the decoding process of C1.

If there is an error after the decoding of the C1 system is performed in step 209, it is necessary to correct the syndrome value corresponding to the error position. Therefore, in step 209, correction of the syndrome value corresponding to the detected error position is performed through four RAM access processes.

After C1 decoding by performing step 209, the RAM stores corrected data up to two errors detected in the C1 decoding process. As described above, in order to perform C2 decoding on the data on which the decoding of C1 is performed, 28 symbols of data of the C2 system are read from the RAM (step 211). Therefore, in step 211, all RAM accesses are required 28 times.

28 symbols of the C2 system read in step 211 are decoded by the C2 system in step 213. The decoding of the C2 system is a process of decoding the data which has already been decoded by the C1 system again. In this case, the decoding is performed by referring to the error flag detected in the decoding process of the C1 system. Thus, in the C2 decoding process, error correction of up to 4 words is possible.

If an error of 4 words is detected in the decoding process of C2, the process of loading from RAM is performed four times to remove the error value of the position where the error occurred, and similarly, the corrected error value is the position where the error occurred. It is written four times. Therefore, up to eight RAM access operations are performed in the decoding process of C2 in step 213.

If there is no error in the decoding process of C2, since there is no change in the data value, there is no need to modify the syndrome value. However, when an error occurs (up to 4 symbols), the syndrome value of the frame where each error occurs must be corrected. Therefore, when the K-th error of the C1 data is corrected, the syndrome corresponding to the frame must be calculated again.

Syndrome correction is performed as follows.

R '(x) = R (x) + e _k x ^k , R (x): data before C2 error correction

R '(x): Data after C2 error correction.

Since Sj = R (a ^j ), Sj '= R (a ^j ) + e _k a ^jk ,

Sj: C1 syndrome before C2 error correction,

Sj ': C1 syndrome after C2 error correction.

Fig. 6 shows a configuration for the syndrome calculation after the C2 error correction calculated as described above.

The syndrome operator inputs the C1 syndrome before the C2 error correction, multiplies the root of the generated polynomial obtained by the register 72 and the multiplier 74 by the error value in the multiplier 76, and adds the newly calculated syndrome to the adder 78 ), And correct the C2 error, then write the C1 data into the syndrome. Similarly, four configurations for the syndrome calculation after the C2 error correction are configured with the same configuration to obtain a new syndrome value according to the root of each generated polynomial.

With this configuration, four syndromes (S0 ', S1', S2 ', S3') based on the root of each generated polynomial are obtained.

S0 '= S0 + e _k

S1 '= S1 + e _k a ^k

S2 '= S2 + e _k7 a ^2k

S3 '= S3 + e _k a ^3k (for CD).

On the other hand, in the error correction process of C2, four syndrome values are obtained for each detected error. Therefore, when the maximum number of detected errors is four, 16 syndrome values should be corrected, and thus 16 RAM access procedures are performed. The modified syndrome value is stored in the syndrome position of the C1 data after the C2 correction.

Up to this point, the error correction of C1 and C2 was performed once, and in the second C1 error correction, since the erasure correction is possible by using the error flag generated by the decoding of the first C1 and the C2 decoding, the maximum Error correction is possible up to 4 symbols.

Thus, to perform C1 error correction again, the C1 syndrome is read from the RAM 35. At this time, since the read data is a C1 syndrome of four symbols, all four RAM accesses are performed (step 215).

Error correction using the C1 syndrome is performed (step 217). At this time, error correction is performed up to 4 symbols. Therefore, if there are 4 detected errors, 4 reads and 4 write operations are performed and up to 8 RAM accesses are required. That is, in operation 217, since error correction is possible using error flags generated by the decoding of the first C1 and the decoding of C2, error correction is performed up to 4 symbols.

The error correction data according to C1? C2? C1 is stored in the RAM. After that, the 24 symbols minus parity symbols are read from the RAM and output as a block for digital signal processing (step 219).

Table 3 shows the RAM access timing in error correction proposed by the present invention. When the syndrome operation according to step 203 is performed, if the syndrome is stored after error correction, the four syndrome data reading processes of step 207 may be omitted.

That is, in the error correction process of the present invention, the C1 error correction by C1 → C2 → C1 process is performed once more, but since only 132 RAM accesses are performed in all, it was possible to reduce the RAM access time, which has been presented as a big problem in the prior art. . Therefore, in case of CD and DVD, the RAM access time can be shortened, and the error correction capability can be further increased while increasing the speed.

As described above, the error correction method according to the present invention improves error correction capability by repeatedly performing error correction three times, thereby dramatically reducing the probability of false correction. In particular, by shortening the ram access time, it is possible to adjust the ram access time required for high-speed playback.

In the description of the present invention, the case of CD is described as an example. However, the DVD also stores the syndrome value obtained at the first error correction as in the present invention, and at the time of the first error correction at the time of error correction in a repeated manner. By reading the stored syndrome value, error correction using the same can be performed.

TABLE 1

TABLE 2

TABLE 3

Claims (4)

Synthesizing the demodulated data; Constructing and storing a frame with main data and syndrome values; Error correcting in a first manner based on the syndrome value and simultaneously correcting the syndrome; Error correcting the data corrected in the first manner in a second manner and simultaneously correcting the syndromes; And repeating the error correction of the first method again using the syndrome corrected by the second method. The error correcting method of claim 1, wherein the syndrome value is stored in a parity region. The error correction method of claim 2, wherein the syndrome value is composed of 4 symbols. 4. The method of claim 3, wherein the first scheme is decoding by C1 and the second scheme is decoding by C2.