KR19990047721A - Data redundancy processing unit - Google Patents

Abstract

The present invention relates to a data duplication processing apparatus in an all-electronic exchange suitable for providing a data bus between the two boards mounted so as to double the common bus to speed up data processing. In the case of writing data between redundant boards, data is transferred between the redundant boards by using latches. Therefore, a start signal and an end signal are generated to generate a start signal and an end signal between the two redundant boards. Since the processing speed of the processor is lowered because the data is processed by the memory cycle which finishes data transfer, in the present invention, the common bus 17 is used to sequentially send data to the other board to write the data to the other board. Almost the same time you spend on It is possible to do more work by redundancy, and in case of a changeover, it minimizes the loss of data when switching between active / standby, and transmits the data so that the call service is not disconnected. It can be improved.

Description

Data redundancy processing unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data duplication processing device, and more particularly, to a data duplication processing device in an electronic switching system for speeding up data processing by dualizing a common bus in a data mutual processing device between two mounted boards. It is about.

In the prior art, when data is to be written between redundant boards, data is transferred between the redundant boards by using a latch. Thus, a start signal and an end signal are generated so that a start signal and an end signal are duplicated between the two redundant boards. There is a drawback that the processing speed of the processor is reduced because it is processed by the memory cycle that finishes data transfer when all the boards occur.

The present invention has been made to solve the above-mentioned drawbacks of the prior art, and by using a common bus to replace an existing latch, it is possible to write to the memory of the other party through the common bus irrespective of the start signal and the end signal. The purpose is to increase the data transfer rate of the processor when switching between the boards that are dualized into active / standby.

Since the present invention can write to the memory of the other side using a common bus, there is almost no difference between the speed of writing to the memory of the other side and the speed of writing to the memory of the other side in the active processor. Another object of the present invention is to provide a data redundancy processing device that minimizes data and address loss during transfer between boards.

In order to achieve the above object, the present invention provides a processor that is active in charge of controlling an active board in an active / standby redundant board, an active memory controller controlled by a processor, and a control of a memory controller. A memory configured to be active to receive data and address information from the processor and store data and address information, a common bus to receive data and address information from the processor on the board and transmit it to a board set to standby, and active / standby redundant The board configured as standby in the board includes a second processor configured as standby in charge of controlling the board, a second memory controller controlled by the second processor, and data and address information received from the common bus. By standby It provides redundancy of data processing apparatus characterized in that comprises the specified memory.

1 is a block diagram showing an embodiment of a data redundancy processing apparatus using a common bus in an all-electronic exchange according to the present invention.

<Description of the code | symbol about the principal part of drawing>

10, 20: first, second board 11, 21: first, second processor

13, 23: first and second memory control unit

17, 27: 1st, 2nd memory 18: common bus

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the invention described below with reference to the accompanying drawings.

According to the configuration of the present invention, the first board 10 set to be active in a board duplexed by active / standby includes a first processor 11 that is in charge of controlling the first board 10 and a first processor 11. The first memory controller 13 under control of the first memory 17 and the first memory 17 receiving data and address information from the first processor 11 under the control of the first memory controller 13 and storing the data and address information. A common bus 17 configured to receive data and address information from the first processor 11 of the first board 10 and transmit the data and address information to the second board 20, and a board duplexed with active / standby. The second board 20 set in the standby state in FIG. 2 includes a second processor 21 that is in control of the second board 20 and a second memory controller 23 that is controlled by the second processor 21. Data from the common bus 17 and address information It is comprised of a second memory 27 for storing the address information.

Since the start signal is generated from the second board 20 to the first board 10 to write data and addresses to the first board 20 and the end signal is generated again, the description thereof is similar. Will be omitted.

Referring to FIG. 1, a block diagram showing an embodiment of a data duplication processing apparatus using a common bus in an all-electronic exchange will be described in more detail with reference to FIG. 1. 1 is transferred to the memory control unit 13, and the data and address are transferred to the first memory 17 and the first DPRAM 18 via the data and address buses.

The first memory controller 13 transmits a start signal received from the first processor 11 to the first memory 17.

The first memory 17 stores a start signal received from the first processor 11 and exchanges information with the first DPRAM 18 through a data and address bus.

The common bus 17

The first DPRAM 18 receiving the data and the address from the first processor 11 sequentially transmits the data and the address to the counterpart memory under the control of the second memory controller 23 of the second board 20.

The second memory controller 23 controls the second memory 27 to write data to the second memory 27 using the corresponding address.

In addition, when data writing is completed on the second board 20, the common bus 17 detects this to allow another device to occupy the bus. After writing data, each board is independent of each other and the termination signal is only relevant to its board.

On the other hand, when writing is finished in the first memory 17, the first processor 11 ends by a common bus 17 cycle when writing is completed regardless of the signal of the second board 20.

In the second memory 27, when the writing is completed, the second memory 27 receives the data from the first processor through the bus cycle and transmits the same to the second processor 11, and the second processor 21 recognizes that the writing is finished.

Unlike the write end, when an error occurs in the first board 10 that was active and stops operation, the data transfer is the same as the data and address in the first memory 17 through the common bus 17. Without the second board 20 can be active.

The principles of the invention have been described above in connection with specific devices, which are described by way of example only, and are not limited to the spirit of the invention as described in the appended claims.

As described above, the present invention sequentially sends data to the other board by using the common bus 17, so that the write cycle can be kept almost the same as the writing time of its own board so that more work can be duplicated and processed. When switching occurs, the transfer of data by minimizing the loss of data when switching between active / standby is effective, so that the call service is not interrupted.

Claims (1)

A corresponding processor 11 operating in an active state in charge of controlling the active board 10 in a board duplexed by active / standby; A memory controller 13 set to active under the control of the processor 11; A memory (17) set to be active for receiving data and address information from the processor (11) under the control of the memory controller (13) and storing data and address information; A common bus 17 for receiving data and address information from the processor 11 of the board 10 and transmitting the data and address information to a board 20 set as a standby; In the board duplexed with active / standby, the board 20 set as the standby is A second processor 21 set as a standby in charge of controlling the board 20; A second memory controller 23 under the control of the second processor 21; And a memory (27) set as standby for receiving data and address information from the common bus (17) and storing data and address information.