KR19990031547A - Router for packet data transmission of upper data link control protocol - Google Patents

Abstract

The present invention supports the routing of 1: N and N: 1, and is configured as a full duplex structure to process and analyze data in real time without degrading the transmission processing speed. One preferred embodiment of a router for,

A GCIN interface that converts the data flowing in the form of high-speed HDLC packets into pure data and analyzes and transmits the data in real time; Four channel cards for converting the pure data transmitted from the GCIN interface into HDLC packet data, and four line interfaces for connecting the HDLC data transmitted from each channel card with eight E1 links, respectively.

Description

Router for packet data transmission of upper data link control protocol

The present invention relates to a 1: N router for high-level data link control (HDLC) packet data transmission, and in particular, to analyze and process data flowing in the form of a high-speed HDLC packet. Four COMMPORTs in the Digital Signaling Processor (DSP) process the data in 8-bit parallel and insert a FIFO to implement zero wait between the DSP and the MC68360. It is about 1: N and N: 1 bidirectional routers that transmit data in real time.

Transmission of signals over a transmission link requires data link control and a data link protocol.

HDLC is a representative protocol for controlling data links and is defined by the International Organization for Standardization (ISO). HDLC uses synchronous transmission and is used for all kinds of data and control exchanges in a single frame format.

The data to be transmitted is combined with some overhead to form one frame for use in HDLC.

The frame used in HDLC includes an 8-bit start flag field, an address field composed of one or more octets (8-bit), an 8- or 16-bit control field, It consists of an information field of arbitrary size which is actual data, a frame check sequence (FCS) field of 16 or 32 bits, and an end flag field of 8 bits.

The frame configured as described above is packetized and transmitted through the data link.

Packet data transmitted through the data link is converted into data through a router and analyzed for use in other networks that may use different protocols.

The router having the above role has a structure for connecting N links and N links, and performs operations such as connection of a call, transmission of data and interrupts, call removal, reset, and system restart.

As the number of subscribers increases and the circuits become more complex, there is a need to connect a single link to multiple links or, conversely, to connect data transmitted through multiple links to a single link.

Therefore, there is a need to implement a router that can analyze HDLC data packets transmitted through a single data link path in real time without waiting time and transmit them to multiple transmission links.

Therefore, in order to solve the problems as described above,

It aims to provide a router configured to support both directions and connect 1: N and N: 1 paths so that data flowing in a high speed HDLC packet can be analyzed in real time and transmitted to multiple nodes.

1 is a structural diagram of a router according to the present invention;

2 is a structural diagram of a GCIN interface according to the present invention;

3 is a structural diagram of a channel card according to the present invention;

<Description of Symbols for Main Parts of Drawings>

100: GCIN interface 200: channel card

300: line interface 110: A module

120: B module 130: C module

140: D module 111,131: transceiver

112,132: CPU 113,133: SRAM

114,134 EPROM 115,135 DPRAM

116,126,136: control logic 117,127,137: buffer

121: buffer 122: DSP

123: address decoder 124: EPROM

125: SRAM 141: VME control logic

142: VME interface controller 210: A module

220: B module 211,221: transceiver

212,222 CPU 213,223 SRAM

214,224 EPROM 215,225: DPRAM

216,226: control logic 217,227: buffer

218,228: FIFO

One preferred embodiment of the present invention created to achieve the above object,

A GCIN interface for converting the data flowing in the form of a high speed HDLC packet into pure data and analyzing and transmitting the data in real time; Four channel cards for converting the pure data transmitted from the GCIN interface into HDLC packet data; And four line interfaces that connect HDLC data transmitted from the respective channel cards to eight E1 links, respectively.

In the present invention, the GCIN interface, each channel card and each line interface preferably has a fully redundant structure,

The GCIN interface comprises: an A module for converting HDLC packet data received from an external data link into pure data; A B module for receiving pure data from the A module and routing the received pure data to four channel card interfaces; A C module constituting a redundant structure with the A module; And a D module for controlling a VME bus for signal transmission / reception in each module.

The A and C modules include: a transceiver for transmitting / receiving HDLC packet data through a data link; A CPU for converting the HDLC packet data transmitted from the transceiver into pure data; A memory storing information for data conversion of the CPU; Control logic to control bus usage between the memory and the CPU; And a buffer controlling a bus usage between the memory and the CPU,

The B module includes a buffer for temporarily storing data to be transmitted to four channel card interfaces; A DSP for analyzing and routing the data transmitted from the A module or the C module to the buffer; An address decoder for decoding an address for data analysis of the DSP; An EPROM storing information for data analysis of the DSP; An SRAM storing information for data analysis of the DSP; Control logic to control bus usage between the address decoder, EPROM, DPRAM and the DSP; And a buffer controlling a bus use between the address decoder, the EPROM, the DPRAM, and the DSP.

The DSP transmits data to the buffer using four ports, and each buffer transmits data to four channel cards using one port.

The D module includes: VME control logic for controlling control logic in the A module, the B module, and the C module; It is preferable to include a VME interface controller for controlling the buffer in the A module, B module and C module,

The channel card performs a function of receiving pure data from a GCIN interface and converting the data into HDLC packet data. The channel card has a redundancy structure. Desirable,

The two modules include an RS422 transceiver for transmitting data transmitted from a CPU to a framer of a line interface; A CPU for converting pure data transmitted from a GCIN interface into HDLC packet data and transmitting the converted data to the transceiver; A memory for storing information for converting data in the CPU; Control logic to control bus usage between the memory and the CPU; And a buffer controlling a bus usage between the memory and the CPU,

It is preferable to additionally install a FIFO between the CPU and the GCIN interface to compensate for the processing speed of the GCIN interface and the processing speed of the channel card.

The CPU transmits data to the transceiver using four SCC ports, and the transceiver transmits data in parallel to a line interface using four ports.

1 shows a structural diagram of a router according to the present invention.

As shown, a gateway communication interface network (GCIN) interface 100 for converting data flowing in the form of high-speed HDLC packet into pure data, and analyzing and transmitting the data in real time; Four channel cards 200 for converting the pure data transmitted through the COMMPORT from the GCIN interface into HDLC packet data, and four line interfaces connected to each channel card through eight SCCs to handle communication lines between routers ( 300).

The router configured as described above is a bidirectional router having a full duplex structure in order to increase the reliability of the equipment.

Therefore, HDLC packet data transmitted through a single path can be converted into pure data and transmitted to multiple E1 links, while pure data transmitted through E1 link can be converted into HDLC packet data and transmitted using a data link.

Hereinafter, the internal structure of the modules will be described in detail.

2 shows a structural diagram of a GCIN interface according to the present invention.

As shown, A module 110 for converting HDLC packet data transmitted from an external data link into pure data; Receiving and routing pure data from the A module, and then transmitting the B data to each of four channel card interfaces through four COMMPORTs; It includes a C module 130 and the D module 140 for controlling the VME bus connecting the respective modules forming a redundant structure with the A module.

The A module 110 and the C module 130 having a redundant structure include a transceiver 111 and 131 for transmitting and receiving HDLC packet data through a data link; A CPU (MC68360) (112) (132) for converting HDLC packet data received from the transceivers (111) (131) connected through SCC1 into pure data; An SRAM (113) (133) for storing information for data conversion of the CPU (112) (132); An EPROM (114) (134) for storing information for data conversion of the CPU (112) (132); DPRAM (115) (135) for storing information for data conversion of the CPU (112) (132); Control logic 116 (136) for controlling the bus usage between the SRAM, EPROM, DPRAM and the CPU (112) 132 and controlling bus usage between the SRAM, EPROM, DPRAM and the CPU (112) 132 And buffers 117 and 137.

The B module 120 for matching pure data converted in the A module or the C module to the channel card interface includes: a buffer 121 for temporarily storing data to be transmitted to the four channel card interfaces; A DSP (122) for analyzing and routing data transmitted from the A module (110) or the C module (130) through COMMPORT 1 and transmitting the data to the buffer (121) through COMMPORT 0, 2, 3, and 4; An address decoder 123 for decoding an address for data analysis of the DSP 122; An EPROM 124 storing information for data analysis of the DSP 122; An SRAM 125 storing information for data analysis of the DSP 122; Control logic 126 for controlling bus usage between the address decoder, EPROM, DPRAM and the DSP 122 and a buffer 127 for controlling bus usage between the address decoder, EPROM, DPRAM and the DSP 122; It is composed.

The D module 140 includes VME control logic 141 for controlling the control logic 116, 126, 136 of each module; And a VME interface controller 142 that controls the buffers 117, 127, 137 of each module.

Hereinafter, the operation of the GCIN interface when the A module is in the Active state and the C module 130 is in the Standby state will be described.

Data in the form of HDLC packets flowing into the SCC1 of the processor 112 of the A module 110 through the transceiver 111 is converted into pure data and transferred to the COMMPORT1 of the DSP 122 in the B module 120 through the PIP. .

The DSP 122 analyzes and routes the transmitted data and channels each as 8-bit parallel data through each of the four 8-bit Wide-Wide Bidirectional Inter-Porcessor Communication (IPC) ports COMMPORT 0, 2, 3, and 4. The CPU 200 transfers the card 200 to the CPU MC68360.

As described above, each module and board constituting the GCIN interface 100 communicate with each other using the VME bus method, and the GCIN interface 100 has a full-duplex structure in order to increase the reliability of the structure.

Therefore, HDLC packet data transmitted from the data link can be processed and transmitted to the channel card 200, or pure data transmitted from the channel card can be processed and transmitted to the data link.

The pure data routed after conversion in the GCIN interface 100 is transmitted to the channel card 200 and reconverted to HDLC packet data.

3 shows a structural diagram of a channel card according to the present invention.

As shown, a module 210 for receiving pure data from the GCIN interface 100 and converting it into HDLC packet data; It consists of a module 220 to perform the same role as the module 210.

The module 210 and the module 220 may include: an RS422 transceiver (211) (221) for matching the analyzed data with a framer of a line interface through four SCCs; A CPU (212) (222) for converting pure data transmitted from a GCIN interface into HDLC packet data and transferring the data to the transceivers (211) (221) through four SCCs; An SRAM (213) (223) for storing information for analyzing data in the CPU (212) (222); An EPROM (214) (224) for storing information for analyzing data in the CPU (212) (222); DPRAM (215) (225) for storing information for analyzing data in the CPU (212, 222); Control logic 216 and 226 for controlling bus usage between the SRAM, EPROM, DPRAM and the CPU 212 and 222 and controlling bus usage between the SRAM, EPROM, DPRAM and the CPU 212 and 222 A first input first output (FIFO) 218 (228) for temporarily storing the data transmitted from the buffer 217 (227) and the GCIN interface 100 to the CPU (212) (222) Consists of.

The DSP 122 in the GCIN interface 100 at any time has a maximum transfer rate of 20 Mbyte / sec (at 40 ns cycle time), whereas the maximum transfer rate of the MC68360 in the channel card 200 is 10 Mbyte / sec. A standby state may occur due to a decrease in speed of the CPUs MC68360, 212, and 222, thereby lowering the speed of the DSP 122.

In the four COMMPORTs of the DSP 122, since two CPUs are connected to each port, a total of eight CPUs communicate. Therefore, the slowdown caused by the CPU has a great effect on the data transfer.

In order to minimize the effect of this speed and eliminate the wait state, the FIFO 218 (228) between the DSP 122 of the GCIN interface 100 and the CPU 212 (222) of the channel card 200. Are inserted in the transmission / reception respectively.

Then, even if the CPU 212 and 222 are currently performing work, the DSP 122 can transmit data directly to the FIFOs 218 and 228 without waiting, and thus can communicate with each other regardless of speed. .

The data thus transmitted and stored in the FIFOs 218 and 228 is transferred to the line interface 300 in the form of HDLC packets through four ports SCC1, SCC2, SCC3 and SCC4 of the CPU 212 and 222 in the channel card.

The packet data is transmitted to the counterpart router through each link of the line interface 300.

In this case, packet data may be transmitted to up to 32 E1 nodes through the line interface 300, and HDLC packet data transmitted through up to 32 E1 nodes may be transmitted to one node.

As described above, since the router according to the present invention has a full redundancy structure, real time processing supporting 1: N and N: 1 is possible.

The present invention operating as described above,

By adding the FIFO to the MC68360 input of the channel card and storing the data transmitted from the DSP, the data flowing in the form of high speed HDLC packets can be analyzed in real time and transmitted to up to 32 E1 transmission nodes. HDLC packet data transmitted can be transmitted to one node.

Claims (11)

A GCIN interface 100 for converting data flowing in the form of a high-speed HDLC packet into pure data and analyzing and transmitting the data in real time; Four channel cards 200 for converting the pure data transmitted from the GCIN interface 100 into HDLC packet data; And four line interfaces (300) for connecting HDLC data transmitted from each channel card (200) with eight E1 links, respectively. The method of claim 1, And the GCIN interface, each channel card, and each line interface have a full redundancy structure. The method of claim 1, wherein the GCIN interface, An A module 110 for converting HDLC packet data received from an external data link into pure data; A B module 120 for receiving pure data from the A module and routing the received pure data to four channel card interfaces; C module 130 forming a redundant structure with the A module and And a D module (140) for controlling a VME bus for signal transmission / reception in each module. The method of claim 3, wherein the A module 110 and C module 130, A transceiver for transmitting / receiving HDLC packet data through a data link; A CPU for converting the HDLC packet data transmitted from the transceiver into pure data; A memory storing information for data conversion of the CPU; Control logic to control bus usage between the memory and the CPU; and And a buffer for controlling bus usage between the memory and the CPU. The method of claim 3, wherein the B module 120, A buffer for temporarily storing data to be transmitted to the four channel card interfaces; A DSP for analyzing and routing the data transmitted from the A module or the C module to the buffer; An address decoder for decoding an address for data analysis of the DSP; An EPROM storing information for data analysis of the DSP; An SRAM storing information for data analysis of the DSP; Control logic to control bus usage between the address decoder, EPROM, DPRAM and the DSP; And a buffer for controlling bus usage between the address decoder, EPROM, DPRAM and the DSP. The method of claim 5, The DSP uses four ports to transmit data to the buffer, and the buffers transmit data to four channel cards using one port each, the router for packet data transmission of the higher data link control protocol. The method of claim 3, wherein the D module 140, VME control logic to control the control logic in the A module, B module and C module; And a VME interface controller for controlling buffers in the A module, the B module, and the C module. The method of claim 1, wherein the channel card, It receives the pure data from the GCIN interface 100 and converts it into HDLC packet data, and has a redundancy structure. If one module is active, the other module is composed of two modules 210 which maintain a standby state. Router for packet data transmission of the higher data link control protocol The method of claim 8, wherein the module, An RS422 transceiver for transmitting the data transmitted from the CPU to the framer of the line interface 300; A CPU for converting the pure data transmitted from the GCIN interface 100 into HDLC packet data and transmitting the converted data to the transceiver; A memory for storing information for converting data in the CPU; Control logic to control bus usage between the memory and the CPU; And a buffer for controlling bus usage between the memory and the CPU. The method of claim 9, And a FIFO for compensating for the processing speed of the GCIN interface and the processing speed of the channel card between the CPU and the GCIN interface. The method of claim 9, The CPU transmits data to the transceiver using four SCC ports, and the transceiver transmits data in parallel to the line interface 300 using four ports, for packet data transmission of a higher data link control protocol. router.