KR19990025041A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents
Capacitor Manufacturing Method of Semiconductor Device Download PDFInfo
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- KR19990025041A KR19990025041A KR1019970046481A KR19970046481A KR19990025041A KR 19990025041 A KR19990025041 A KR 19990025041A KR 1019970046481 A KR1019970046481 A KR 1019970046481A KR 19970046481 A KR19970046481 A KR 19970046481A KR 19990025041 A KR19990025041 A KR 19990025041A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체장치의 캐패시터 제조방법에 관한 것으로서, 본 발명의 목적은 메모리장치의 제조공정중 정보를 저장하는 셀캐패시터의 형성과정에서 장벽층 공정을 삽입하여 콘택의 접합손실을 감소시킴으로서 리플래쉬 특성을 향상시키도록 한 반도체장치의 캐패시터 제조방법를 제공함에 있다. 상기와 같은 목적을 실현하기 위한 본 발명은 캐패시터의 하부전극을 접합시키기 위한 콘택식각을 행하는 단계와, 콘택식각후 콘택플러그주입을 행하는 단계를 포함하여 이루어진 반도체장치의 캐패시터 제조방법에 있어서, 상기 콘택식각후 장벽층을 형성하는 단계와, 콘택플러그주입후 열공정하는 단계를 더 포함하여 이루어져 콘택형성시 발생되는 손상을 큐링시킬 수 있어 캐패시터의 특성향상 및 생산수율개선에 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and an object of the present invention is to insert a barrier layer process in a process of forming a cell capacitor for storing information during a manufacturing process of a memory device, thereby reducing contact loss of a contact, thereby reducing refresh characteristics The present invention provides a method for manufacturing a capacitor of a semiconductor device. According to an aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, comprising: performing contact etching for bonding a lower electrode of a capacitor; and performing contact plug injection after contact etching. The method may further include forming a barrier layer after etching and thermally processing the contact plug after injection, thereby quenching damage generated during contact formation, thereby improving the characteristics of the capacitor and improving the production yield.
Description
본 발명은 반도체장치의 캐패시터 제조방법에 관한 것으로서, 보다 상세하게는 메모리제조공정중 정보를 저장하는 셀캐패시터의 형성과정에서 장벽층형성 공정을 삽입하여 콘택의 접합손실을 감소시킴으로서 리플래쉬 특성을 향상시키도록 한 반도체장치의 캐패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and more particularly, to improve refresh characteristics by inserting a barrier layer forming process in the process of forming a cell capacitor for storing information during a memory manufacturing process, thereby reducing contact loss of a contact. The present invention relates to a method for manufacturing a capacitor of a semiconductor device.
메모리장치는 컴퓨터, 통신시스템, 화상처리시스템등에 사용되는 데이타나 명령어등을 일시적으로 또는 영구적으로 저장하기 위해 사용되는 총칭으로서 반도체, 데이프, 디스크, 광방식 등이 있는데 현재 반도체 메모리가 많은 비중을 차지하고 있다.Memory device is a general term used to temporarily or permanently store data or instructions used in computers, communication systems, image processing systems, etc. There are semiconductors, tapes, disks, and optical methods. have.
이러한 반도체 메모리장치도 데이타의 저장방식의 전기적인 특성에 따라 DRAM, SRAM, Flash 메모리, ROM 등으로 구분된다. 이중 전체 반도체메모리 시장의 대부분을 차지하고 있는 DRAM(Dynamic Random Access Memory)의 특징은 랜덤억세스가 가능하고 전기적으로 데이타의 읽기와 쓰기가 가능하며 특히 쓰기의 횟수에 제한이 없으며, 전원 공급이 중단되면 기억중인 데이타가 소실되는 휘발성 메모리이며, 주기적으로 리플레쉬(Refresh)가 필요하며, 리스토어동작을 만족시키기 위해 매 ROW사이클 동작마다 프리차지(Precharge)시간이 필요하다는 특징이있다.Such semiconductor memory devices are also classified into DRAM, SRAM, Flash memory, and ROM according to the electrical characteristics of the data storage method. The characteristic of the DRAM (Dynamic Random Access Memory), which occupies most of the entire semiconductor memory market, is that random access is possible, and data can be read and written electrically. In particular, there is no limit on the number of writes. It is a volatile memory that loses existing data. It needs periodic refresh, and precharge time is required for every ROW cycle operation to satisfy the restore operation.
메모리장치를 구성하는 소자로는 트랜지스터 및 캐패시터등으로 구성되는데 개패시터의 경우에는 적은 면적에도 불구하고 정전용량이 증가되어야 하며 캐패시터의 리플레쉬특성을 향상시키기 위한 리키지의 감소문제가 있다.The device constituting the memory device is composed of a transistor, a capacitor, and the like. In the case of a capacitor, the capacitance has to be increased despite a small area, and there is a problem of reducing the package to improve the refresh characteristics of the capacitor.
도1은 일반적인 반도체장치의 캐패시터 제조방법에 의해 형성된 메모리장치의 셀캐패시터의 하부전극부분을 나타낸 단면도이다.1 is a cross-sectional view showing a lower electrode portion of a cell capacitor of a memory device formed by a capacitor manufacturing method of a general semiconductor device.
도1은 기판(10)위에 형성된 트랜지스터(20)의 소오스/드레인(22)에 캐패시터의 하부전극(40)을 접합시키기 위해 BPSG(Boro Phospho Silicate Glass)층(25)위에 콘택마스크를 형성하여 콘택식각한후 콘택의 접합저항을 감소시키기위한 이온주입을 실행한후 콘택 스페이서(30)와 하부전극(40)을 증착한 상태를 나타낸 단면도이다.1 shows a contact mask formed on a BOSG (Boro Phospho Silicate Glass) layer 25 to bond a lower electrode 40 of a capacitor to a source / drain 22 of a transistor 20 formed on a substrate 10. A cross-sectional view showing a state in which the contact spacer 30 and the lower electrode 40 are deposited after etching after ion implantation is performed to reduce the junction resistance of the contact.
일반적인 캐패시터의 셀구조는 스택(Stack)이나 핀(Fin) 또는 실린더(Cylinder)등의 구조로 이루어져 도1에서 보는 바와 같이 셀캐패시터의 노드로써 n-가 p기판위에 형성하는 접촉접합을 주로 사용하고 있다.The cell structure of a general capacitor is composed of a stack, a fin, a cylinder, or the like, and as shown in FIG. 1, a contact junction formed by n- on a p substrate is mainly used as a node of a cell capacitor. have.
셀캐패시터에 저장되는 정보의 손실은 주로 이 접촉접합을 통하여 발생하게 되는데 하부전극(40)을 형성하기 위해 콘택식각하고 그위에 이온을 주입시키면서 물리적인 충격에 의한 손상으로 'A'와 같은 손상이 발생하여 이곳으로 접합손실이 발생된다. 이 손실은 DRAM의 경우에는 리플래쉬특성에 큰 영향을 준다는 문제점이 있다.The loss of information stored in the cell capacitor is mainly generated through this contact junction. The damage such as 'A' is caused by damage due to physical impact while contact etching and implanting ions thereon to form the lower electrode 40. Occurs and there is a loss of junction. This loss has a problem in that it greatly affects the refresh characteristics in the case of DRAM.
또한 이온주입에 의한 물리적 충격으로 손상된 기판(10)을 큐링(Curing)하는 공정으로 고온에서 어닐링을 수행하는데 일반적인 방법에서는 하부전극(40)이 완성된 뒤에 행하기 때문에 충분한 큐링이 이루어지지 않는다는 문제점이 있다.In addition, in the general method, the annealing is performed at a high temperature by a process of curing the substrate 10 damaged by the physical impact caused by ion implantation. have.
본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은 반도체장치의 캐패시터 제조공정시 캐패시터의 하부전극을 위한 콘택식각에 의한 손상과 콘택저항을 감소시키기 위한 이온주입공정시의 손상을 줄이기 위해 콘택식각후 산화막을 형성하고 이온주입후 열공정을 추가하여 손상으로 인한 접합누설의 발생을 줄이도록 하는 반도체장치의 캐패시터 제조방법을 제공함에 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to reduce damage caused by contact etching for a lower electrode of a capacitor and a contact resistance during a capacitor manufacturing process of a semiconductor device. The present invention provides a method of manufacturing a capacitor of a semiconductor device that forms an oxide film after contact etching to reduce damage and adds a thermal process after ion implantation to reduce the occurrence of junction leakage due to damage.
도1은 일반적인 방법에 의한 반도체장치의 캐패시터 제조공정중 캐패시터의 하부전극의 접합을 위한 콘택형성공정을 나타낸 단면도이다.1 is a cross-sectional view illustrating a contact forming process for bonding a lower electrode of a capacitor during a capacitor manufacturing process of a semiconductor device according to a general method.
도2 내지 도3은 본 발명에 의한 방법으로 반도체장치의 캐패시터 제조공정중 캐패시터의 하부전극의 접합을 위한 콘택형성공정을 나타낸 단면도이다.2 to 3 are cross-sectional views illustrating a contact forming process for joining a lower electrode of a capacitor during a capacitor manufacturing process of a semiconductor device by the method of the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
10 : 기판 30 : 스페이서10: substrate 30: spacer
40 : 하부전극 50 : 장벽층40: lower electrode 50: barrier layer
상기와 같은 목적을 실현하기 위한 본 발명은 캐패시터의 하부전극을 접합시키기 위한 콘택식각을 행하는 단계와, 콘택식각후 콘택플러그 이온주입을 행하는 단계를 포함하여 이루어진 반도체장치의 캐패시터 제조방법에 있어서, 상기 콘택식각후 장벽층을 형성하는 단계와, 콘택플러그 이온주입후 열공정하는 단계를 더 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, comprising: performing contact etching for bonding a lower electrode of a capacitor; and performing contact plug ion implantation after contact etching. And forming a barrier layer after contact etching and thermally processing the contact plug after ion implantation.
상기와 같은 방법에 의하여 제조된 캐패시터는 콘택식각에 의한 손상과 장벽층에 의해 이온주입시 발생되는 손상을 방지할 수 있고 열공정을 통해 손상된 기판을 큐링시킬 수 있어 캐패시터에 저장된 전하의 손실을 방지하여 리플래쉬의 특성을 향상시킬 수 있게 된다.The capacitor manufactured by the above method can prevent damage caused by contact etching and damage caused by ion implantation by the barrier layer and can cure the damaged substrate through the thermal process, thereby preventing the loss of charge stored in the capacitor. It is possible to improve the characteristics of the refresh.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.
도2 내지 도3은 본 발명의 방법에 따라 종래의 방법에 추가되는 공정을 단계적으로 나타낸 단면도이다.2 to 3 are cross-sectional views showing steps added to a conventional method in accordance with the method of the present invention.
도2는 기판(10)위에 형성된 캐패시터의 하부전극(40)부분을 나타낸 것으로서 기판(10)에 격리산화막(15)을 형성하고 트랜지스터(20)를 형성한후 BPSG층(25)을 증착한 다음 캐패시터를 형성하기 위해 트랜지스터(20)의 소오스/드레인(22) 영역에 콘택홀을 형성한 다음 장벽층(50)을 형성한 상태를 나타낸 단면도이다.2 shows a portion of the lower electrode 40 of the capacitor formed on the substrate 10. The isolation oxide layer 15 is formed on the substrate 10, the transistor 20 is formed, and the BPSG layer 25 is deposited. A cross-sectional view showing a state in which a contact hole is formed in a source / drain 22 region of the transistor 20 and then a barrier layer 50 is formed to form a capacitor.
장벽층(50)은 산화공정으로 50Å정도의 두께로 형성된 산화막층이다.The barrier layer 50 is an oxide film layer formed to a thickness of about 50 kV by an oxidation process.
도3은 도2의 결과물에 접촉저항을 줄이기 위한 이온주입공정으로 인(PHOSPHORUS 31)이 주입된 상태를 나타낸 단면도이다.FIG. 3 is a cross-sectional view illustrating a state in which phosphorus (PHOSPHORUS 31) is injected into an ion implantation process to reduce contact resistance to the resultant of FIG. 2.
그런다음 900℃의 질소분위기에서 약 30분동안 열공정을 통해 콘택식각시 발생된 손상과 이온주입시 발생된 손상을 큐링시킨다.Then, heat treatment for about 30 minutes in a nitrogen atmosphere at 900 ℃ to quench the damage caused by contact etching and the damage caused by ion implantation.
이후 공정은 종래의 반도체장치의 캐패시터 제조방법과 동일하게 진행된다. 본 실시예에서는 콘택형성시와 이온주입시 발생되는 손상을 큐링하고 다음 공정을 진행하기 때문에 접합손실을 줄일 수 있게된다.Thereafter, the process proceeds in the same manner as the capacitor manufacturing method of the conventional semiconductor device. In this embodiment, since the damage generated at the time of contact formation and ion implantation is cured and the next process is performed, the bonding loss can be reduced.
상기한 바와 같이 본 발명은 반도체장치에서 캐패시터의 하부전극을 접촉시키기 위한 콘택형성시 콘택식각과 접합저항을 줄이기 위한 이온주입시 발생되는 손상을 줄이기 위해 콘택형성후 장벽층을 형성하고 이온주입후 열공정을 통해 발생된 손상을 큐링시킴으로서 접합손실을 줄일수 있어 캐패시터의 리플래쉬 특성을 향상시켜 생산수율의 개선 및 제품의 수명은 연장시킬 수 있다는 이점이 있다.As described above, the present invention forms a barrier layer after forming a contact to reduce damage generated during ion implantation to reduce contact etching and bonding resistance when forming a contact for contacting a lower electrode of a capacitor in a semiconductor device, and heat after ion implantation. By curing the damage caused by the process, it is possible to reduce the bonding loss, thereby improving the refresh characteristics of the capacitor, thereby improving production yield and extending the life of the product.
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| US10872964B2 (en) | 2016-06-17 | 2020-12-22 | Acorn Semi, Llc | MIS contact structure with metal oxide conductor |
| US10879366B2 (en) | 2011-11-23 | 2020-12-29 | Acorn Semi, Llc | Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers |
| US10937880B2 (en) | 2002-08-12 | 2021-03-02 | Acorn Semi, Llc | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
| US11043571B2 (en) | 2002-08-12 | 2021-06-22 | Acorn Semi, Llc | Insulated gate field effect transistor having passivated schottky barriers to the channel |
-
1997
- 1997-09-10 KR KR1019970046481A patent/KR19990025041A/en not_active Application Discontinuation
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| US11043571B2 (en) | 2002-08-12 | 2021-06-22 | Acorn Semi, Llc | Insulated gate field effect transistor having passivated schottky barriers to the channel |
| US10937880B2 (en) | 2002-08-12 | 2021-03-02 | Acorn Semi, Llc | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
| US10950707B2 (en) | 2002-08-12 | 2021-03-16 | Acorn Semi, Llc | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
| US11018237B2 (en) | 2002-08-12 | 2021-05-25 | Acorn Semi, Llc | Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
| US11056569B2 (en) | 2002-08-12 | 2021-07-06 | Acorn Semi, Llc | Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
| US11355613B2 (en) | 2002-08-12 | 2022-06-07 | Acorn Semi, Llc | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
| US10879366B2 (en) | 2011-11-23 | 2020-12-29 | Acorn Semi, Llc | Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers |
| US11610974B2 (en) | 2011-11-23 | 2023-03-21 | Acorn Semi, Llc | Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers |
| US11804533B2 (en) | 2011-11-23 | 2023-10-31 | Acorn Semi, Llc | Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers |
| US10872964B2 (en) | 2016-06-17 | 2020-12-22 | Acorn Semi, Llc | MIS contact structure with metal oxide conductor |
| US11843040B2 (en) | 2016-06-17 | 2023-12-12 | Acorn Semi, Llc | MIS contact structure with metal oxide conductor |
| US10833199B2 (en) | 2016-11-18 | 2020-11-10 | Acorn Semi, Llc | Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height |
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