KR19990024309A - Multiprocessor device with distributed shared memory structure - Google Patents

Abstract

The present invention relates to a multiprocessor device of a distributed shared memory structure including a snooping ring bus, and includes a plurality of processor nodes 500A to 500H having a distributed shared memory structure arranged in a ring shape. The processor node group which generates a request signal for requesting data from the predetermined processor node 500A, and outputs data corresponding to the request signal by snooping inside the other processor nodes 500B to 500H having received the request signal. ; A path connecting the plurality of processor nodes 500A to 500H in a ring shape so that the request signal and data corresponding to the request signal are circulated through the processor nodes to be delivered to the generated processor node 500A. It characterized in that it comprises a ring bus 510 to provide.

Description

Multiprocessor device with distributed shared memory structure

The present invention relates to a multiprocessor device of a distributed shared memory structure and a control method thereof, and more particularly, to a multiprocessor device of a distributed shared memory structure including a snooping ring bus and a control method thereof.

In general, large shared memory multiprocessor systems with a single address space and cache that maintain coherence provide a flexible and powerful computing environment. In other words, two elements of the cache that are consistent with a single address space ease data partitioning and dynamic load balancing issues, and provide a better environment for parallel compilers, standard operating systems, and multiprogramming. Thus, it is possible to use a more fluid and effective machine.

Such a shared memory multiprocessor system may include a uniform memory access (UMA) multiprocessor as shown in FIG. 1 and a non-uniform memory access (NUMA) as shown in FIG. 2 according to a method of accessing shared memory. It can be classified as distributed shared memory multiprocessor. Referring to FIG. 1, in multiple processors, local caches 12, 12 ′ provide a much faster access time with less capacity than shared memory 30, 30 ′, and processors 11, 11 ′ frequently. By storing data blocks of shared memory 30, 30 'that are expected to be used, the number of access requests to shared bus 32 and shared memory 30, 30' is reduced, resulting in faster memory access times. Can provide. However, the use of the cache, for example, if the processor 11 in one processor module 10 performs a write operation on a block of data stored in its local cache 12, the result of the write operation is A so-called cache coherence problem arises that must be reflected in the corresponding data blocks stored in the local cache 12 'in another processor module 10', which is common in bus-based shared memory multiprocessors. The cache coherence method of the snooping scheme is widely used.

As shown in FIG. 1, the even memory access multiprocessor has shared memory 30, 30 'equally accessed by all processors 11, 11' of the system, and this shared memory 30, 30 Scalability due to increased bus access delay time due to increased traffic of the system bus 32 connected to '), increased access latency of shared memory, and system performance limitation due to memory bandwidth. ) And barriers to performance improvement. As a form of overcoming this problem, a widely used distributed shared memory multiprocessor may be configured by distributing shared memory 30, 30 'close to each processor 11, 11' as shown in FIG. Compared to accessing the shared memory 30 'and 30 near the processors 11' and 11, the access time of the shared memory 30 and 30 'near the processor is shorter, so that the memory in which the instruction or data to be accessed is stored. Depending on the location of the memory access time will vary. Therefore, the distributed shared memory multiprocessor can increase the number of accesses of the local shared memory as much as possible to mitigate the traffic on the system bus 32, improve the system performance by expanding the memory bandwidth of the whole system and reducing the memory access delay. have.

The multiprocessor system is configured by connecting system resources such as multiple processors and memory through an interconnection network. Due to the complexity and cost of the interconnection network connecting processor modules in a multiprocessor system, In small commercial systems, buses are preferred, as shown in FIGS. Such a bus structure system has a problem of scalability due to the physical characteristics of the bus and a problem of bus bandwidth due to an increase in bus usage. This limitation is a serious obstacle to the transfer of large amounts of data as computers become more computationally powerful. In order to overcome this limitation, the method of increasing the bus width does not show the effect of real bandwidth improvement due to the fixed overhead required for bus arbitration or addressing. In order to reduce overhead, increasing the size of the line transfer has little effect when the size of the cache line is exceeded. By shortening the bus length, the signal cycle can be made faster, but there is a problem of signal noise, and the method of having a plurality of buses is complicated to control and difficult to maintain cache coherency.

As a way of overcoming the limitations of the bus structure, we can think of an interconnection network composed of high-speed point-to-point links.The interconnection networks include Mesh, Torus, Hypercubes, N-cube, Various structures such as MIN, omega network and ring can be considered. The ring structure is simpler to design and implement than other structures, and the bus can transmit each transaction sequentially, but the ring can increase bandwidth by allowing multiple transactions to be sent at the same time.

3 illustrates a distributed shared memory multiprocessor system configured as a unidirectional ring that maintains cache coherency in a directory manner. In FIG. 3, when a cache read miss occurs in the first processor node 40, the first processor node 40 sends a request for the data block to a home corresponding to the original memory area of the data block. A single transmission to the processor node 41, and if the data block is stored in an updated state in the cache of the second processor node 42, then the home processor node 41 again sends a request for that block to the second. A single transmission to processor node 42 is made.

Therefore, the second processor node 42 transmits the requested data block to the home processor node 41 in a single transmission, and the home processor node 41 updates the memory and then sends the requested block again to the first processor node. 40).

As described above, the distributed shared memory multiprocessor system configured as a unidirectional ring that maintains cache coherency in a directory method has a problem in that ring utilization is relatively high and delay is increased because a transaction for maintaining cache coherency must be generated.

Accordingly, an object of the present invention is to provide a multi-processor system with a distributed shared memory structure that can maintain cache coherency in a snooping manner, thereby reducing ring utilization and delay.

The present invention is a plurality of processor nodes having a distributed shared memory structure, arranged in a ring to achieve the above object, and generates a request signal for requesting data at the predetermined processor node, the other receiving the request signal A processor node group that snoops inside and outputs data corresponding to a request signal; And a ring bus connecting the plurality of processor nodes in a ring shape to provide a path through which the request signal and data corresponding to the request signal are traversed through each of the processor nodes and delivered to the processor node that generated the request signal. It is characterized by the configuration.

1 is a schematic block diagram of an even memory access shared memory multiprocessor in a general bus structure;

2 is a schematic structural diagram of a non-uniform memory access shared memory multiprocessor system of a general bus structure;

3 is a configuration diagram of a distributed shared memory multiprocessor system having a ring structure using a conventional directory method;

4 is an overall configuration diagram illustrating an embodiment of a distributed shared memory multiprocessor device including a snooping ringbus according to the present invention;

5 is a view for explaining an operation of an embodiment of the present invention based on FIG. 4;

6 is a diagram illustrating an operation of a processor node observing a snooping request in a different order in a ring bus structure;

7 is a block diagram illustrating another embodiment of a distributed shared memory multiprocessor device including the snooping ringbus of the present invention;

8, 9, and 10 illustrate a modified structure of a distributed shared memory multiprocessor including a ringbus of snooping according to an embodiment of the present invention.

<Description of the code | symbol about the principal part of drawing>

100A, 100B: Processor module 110A, 110B: Processor

120A, 120B: Local Cache 140: Local System Bus

150: node controller 160: ring interface

170: remote cache 172A, 172B: remote tag cache

176: remote data cache 180: I / O bridge

190: pending buffer 300: local shared memory section

310: data memory 320A, 320B: memory directory

320: system bus 500A to 500H: processor node

510: ring bus 600: interconnection network

Hereinafter, with reference to the accompanying drawings, the present invention will be described in detail.

4 illustrates a multiprocessor system of distributed shared memory architecture coupled to a unidirectional ring (hereinafter referred to as a ring bus) that supports snooping in accordance with one embodiment of the present invention.

In FIG. 4, each processor node 500A-500H is connected to a unidirectional point-to-point ring bus 510 that supports snooping. In addition, each processor node 500A to 500H includes a processor 110, a plurality of processor modules 100A and 100B including a local cache 120, a local shared memory unit 300, and an I / O bridge 180. , Ring interface 160, node controller 150, and remote cache 170, including processor modules 100A, 100B, I / O bridge 180, and node controller 150. ) Is connected via a local system bus 140.

Herein, the node controller 150 includes an instruction or data block corresponding to a data request signal from the processor modules 100A and 100B of the processor node 500A in the remote cache 170 or the region within the processor node 500A. Search whether the data is stored in the shared memory unit 300 in a valid state, and if the data is stored in the valid state, the data block is provided to the processor modules 100A and 100B, but the remote cache 170 or the local shared memory unit is provided. If it is not stored in a valid state (300), and serves to transmit the request signal to the other processor nodes (500B to 500H) through the ring interface 160. In addition, when a request signal is input from other processor nodes 500B to 500H through the ring interface 160, the node controller 150 stores a data block corresponding to the request signal in its remote cache 170 or the local shared memory unit. If it is stored in the valid state, and if it is stored in the valid state, the valid data is transmitted to the other processor nodes 500B to 500H generating the request signal through the ring interface 160.

The ring interface 160 acts as a data path that connects the processor node 500A to the ring bus 510 so that a request signal or data block from the node controller 150 can be transferred via the ring bus 510. It transmits to the processor nodes 500B to 500H and selects and transmits a request signal or data block transmitted from another processor node 500B to 500H through the ring bus 510 to the node controller 150 as well. If the incoming signal is a broadcast packet, it is responsible for bypassing the other processor node 500B and all flow control necessary for packet transmission.

The remote cache 170 in the processor node 500A is a cache that caches only data blocks stored in the shared memory portion of the other processor nodes 500B to 500H, that is, the remote shared memory portion. The local system bus 140 In the case of a reference failure for a remote shared memory address region reference transaction from the processor modules 100A and 100B connected to the corresponding module, the corresponding data block is allocated to the remote cache 170, and the block in the region shared memory 300 region is Do not cache.

The remote cache 170 of the processor node 500A can be configured to operate relatively small and fast by caching only the remote shared memory portion within the other processor nodes 500B to 500H and the local bus 140 due to the replacement of the data block. This has the effect of reducing traffic to.

The remote cache 170 applies the MLI property (Multi-Level Inclusion Property) to the local cache 120 in the processor node 500A and the memory area of the remote local shared memory portion in the other processor nodes 500B to 500H. As it satisfies, it has the function of snoop filtering on the remote memory reference request signal from other processor nodes 500B to 500H. In this case, the MLI property means that the data block stored in the lower layer cache must always be stored in the upper cache. For this purpose, if the upper level cache line is replaced, the line should not exist in any lower cache. Should be ensured.

Thus, the remote cache 170 stores the remote data blocks stored in the local caches 120 of the processor node 500A, and responds to remote memory reference request signals from other processor nodes 500B through 500H. If the data block is not stored in the remote cache 170 in a valid state, the local system bus 140 is responsible for the snooping filtering function that does not need to send a request for the data block.

In this case, the remote cache 170 preferably stores the contents of the data block as shown in FIG. 4, and the remote tag cache 172 stores a part of the state and address of the data block. In this case, the data block stored in the remote data cache 176 can be updated, or a corresponding data block can be provided if necessary.

More preferably, a processor connected via a local system bus 140 is configured by configuring two independent remote tag caches 172A and 172B, which comprise an address for a remote data block and a remote data cache 172 that stores this state. The remote cache 170 access request from 110A and 110B and the remote cache 170 access request from neighboring processor nodes 500B to 500H through the ring interface 160 may be processed in parallel.

Here, the data block of the remote cache 170 may be represented in the following four states, namely 'update', 'update-share', 'share', and 'invalid' state.

* Update: The data block is valid, updated in the remote cache, and the only valid copy.

Update-Shared: The data block is valid and updated in the remote cache, and another remote cache is sharing the data block.

* Share: The data block is valid and another remote cache may be sharing the data block.

* Invalid: The data block is invalid.

In addition, the shared memory unit 300 includes a data memory 310 that stores the contents of the data block, and a memory directory 320 that stores the state of the data block stored in the data memory 310. Local shared memory reference request signals from processors 110A and 110B connected through 140 and local shared memory reference requests from other processor nodes 500B to 500H transmitted via ring interface 160 in parallel. The memory directory 320 is composed of two independent memory directories 320A and 320B for processing.

Here, the memory directory 320A for minimizing cache coherency traffic for local shared memory reference requests sent over local system bus 140 and reducing unnecessary transactions to the ring bus is provided from local system bus 140. Maintain six states: EXL, LS, RS, LRS, STALE, and GONE to handle the request.

* EXL: Memory initial state

* LS: It may be stored as read only in the local cache of the processor node of the corresponding block data.

* RS: The block data may be stored as read only in the remote cache of another processor node.

* LRS: The block data may be stored as read only in the local cache of the processor node and the remote cache of another processor node.

* GONE: The block data is stored in a valid state changed in the remote cache of another processor node.

* STABLE: The block data is stored in the valid state changed in the local cache of the processor node.

Meanwhile, memory directory 320B maintains three states of GN, EX, and NE to generate snooping results for snooping requests from the ring bus, where GN is GONE and EX is EXL, LS, STALE. NE is a state encompassing RS and LRS.

On the other hand, all communication on the unidirectional point-to-point ring bus 510 connecting each processor node 500A to 500H is via a packet, the packets being a request packet corresponding to the request signal, a response packet corresponding to the response signal, and recognition. It can be classified into a recognition packet corresponding to the signal. A request packet is a packet sent by a processor node that requires a transaction to a ring bus. The request packet may be divided into a broadcasting packet and a unicasting packet, and only the broadcast packet is snooped by other processor nodes. do.

A response packet is always sent in a single packet generated by the responding processor node that receives the request packet in response to the request, and an acknowledgment packet is generated by the receiving processor node in recognition of the single transmission packet and sent to the sending processor node in a single transmission. . After transmitting a single packet, the processor node maintains the information on the transport packet until the acknowledgment packet arrives. After confirming the response, the processor node checks the response information and retries as necessary.

Here, in more detail, the broadcast packets in the request packet include MRFR (Memory Read For Read), MRFW (Memory Read For Write), MINV (Memory Invalidate), MPRG (Memory Purge), MCASTOUT (Memory Castout), There is a MFLSH (Momery Flush), and a single transport packet includes a memory writeback exclusive (MWBE), a memory writeback shared (MWBS), and a memory reply (MRPLY). Among the broadcast request packets, MRFR, MRFW, and MINV are request signals for a memory area of a remote shared memory part in other processor nodes 500B to 500H, and MPRG, MCASTOUT, and MFLSH are memories of a local shared memory part in their processor node. This is a request signal sent by the processor node for the zone.

① MRFR

A request sent to the cache block as a packet sent when a read reference failure in the remote cache for a read request from a processor within a processor node.

② MRFW

A packet sent when the remote cache fails to write a reference to a write request from a processor within a processor node. A request to read and invalidate a cache block.

③ MINV

Invalidation request packet sent when the remote cache is shared for a write or invalidation request from a processor within a processor node

④ MPRG

Invalidation request packet sent when the state of local shared memory is valid for a write or invalidation request from a processor within a processor node to a local shared memory area and the block is cached in the remote cache of another processor node.

⑤ MCASTOUT

Another processor node is caching the block in a modified state (for example, 'update' or 'update-shared' state) for a write or invalidate request from the processor within the processor node to a local shared memory area. Outgoing Read and Invalidate Request Packets

⑥ MFLSH

For a read request to a local shared memory region from a processor within a processor node, another processor node is dispatching the block to the remote cache if it is modified (for example, 'update' or 'update-shared' state). Flush request packet

⑦ MWBE, MWBS

Rewrite packet to the processor node corresponding to the memory area of the block to be replaced due to block replacement of the remote cache. Sends MWBE when the status of the remote cache is 'update' and MWBS when the status is 'update-shared'.

⑧ MRPLY

Data provision response transaction for request packet

5 shows an example of operation for a distributed shared memory multiprocessor of the ring bus structure of the present invention configured as described above.

In FIG. 5, for a memory reference request from one processor 110 of processor node 500A, if processor node 500A cannot process the request packet within itself, i.e., instructions or data corresponding to the request packet are generated. If the included block is not stored in the remote cache 170 or the local shared memory 300 in a valid state, the processor 500A may pass the MRFR or MFLSH to the other processor nodes 500B to 500H via the ring bus 510. Broadcast the request packet.

Accordingly, the request packet is sequentially traversed from the processor node 500B to the processor node 500H along the ring bus 510, and while the request packet traverses the ring bus 510, each processor node 500B to 500H. ) Checks the internal remote tag cache or memory directory for this request packet, snoops about how the data block is stored, and bypasses the request packet to an adjacent neighboring processor node. .

For example, as a result of snooping inside the processor node 500D, the data block is stored in the remote cache in a modified state (eg, 'update' or 'update-sharing' state) There is no processor node that stores the block in the local shared memory in a valid state). If the data block is stored in the local shared memory in a valid state, the processor node 500D is responsible for responding to the request packet. And a response packet including the requested data block is transmitted to the processor node 500A which generated the request packet.

At this time, the preceding broadcast request packet is removed by the processor node 500A after iterating through the ring bus 510. On the other hand, when the processor node 500A receives the response packet from the processor node 500D, the processor node 500A transmits a single acknowledgment packet back to the processor node 500D, and the request is made through the local system bus 140 of the processor node 500A. The data block is transmitted to the processor 110 that generates the data block. When the data block corresponding to the request signal corresponds to the memory area of the remote shared memory unit, the data block is stored in the remote cache 170 in a valid state. When the data block corresponding to the request signal corresponds to the memory area of the local shared memory unit 300, The data is stored in the local shared memory unit 300 in a valid state.

The processor node 500A is not storing the data block in the remote cache 170 or the local shared memory 300 in a valid state for a memory write reference request from one processor 110 of the processor node 500A. In turn, processor node 500A broadcasts an MRFW or MCASTOUT request packet to ring processor buses to neighboring processor nodes 500B to 500H. While the request packet traverses the ring bus, each processor node 500B-500H examines the remote tag cache or the memory directory of the local shared memory for this request packet and snoops on how the data block is stored, etc. At the same time, it bypasses the request packet to an adjacent neighboring processor node.

For example, as a result of snooping inside the processor node 500D, the data block is stored in the remote cache in a modified state (eg, 'update' or 'update-sharing' state) There is no processor node that stores the block in the local shared memory in a valid state). If the data block is stored in the local shared memory in a valid state, the processor node 500D is responsible for the response of the request packet. Determining responsibility, it transmits a single response packet containing the requested data block to the processor node 500A that generated the request while invalidating the state of the remote cache storing the data block (e.g., Invalid ') or invalidate the state of the memory directory of the local shared memory where the data block is being stored (for example, the GN state). Updates. In this case, the preceding broadcast request packet is removed by the processor node 500A after iterating through the ring bus, and as a result of snooping, the corresponding data block is stored in the remote cache in a valid unmodified state (for example, a 'shared' state). The processor node changes the remote cache state of the block to an invalidated state (eg, an 'invalid' state).

When the processor node 500A receives the response packet from the processor node 500D, the processor node transmits a single acknowledgment packet to the processor node 500D, and simultaneously generates the request signal through the local system bus 140 of the processor node 500A. The data block is transmitted to 110. In addition, if the requested data block corresponds to a memory area of the remote shared memory unit, the block is stored in the remote cache 170 in a modified valid state (for example, an 'update' state). The data is stored in the local shared memory unit 300 in a valid state.

For a memory write reference request or invalidation request from one processor 110 of the processor node 500A, the processor node 500A stores the block in a valid state in the remote cache 170 or the local shared memory unit 300. And the block is stored in a valid state (eg, 'shared' or 'update-shared') in the remote cache of another processor node, the processor node 500A is the neighboring processor nodes 500B to 500H. The MINV or MPRG request packet is broadcast through the low ring bus 510. While the request packet traverses the ring, each processor node 500B-500H examines the internal remote tag cache or memory directory for this request packet, while snooping on how the data block is stored, and so on. Bypass the request packet to an adjacent neighbor processor node. For example, a processor that has been snooped internally by the processor node 500D and the data block is stored in the remote cache as 'update-shared' (in this case, the processor is valid in local shared memory). Node does not exist), if the corresponding data block is stored in the local shared memory in a valid state, it is determined that it is responsible for the response to the request packet, and thus the processor node 500D responds to the invalidation request. Sends the request packet to the processor node 500A that generated the request packet, and at the same time makes the state of the remote cache storing the data block invalidated (e.g., 'invalid') or the area storing the data block. The state of the memory directory of the shared memory unit is updated to an invalidated state (for example, the GN state).

In this case, the preceding broadcast request packet is removed by the processor node 500A after iterating through the ring bus, and as a result of snooping, the corresponding data block is stored in the remote cache in a valid unmodified state (for example, a 'shared' state). The processor node changes the remote cache state of the data block to an invalidated state (eg, an 'invalid' state). When the processor node 500A receives the response packet from the processor node 500D, the processor node 500A transmits a single recognition packet to the processor node 500D.

In addition, if the state of the data block to be evicted due to data block replacement in the remote cache 170 of the processor node 500A is in a modified state (eg, an 'update' or 'update-shared' state), the processor Node 500A transmits a single MWBE or MWBS request packet over ring bus 510 to a processor node, for example processor node 500D, having a shared memory area where the data block to be evicted should originally be stored. .

Processor node 500D then updates its data memory and memory directory for that request packet, and transmits a single response packet to the data block eviction request to processor node 500A that generated the request packet. When the processor node 500A receives the response packet from the processor node 500D, the processor node 500A transmits a single recognition packet back to the processor node 500D.

Meanwhile, in a distributed shared memory multiprocessor device connected by a ring bus according to the present invention, each processor node may observe each packet in a different order unlike a conventional bus.

For example, referring to FIG. 6, when the processor node 500A generates the first request packet R1 and the processor node 500C generates the second request packet R2, the processor node 500B generates the first request packet R1. While observing a snooping request packet in the order of one request packet R1 → a second request packet R2, the processor node 500H snoops in the order of the second request packet R2 → the first request packet R1. Observe the request packet. Therefore, from the standpoint of the processor node participating in snooping, the snooping order and the service order in which the corresponding broadcast request is processed are irrelevant, and the processor node participating in each snooping decides the state transition using only its own local information. The service order for a plurality of request packets for the same address is the processor node responsible for processing the request (hereinafter referred to as the processor node with ownership, and there can be only one). That is, the requested data block is placed in the remote cache. Request packets arrive at processor nodes that have been saved in a modified valid state (for example, 'update' or 'update-shared'), or at processor nodes that have stored the requested data blocks in local shared memory. Defined in order. Therefore, every processor node that sends a request over the ring bus receives a response packet or a retry packet by an owner of the processor node. The processor node with ownership transfers the requested block through the MRPLY packet or sends an acknowledgment for the invalidation request to the processor node for MRFR, MRFW, MINV, MFLSH, MCASTOUT, MPRG request packets, etc. from another processor node. If the processor receives the request for the same block from another processor node before receiving the acknowledgment packet from the processor node receiving the packet, the packet is transmitted to the processor node, which means to retry.

Therefore, in another embodiment of the present invention, as shown in Figure 7, in addition to the memory directory (320A, 320B) for the local shared memory unit 300 and the remote tag cache (172A, 172B) for the remote cache 170, It further includes a pending buffer (190) for storing information on the data block request that has transmitted the MRPLY packet but has not yet received the recognition packet, when performing the snooping, the memory directory for the local shared memory unit 300 Refers to the pending buffer 190 as well as the remote tag cache 172B for the 320B and the remote cache 170, and a packet which means to retry when a request for a block stored in the pending buffer 190 occurs. Send it.

In the description of the embodiment of the present invention, a case in which MRFR, MRFW, and MINV are divided into requests for a remote shared memory area and MFLSH, MCASTOUT, and MPRG are divided into requests for a local shared memory area among broadcast request packets has been described. The present invention can be equally applied to the case where the two cases are combined, that is, MRFR and MFLSH, MRFW and MCASTOUT, MINV and MPRG, respectively, in the same request. Although we have described the case where it is separated into two parts, it should be understood that the same can be applied when two requests are treated as the same request.

In addition, in the embodiment of the present invention, the case in which the remote cache has a 'update' and 'update-share', 'share', 'invalid', the present invention has been described in other states that the remote cache is modified, that is, The same may be applied to various cases including 'update', 'shared', and 'invalid', or 'update', 'shared', 'exculsive', and 'invalid'. In the embodiment of the present invention, a case in which two directories for independently accessed local shared memories maintain EXL, LS, RS, LRS, GONE, STALE states and GN, EX, NE states, respectively, is described. It is to be understood that the same applies to a directory in which it has a variety of different states.

In the description of the embodiment of the present invention, the case in which all the processor nodes use a plurality of processors, a cache and an I / O system, and a single system bus has been described. However, some processor nodes may include one or more processors as shown in FIG. When only the processor and the cache are included, or when the local node includes only the local shared memory module as shown in FIG. 9, when the processor node includes the hierarchical bus of any stage, the plurality of ring buses are illustrated as shown in FIG. 10. Obviously, the present invention can be equally applied when connected and transmitted in both directions.

In addition, it will be appreciated by those skilled in the art that the present invention can be applied equally even when a processor in a processor node is connected to any interconnection network.

As described above, since the present invention does not generate a transaction for maintaining a separate cache coherency, there is an effect of reducing the utilization and delay of the ring.

Claims (14)

A plurality of processor nodes 500A to 500H having a distributed shared memory structure arranged in a ring shape to generate a request signal for requesting data from the predetermined processor node 500A, and to receive the request signal. Nodes 500B to 500H include: a processor node group that snoops inside and outputs data corresponding to a request signal; A path connecting the plurality of processor nodes 500A to 500H in a ring shape so that the request signal and data corresponding to the request signal are circulated through the processor nodes to be delivered to the generated processor node 500A. Multiprocessor device of a distributed shared memory structure including a ring bus 510 to provide a The method of claim 1, The request signal is a multiprocessor device of a distributed shared memory structure consisting of broadcast packets The method of claim 1, The request signal is a multi-processor device of a distributed shared memory structure consisting of a single transport packet The method of claim 1, The data corresponding to the request signal is a multi-processor device of a distributed shared memory structure consisting of a single transport packet The method of claim 1, The ring bus 510 is a unidirectional ring bus that unidirectionally connects the plurality of processor nodes. The method of claim 1, The ring bus 510 is a bidirectional ring bus that connects the plurality of processor nodes in both directions. The method of claim 1, wherein each of the processor nodes 500A to 500H is: A plurality of processor modules 100A, 100B; Local shared memory unit 300 for storing data that can be shared by each of the plurality of processor modules (100A to 100B); A remote cache 170 storing data corresponding to the request signal; When the data stored in the local shared memory unit 300 and the remote cache 170 is searched and provided by the processor module 100A or 100B, the desired data is not provided by the processor module 100A or 100B. After generating the request signal, when data corresponding to the request signal is input, the request signal is provided to the processor modules 100A and 100B, and the request signal requested by the other processor node from the ring bus 510 is generated. A node controller 150 that searches for data stored in the local shared memory unit 300 and the remote cache 170 and provides valid data corresponding to the request signal on the ring bus when inputted; Multiprocessor device of a distributed shared memory structure consisting of a ring interface 160 connecting the node controller 150 and the ring bus 510 The method of claim 7, wherein Storing information indicating when data corresponding to a request signal provided from the other processor node is transmitted through the linker, but whether or not another processor generating the request signal has received data corresponding to the request signal Multiprocessor device with a distributed shared memory structure further comprising a pending buffer 190 for The method according to claim 7 or 8, The remote cache 170 is: A remote data cache (176) for storing the contents of the data; And a tag address for data stored in the remote data cache (176) and a remote tag cache (172) for storing data state. The method of claim 9, The remote tag cache 172 is: Multiprocessor device with distributed shared memory structure consisting of two independent remote tag caches (172A, 172B). The method according to claim 7 or 8: The local shared memory unit 300 is: A data memory 310 for storing contents of the data; And a directory memory (320) for storing data representing a state of data stored in the data memory (310). The method of claim 11, The directory memory 320 is: Multiprocessor device with distributed shared memory structure consisting of two independent directory memories (320A 320B). The method according to claim 7 or 8, A plurality of processor modules (100A, 100B) and the node controller 160 is a multi-processor device of a distributed shared memory structure connected by a local system bus. The method of claim 7, wherein The plurality of processor modules (100A) and the node control unit 160 is a multi-processor device of a distributed shared memory structure connected by an interconnection network.