KR19990012462A - Video mode determination device - Google Patents

Abstract

The discrimination apparatus disclosed is for discriminating the video mode of an image signal input from a computer system with hardware of a simple configuration.

The present invention is input by counting the number of horizontal synchronizing signals at the time of the vertical synchronizing signal by using different frequencies of the vertical synchronizing signal and the horizontal synchronizing signal according to the video mode from the computer system, and determining the video mode by the count value. The number of horizontal sync signals is counted during the period of the vertical sync signal, and the number of horizontal sync signals is used to determine the video mode. The first counter counts the horizontal sync signals according to the vertical sync signals, and the inverted vertical sync signals Counts the horizontal synchronization signal in which the second counter is inverted, and stores and outputs the counted horizontal synchronization signal by the first and second registers, and among the number of horizontal synchronization signals output by the first and second registers. The comparator compares the number of large horizontal sync signals with a preset reference value to determine the video mode. A mode control signal corresponding to the determined video mode is output to control the operation of the video display device.

Description

Video mode determination device

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a video mode determination device for determining a video mode of a video signal output from a video card of a computer system in a video display device such as a monitor connected to a computer system such as a personal computer and used as a screen display device. .

In general, an image display device such as a monitor allows a user to simply monitor and confirm an operation state of a computer system.

The computer system incorporates a video card to output a predetermined video signal according to an operation currently performed by the computer system, and the video display device inputs and displays a predetermined video signal output from the computer system on the screen.

In order for a video display device to display a predetermined video signal output from a video card of a computer system, a vertical sync signal and a horizontal sync signal that the computer system outputs along with a predetermined video signal to be displayed on the video display device must be used. do.

The frequencies of the horizontal synchronizing signal and the vertical synchronizing signal output from the computer system to the image display device differ depending on the video mode.

For example, the VGA compatible video graphic array (VGA) mode having a resolution of 640x480 has a frequency of 31.47KHz and 60Hz of a vertical synchronization signal.

In addition, the SVGA (Super Video Graphic Array) mode, which has an 800-by-600 resolution of VESA type, is 37.88KHz for horizontal sync signal and 60Hz for vertical sync signal.

In the XGA mode, the horizontal synchronization signal has a frequency of 48.36 KHz and the vertical synchronization signal has a frequency of 60 Hz.

In addition to the video modes described above, there are various video modes, and the frequencies of the horizontal synchronizing signal and the vertical synchronizing signal differ according to these video modes.

The user may operate and set the image display device according to the video mode of the image signal output from the computer system.

However, setting the video mode of the video display device causes a lot of inconvenience and inconvenience for the user.

In addition, users who lack the knowledge of the video mode did not correctly set the video mode of the video display device according to the video mode of the video signal output from the computer system.

Therefore, it is preferable to automatically set the video mode of the video display device according to the video mode of the video signal output from the video card of the computer system.

In order to determine the video mode of the video signal output from the video card of the computer system, conventionally, the frequency of the horizontal sync signal and the vertical sync signal output together with the video signal from the video card is measured, and the corresponding operation mode is determined based on the measured frequency. An operation according to the determined operation mode is performed.

Conventional techniques for determining the video mode use software or hardware.

The use of the software is to input a horizontal synchronizing signal and a vertical synchronizing signal input from a computer system to a microcomputer to count frequencies, and determine the video mode by the counted frequencies.

Therefore, using the software has a problem that the production cost of the product is increased by using an expensive microcomputer, and the production of the software is difficult.

The hardware is used to input a horizontal sync signal and a vertical sync signal from a computer system to a frequency / voltage converter, convert the voltage into a voltage, input the converted voltage to a plurality of comparators, determine a video mode, and determine the video mode. The switching element is controlled to perform the operation corresponding to the video mode determined by each circuit part.

In addition, since the polarity of the horizontal synchronizing signal and the vertical synchronizing signal inputted from the computer system are different, the use of hardware includes a separate polarity discriminating unit for discriminating the polarity of the horizontal synchronizing signal and the vertical synchronizing signal.

Therefore, using the hardware described above has a problem in that the circuit configuration is very complicated and many parts are difficult to manufacture.

Accordingly, an object of the present invention is to provide a video mode discrimination apparatus for discriminating a video mode of an image signal input from a computer system with hardware having a simple configuration.

1 is a circuit diagram showing the configuration of the discriminating device of the present invention;

2A to 2G are operation waveform diagrams of each part of FIG. 1 in the VGA mode;

3A to 3G are operation waveform diagrams of each part of FIG. 1 in the SVGA mode.

* Description of the symbols for the main parts of the drawings *

100: horizontal synchronizing signal counting unit 110: negative polarity counting unit

111: first counter 112: first register

120: positive counting unit 121: second counter

122: second register 200: mode detector

VSYNC: Vertical Sync SignalHSYNC: Horizontal Sync Signal

In order to achieve the above object, the video mode discrimination apparatus of the present invention uses different frequencies of the vertical sync signal and the horizontal sync signal according to the video mode, and counts the number of horizontal sync signals during the time of the vertical sync signal to determine the video mode. do.

In some video modes, the number of horizontal sync signals may be the same during the vertical sync signal period.

For example, a video mode having a resolution of 640x480 for an IBM compatible model and a video mode having a resolution of 640x480 for a Macintosh compatible model has both 525 horizontal sync signals during the vertical sync signal period.

However, the video mode with 640 × 480 resolution in IBM compatible model has 523 horizontal sync signals during the high potential period of vertical sync signal, and the video mode with 640 × 480 resolution in Macintosh compatible model is used for vertical sync signal. The number of horizontal sync signals during the high potential period is 522 different.

In addition, the polarity of the vertical synchronizing signal and the horizontal synchronizing signal is not constant, and differs depending on the video mode.

Therefore, according to the video mode determining apparatus of the present invention, the video mode is determined by counting the number of horizontal sync signals during the high potential period and the low potential period of the vertical sync signal input from the computer system, respectively. The counter counts the horizontal synchronizing signal, and the second counter counts the inverted horizontal synchronizing signal according to the inverted vertical synchronizing signal, and the first and second registers store and output the counted horizontal synchronizing signal.

A video mode is determined by comparing a number of horizontal sync signals having a large value among the horizontal sync signals output by the first and second registers with a preset reference value, and outputs a control signal according to the determined video mode. Control the operation of the video display device.

Hereinafter, a video mode determination apparatus of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram showing the configuration of the discriminating apparatus of the present invention.

Here, reference numeral 100 denotes a horizontal synchronizing signal counting unit for counting the number of horizontal synchronizing signals HSYNC during a period of the vertical synchronizing signal VSYNC input from a computer system (not shown in the figure), and reference numeral 200 denotes each The reference value according to the video mode is stored in advance, and the mode detection unit determines the video mode by comparing the number of horizontal synchronization signals HSYNC counted by the horizontal synchronization signal counting unit 100 with previously stored reference values.

The horizontal synchronizing signal counting unit 100 includes a vertical synchronizing unit 110 for counting the horizontal synchronizing signal HSYNC and outputting the horizontal synchronizing signal HSYNC to the mode detection unit 200 when the vertical synchronizing signal VSYNC is negative. When the signal VSYNC is positive, the positive counting unit 120 counts the horizontal synchronizing signal HSYNC and outputs the counted signal to the mode detector 200.

The negative count unit 110 is enabled according to the vertical sync signal VSYNC and counts the first counter 111 to count the horizontal sync signal HSYNC and the inverted signal of the vertical sync signal VSYNC. The first register 112 stores the output signal of the first counter 111 and outputs the output signal to the mode detector 200.

The positive counting unit 120 is enabled according to the inverted signal of the vertical synchronizing signal VSYNC, and the second counter 121 for counting the inverted signal of the horizontal synchronizing signal HSYNC and the vertical synchronizing signal VSYNC. The first register 122 stores the output signal of the second counter 121 and outputs the output signal to the mode detector 200.

In the drawing description of FIG. 1, reference numeral EN1 is an enable terminal enabled when the vertical sync signal VSYNC is at high potential, and / EN2 is enabled when the vertical sync signal VSYNC is at a low potential. Terminals, CK1 and CK4 are clock terminals operating in the rising deg of the horizontal synchronizing signal HSYNC, and / CK2 and / CK3 are clock operating in the falling edge of the horizontal synchronizing signal HSYNC. It is a terminal.

D1 and D2 are input terminals of the first and second registers 112 and 122.

The video mode determination apparatus of the present invention configured as described above will be described by taking an example of a VGA mode having a resolution of 640 × 480 in the IBM method and an SVGA mode having a resolution of 800 × 600 in the VESA method.

1. VGA mode with 640 × 480 resolution using IBM method

In the IBM mode, the VGA mode having a resolution of 640 × 480 has a frequency of 31.47 KHz, a frequency of 60 Hz, and a pixel frequency of 25.18 MHz.

The polarity of the vertical synchronizing signal and the horizontal synchronizing signal is negative.

When the vertical synchronizing signal VSYNC and the horizontal synchronizing signal HSYNC having negative polarity are input from the computer system as shown in Figs. 2A and 2B, the second counter 121 during the low potential period of the vertical synchronizing signal VSYNC. Is enabled, the second counter 121 counts the horizontal sync signal HSYNC during the low potential period of the vertical sync signal VSYNC, as shown in FIG. 2C.

In this state, when the vertical synchronization signal VSYNC is switched to the high potential, the second counter 121 is not enabled and the counting operation is stopped.

In addition, since the high potential vertical synchronizing signal VSYNC is applied to the clock terminal CK4 of the second register 122 as a clock signal, the second register 122 operates to '2' which is a count value of the second counter 121. 'Is stored as shown in FIG. 2D and output to the mode detector 200.

Since the first counter 111 is enabled as the vertical synchronizing signal VSYNC is switched to the high potential, the first counter 111 shows the horizontal synchronizing signal HSYNC during the high potential period of the vertical synchronizing signal VSYNC. It will count as shown in 2e.

When the vertical synchronizing signal VSYNC is switched to the low potential in this state, the first counter 111 is not enabled and the counting operation is stopped.

In addition, since the low potential vertical synchronizing signal VSYNC is applied to the clock terminal / CK3 of the first register 112 as a clock signal, the first register 112 operates to operate as a count value of the first counter 111. 523 'is stored as shown in FIG. 2F and outputted to the mode detector 200.

Then, the mode detector 200 prestores the signal having the larger value among the output signals of the first register 112 and the second register 122, that is, the output signal of the first register 112, '523' according to the video mode. Compared with the reference value, it is determined that the video mode is a VGA mode having a resolution of 640x480 by the IBM method as shown in FIG. 2G, and outputs a mode determination signal.

2. SVGA mode with 800 × 600 resolution by VESA

In the SVGA mode having a resolution of 800 × 600 in the VESA method, the frequency of the horizontal synchronization signal is 37.88 KHz, the frequency of the vertical synchronization signal is 60 Hz, and the pixel frequency is 40 MHz.

The polarity of the vertical synchronizing signal and the horizontal synchronizing signal is positive.

When the vertical sync signal VSYNC and the horizontal sync signal HSYNC having positive polarity are input from the computer system as shown in FIGS. 3A and 3B, the first counter 111 is applied during the high potential period of the vertical sync signal VSYNC. Since the first counter 111 counts the horizontal sync signal HSYNC during the low potential period of the vertical sync signal VSYNC, as shown in FIG.

In this state, when the vertical synchronization signal VSYNC is switched to the low potential, the first counter 111 is not enabled and the counting operation is stopped.

In addition, since the low potential vertical synchronizing signal VSYNC is applied to the clock terminal / CK3 of the first register 112 as a clock signal, the first register 112 operates to operate as a count value of the first counter 111. 4 'is stored as shown in FIG. 2F and output to the mode detector 200.

In addition, since the second counter 121 is enabled as the vertical sync signal VSYNC is switched to the low potential, the second counter 121 may decode the horizontal sync signal HSYNC during the low potential period of the vertical sync signal VSYNC. It will count as shown in 3c.

In this state, when the vertical synchronizing signal VSYNC is switched to the high potential again, the second counter 121 is not enabled and the counting operation is stopped.

In addition, since the high potential vertical synchronizing signal VSYNC is applied to the clock terminal CK4 of the second register 122 as a clock signal, the second register 122 operates to '624, which is a count value of the second counter 121. 'Is stored as shown in FIG. 3D and output to the mode detector 200.

Then, the mode detector 200 stores in advance the output signal of the first register 112 and the second register 122 having a large value, that is, the output signal of the second register 122 in accordance with the video mode. Compared with the reference value, it is determined that the video mode is the SVGA mode having a resolution of 800x600 by the VESA method as shown in FIG. 3G, and outputs a mode determination signal.

As described above, according to the present invention, the video mode can be determined by counting the number of horizontal sync signals during the vertical sync signal input from the computer system. It can be produced easily and inexpensively.

Claims (5)

A horizontal synchronizing signal counting unit for counting the number of horizontal synchronizing signals during the period of the vertical synchronizing signal input from the computer system; And And a mode detector which stores a reference value according to each video mode in advance and compares the number of horizontal sync signals counted by the horizontal sync signal count unit with a pre-stored reference value to determine a video mode. The display apparatus of claim 1, wherein the horizontal synchronization signal counting unit; Count the number of horizontal synchronization signals during the high potential period and the low potential period of the vertical synchronization signal, respectively, A mode detector; The horizontal synchronizing signal counting unit determines a video mode by comparing the number of horizontal synchronizing signals having a large magnitude with a reference value previously stored among the number of horizontal synchronizing signals during the high potential period and the low potential period of the vertical synchronizing signal, respectively. Video mode determination device. The horizontal synchronization signal counting unit of claim 1 or 2; A negative counting unit for counting the horizontal synchronizing signal and outputting the horizontal synchronizing signal to the mode detecting unit when the vertical synchronizing signal is negative; And And a positive counting unit for counting the horizontal synchronizing signal and outputting the horizontal synchronizing signal to the mode detecting unit when the vertical synchronizing signal is positive. The battery pack of claim 3, wherein the negative count unit comprises: a negative count unit; A first counter enabled according to the vertical synchronization signal to count a horizontal synchronization signal; And And a first register configured to store and output an output signal of the first counter to the mode detector according to an inverted signal of a vertical synchronization signal. The battery pack of claim 3, wherein the positive count unit comprises: a positive count unit; A second counter that is enabled according to the inverted signal of the vertical sync signal and counts the inverted signal of the horizontal sync signal; And And a first register configured to store and output an output signal of the second counter to the mode detector according to a vertical synchronization signal.