KR19990002610A - High Speed Digital Subscriber Line (HDSL) Matching Device in ATM Switching System - Google Patents

Abstract

The present invention relates to a high-speed digital subscriber line (HDSL) matching device for providing various multimedia services to copper telephone line subscribers in an ATM switch, using a copper telephone line installed for voice telephone service by implementing an HDSL function in an ATM switch. To provide four-line ATM multimedia service to voice subscribers, the ATM physical layer interface is matched to the ATM switcher for low-speed subscriber access, and the signal line is matched between the HDSL module and the ATM physical layer device. By implementing the ATM-based HDSL matching function, it brings innovation to domestic DSL technology and terminal technology that provides various services to HDSL subscribers. Band to one subscriber line It can be used to provide subscribers with high-speed multimedia services at all times, and various multimedia services such as commercial broadcasting advertisements, distance education, and games, including typical services such as video-on-demand, video conferencing, and high-speed Internet access services to general telephone subscribers. Has the effect to provide.

Description

High Speed Digital Subscriber Line (HDSL) Matching Device in ATM Switching System

The present invention relates to High-rate Digital Subscriber Lines (HDSL) based on an Asyncronous Transfer Mode (hereinafter referred to as ATM) exchange.

As the full-fledged development of this field has recently become active, DAVIC, which was launched internationally in 1995, first provided an ATM-based service specification standard. It is inadequate and there is no mutual compatibility between products, and it is a pilot service by introducing foreign system to some parts of Korea such as Seoul and Daejeon.

In the past, HDSL matching devices are being developed using AT & T chips in Korea, and other small specialized companies are developing commercial chipsets, and HDSL research is conducted by many telecommunication companies in the US and Europe, which are advanced countries of HDSL technology. And core chips have been developed, and following the commercialization of chipsets, pilot services are being offered to some regions.

However, these chipsets have been developed independently by each telecommunication company, so the transmission technology used is different, and there is a problem of incompatibility.

In order to solve the above problems, an object of the present invention is to provide an HDSL subscriber matching function for providing ATM multimedia service on a copper telephone line installed for voice service in an ATM exchange.

1 is a block diagram of a configuration of an internal HDSL subscriber matching device in an ATM switch and a peripheral device according to the present invention.

Figure 2 is an internal configuration of the HDSL module of the present invention.

Figure 3 is a block diagram of a HDSL subscriber registration device according to the present invention.

4 is a diagram illustrating a service connection between an exchange and a subscriber according to the present invention;

* Explanation of symbols for the main parts of the drawings *

11: central processing control unit 11a: memory unit

12: common memory

13 high speed digital subscriber line (HDSL) matching unit

14: ATM physical layer processing unit 15: receiving side temporary storage unit

16: Receiving side storage unit 17: Cell bus receiving matching unit

18: Received temporary storage unit 19: Received temporary storage unit

20 loopback function unit 21 transmission cell storage unit

22: multi subscriber processing unit 23: cell bus transmission matching unit

24: sending side temporary storage section 25: sending side storage section

26: test cell transmission storage 27: test cell reception storage

28: internal clock generator 30: termination signal connection unit

40: First High Speed Digital Subscriber Line (HDSL) Transceiver

50: Second High Speed Digital Subscriber Line (HDSL) Transceiver

60: first voltage controlled crystal oscillator (VCXO)

70: second voltage controlled crystal oscillator (VCXO)

80: High Speed Digital Subscriber Line (HDSL) Framer

90 controller 100 low speed subscriber backplane board (LSBB)

110: internal clock distribution device (LCDA)

120: low speed subscriber access device (LSAA)

130: system control bus (VME)

140: HDSL subscriber physical layer interface board assembly (HSPA)

200: ATM Switching Processor (CCCP)

300: system clock providing device (LTGA)

400: hardware failure monitoring device (AGIA)

500: personal computer (PC) 600: HDSL-RT

700: HDSL-COT800: Information Provider (Server)

900: medium and low speed subscriber access data unit (LAN MSAD)

1000: Ethernet Backbone 1100: ATM Switch

In order to achieve the above object, the present invention connects to an operator, monitors whether the link operates normally for the inner subscriber loop, creates a cell of itself, tests the device inner loop path (11), and provides a protocol for maintaining the device. Storing and providing memory map and address decode information (11a), recording various status information for the internal HDSL subscriber link, and commonly managing information for the ATM layer processor (LSAA) to read periodically (12), By connecting three signal lines, each of which transmits / receives, it provides matching between the ATM physical layer processor 14 and the transmit / receive data frame, extracts the data and the clock input from the HDSL line, generates the frame, and maintains the maintenance signal included in the frame overhead. And processing the ATM cell received from the upper processor with a maintenance signal to configure a frame. It transmits to its own line (13), performs ATM physical layer processing function using PMC7345 S / UNI-PDH device, matches with HDSL module, extracts from E1 frame, and delivers to cell multiplexer of cell bus transmission matching unit 23 The cell received from the cell demultiplexing unit of the cell bus receiving matching unit is loaded into the frame and transmitted to the HDSL matching unit 13.

It checks the bit board bit map which is the same as its board identification number among the predetermined number of cell bus receive frames received from the cell bus, and if its bit is set, receives the cell and accumulates it in the cell bus receive storage of the corresponding subscriber link. 17), multiplexing the ATM cell received from the ATM physical layer processor 14, transmitting a multibyte ATM cell bus transmission frame including the subscriber information including the board identification number and the link identification number to the upper processor, and matching the cell bus transmission; Performs address mapping, decoding, and various signal selection for a cell, and provides loop back cell read, cell bus loop back timing, and cell path loop back functions to receive a cell bus of bytes received from the cell bus matching unit 23. It checks the board beak map of the same bit as its board identification number among the frames and sets its own bit Receive and stack cells temporarily and store them temporarily (15), temporarily store the multiplexed or demultiplexed cells when the cell bus is transmitted and received so that the corresponding processor reads a predetermined byte of ATM cells by a higher processor (16), and the cells If a multi-subscriber cell is received from the bus, the virtual path identifier / virtual channel identifier (VPI / VCI) conversion table is read using the multi-subscriber identification (MPID) table of the common memory unit 12, and the virtual path identifier / virtual channel identifier is read. (Virtual Path Identifier / Virtual Channel Identifier, hereinafter referred to as VPI / VCI) is converted and sent to the ATM physical layer processor.

The present invention relates to the development of an HDSL Subscriber Physical Interface Board Assembly (hereinafter referred to as HSPA) having an HDSL subscriber matching device function for providing various multimedia services to an existing copper telephone line subscriber in an ATM exchange. .

According to the national high-speed communication network construction plan, the construction of high-speed communication network will be completed by replacing fiber optic cable with subscriber lines of domestic copper telephone line including optical fiber by 2015. The need to continue providing high-speed data and video services to regular telephone subscribers by utilizing the existing two-wire copper telephone line subscriber lines in use in PSTN / ISDN and ultimately as a subscriber communication medium, copper telephone lines are optical fibers. It is a temporary technology that can be used for the next 40 years as long as copper telephone line exists as subscriber line because it can satisfy subscriber's demand for high speed service while providing more economical service to subscriber network part even if it is replaced by cable. Has been evaluated internationally recently A technology that is rapidly getting popularity worldwide.

HDSL technology transmits 1.544 Mbps or 2.048 Mbps bidirectional data depending on the signaling method without the repeater installed at regular intervals in the existing telephone network, and according to the transmission format, 2B1Q (2Bit 1 Quaternary) and no-carrier AM / PM (Carrierless AM / PM, CAP) and Discrete Multitone (DMT), and the technology introduced in the present invention is a 2B1Q method and there is a 2-wire or 4-wire implementation type depending on the configuration of the connection line, but the present invention is applied to a 4-wire line. Is provided.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a configuration of an internal HDSL subscriber matching device in an ATM switch and a peripheral device and an interconnection block according to the present invention.

The address bus and the control bus of the central processing control unit MC68340 (11) are address decoded by the cell bus transmission matching unit 23 to generate selection signals and control signals of the memory unit 11a, the ATM physical layer processing unit 14, and the like. Through the initialization and common storage unit 12 of each peripheral device, exchange information such as alert status, loop back control, multipoint identification (MPID) registration information, etc., with the ISAA ATM layer is exchanged.

The two RS-485 serial communication ports and the MAX232C device are used to periodically monitor the internal HDSL subscriber link. If the internal link fails, the fault is written to the internal common memory 12 with 8-bit code.

One of the two RS-485 serial ports is connected to the serial communication port of the HDSL module inside the device for multi-communication with the four HDSL modules on the board, and the status of the HDSL loop is always displayed by the control processor inside the HDSL matching unit. When monitoring and requesting transmission of status information of the link from the central control processor of HSPA, it reports status and format through the connected port.

This is done in the form of a protocol of command interrupts between the HSPA central processing controller and the HDSL module, respectively.

The other port is connected to the operator and loop back for testing link status, synchronization status, Cyclic Redundance Check (CRC) information, maintenance for maintenance and line loop status for each of the four subscriber loops housed in HSPA. Provide a test function.

The central processing control unit of HSPA interfaces with the LSAA through control bus matching and reports the status and shape of 16 HSPAs.

The memory portion 11a incorporates a status monitor firmware for maintaining the apparatus of the present invention and stores memory map and address decode information.

The common storage unit 12 is a place where the central control unit records various maintenance information in the HSPA when a failure occurs in the internal HDSL subscriber link, and the LSAA communicates with the HSPA through the control bus to read this maintenance information. Periodically report the status of all 16 boards to the ATM system.

If the multi-subscriber processor 22 is a multi-subscriber cell among the cells received from the cell bus, the multi-subscription identification table (hereinafter referred to as MPID) is provided to convert the VPI / VCI and send it to the ATM physical layer processor 12. .

As shown in Table 1, the HDSL matching unit 13 connects three signal lines, respectively, to match transmission / reception data frames between the HDSL matching unit 13 and the ATM physical layer processing unit 14.

The HDSL matching unit extracts data and clocks from the HDSL line input signal to generate a frame, processes the maintenance signal included in the frame overhead, extracts the ATM cell, and delivers the signal to the LSAA.

The HDSL matching unit 13 constructs a frame with the maintenance signal and transmits the ATM cell received from the LSAA to the HDSL subscriber line.

TABLE 1

Signal line matched between HDSL matcher and ATM physical layer device

Matching signal Signal name ATM physical layer device HDSL Matching Part Transmit frame pulse Tx frame pulse TOHM TMSYNC Send data Tx data TDAT TSER Transmit clock Tx clock TCLK TCLK Receive frame pulse Rx frame pulse ROHM RMSYNC Received data Rx data RDAT RSER Receive clock Rx clock RCLK RCLK

The ATM physical layer processor 14 performs an ATM physical layer processing function using the PMC7345 S / UNI-PDH device, matches the HDSL matcher 13, extracts a cell from the E1 frame, and then transmits the cell bus matcher 23. The cell is transmitted to the cell multiplexer, and the cell received from the cell demultiplexer of the cell bus matcher is loaded into a frame and sent to the HDSL matcher.

The cell bus transmission matching unit 23 performs address mapping, decoding, and various signal selection for cell bus transmission matching using the EPLD.

In HSPA, two subscribers are first multiplexed, the cell is stored in a cell bus storage unit on the cell bus matching side, and the ATM layer processor (LSAA) performs second multiplexing of 64 subscribers of 16 PBAs.

The cell bus transmission matching section 23 multiplexes the ATM cells received from the ATM physical layer processing section and attaches a 3-byte header including a board identification number and a link identification number (b'd ID, link ID) to 56 bytes as shown in Table 1 above. Sends a cell bus transmission frame to the LSAA.

The cell bus transmission matching unit 23 transmits a cell in which a transmission subscriber number is added as a bitmap to each subscriber device, and the subscriber device extracts only the cell in which the corresponding bit is set. In the case of a PTMP cell, the output VPI / VCI Find the value and perform the output header transformation.

TABLE 2

Cell Bus Transmit Frame Format

FF (15: 8) FF (7: 0) Loopback (15), RES (14) Board_ID (13:10), Link_ID (9: 8) ATM cell 54 bytes (header 5 + payload 48)

The cell transmission matching unit 23 provides a cell path loopback function together with a loop back cell read counter and cell bus loop back timing.

Referring to the cell transmission process, whether the cell of Table 2 received from the LSAA ATM 5 layer through the cell bus will receive the cell compared to its own board identification number using the board bitmap located in the header of the first 2 bytes. Judge.

The received cell determines whether the cell is multicasting through the cell bus reception matching unit 17, and if the cell is a multicasting cell, performs the VPI / VCI conversion according to the MPID table registered in the common storage unit 12 using the MPID. .

By referring to the link identification number, a 53-byte pure ATM cell is stored in storage 24 of the link.

The stored cell is read by the ATM physical layer processor 14 and then modulated into an HDSL serial data stream and transmitted to the voice subscriber telephone network.

The cell bus reception matching section 17 has a reception signal and a storage read signal (FIFO read) for multiplexing various signal selections for cell bus reception matching using an EPLD.

It is a cell type in which a line number is added to an ATM cell in the form of a bit map in order to distinguish a line for a signal channel.

From the 56-byte cell bus receive frame received from the cell bus, it examines the 16-bit board bitmap that is identical to its board identification number and, if its bit is set, receives the cell and receives the cell bus of the corresponding subscriber link, which is 4 links per board. Are accumulated in the receiving side temporary storage unit 15.

TABLE 3

Cell Bus Receive Frame Format

Board bitmap (15: 0): active low PTMP (15), MPID (14: 8) Link_ID (9: 8) 53 bytes of ATM cell (header 5 + payload 48)

In the cell reception process, the serial data received from the HDSL matching unit 13 is generated through the ATM physical layer processing unit 14 to generate a 53-byte ATM cell to the cell bus transmission matching unit 23 through an 8-bit bus. Is sent.

The cell bus transmission matching section 23 multiplexes the ATM cells from the ATM physical layer processing section 14, and attaches a board identification number to each cell in a header and sends them to the LSAA for processing the ATM layer.

The cell of Table 3 with a header is stored in the receiving side temporary storage unit 15, which is a temporary waiting place for the LSAA to read the cell.

The multi-subscriber processor 22 reads the VPI / VCI conversion table of the common storage unit 12 using the MPID and converts the VPI / VCI if it is a multi-subscriber cell among the cells received from the cell bus, and converts the VPI / VCI to the ATM physical layer processor (PLPP) 14. Send to).

The internal clock generator 28 generates 16.384 MHz using an internal oscillator, and may select an internal clock or an external clock source using an internal jumper in hardware.

The apparatus of the present invention generates its own cell to perform a self test function through the cell bus loop back.

The 53-byte ATM cell is passed to the test transmission cell storage 25, and the cell stored therein is read into the cell bus transmission matching section 23 in the same manner as the cell received from the line, and the cell format shown in Table 1 below. Is converted to the cell bus.

In the test mode, the cell is not sent to the LSAA, but is transmitted to the test transmission side storage unit 25 through the loop back function unit 20.

After the transfer, the cell is delivered to the transmitting side temporary storage unit 24, the ATM physical layer processing unit 14, and the HDSL matching unit 13 through the same path as the cell received from the LSAA from the cell bus.

In the case of the loop back test, the cells of the serial data stream transmitted from the ATM physical layer processing unit 14 to the HDSL matching unit 13 are read back to the cell bus transmission matching unit 23, and the self test cell receives the test cell receiving storage unit. It is stored in (27) and read by the central processing control unit (11).

The central processing control unit 11 compares the received cell with a cell generated by itself to determine whether an error of the loopback test is displayed on the console.

FIG. 2 is an internal configuration diagram of an HDSL module of the present invention, and illustrates a HDSL transceiver configuration in which a framer, a digital signal processor (DSP), an analog signal processor (ASP), and a controller device of Metalink are combined.

The HDSL module supports a full-duplex 2B1Q scheme, and European technical specifications (0 dB ETSI) noise for two-pair (four-wire) E1 when transmitting E48 data at 2.048 Mb / s ± 50 pulses / minute. Under the conditions, it is possible to transmit up to about 2.7km through the 26AWG (0.4mm) line, and up to about 3.5km through the 24AWG (0.5mm) line, and the subscriber line such as shape control, performance monitoring and loop back control function. It has a management function.

The HDSL module performs HDSL subscriber line matching, that is, converts a standard T1 or E1 format into an HDSL format, restores data and a clock, and transfers the data and the clock to the physical layer processor (PLPP) 14.

The transmitter changes the base rate channel to an HDSL 2 loop channel, multiplexes the channel with overhead bits and loop data using the base rate frame information supplied by the framer, then scrambles the loop data and uses the 2B1Q code to Is coded.

The receiver descrambles the loop data and demultiplexes the HDSL loop channel into a base rate channel.

3 is a block diagram of an HDSL subscriber matching device according to the present invention, which illustrates the configuration of the HDSL subscriber matching device and the relationship between the HDSL subscriber matching device and the peripheral device in the ATM switch.

One LSAA and one LDCA manage 16 HSPAs, which are all mounted on LSBB to form a hardware block.

The internal clock distribution device (LCDA) supplies clocks to the backplane board (LSBB) and low speed subscriber access device (LSAA) on which 16 HSPAs are mounted, receives the cells from the LSAA, multiplexes them, transfers them to the switch, and receives them from the switch. Demultiplex the cells with HSPA.

HSPA multiplexes the ATM cells received from the four subscribers and forwards them to the LSAA, and demultiplexes the cells received by the LSAA to the four subscribers.

The control information is transmitted and received with the LSAA through the system control bus (VME bus) of the backplane.

4 is a diagram illustrating a service connection between an exchange and a subscriber according to the present invention, and illustrates a diagram of a service connection between an exchange and a subscriber for an HDSL service.

The VOD service connects a home PC terminal equipped with an MPEG-1 card, an E1 card supporting 2.048 Mb / s, to an HDSL subscriber station modem, and is an HDSL matching device of the present invention mounted on the HDSL subscriber station modem and the interrogator side. It connects between HSPAs and is serviced through a server.

The video conferencing service is serviced through the subscriber E1 line between home multimedia PC terminals equipped with audio / visual cards.

The Internet access service connects the HDSL subscriber station and the internet network to a medium-low speed subscriber access data unit (LAN-MSAD) and is serviced through a server.

As described above, the present invention revolutionizes domestic DSL technology for ATM-based HDSL service by a general telephone copper telephone line medium and terminal technology that provides various multimedia services to HDSL subscribers.

In addition, as the number of subscribers increases, all bands can be used in one subscriber line as compared to cable cables, which are relatively slow, providing subscribers with high-speed multimedia services at all times.

In addition, the domestic market is eroded by foreign companies (AT & T, Amati, Brooktri, Metalink, Pairgain) that are already competitive in the field of significant technology accumulation and commercialization of core parts technology due to the rapid growth of the overseas DSL market and the lack of domestic technology. It is still in the process of being commercialized or in the commercialization stage in HDSL developed countries such as the US and Europe, and it has secured competitiveness and export-oriented system for foreign countries by developing core parts, developing HDSL-COT, developing HDSL-RT and technology. It has the effect that development is possible.

Claims (10)

A high speed digital subscriber line (HDSL) matching device for providing multimedia services to subscribers at an ATM exchange, A central processing control unit connected to an operator to monitor whether the link is properly connected to the internal subscriber loop and to generate its own cell to test the device internal loop path; A memory section in the central processing control section for storing a protocol for maintaining the device and providing a memory map and address decode information; An information common storage section for recording status information on the internal HDSL subscriber link and having the upper processor (LSAA) read it periodically; It connects each signal line to transmit / receive, provides matching between the ATM physical layer processor and the transmit / receive data frame, extracts data and clock input from the HDSL line, generates a frame, processes maintenance signal included in frame overhead, and receives from the LSAA. An HDSL matching unit for constructing a cell with a maintenance signal and transmitting the frame to the HDSL subscriber line; Performs the ATM physical layer processing function using the device, matches the HDSL module, transfers the cell to the cell multiplexer of the cell bus transmission matcher in the E1 frame, and transfers the cell received from the cell demultiplexer of the cell bus reception matcher to the HDSL matcher. An ATM physical layer processor for transmitting; Cell bus reception matching that checks the mode bitmap identical to its board identification number among cell bus frames received from the cell bus and receives the cell and stores it in the cell bus reception storage of the subscriber link if its bit is set. Wealth; ATM cells received from the ATM physical layer processor are multiplexed to transmit ATM cell bus transmission frames to the upper processor, including subscriber information including board identification numbers and link identification numbers, address mapping, decoding, and various types of cell bus transmission matching. A cell bus transmission matching unit performing signal selection and providing loop back cell read, cell bus loop timing, and cell path loop back functions; A receiving side temporary storage unit which checks a board bit map identical to its board identification number among the cell bus receiving frames received from the cell bus transmission matching unit and receives and stores a cell if its bit is set; A reception side storage unit for temporarily storing a multiplexed or demultiplexed cell with a corresponding subscriber identification number in order to read a multi-byte ATM cell by a higher processor when transmitting and receiving a cell bus; A multi-subscriber processor which reads a VPI / VCI conversion table using the multi-subscriber identification (MPID) table of the common storage and converts the VPI / VCI to an ATM physical layer processor if the cell is received from a cell bus; A test cell transmitting / receiving storing unit for generating a multi-byte ATM cell by the central processing controller and performing cell bus loopback to perform a self test function; A high speed digital subscriber line (HDSL) matching device for an ATM switch comprising an internal clock generator for generating a clock of a predetermined frequency using an internal oscillator to provide a stable clock to the system. The method of claim 1, wherein the central processing control unit Maintenance using two serial communication ports and MAX232C device to monitor link operation for 64 subscriber loops housed on 16-board boards housed on backplane boards (LSBB) with 16 HDSL Subscriber Physical Layer Interface Board Assemblies (HSPA) Function; A loop back test function for finding a point of failure of the subscriber line; A high speed digital subscriber line (HDSL) matching device for an ATM switch comprising a function of reporting information on the state and shape of 16 HSPAs to a higher processor (LSAA) via a control bus interface. The memory unit of claim 1, wherein the memory unit stores the ATM cell signals. A high speed digital subscriber line (HDSL) matching device for an ATM switch characterized by performing a state monitoring for maintaining a device in an ATM, and storing a memory map and address decode information. The method of claim 1, wherein the common storage unit In the event of a failure of the internal HDSL subscriber link, a record of various maintenance information in the HSPA is stored from the central processing controller, and the LSAA communicates with the HSPA through the control bus to read this maintenance information to obtain the status information of the entire 16-board board. A high speed digital subscriber line (HDSL) matching device for an ATM switch characterized in that it periodically reports to an ATM system. The method of claim 1, wherein the internal clock generator A high speed digital subscriber line (HDSL) matching device for an ATM switch characterized by generating a constant frequency using an internal oscillator to provide a stabilized clock to its own device. The method of claim 1, wherein the HDSL matching unit Signal lines are transmitted and received between HDSL module and ATM physical layer processing unit by connecting each transmit / receive signal line, and data and clock are recovered from HDSL subscriber line input signal and frames are generated to process maintenance signals included in frame overhead. A high speed digital subscriber line (HDSL) matching device for an ATM switch, characterized in that the ATM cell received from the LSAA from the ATM physical layer processing unit is configured to transmit a frame along with a maintenance signal to the HDSL subscriber line. . The method of claim 1, wherein the ATM physical layer processing unit Using the PMC7345 S / UNI-PDH device, it captures the cell contained in the E1 frame, extracts the ATM cell, passes it to the cell bus transmission matching unit, and loads the cell received from the cell demultiplexing unit of the cell bus receiving matching unit into the frame. A high speed digital subscriber line (HDSL) matching device for an ATM switch, characterized in that it is sent to the matching section and matched with the HDSL matching section. 6. The cell bus transmission matching unit of claim 5, wherein the cell bus transmission matching unit Transmit the cell of the form of adding the transmitting subscriber number to the bitmap to each subscriber device, extract the cell with the corresponding bit set in the subscriber device, and find the output VPI / VCI value to perform output header conversion. And a loop back cell read counter, cell bus loop back timing, and cell path loop back functionality. The method of claim 6, wherein the cell bus matching unit If a bit board map identical to its own board identification number is checked among the multi-byte cell bus receive frames received from the cell bus and its bit is set, the cell is received and stored in the cell bus receive storage of the subscriber link. A high speed digital subscriber line (HDSL) matching device for an ATM switch. The method of claim 7, wherein the multi-subscriber processing unit A high-speed digital subscriber line of an ATM exchanger that provides a multi-subscriber identification (MPID) table and reads the VPI / VCI conversion table and converts the VPI / VCI to the ATM physical layer processor if the multi-subscriber cell is received from the cell bus. HDSL) matching device.