KR19980075620A - How to Process Reassembled Packets in ATM Networks - Google Patents

Abstract

The present invention relates to a method for delivering a packet formed by reassembling ATM cells received at a receiving end of an ATM network interface card (NIC) to an upper layer.

According to the method of the present invention, the ATM network connector driver controls the ATM network connector according to the request of an application program operating in the host system, and transmits data in the ATM communication method, and the ATM network connector reassembles the received ATM cells to send the packet. In an ATM terminal configured to notify the ATM network driver driver through an interrupt after forming a packet, the number of packets formed after reassembling a received ATM cell to form a packet reaches a predetermined number or after the first packet is received. When a predetermined time has elapsed, an interrupt is generated to request processing from the ATM network driver.

Therefore, the present invention can reduce the burden caused by frequent interrupt processing on the NIC driver operating in the host.

Description

How to Process Reassembled Packets in ATM Networks

The present invention relates to a method for delivering a packet formed by reassembling ATM cells received at a receiving end of an ATM network interface card (NIC) to an upper layer.

In general, ATM communication is implemented as a layered protocol to support various services of consumers as one integrated network. In other words, the conventional public telephone network (PSTN) or packet switched network (PSDN) was a dedicated network for providing voice or data services, whereas the ATM network was designed to provide voice, data, and video services in one integrated network. It is the basis of 'B-ISDN'.

1 is a conceptual diagram illustrating an ATM protocol reference model. Here, the protocol model is composed of a management plane, a control plane, and a user plane, and the management plane is composed of hierarchical management and plane management. In addition, the plane management means the overall management of the system, and the hierarchical management manages resource and usage variables and OAM information management.

In addition, the control plane manages call control and connection (also called connection) control information, and the user plane transmits user information. The protocol of the control plane and the user plane is composed of a higher layer, an ATM adaptation (AAL) layer, an ATM layer, and a physical layer.

Here, the ATM Adaptation Layer performs a function of adapting a service provided by the ATM layer to the requirements of a higher layer user. Therefore, the ATM adaptation layer should be able to provide an interface between the ATM communication environment and the non-ATM communication environment, while supporting the user plane, the higher level control plane and the management plane.

In addition, the ATM adaptation layer (AAL) maps a protocol data unit (PDU) of a higher layer to the payload interval of an ATM cell, handles transmission errors, processes lost cells and inserted cells, Flow control and timing control must be provided. The ATM adaptation layer is further subdivided into two sublayers: a segmentation and reassembly (SAR) sublayer and a convergence sublayer (CS).

The convergence sublayer (CS) performs a function related to a specific service, and the segmentation and recombination (SAR) sublayer processes a function related to division and recombination of user information by processing a function irrespective of a service type. Therefore, at the transmitting side, the convergent sublayer (CS) is applied as user information from an upper layer, attaches a header and a trailer, forms a convergent sublayer protocol data unit (CS-PDU), and sends it to a split and recombination (SAR) sublayer. This split and recombine (SAR) sublayer cuts it to the size of an ATM cell, attaches a header and trailer to form a split and recombine protocol data unit (SAR-PDU), and transmits it through the ATM layer.

In addition, the receiving side extracts only the payload section of the segmentation and recombination protocol data unit (SAR-PDU) received through the ATM layer to form a convergence sublayer protocol data unit (CS-PDU). After that, the information is transferred to the convergence sublayer CS, and the convergence sublayer CS extracts only upper layer user information among the received convergence sublayer protocol data units CS-PDUs and delivers the information to the upper layer.

At this time, the header and the trailer attached to each sub-layer in the transmission process are related to error processing, buffer management, and order preservation. Will be passed to the layer.

This asynchronous transmission mode (ATM) communication method has a hierarchical structure as shown in Table 1 below, and has standardized standards for each layer.

TABLE 1

Hierarchy Tier function Upper hierarchy Higher layer function ATM Adaptation Layer Convergence (CS) sublayer Convergence function Cutting and Recombination (SAR) Cutting function and recombination function ATM layer General flow control and cell header processing Physical layer Transmission Convergence (TC) HEC signal generation and extraction function Physical medium Bit time information function

As shown in Table 1, the asynchronous transmission mode communication method is divided into vertical structures such as a physical layer, an ATM layer, an ATM adaptation layer (AAL), and an upper layer, and the AAL layer is a cut and recombination sublayer (SAR). It is divided into segmentation and reassembly sublayer (CS) and convergence sublayer (CS) sublayers, and the physical layer is divided into physical media (PM) and transmission convergence (TC) sublayers.

In addition, a service required by a user in an asynchronous transmission mode communication method may be classified as shown in Table 2 below according to its characteristics.

TABLE 2

Type of service End-to-end time relationship Bit rate Connection mode Example of service Class A Real time Identity Connectivity Video signal Class B Real time variable Connectivity Variable Rate Video Signal Class C Non-real-time variable Connectivity Connectivity data Class D Non-real-time variable Connectionless Connectionless data

The AAL protocol corresponding to the service is divided into AAL 1 to AAL 5 as shown in Table 3 below.

AAL form Typical feature AAL 1 Support class A service of equal bit rate AAL 2 Support real-time, variable bit rate Class B service AAL 3/4 Support class C and D services with variable bit rate AAL 5 High speed service by simplifying AAL 3/4 function

In Table 3, the type of the AAL layer is horizontally divided as AAL 1, AAL 2, AAL 3/4, and AAL 5 to efficiently process the corresponding service according to the type of service.

On the other hand, an ATM terminal using an ATM network connector (NIC) usually performs an ATM network connector (NIC), which is responsible for the functions of the AAL layer, the ATM layer, and the physical layer, controls the ATM network connector, and performs higher layer functions. NIC driver is provided. The NIC driver allocates and frees memory to send and receive packets, updates the values of control variables, and handles interrupts caused by various causes.

However, the receiving end of the ATM network connector reassembles the ATM cell and generates an interrupt to inform the driver routine when the packet is completed. That is, conventionally, since an interrupt is generated every time a packet is received, when a packet is continuously received, there is a case where the interrupt occurrence frequency is excessive and the NIC driver routine cannot handle it properly, thus communicating with the ATM terminal. There is a problem that the related operation becomes unstable.

Accordingly, the present invention has been proposed to solve the above problems, and generates a interrupt when a predetermined number of packets are reassembled at the receiving end of an ATM network connector (NIC) so that the network driver driver routine aggregates several packets. An object of the present invention is to provide a method for processing a received packet of an ATM network accessor.

In order to achieve the above object, the ATM network connector of the present invention transmits data in an ATM communication method by controlling an ATM network connector according to a request of an application program operating in a host system. The ATM terminal is configured to reassemble the received ATM cells to form a packet and inform the ATM network driver driver through an interrupt, wherein the number of packets formed after reassembling the received ATM cell to form a packet is determined. When it arrives, it generates an interrupt to request processing from the ATM network driver.

1 is a conceptual diagram illustrating a general ATM protocol reference model;

2 is a block diagram illustrating a general ATM network connector;

3 is a schematic diagram showing an example of a data format processed in FIG. 2;

4 illustrates a concept of the prior art that generates an interrupt each time a packet is received;

5A and 5B illustrate a concept of generating an interrupt when a certain number of packets or a predetermined time elapse according to the present invention;

6 is a flowchart illustrating a process of processing an reassembled packet by generating an interrupt when the number of received packets is a certain number according to the present invention;

FIG. 7 is a flowchart illustrating a process of processing an reassembled packet by generating an interrupt when a predetermined number of received packets or a predetermined time elapse according to the present invention.

* Explanation of symbols for the main parts of the drawings

10: host system 11: host memory

12: processor 13: bus controller

20: ATM network connector 21: AAL processing unit

22: SONET / ATM line matching unit 23: transceiver

30: I / O bus

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

First, an example of a configuration and operation example of a typical ATM network connector suitable for applying the present invention will be described, followed by an embodiment of a method for processing a received packet according to the present invention.

2 is a block diagram showing an example of an ATM network accessor (NIC) suitable for application of the present invention. Referring to FIG. 2, the host system 10 is connected to an ATM network (not shown) through an ATM network connector 20 to exchange data with an opposite host system in an ATM manner.

In an embodiment of the present invention, the host system 10 is a computer, such as a workstation, and includes at least a host memory 11, a processor 12, and a bus controller 13. In the embodiment, the S bus 30 is connected to the ATM network connector 20. In the host system 10, an application program for providing a service to a user is executed at a top level, and an ATM network connector driver is installed to provide an ATM communication function according to a request of the application program. Therefore, during the initialization process, the ATM driver sets up various tables and rings related to ATM communication and updates the data of the various tables according to the request of the application program.

Under the direct control of the NIC driver, the ATM network accessor (NIC: 20) divides a packet to be transmitted into an ATM cell according to a request of an application program and transmits the packet to the ATM network, reassembles the received ATM cells, forms a packet, and then applies the application. Deliver to the program. The ATM network connector 20 is usually mounted in an expansion slot of the host system, and is connected to the host system 10 through the input / output bus 30.

As shown in FIG. 2, the ATM network connector 20 includes an AAL processing unit 21, a SONET / ATM line matching unit 22, a transceiver 23, a control RAM 25, an pyramid 26, and the like. It handles the functions of physical layer, ATM layer and AAL layer of ATM communication system. In particular, in the embodiment of the present invention, the ATM network connector (NIC) 20 maps ATM cells to a synchronous optical network (SONET) STS-3c frame format (155.52M bps) and then, through the optical synchronization network, the ATM. It is intended to be connected to the network.

Referring to FIG. 2, the AAL processor 21 is connected to the control RAM 25 through a local memory bus and to the pyramid 26 through a local slave bus. In this case, the pyramid 26 is also connected to the line matching unit 22 through the local bus.

In addition, the AAL processor 21 is connected to the input / output bus 30 to directly access the memory 11 of the host system and to read / write the control memory 25. The processor 12 of the host system can be read. In addition, the control memory 25 can be directly accessed and read / written through the I / O bus.

When an application program operating in the host system 10 requests an ATM related service, the NIC driver operating in the host system controls the ATM network connector 20 according to the request to provide the ATM related service to the application program. For example, when an application program stores predetermined message data in the host memory 11 and requests data to be transmitted, the NIC driver requests data transmission to the AAL processing unit 21 through the input / output bus 30.

The AAL processing unit 21 reads the message stored in the host memory 11 in units of a predetermined length (48 bytes), forms an ATM cell in accordance with the AAL protocol format, and then sends it to the line matching unit 22 of the physical layer 24. Send it down. The SONET / ATM line matching unit 22 maps the ATM cells to the SONET STS-3c format, and the transceiver 23 converts the serial data of the STS-3c format into an optical signal and outputs the optical signal to the ATM network side through the optical cable.

On the other hand, the data received through the transceiver 23 is separated from the line matching section 22 to the ATM cell and input to the AAL processing section 21. The AAL processor 21 separates the header and the payload from the received ATM cells, recombines the payload, restores the message (packet), and interrupts the host system 10 when the message reassembly is completed. Inform this. When an interrupt indicating completion of reassembly is received from the AAL processing unit 21, the NIC driver of the host system delivers the received message to the application program side according to a predetermined processing procedure.

As described above, the AAL processor 21 divides the message transmitted from the upper layer into ATM cells, transmits the message to the counterpart, and reassembles the received ATM cells to restore the message. Notify the NIC driver.

Looking at the structure of the data transfer between the upper layer and the AAL processing unit in such an ATM network connector in more detail as follows.

The data format transmitted between the host system 10 and the AAL processing unit 20 is divided into a transmission and a reception, as shown in FIG. 3, and located in the host memory 11 and the control memory 25, respectively. That is, the host memory 11 includes a TX descripter ring, TX completion ring, and data buffers used for transmission, and a data buffer and reception used for reception. A completion ring (RX completion ring) and two free buffer rings are located. In the control RAM 25 of the NIC, a band allocation table and a transmission DMA state table used for transmission are located, and a reception DMA state table used for reception is located.

The transmission descriptor ring implemented in the host memory 11 may be composed of 255, and may have 255 virtual channels (VCs), and each ring has 256 entries. Each entry is then implemented in four words (one word is 32 bits) to point to one transmission data buffer queued for transmission. Typically, not all 255 transmit descriptor rings are used, and each ring is only used for the required number of virtual channels. For example, the first transmission descriptor ring may be used as a voice channel, the second transmission descriptor ring may be used as a video channel, and the third descriptor ring may be used for TCP / IP.

Each entry in the transmit descriptor ring consists of 4 words, where word 3 represents the tail of AAL5, word 2 represents the 4-byte ATM header, and word 1 indicates the start of the transmit data buffer. And word 0 represents a control field, a packet length, a buffer length, and the like. Looking further at word 0, bit 31 of word 0 is an OWN bit, which is set by the host when the packet for transmission is queued, to be accessed by the AAL processor, and reset when the packet has been transmitted. To be. Bit 30 of word 0 represents the start buffer when multiple buffers are used to transmit one packet, and bit 29 represents the last buffer. Bit 27 represents the AAL type, bits 26 through 16 represent the length of the packet, and bits 15 through 0 represent the length of the buffer. The maximum size of the buffer is 64K bytes. As such, the transmit descriptors represent the buffers on the host memory where the packets to be transmitted are located.

The transmission data buffers store data to be transmitted, and after the transmission preparation is completed, the data stored in the transmission buffer are read and transmitted by the AAL processing unit 21.

Referring to Figure 3, the transmission complete ring has 256 entries, one entry indicating that one packet has been transmitted, each entry consisting of four words. If bit 31 of word 0 of the 4 words is set to 1 as an OWN bit, the bit is used in the AAL processing unit 21, and when the bit is reset to 0, the host 10 is entitled to use. Bits 30 through 8 of word 0 are not used, and bits 7 through 0 represent the index of the band allocation table.

Receive pre-buffering consists of two rings to point to free buffers of different sizes, each ring consisting of 256 entries. The host system 10 writes a pointer to an empty buffer in each ring, and determines the size of the buffer during initialization. For example, two prebuffer rings are divided into a large first prebuffer ring and a second prebuffer ring such that the first prebuffer ring is used to indicate 8K byte sized buffers for TCP / IP based applications. The free buffer ring can be used to point to 48 byte buffers for CBR services. Therefore, the virtual channel set up for the CBR application uses the buffers indicated by the second free buffering ring, and the virtual channel set up for the TCP / IP application uses the buffers indicated by the first free buffering ring.

At this time, the entry of each pre-buffering ring is composed of 4 words, bit 31 of word 0 is an OWN bit, and is set when the entry of each pre-buffering ring is owned by the AAL processing unit 21, and the host 10 It is reset when owned by. And bits 30 through 28 are not used, and bits 27 through 0 represent the start pointer of the buffer. In the initialization process, the receiving buffers are formed into 16-byte boundaries from the minimum size of 48 bytes to the maximum length of 64K bytes. The size of the buffers indicated by one pre-buffering ring is the same.

The reception completion ring consists of 256 entries, each entry consisting of four words. Word 0 is used to indicate a control field, packet length, etc., word 1 indicates a pointer to a 28-bit start buffer, and word 2 Indicates a 4-byte ATM header. Bit 31 of word 0 is an OWN bit, and when it is set, it indicates that it is processed by the AAL processing unit 21, and when it is reset, it indicates that it is processed by the host system 10. Bit 30 is a packet overflow bit, which indicates that an overflow occurs in the reception buffer while the current packet is being processed. Bit 29 is a CRC condition bit that informs the host that a CRC error has occurred in an AAL5 packet. Bits 21 through 11 represent the reception of congested cells, and bits 10 through 0 represent the length of the packet.

The receive complete ring also contains a pointer to the received packet in host memory to be processed, and upon receipt of an interrupt, the host system 10 examines the receive complete ring and processes entries whose OWN bit is reset. .

On the other hand, as shown in Fig. 3, the control memory includes a band allocation table, a transmission DMA state table, and a reception DMA state table. Such a table can be accessed by the AAL processing unit and the host.

The band allocation table has 4800 entries, each entry consisting of 1 byte. The transmit DMA status table consists of 255 DMA entries, each DMA entry consists of eight words, the receive DMA status table is used for reception and consists of 1024 DMA entries (each entry is eight words).

The band allocation table allocates bands for 255 transmit descriptor rings by assigning indices from 0 to 255 for each 8-bit entry. At this time, 0 indicates that an invalid cell is transmitted. This band allocation table is set during initialization. The band allocation table includes a pointer indicating a transmission DMA state table, and the AAL processing unit 21 sequentially accesses a table having a predetermined size and transmits data of a transmission descriptor indicated by an index of the table.

The transmit DMA status table consists of 255 band allocation DMA entries, each DMA entry consisting of 8 words to indicate the transmit buffer to be split. Word 8, Word 1, Word 2, and Word 7 are copied from the transmit descriptor ring as they are in the 8 words constituting the DMA entry. Word 0 represents the control field, packet length, and buffer length. A pointer to the current buffer, word 2 represents a 4-byte ATM header, and word 7 represents the tail of AAL5. Word 3 is an area programmed only by the host. If bit 31 of word 3 is a BWG_ON bit, if 1, data is transmitted based on a band allocation table. If 0, transmission data is not transmitted and a null cell is transmitted. Bits 31 through 12 in word 4 are the transmission descriptor ring pointers, which are DVMA addresses indicating the location of the current entry of the corresponding transmission descriptor ring. Word 6 is the part used for CRC calculation of the AAL5 packet.

The Receive DMA Status Table is a table used for reception and consists of 1024 Receive DMA entries, each DMA entry consisting of 8 words. Bit 31 of word 0 is set when the DMA channel is activated, bits 21 through 11 are used as an Explicit Forward Congestion Notification (EFCN) cell counter, and bits 10 through 0 represent the length of the packet. Word 1 represents the current buffer pointer, word 2 represents the starting buffer pointer, and word 3 represents the AAL packet length. The VC_ON bit of word 4 is turned on during packet reassembly. If it is reset, the AAL processor 21 discards the reception cell of the VC. The buffer type bit indicates whether the corresponding buffer belongs to the first prebuffer ring or the second prebuffer ring.

In more detail, the transmission and reception of a packet through such a data format will be described below.

The transmit buffer can be formed anywhere on the host memory, up to 64K bytes in size. When a packet to be transmitted from the host is prepared, the ATM network connector 20 sequentially transmits data included in each packet. The received packet is stored in one receive buffer in host memory 11. At this time, there are two types of buffers, which are indicated by the first or second prebuffer ring.

First, the application program of the host stores the data to be transmitted in the transmission data buffer, and sets the transmission descriptor ring by writing a pointer to these buffers in the transmission descriptor ring. When the host processing of the packet is completed, the OWN bit of the corresponding entry of the transmission descriptor ring is set to transfer the processing of the packet from the host 10 to the AAL processing unit 21.

The AAL processing unit 21 sequentially processes the data stored in the transmission data buffer in accordance with the transmission DMA status table indicated by the index of the band allocation table entry while sequentially cycling the band allocation table. At this time, the entry data of the transmission descriptor ring is copied (COPY) in the transmission DMA state table. Therefore, the AAL processing unit 21 reads out 48 bytes of data from the transmission data buffer indicated by the pointer of the transmission DMA status table and transmits it.

Subsequently, when the 48-byte payload is transmitted, the AAL processing unit 21 updates the internal register and processes the entry of the transmission DMA status table indicated by the next entry in the band allocation table. As described above, the AAL processing unit 21 continuously transmits data according to the index of the table entry while circulating the bandwidth allocation table, and then returns to the transmitting DMA state table which is being processed again. This time, the access descriptor ring is not accessed. Only the transmitting DMA state table is accessed. Access and process At this time, the transmission DMA state table is updated with a pointer of a transmission data buffer indicating a cell to be transmitted next.

When the data is transmitted in this manner and the transmission of one transmission data buffer is completed, the AAL processing unit 21 copies the data of the next entry of the transmission descriptor ring to the entry of the transmission DMA status table to continue processing on the second buffer. do. That is, one entry of the transmission descriptor ring points to one transmission data buffer. If a packet to be transmitted requires five buffers, five transmission descriptor ring entries are required to process the packet. At this time, if the first buffer does not end in 48-byte units and 16 bytes of data remain, the AAL processor 21 processes 16 bytes of the first buffer and updates the DMA state table to store the remaining 32 bytes of data from the second buffer. Read data and process in 48 byte units.

In this way, when the processing of the last buffer forming one packet is completed and the transmission of the packet is completed, the end-of-packet (EOP) processing procedure is performed. For example, in the case of transmission according to the AAL5 type, the EOP processing procedure fills the pad and forms the AAL5 tail.

As such, when the transmission of one packet is completed, the AAL processing unit 21 clears the OWN bit of the transmission descriptor ring entry assigned to the packet, forms an transmission completion ring entry, and interrupts the host 10. Occurs. At this time, the OWN bit and the band allocation index are recorded in the transmission completion ring entry, which is used by the host to reuse the memory of the processed packet.

Meanwhile, referring to the reception process, one DMA entry of the reception DMA table is allocated according to the 10-bit VCI of the received ATM cell. One DMA entry of the received DMA table corresponds one-to-one with one of the two received pre-buffering rings, respectively.

If the received ATM cell is the first cell of the corresponding VCI, the DMA entry indicates which free buffer will be used to store the received cell. For example, after determining whether the buffer to be allocated to the DMA entry indicated by the VCI belongs to the first prebuffer ring or the second prebuffer ring, the first descriptor of the prebuffer ring is accessed, and the address of the prebuffer is copied to the DMA entry. do. The first received cell is then stored in the buffer indicated by the corresponding DMA entry.

When the next cell having the same VCI is received, 48 bytes are stored in the buffer indicated by the DMA entry without accessing the reception prebuffer ring. The DMA entry is then updated to point to the address to be stored next.

If the VCI of the received ATM cell is different from the VCI of the previous cell, the corresponding DMA entry is accessed, the start address of the prebuffer is obtained from the reception prebuffer ring, and the ATM cell is stored in the buffer.

If the above operation is repeated and the reception of any one packet is completed, the AAL processing unit 21 writes it to the reception completion ring and generates an interrupt to notify the host 10. At this time, the right is transferred to the host 10 by resetting the OWN bit of the reception descriptor and the OWN bit of the reception completion ring entry.

Although the ATM network accessor described above implements a transmission and reception buffer in a host memory, such a transmission / reception buffer may be implemented in a memory inside the network accessor, and a variety of control data formats for transmission and reception control may be used.

Meanwhile, as shown in FIG. 4, the conventional method for processing a received packet generates an interrupt every time a packet is received and notifies the host, and the NIC driver of the host processes the received packet every time an interrupt occurs. As shown in FIG. 5, when a predetermined number of packets are received or a predetermined time has elapsed after the first packet is received, an interrupt is generated to reduce the frequency of interrupts, thereby reducing the burden on the NIC driver.

FIG. 5A is a conceptual diagram illustrating a concept of generating an interrupt when a predetermined number of packets arrive, and FIG. 5B shows a predetermined time after the arrival of the first packet to be delivered to a higher layer. It is a conceptual diagram showing the concept of generating an interrupt when elapsed.

Referring to FIG. 5A, it can be seen that when K packets arrive, the AAL processing unit 21 generates an interrupt and requests the NIC driver to process the packets. However, when an interrupt occurs only when a predetermined number of packets are received as described above, there is a problem in that the packet cannot be processed if a predetermined number of packets are not formed at the end of the transmission.

In order to solve this problem, as shown in (b) of FIG. 5, a time concept is introduced into a packet batch, and when the first packet is reached, a timer is operated to interrupt an interrupt when a certain number of packets are reached or a predetermined time elapses. Occurs.

Referring to (b) of FIG. 5, when the first packet to be transmitted each time is reached, a timer is started, and when the number of received packets reaches a predetermined number K before the predetermined time, an interrupt is generated and the timer is reset. . After the first packet to be transmitted arrives and starts the timer, when a predetermined time elapses (tp? Tth), an interrupt is generated and the timer is reset regardless of the number of received packets.

FIG. 6 is a flowchart illustrating a first embodiment according to the present invention, and shows an order in which interrupts are generated when a predetermined number of packets are reached as shown in FIG.

Referring to FIG. 6, the variable n representing the number of packets received in the initialization step is initialized to 0, and the packet number K for generating an interrupt is defined. For example, if K = 5, an interrupt is generated when six packets from 0 to 5 are received (100).

Subsequently, when the packet arrives, it is determined whether the number n of received packets is greater than or equal to K, and an interrupt is generated if the number is greater than or equal to K, and then the number n of received packets is cleared to 0 (101, 102, 104, 105). .

If the number n of received packets is less than K, n is incremented by 1 and waits for the reception of the next packet (103).

7 is a flowchart of a second embodiment according to the present invention. As shown in (b) of FIG. 5, an interrupt is generated when a certain number of packets are received or a predetermined time elapses after the first packet is reached.

Referring to FIG. 7, the variable n indicating the number of packets received in the initialization step is cleared to 0, and a variable K indicating the number of packets for generating an interrupt is defined. After the timer starts, the elapsed time is represented by tp and a time variable Tth representing a reference time for generating an interrupt is defined (200).

Subsequently, when a packet is received, it is determined whether the number of received packets (n) is greater than or equal to K. When the packet is greater than or equal to K, an interrupt is generated, the timer is reset, and the number of received packets (n) is zero. Clear (201, 202, 203, 204, 205).

If the number n of received packets is less than K, it is determined whether the first packet is the first packet. If the first packet is n, the timer is started, and if not, the number of received packets is increased by one (206, 207, 208).

Subsequently, it is determined whether the elapsed time of the timer is greater than or equal to the reference time, and if greater than or equal, the interrupt is generated, n is cleared to 0, and the timer is reset. If the timer elapsed time is less than the reference time, the timer continues to run and waits for the next packet to be received (209, 210, 211).

As described above, according to the present invention, when one packet is received, the network connector does not immediately generate an interrupt to the host side, but generates an interrupt after a certain number of packets are received or a predetermined time elapses. We can reduce burden on NIC driver.

Claims (2)

At the request of the application program running in the host system, the ATM network driver controls the ATM network connector to transmit data through the ATM communication method, and the ATM network connector reassembles the received ATM cells to form a packet and then interrupts. In the ATM terminal to notify the ATM network driver through the After reassembling the received ATM cell to form a packet, if the number of formed packets reaches a predetermined number, an interrupt is generated to request processing from the ATM network connector driver. How to deal. The method of claim 1, wherein the method of processing the reassembled packets in the ATM network accessor starts a timer after the first packet to be delivered to a higher layer is reassembled, and generates an interrupt when the timer has passed a predetermined time. A method for processing reassembled packets in an ATM network connector, characterized in that the.