KR19980075417A - DDC Error Prevention Circuit and Method of Display Device - Google Patents

Abstract

The present invention relates to a display device, and, when the SCL and SDA lines are superimposed with the SCL and SDA lines for the DDC 1 / 2B of the EEPROM for automatic screen adjustment, the DDC 1 generated when the initial state of the microcomputer is low. An error correction circuit and method for preventing an error are provided.

After the initialization process, the microcomputer resets the EEPROM to reset the EEPROM to DDC 1 to maintain the normal operation.

The configuration adds a switching element to the power supply terminal of the EEPROM, and is configured to output an operation control signal of the switching element at a specific port of the microcomputer.

Description

DDC Error Prevention Circuit and Method of Display Device

The present invention relates to a display device, and more particularly, in a display device that provides a DDC 1 scheme and a DDC 2B scheme when exchanging information of a display apparatus with a computer, it is possible to prevent a defective DDC operation due to an initial state of a microcomputer. DDC error correction circuit and error correction method.

A general display device is a representative peripheral device of a computer that forms and displays an image so that a user can recognize a signal transmitted from the computer.

The basic configuration of the internal circuit will be briefly described with reference to FIG. 1.

As shown, a video card 10 mounted in a computer (not shown) for providing color signals (R, G, B) and horizontal / vertical synchronization signals (H_Sync / V_Sync) necessary for image formation, and the video The microcomputer 20 generates a screen control signal for controlling the monitor screen by receiving the horizontal / vertical sync signal from the card 10, and receives the horizontal sync signal H_Sync and the vertical sync signal V_Sync, respectively, and receives the CRT ( The electron beam generated by the electron gun of 80) is deflected in order from the upper left to the lower right of the CRT 80 by deflection yoke (DY) to perform horizontal and vertical deflection so as to form an image like a picture. An anode of the CRT 80 using a deflection circuit 30 and a horizontal deflection circuit 40 and a retrace pulse generated from an output terminal of the horizontal deflection circuit 40 using the principle of switching circuitry and high voltage technology. To A high voltage circuit 50, which is a device for supplying a voltage, and a video preamplifier 60 that maintains a constant voltage level by amplifying low image signals R, G, and B transmitted from the video card 10 by a low voltage amplifier. And a video main amplifier 70 for supplying energy to each pixel by amplifying the amplified signal through the video preamplifier 60 to a signal of 40V _pp to 60V _pp .

On the other hand, there are two methods of transferring such horizontal and vertical synchronization signals and video signals from a computer or other data processing apparatus to a display device. First, as shown in FIG. 2A, a video signal line and a sync signal line of R, G, and B are all put in one cable and transferred. At this time, the signal transmitted to each pin of the connector may vary slightly depending on the display manufacturer.

The other is that the R, G, B video signal lines and the horizontal / vertical sync signals are transmitted through one cable as shown in FIG. 2B.

Here, the D-Sub method is used to run an operating system (OS) program that operates a computer because the high-frequency characteristic is weak, and the BNC is used to increase the resolution in a high frequency band and is mainly used when using a program such as CAD. do.

Meanwhile, a function of exchanging information with a computer using a D-Sub method is called a display data channel (DDC). By transmitting various information about the monitor you are using to your computer, it is the function that your computer displays the screen optimized for your monitor even if you do not have knowledge about the monitor you are using.

Most average computer users are able to support the resolution of their monitors and have little knowledge of what resolution is appropriate for their current software. Therefore, even software that requires high resolution screens such as CAD or games is not fully utilized even if a user has a high-performance monitor because the user does not have the knowledge of the resolution and the ability to convert and display the resolution directly.

However, if the DDC is supported, the monitor sends its information (EDID) to the computer, and the computer receives the information and automatically displays the optimal screen within the range supported by the monitor, no matter what software you use. . Therefore, the user can use the optimal state.

Information sent from the monitor to the computer (called EDID) includes the manufacturer's ID, which represents the manufacturer, the product ID, which indicates the model name of the product, whether the DPMS (Display Power Management Signaling) feature is supported, the CRT characteristics, and support It consists of Timing.

According to the method of transmitting the information about the monitor (EDID) to the computer, it is divided into DDC 1 and DDC 2B. That is, the monitor transmits its data to the computer, but it is divided into DDC 1 and DDC 2B depending on how it is to be transmitted.

First, the DDC 1 method is a bit from the monitor to the computer through the signal cable # 12 pin by 1 bit in accordance with the vertical synchronization signal (V-Sync) transmitted from the computer through the # 14 pin of the D-Sub signal cable as shown in FIG. Send the data. As long as V-Sync is inputted, 128 bytes of EDID information are continuously sent out.

In the DDC 2B method, as shown in FIG. 3B, the computer requests to send data to the monitor through pins # 12 and # 15 of the signal cable. Only then does the monitor send EDID data to the computer through signal cable # 12. If the computer determines that it has received enough data and sends a stop signal to the monitor, the monitor will stop transmitting.

Most DDC data monitors support both. In some cases, a microcomputer internal block is used to support DDC 1 / 2B in a monitor, but in most cases, a DDC 1 / 2B dedicated IC is implemented as shown in FIG. 4.

The data signal SDA is transmitted through pin # 12 of the D-Sub cable and the clock signal SCL is transmitted through pin # 15. The transition from the DDC 1 method to the DDC 2B method is performed while the SCL line # 15 goes low.

Once switched to DDC 2B, it does not return to DDC 1 until the monitor power is reset.

On the other hand, when storing the factory-adjusted image data in an externally mounted EEPROM (Electric Erasable Programmable Rom), the # 12 and # 15 of the signal cable are used by using the microcomputer clock signal (SCL) and data signal (SDA) lines. Communicate by pin to save data.

Thus, as shown in FIG. 5, the data line and the clock line of the DDC 1 / 2B overlap the data and clock lines of the microcomputer.

In this case, when the microcomputer is reset at power on, when all the ports are kept low, the clock signal (SCL) of the EEPROM overlapped with the microcomputer clock signal (SCL). It will be kept low.

Therefore, the EEPROM switches to DDC 2B mode because the clock signal SCL is changed to low. Therefore, as the power on reset state of the microcomputer is determined to be low when the monitor is powered on, the operation of the DDC 1 becomes impossible.

This operation process will be described in more detail using the waveform diagram shown in FIG. 6.

FIG. 6A shows that the operating voltage of the EEPROM is secured at power on, and FIG. 6B shows that the microcomputer has not completed the power on reset operation process until then.

If the power on reset is completed within the time of 8 ~ 10 의 of the microcomputer, all the ports are kept in the low state for about 12 후 and then normal operation starts when the port initialization is completed.

The problem is that with a low state for about 12 ms, the EEPROM, which is already ready for operation, will perform a mode switch. That is, the execution of the high-to-low mode switching of 12 s causes high-to-low switching of the clock signal SCL line, resulting in an error of DDC1.

In other words, when the EEPROM in the DDC1 state changes the mode for 12 s during the initial operation reset of the microcomputer, it is determined that the EEPROM is switched to the DDC 2B and an error of the DDC 1 occurs.

This is a problem that occurs when all ports of the microcomputer's power-on state are low and the data signal SDA and the clock signal SCL of the EEPROM are connected.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and an object thereof is to correct a DDC1 error by forcibly resetting an EEPROM after a power on reset of a microcomputer.

The present invention for achieving the above object is to connect the switching element (Tr) to the power supply terminal of the EEPROM, the switching to switch the switching element (Tr) once through a specific port after the microcomputer starts normal operation Characterized in that configured to deliver the output signal of the specific port of the microcomputer to the device.

1 is a block diagram showing a configuration of a general display device;

2 is a cross-sectional view illustrating a signal line connecting a computer system and a display device;

3 is a block diagram showing a DDC transmission method between a computer system and a display device;

4 is a configuration diagram showing a connection method of a dedicated IC according to the DDC transmission method;

5 shows that the data and clock lines of the EEPROM and the microcomputer are overlapped.

Diagram,

6 is a waveform diagram of an EEPROM and a microcomputer operating voltage;

7 is a circuit diagram showing a configuration of a DDC error correction circuit according to the present invention;

8 is a flowchart illustrating the process of the present invention.

Hereinafter, with reference to the accompanying drawings will be described the operation of the configuration and configuration of the present invention.

7 is a circuit diagram illustrating a wiring structure for correcting a DDC error according to an embodiment of the present invention.

As shown, the D-sub signal cable (1) and the signal cable for receiving the color signals (R, G, B) and the synchronization signal (H / V Sync) from the computer to exchange information using a specific pin Pin # 12 of (1) connects EEPROM (2) to receive data signal (SDA) and pin # 15 to clock signal (SCL), and # 12 pin and # 15 pin of signal cable (1) Exchanges a clock signal and a data signal and outputs an output signal capable of resetting the EEPROM 2 to a specific port, and a control signal provided through a specific port of the microcomputer 3. And a switching element Tr, which is received at the base end and configured to output the EEPROM control signal to the collector end.

Operation of the present invention configured as described above proceeds as follows.

As the power is applied, the EEPROM 2 maintains its normal operating voltage within 8-10 kHz. The microcomputer 3 keeps all the ports low for 12 ms when the power on reset is completed.

The EEPROM 2 is switched to the DDC 2B mode. The microcomputer 3 outputs the drive control signal of the switching element Tr instantaneously to a specific port after the reset is completed.

This signal is transmitted to the base end of the switching element Tr. Accordingly, the switching element Tr is turned on instantaneously. Therefore, the power supply Vcc provided to the power supply terminal of the EEPROM 2 is momentarily cut off, and accordingly, the EEPROM 2 is reset to return to the initial state DDC 1 state.

8 is a flowchart illustrating the process according to the present invention.

The EEPROM 2 maintains a normal operating voltage upon application of power. Until this time, the microcomputer has not completed the initial process for normal operation. (S1 course)

When the microcomputer 3 completes the power-on reset process for about 8 to 10 ms, all ports are set low for about 12 ms to perform port initialization. (S2 course)

Accordingly, the EEPROM 2 transitions from the initial DDC 1 state to the DDC 2B state. (S3 course)

After commencing port initialization and starting normal operation, the microcomputer 3 outputs a drive signal of the switching element Tr through a specific port. (S4 course)

In response to the driving signal of the microcomputer, the switching element Tr is temporarily turned on and the power supply to the EEPROM 2 is temporarily suspended. (S5 course)

When the power supplied to the base end of the switching element Tr is cut off and the switching element Tr returns to the turn-off state, the power supply of the EEPROM 2 is resumed. (S6 course)

Upon resumption of power supply, the EEPROM 2 enters the initial state of DDC 1 mode. (S7 course)

Once again the present invention is summarized and described by adding a switching element to the power supply terminal of the EEPROM (2) to control the On (On) / Off (Off) of the switching element in the microcomputer (3). That is, after the microcomputer 3 starts the normal operation, the Vcc of the EEPROM 2 is switched and reset once to maintain the normal DDC 1 operation.

When the SCL and SDA lines overlap with the SCL and SDA lines for DDC 1 / 2B of the EEPROM by automatic screen adjustment, the EEPROM is reset to DDC 1 by resetting the EEPROM after the normal operation of the microcomputer. It has the effect of maintaining operation.

Claims (2)

In a method of performing information exchange using a D-Sub cable between a display device and a computer that simultaneously support the DDC 1 (Display Data Channel) method and the DDC 2B method, It is configured by connecting a switching element to the power supply terminal of the EEPROM that stores information such as product specifications of the display device.After the microcomputer starts normal operation, the switching element is connected once by using one of the microcom output ports. A method of compensating for a DDC error, wherein the EEPROM, which has been converted to DDC 2B according to the initialization process of the microcomputer, is restored to DDC 1 by switching and forcibly reset. A memory device (EEPROM) for storing product specification information such as the manufacturer of the display device and the characteristics of the CRT; A switching element Tr connected to a power supply terminal of the memory device EEPROM; The control signal transmitted from the computer is provided through the D-Sub cable, and after the normal operation is started, it is forced by switching the power supply of the EEPROM once to control the switching operation of the switching element Tr using a certain port. DDC error correction circuit consisting of a microcomputer to reset.