KR19980065942A - Interface circuit and method between the central processing unit and peripheral devices of independent bus type - Google Patents

Abstract

The present invention relates to a circuit and an interface method for more efficiently interfacing between a bus-type central processing unit and peripheral devices. The present invention relates to a central processing unit having a separate address bus and data bus, a peripheral device having a bus in which the address bus and data bus are used in the same manner, an address bus of the central processing device and a bus of the peripheral device. Control means connected to each other and between the data bus of the central processing unit and the bus of the peripheral device to control the first buffer and the second buffer, and the first buffer and the second buffer to be complementarily enabled. An interface circuit is provided.

Description

Interface circuit and method between bus-based central processing unit and peripheral devices

The present invention relates to a circuit for interfacing between a central processing unit and a peripheral device of a bus type independent of each other, and an interface method thereof.

In general, a central processing unit (CPU) is composed of a computing device and a control device, and is a key component in a system using a computer, such as controlling data processing operations such as arithmetic operations or logical operations, and controlling input / output operations. to be. Such a central processing unit has been designed and manufactured to have a unique form for each manufacturer, and peripheral devices connected thereto have been manufactured in a form that can be independently connected. For example, Motorola, a leading processor manufacturer, designs and manufactures peripherals that are suitable for interfacing to their central processing units, and Intel is similarly suitable for interfacing to their central processing units. Are designed and manufactured.

On the other hand, if you want to use the central processing unit and peripheral devices that exist independently of each other to interlock with each other, an appropriate interface method should be taken. For example, in order to link peripheral devices manufactured by Intel to a CPU manufactured by Motorola, an appropriate interface method is required accordingly. Because CPUs and peripherals manufactured by Intel use the same address bus and data bus, CPUs and peripherals manufactured by Motorola use address bus and data. This is because buses are used separately.

Therefore, in order to interface peripheral devices using the same address bus and data bus to the central processing unit using the address bus and the data bus separately, a corresponding interface method is required.

Accordingly, an object of the present invention is to provide a circuit and a method for interfacing a CPU and a peripheral device using an independent address / data bus method.

Another object of the present invention is to provide a circuit and method for interfacing peripheral devices using the same address bus and data bus to a central processing unit using the address bus and data bus separately.

To achieve these objects, the present invention provides a central processing unit having a separately divided address bus and a data bus, a peripheral device having a bus in which the address bus and the data bus are used identically, an address bus of the central processing unit, Connected between the bus of the peripheral device and between the data bus of the CPU and the bus of the peripheral device so that the first buffer and the second buffer, and the first buffer and the second buffer are complementarily enabled. Provided is an interface circuit comprising a control means for controlling.

1 shows a configuration of an interface circuit according to the present invention.

2 is a diagram showing the configuration of a block for generating a signal for controlling the operation of the buffer shown in FIG.

3 is a diagram illustrating a timing at which a central processing unit and a peripheral device interface with each other according to the present invention.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, the terms to be described below are terms defined in consideration of functions in the present invention, which may vary according to the intention or custom of the user or chip designer, and the definitions should be made based on the contents throughout the present specification.

Referring to FIG. 1, it can be seen that the interface circuit according to the present invention includes a central processing unit (CPU) 10 that uses data bus data and address bus addr separately. The data bus data and the address bus addr of the CPU 10 are connected to one side of the first buffer 12 and one side of the second buffer 14, respectively. The other side of the first buffer 12 and the second buffer 14 is connected to a peripheral through one address / data bus addr / bus. At this time, the control signal BCN is applied to the OE terminal of the first buffer 12, and the control signal BCN inverted through the inverter 16 is applied to the OE terminal of the second buffer 14. Therefore, the first buffer 12 and the second buffer 14 are mutually enabled in response to the input of the control signal BCN. For example, when the high level control signal BCN is applied, since the high level is applied to the OE terminal of the first buffer 12, the first buffer 12 is not enabled, but instead, the inverter 16 is applied to the OE terminal of the second buffer 14. Since the low level control signal BCN is applied, the second buffer 14 is enabled. On the other hand, when the low-level control signal BCN is applied, the first buffer 12 is enabled and the second buffer 14 is not enabled.

FIG. 2 is a diagram illustrating a configuration of a processing block for generating a control signal BCN for controlling complementary enable operations of the first buffer 12 and the second buffer 14 shown in FIG. 1.

Referring to FIG. 2, the control signal BCN generation block includes a series of D flip flops 20, 22, 24, two inverters IV1, IV2, and an end gate 26. As the D terminal of the first flip-flop, an address strobe signal AS (Address Strobe) to which the CPU 10 is applied to use the address bus is applied. This AS signal is also applied to one input terminal of the AND gate 26 via inverter IV2. The other terminal of the AND gate 26 is connected to the Q terminal of the second flip-flop 22, and the Q terminal of the third deflip-flop 24 is connected. CLK provided from the CPU 10 is applied to the clock terminals of the first flip-flop 20 and the third flip-flop 24, and an inverted clock CLK is applied to the clock terminals of the second flip-flop 22.

FIG. 3 shows a clock CLK applied to the clock terminals of the first and second flip-flops 20 and 24 from the CPU 10 shown in FIG. 2, and an address strobe signal AS is applied to the D terminals of the first dip-flop 20. In this case, the timing for generating the buffer control signal BCN for enabling the first buffer 12 and the second buffer 14 to be complementary is shown.

As described above, the present invention provides a data bus of the central processing unit simply by providing a first buffer and a second buffer between the central processing unit and peripheral devices having independent bus methods and controlling the enable operation of the buffers. There is an advantage of interlocking the bus of the peripheral device and the bus of the peripheral device and the address bus of the central processing unit.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

Claims (3)

A circuit for interfacing a central processing unit and a peripheral device having independent bus methods, comprising: a central processing unit having separate address buses and data buses; and a bus having the same address bus and data buses. A first buffer, a second buffer, and a first buffer connected between a peripheral device, an address bus of the central processing unit and a bus of the peripheral device, and a data bus of the central processing device and a bus of the peripheral device, respectively. And control means for controlling the second buffer to be complementarily enabled. 2. The apparatus of claim 1, wherein the control means enables the first buffer when the strobe signal for using the address bus is applied from the central processing unit so that the address bus of the central processing unit and the bus of the peripheral device are mutually separated. Interface circuit characterized in that the connection. A method of interfacing between a central processing unit having separate address buses and data buses, and peripheral devices using the address and data buses as the same bus, the method comprising: And interfacing between the central processing unit and the peripheral device by complementarily enabling between buses and between the data bus of the central processing unit and the bus of the peripheral device.