KR19980065477A - Modular Multipliers for Digital Signatures - Google Patents

Abstract

The present invention relates to a modular multiplication apparatus for digital signature, comprising: P = 2 ²ⁿ mod N calculator; T = A · B · 2 ⁻ⁿ mod N calculation unit; And a calculation unit for calculating P · T · 2 ⁻ⁿ mod N = A · B mod N by inputting P and T.

According to the present invention, the modular multiplication apparatus for the digital signature can be quickly calculated in hardware A · B mod N, can be provided as a device that can be used in the device for the generation and verification of the digital signature. It can also be used in devices that encrypt / decrypt by electronic signatures, authentication, encryption / decryption hardware devices based on IC cards, or electronic signature devices that perform modular multiplication.

Description

Modular Multiplication Units for Digital Signatures

The present invention relates to a modular multiplication apparatus for digital signatures, and more particularly, to an apparatus for performing modular multiplication necessary for digital signatures.

Digital signature refers to a technology that enables electronic documents to provide a function of directly signing a conventional paper in electronic exchange of information. Types include the International Organization for Standardization (ISO) / the International Electrotechnical Commission (IEC) 9796, the ElGamal variant of the United States Digital Signiture Standard (DSS), Russia's Ghost (GOST) and Korea's KC-DSA (KC-DSA) are the standard. To implement the digital signatures, a modular power operation is required, and the modular power requires a modular multiplication of A · B · 2 ⁻ⁿ mod N and A · B mod N. Among algorithms proposed for performing the modular multiplication, Montgomery algorithm is known to be the most efficient in terms of computational efficiency.

In general, in order to calculate A · B mod N, it is necessary to estimate the quotient of division and A · B, but the Montgomery algorithm does not require division and quotient estimation. The Montgomery algorithm is as follows.

For numbers A, B, and N, which are each n bits, A and B are A = an-1 · 2 ^n-1 + ··· + a1 · 2 + a0, B = bn-1 · 2 ^n-1 + When expressed as + b1 · 2 + b0, an algorithm for obtaining T = A · B · R ⁻¹ mod N can be expressed as follows.

When T = A · B · R ⁻¹ mod N = (A · B + M · N) / R,

M = A · B · N 'mod R = mn-1 · 2 ^n-1 + ··· + m1 · 2 + m0

However, m _i ∈ {0,1}, 0 ≦ _i ≦ ⁿ −1, R = 2 ⁿ , and N ′ are values satisfying RR ⁻¹ -NN ′ = 1. According to Equation 1, T can be written as follows.

T = (an-1 · 2 ⁻¹ + an-2 · 2 ⁻² + · + a1 · 2 ^{-n + 1} + a0 · 2 ^-n )

+ (mn-1 · 2 ^-1 + mn-2 · 2 ^-2 + · + m1 · 2 ^{-n + 1} + m0 · 2 ^-n ) N

= (·· ((a0 · B + m0 · N) · 2 -1 + a1 · B + m1 · N) · 2 -1 + ·· + an-1 · B + mn-1 · N) · 2 - ^One

((A0 · B + m0 · N + 2 · a1 · B) · 2 ⁻¹ + m1 · N + 2 · a2 · B) · 2 ⁻¹ + · mn-1 · N) ^-One

With R = 2 ⁿ

Here, mi is determined according to ti, i-th bit value of T. Here, if ti is 1, mi is 1, and if ti is 0, mi is always 0.

As described above, the Montgomery algorithm is an efficient algorithm that does not require division, and it can reduce a large amount of computation required when implementing the conventional division and quotient estimation method in software, and many elements are required even when the conventional method is implemented in hardware. It can compensate for the disadvantage. In order to implement the Montgomery algorithm in hardware, the present invention enables fast modular multiplication using only a few logical combination circuits and a few registers for given and temporary values.

SUMMARY OF THE INVENTION The present invention was created to solve the above-mentioned problems, using a Montgomery algorithm that is efficient in computation, and performs modular multiplication for digital signatures using only a few logical combination circuits and a few registers to temporarily store a given temporary value. It is an object of the present invention to provide a modular multiplication apparatus for performing digital signatures.

1 shows a block diagram of a multiplication apparatus for digital signatures in accordance with the present invention.

Fig. 2 shows a block diagram of a block for obtaining A · B · 2 ⁻ⁿ mod N constituting the modular multiplication apparatus.

3 shows a timing diagram of each block for the apparatus of FIG.

4 shows an apparatus diagram for the selective adder of FIG.

FIG. 5 illustrates the NAND gate of FIG. 4.

According to the present invention for achieving the above object, the modular multiplication device for digital signature P = 2 ²ⁿ mod N calculation unit; T = A · B · 2 ⁻ⁿ mod N calculation unit; It is preferable to include a P · T · 2 ⁻ⁿ mod N = A · B mod N calculation unit.

The A · B · 2 ⁻ⁿ mod N calculation unit comprises: a register for storing an input number n of bits B and N; A shift register which stores the input n-bit number A; An n + 2 bit temporary storage register for storing the result of the T = A · B · 2 ⁻ⁿ mod N at every clock; Inputs a0 which is the least significant bit of the A register, t0 which is the least significant bit of the T register, the input value B and the input value N, and if a0t0 is 11, 2B + N, 10 is 2B, 01 is N, 00 is 0 A select adder for outputting n + 2 bits; And an adder which adds the selection adder output and the output of the T register as inputs.

The selection adder includes an adder that adds 2B and N previously calculated; A first NAND gate performing a NAND logic operation on the a0, the inverted input of t0 and the 2B; A second NAND gate performing a NAND logic operation on the inverted input of the a0, the t0 and the N; A third NAND gate performing NAND logic operation on the output of the adder and the outputs of the first and second NAND gates; And a fourth NAND gate performing NAND logic operation on the outputs of the first, second and third NAND gates.

Hereinafter, with reference to the accompanying drawings will be described in detail the operation of the present invention.

Figure 1 as showing a block diagram of a modular multiplication according to the present invention, the modular multiplication device is P = 2 ²ⁿ mod for calculating the N P = 2 ²ⁿ mod N calculation section (100), A, B, and N entered by T = a · B · 2 ^-n calculating a mod N T = a · B · 2 -n mod N calculating unit 110, to the P and T as the input P · T · 2 ^-n mod The A · B mod N calculation unit 120 calculates N = A · B mod N.

The computation block of T = A · B · 2 ⁻ⁿ mod N is composed of several registers and simple logic combination gates as shown in detail in FIG. A (200), B (210), and N (220) input to calculate A · B · 2 ⁻ⁿ mod N are n bit registers for storing A, B, and N, which are n bits, respectively. A is a shift register that shifts one bit to the right every clock. T 230 is initialized to 0 as an n + 2 bit register that stores a temporary value for every clock and replaces it with the latest value. The adder 250 adds the output of the select adder 240 and the output of the T 230 as inputs, and then temporarily stores the least significant bit of the addition result because it is always 0 and is not necessary for the intermediate calculation. It outputs n + 2 bits except the least significant bit to the register T230. As shown in detail in FIG. 4, the selective adder 240 includes n-bit NAND gates 400, 410, 420, and 430 and an adder 440. 4 illustrates the n-bit NAND gates 400, 410, 420, and 430 in detail, showing that the NAND logic operation is performed for each bit. The select adder 240 inputs the B 210 and the N 220 according to the values of a0 and t0, and if a0t0 is 11, 2B + N, 10 is 2B, 01 is N, and 00 is 0. Select and print the result. In order to prevent malfunction of circuits other than the above registers, a clock should be provided to a degree sufficient to ensure propagation delay time of the combination circuit. 3 is a timing diagram according to each operation. When all data is input to each of the registers, the value to be stored in the temporary register T 230 varies with unstable values, and stabilizes to a constant value as time passes. The value is determined by the least significant bits of the A 200 and T 230 registers. The determined value is stored in n + 2 bit sizes after discarding its least significant bit in the T 230 register at the first clock. The above calculation is repeated for n + 1 clocks.

Table 1 shows the values of A ··················· of the modulator multiplier The process of calculating B · 2 ⁻ⁿ mod N is shown.

Calculation process of A · B · 2 ^-n mod N i Ti a0 t0 Ti ' 0 0000000000 0 X 00000000000 One 0000000000 One 0 00111001010 2 0011100101 One One 01110100100 3 0111010010 0 0 00111010010 4 0011101001 0 One 00111011110 5 0011101111 One One 01110101110 6 0111010111 0 One 01011001100 7 0101100110 One 0 01100110000 8 0110011000 X 0 00110011000 9 0011001100

Here, the value of X is 0 and Ti 'is an output value of the adder 250. First, the temporary register Ti 230 is initialized to zero. The output of the select adder 240 is zero, and the adder 250 output Ti 'is also zero. When the first clock (i = 1) is input, the a0, t0 is 10, so the output of the select adder 240 is 0111001010, and the adder output 250 Ti 'is 00111001010. At this time, 0011100101 except the least significant bit is stored in the T register 230 again. When a second clock (i = 2) is input, the output of the select adder 240 is 1010111111, the output of the adder 250 becomes 01110100100 since the a0, t0 is 11 and the T register 230 0111010010 is stored except the least significant bit. In the same way as above, calculation is performed up to n + 1 clocks. As shown in Table 1 above, when n-bit input is input, A · B · 2− ⁿ mod N can be calculated using only n + 1 clocks using n + 2 bit temporary registers. Compared to estimating modular values, the number of clocks and required registers can be significantly reduced.

According to the present invention, the modular multiplication apparatus for the digital signature can be quickly calculated in hardware A · B mod N, can be provided as a device that can be used in the device for the generation and verification of the digital signature. It can also be used in devices that encrypt / decrypt by electronic signatures, authentication, encryption / decryption hardware devices based on IC cards, or electronic signature devices that perform modular multiplication. It can also be used to implement conventional public key cryptographic systems, such as NIST-DSS, Rivest Shamir Adleman, Elgarmal, and Schnorr digital signatures.

Claims (3)

In the modular multiplication apparatus for digital signature which calculates A · B mod N by inputting the numbers A, B, N of predetermined n bits, A P = 2 ²ⁿ mod N calculator for calculating P = 2 ²ⁿ mod N; T = A · B · T = A · B · 2 ^-n mod N calculation section for calculating a 2 ^-n mod N; And And a P · T · 2− ⁿ mod N calculator configured to calculate P · T · 2 ⁻ⁿ mod N by inputting P and T. The method of claim 1, wherein the T = A · B · 2 ⁻ⁿ mod N calculation unit A B register for storing the B; An N register storing the N; An A shift register which stores the A and shifts by one bit every clock; A T register composed of n + 2 bits for storing a temporary calculation result of the T = A · B · 2 ⁻ⁿ mod N every clock; Inputs a0, which is the least significant bit of the A shift register, t0, which is the least significant bit of the T register, the output of the B register, and the output of the N register, and 2B + N if a0t0 is 11, 2B, a0t0 if a0t0 is 10 Is an adder that calculates N when 01 is 0 and 0 when a0t0 is 00, and outputs n + 2 bits; And And an adder which adds the selection adder output and the output of the T register as inputs, discards the least significant bit of the addition result, and outputs the result as the temporary calculation result. The method of claim 2, wherein the optional adder An adder that adds 2B with the B calculated in advance and N; A first NAND gate performing a NAND logic operation on the a0, the inverted input of t0 and the 2B; A second NAND gate performing NAND logic operation on the inverted input of the a0, the t0 and the N; A third NAND gate performing NAND logic operation on the output of the adder and the outputs of the first and second NAND gates; And And a fourth NAND gate performing NAND logic operation on each output of the first, second and third NAND gates.