KR19980054409A - Transmission line driver circuit, output driver circuit, and ATM-LAN adapter card - Google Patents

Abstract

In order to solve the problem that the operating power supply voltage of the semiconductor integrated circuit of the ATM-LAN physical layer interface including the driver circuit can not be lowered, the output driver circuit, the output driver circuit, and the ATM- The circuit includes a CMOS output terminal composed of a first and a second pair each including a P-channel type MOS transistor and an N-channel type MOS transistor connected in series, and the P-channel type MOS transistor has a source connected to the power source line Wherein the N-channel type MOS transistor has a source connected to the line for ground voltage, the MOS transistor forming the first pair has a common drain connected to one side of the transmission terminal, and the MOS A transistor having an output circuit having a common drain connected to the other side of the transmission terminal and an output circuit having a power supply voltage and a ground voltage, And an output control circuit for performing a push-pull operation on the first pair and the second pair of the CMOS output terminals in a reverse phase is provided.

By using such a device, power supply noise and power consumption can be reduced.

Description

Transmission line driver circuit, output driver circuit, and ATM-LAN adapter card

The present invention relates to a transmission line driver circuit, an output driver circuit, and an ATM-LAN adapter card for an ATM-LAN. More particularly, the present invention relates to an output driver circuit for a semiconductor integrated circuit (IC) To a technique for enabling low-voltage operation of an IC circuit.

In general, one specification of a local area network (LAN), called Ethernet, is standardized by the Institute of Electrical and Electronics Engineers (IEEE) 802.3. Japanese Unexamined Patent Publication No. 1992/213940 discloses a driver circuit of a CMOS structure for driving a twisted pair circuit or a pair of twisted lines as a transmission medium for a medium connection unit as a transceiver suitable for such standardization.

This driver circuit has a first circuit composed of PMOS transistors and NMOS transistors connected in series and a second circuit composed of PMOS transistors and NMOS transistors connected in series. The NMOS transistors of these circuits have a source terminal coupled to a reference voltage biased to a potential above the ground potential, and the PMOS transistor of the circuit has a source terminal coupled to the supply voltage. A common drain terminal of the MOS transistor in the first circuit forms a first output terminal. The common drain terminal of the MOS transistor in the second circuit forms the second output terminal. The two output terminals are connected via an impedance functioning as a terminating resistor. The driver circuit alternately switches between the first circuit and the second circuit in a reverse phase in accordance with the input differential signal, and drives the twisted pair circuit or circuit through the first and second output terminals.

Japanese Patent Application Laid-Open No. 1992/213940 discloses that it is necessary to solve the problem of a backswing or undershooting due to the end ETD of a transmission divider signal in the driver circuit of the CMOS configuration described above. That is, if the driver circuit includes a discrete transformer, if the input of the transformer is held high by the ETD, when the ETD is turned off, the discrete transformer introduces undershoot due to the backswing into the signal by the counter electromotive force. This backswing is a meaningless signal transition in which a longer period of time is likely to be monitored as a significant signal change indicative of the beginning of transmission at the receiving end and degrades the functionality of the system operation. According to this publication, it is necessary to add a transistor that short-circuits the first output terminal and the second output terminal (the above-mentioned impedance) when the ETD is terminated in order to suppress the backswing within the allowable range, It is possible to manufacture a driver circuit of a CMOS array that conforms to the standard.

Recently, Asynchronous Transfer Mode (ATM) technology has been introduced in the LAN. ATM technology specifications are being implemented by THE ATM Forum, which was established in the United States. As LAN nodes share one transmission medium, the bandwidth available for each LAN node (determining the range of the speed at which information is transmitted) decreases as the number of LAN nodes increases. When a large number of nodes are transmitted almost simultaneously, the overall throughput is rapidly lowered. In the LAN (ATM-LAN) in which ATM technology is introduced, an ATM conversion technique capable of freely changing a band even during communication ranging from low-speed communication or communication with a small amount of information to high-speed high-band communication has been introduced and transmission / Speed transmission in which the throughput is improved by the corresponding relationship.

For the physical layer interface of the ATM-LAN, bit 0 or 1 included in the information to be transmitted is scrambled and encoded for better transmission efficiency, and each successive bit group is defined so as to define the waveform for each bit group. A template (pulse mask) has been established and standardized. For example, the transmission signal waveform specified by the template for the ATM Forum's 25 Mb / s ATM-LAN physical layer already standardized as a specification has waveforms that require relatively high precision, not just square waves. In addition, the signal amplitude defined by the template is required to be, for example, 2 V (zero to peak). When such a specification is specified, it is necessary to provide a filter at the rear end of the driver circuit for transmission used for the physical layer interface of the ATM-LAN, and to satisfy the signal waveform defined by the template in the transmission signal waveform . It is also necessary to provide a resistor for adjusting the output impedance at the rear end of the driver circuit so as to achieve impedance matching of the transmission line.

The output signal from the driver circuit described above is expected to cause a voltage loss or a voltage drop due to the filter or the impedance. Therefore, the power supply voltage of the driver circuit needs to be a relatively high level that can satisfy the signal amplitude specified by the template, Can not be set.

However, since the driver circuit functions as an output buffer and requires a relatively large current supply capability, the power consumption is increased as the power supply voltage is higher. Therefore, unless a technology for operating the driver circuit used for the physical layer interface of the ATM-LAN is established, the operation power voltage of the semiconductor integrated circuit of the physical layer interface of the ATM-LAN including such driver circuit can be lowered It became clear that there was no. In recent years, in a personal computer or an information communication terminal that has been miniaturized so that it can be carried, it is important to reduce the power consumption of the circuit in consideration of battery driving and the like. Considering that a semiconductor integrated circuit of a physical layer interface is mounted on an ATM-LAN interface card or an ATM-LAN adapter card which is applied to such a personal computer or an information communication terminal or an integrated circuit card, the low- It has been discovered by the present inventors that it has the importance of including low power consumption in the part of the LAN adapter card.

It is an object of the present invention to provide a technique for operating a driver circuit used in a physical layer interface of an ATM-LAN at a low voltage.

Another object of the present invention is to provide a transmission line driving circuit for an ATM-LAN physical layer capable of reducing a power supply voltage of a semiconductor integrated circuit of a physical layer interface used in an ATM-LAN system.

It is still another object of the present invention to provide an adapter card of an ATM-LAN capable of operating at a low voltage.

Other and further objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

1 is a circuit diagram showing an example of an output driver circuit in which a PMD semiconductor chip for an ATM physical layer is connected to a transmission line in a one-

2 is a block diagram showing an example of a system configuration of an ATM-LAN physical layer,

3 is a diagram showing an example of a block diagram of PMD,

4 is a block diagram of an output circuit for comparison including a series circuit of NMOS transistors;

5 is a diagram illustrating a template for 1-bit successive data repetition described in ATM_Forum / 94-1008R5,

6 is a diagram illustrating a template for repeating 2-bit continuous data described in ATM_Forum / 94-1008R5,

7 is a diagram illustrating a template for 3-bit continuous data repetition described in ATM_Forum / 94-1008R5,

8 is a diagram illustrating a template for repeating 4-bit continuous data described in ATM_Forum / 94-1008R5,

9 is a diagram illustrating a template for repeating 5-bit continuous data described in ATM_Forum / 94-1008R5,

10 is a diagram showing an example of an equivalent circuit of a filter satisfying a transmission waveform defined by a template,

11 (A) and 11 (B) are explanatory diagrams showing a return loss,

12 is a layout diagram of a MOS transistor forming the output stage of the output driver circuit,

13 is a sectional view taken along the line a-a in Fig. 12,

14 is a circuit diagram showing another example of an output driver circuit for transmission having a PMD semiconductor chip for an ATM physical layer connected to a transmission line in a one-to-one correspondence;

FIG. 15 is a diagram showing an example of a delay circuit included in the output driver circuit of FIG. 14;

16 is a diagram showing an example of an output driver circuit 50 having three CMOS output stages arranged in parallel,

17 is an equivalent circuit diagram of a simulation target circuit relating to power supply noise,

18A shows a second CMOS output stage delay circuit DEL1 used in the simulation,

18B shows a second CMOS output stage delay circuit DEL2 used in the simulation,

19 (A) shows a third delay circuit for a CMOS output stage DEL3 used in the simulation,

19B shows a third CMOS output stage delay circuit DEL4 used in the simulation,

20 is an explanatory diagram showing a plurality of simulation conditions relating to a size ratio and a delay time of a transistor,

21 is an explanatory diagram showing an example of a size condition for a MOS transistor so as to obtain a size ratio and a delay time of a transistor under simulation conditions # 1 to # 6;

22 is an explanatory diagram showing an example of the transistor size ratio so as to generate the delay time set in the delay circuit under the simulation conditions # 5 and # 7 to # 10,

23A and 23B are explanatory diagrams showing an example of a power supply current waveform obtained by simulation,

24A, 24B, and 24C show a method of determining the amount of power source current noise according to the power source current waveform obtained by the simulation, and FIG. 24A shows a method of determining the amount of power source current noise 24 (B) and 24 (C)

25 is a diagram showing an example of a block diagram of an ATM-LAN;

Outline of the representative ones of the inventions disclosed in the present application will be briefly described as follows.

In the ATM-LAN, a transmission circuit (for example, the element 10 shown in FIG. 1) and a reception circuit 11 are coupled to each other via a transmission line 3 in a one-to-one relationship. The output driver circuit 50 of the transmission circuit 10 has its output circuit 21 formed of a CMOS (complementary MOS transistor). That is, the output circuit 21 has CMOS output terminals 51, 52, 57 each including a first and a second pair of p-channel type MOS transistors and n-channel type MOS transistors connected in series. The source of the P-channel MOS transistor is connected to the power supply voltage Vdd, and the source of the N-channel MOS transistor is connected to the ground potential Vss. The common drain of the MOS transistors constituting the first pair is connected to one of the transmission terminals TxA and the common drain of the MOS transistors constituting the second pair is connected to the other transmission terminal TxB. The output control circuit 20 for controlling the output circuit uses the power supply voltage and the ground voltage as the operating power source, and performs the push-pull operation on the first pair and the second pair of the CMOS output terminal in opposite phases. A pair of transmitting terminals of the output driver circuit are coupled to resistors 33 and 34 for adjusting the output impedance, which are coupled to the input terminal of the filter 35 for shaping the transmission signal waveform. The output terminal of the filter is coupled to the primary side of the transformer 36 (the secondary side of the transformer is coupled to the transmission line). As a result, a transmission line driving circuit for the ATM-LAN physical layer is formed in which the transmission circuit is connected to the reception circuit through a transmission line in a one-to-one correspondence.

Since the CMOS output terminal is used for the output circuit 21 of the output driver circuit 50 for transmission, the gate-source voltage of the P-channel MOS transistor connected to the power supply voltage side when in the ON state depends on the voltage of the transmission terminal And is substantially at the level of the power supply voltage. This can reduce the ON resistance of the MOS transistors Q1, Q3, Q5, Q7, Q9, and Q11 on the power supply voltage side constituting the output circuit as compared with the output circuit that performs the push-pull operation on the NMOS transistors connected in series. Therefore, not only the operating voltage of the output driver circuit is reduced, but also the operating power supply voltage of the internal circuit constituting the semiconductor integrated circuit chip 9 for ATM-LAN physical layer control including the output driver circuit can be lowered.

As described above, the output circuit 21 is formed in the CMOS configuration to reduce the on-resistance of the MOS transistor of the configuration. Thus, for example, 25 Mb / s (megabits per second) of the transistor described in ATM_Forum / 94-1008R5 In the configuration of the system using the filters 35 and 45 and arranging the resistors 33 and 34 for adjusting the output impedance to provide the desired transmission signal waveform defined by the template for the physical layer of the ATM-LAN, The signal amplitude specified by the template can be obtained at a power supply voltage of 3.3 [V], which is lower than 5 [V]. The formation of the output circuit 21 of the CMOS configuration in this way is performed by the operation power of the semiconductor integrated circuit chip 9 such as the PMD semiconductor chip applied to the ATM-LAN physical layer of 25 Mb / s described in ATM_Forum / 94-1008R5 It is optimal to reduce the voltage. In this way, even if the winding ratio between the primary coil and the secondary coil of the transformer 36 is set to 1: 1, the output signal amplitude satisfying the template can be easily obtained. Therefore, It is not necessary to increase the number of windings of the secondary winding of the transformer 36 until such time. This also contributes to low power consumption of the semiconductor integrated circuit chip 9 for ATM-LAN physical layer control.

The transformer has an inductance of 1 mH or more, a series resistance of 5 Ω or less, a coupling coefficient of 0.999 or more, an equivalent capacitance of 5 pF or less, and a frequency band of 12 KHz to 16 MHz.

The PMOS transistors Q1, Q3, Q5 and Q7 constituting the output terminal of the output driver circuit 50 of the semiconductor chip 9 are turned off when the supply of power to the semiconductor integrated circuit chip 9 for ATM- , Q9, and Q11 are not supplied with the power supply voltage Vdd but are in a floating state. In the ATM-LAN, since the transmission circuit and the reception circuit are connected to the transmission line in a one-to-one relationship as described above, even when the N-type well region is in the floating state, the PMOS transistors Q1, Q3, Q5, and Q7 Q3, Q5, Q7, Q9 and Q11 do not flow into the N-type well at the drain, and the PMOS transistors Q1, Q3, Q5, Q7, Q9 and Q11 are destroyed There is no worry. However, when an output driver circuit of a CMOS format is applied to an Ethernet in which output terminals of a plurality of output driver circuits are commonly connected to one transmission line, when the N-type well region of an arbitrary node output driver circuit is in a floating state, There is a possibility that a high level is supplied to the N-type well region of the floating in the output operation of the floating gate. Therefore, when the output terminal of the output driver circuit of the net is formed of CMOS, a large current flows from the drain to the N-type well, which may destroy the PMOS transistor.

The current supply capability (transistor size) of the MOS transistor constituting the CMOS output terminal of the output driver circuit 50 becomes relatively large due to its function as an output circuit. In addition, two or more CMOS output stages each having first and second pairs are provided in parallel, and first timing control means 54 for shifting the timing of the push-pull operation at each stage is connected to the output control circuit 20 use. As a result, the change rate of the current per unit time in the supply line of the supply voltage Vdd to the CMOS output terminal and the supply line of the ground voltage Vss can be reduced, and power supply noise can be reduced.

The second timing control means (for example, elements of (80), (81), (82), and (83) in FIG. 16) for delaying the turn-on operation of the MOS transistor constituting the CMOS output terminal as compared with the turn- And is employed in the control circuit 20. This reduces the through current flowing in the CMOS output stage in the transient response. Also in this respect, the present invention contributes to reduction of power supply noise and low power consumption.

The size between the MOS transistors constituting the first CMOS output stage 52 and the size between the MOS transistors constituting the second CMOS output stage 51 and the size of the third CMOS output stage 57, The ratio of the sizes of the MOS transistors constituting the MOS transistor is approximately 1: 2.5: 6.25. The turn-on operation of the MOS transistor included in the second CMOS output terminal is delayed by approximately 3 ns for the turn-on operation of the MOS transistor included in the first CMOS output terminal, and the delay for delaying the turn- The means (80, 81, 82, 83) are employed in the output control circuit (20). This configuration can significantly reduce the power source noise.

The ATM-LAN adapter card 200, which is an IC card that is mounted on a terminal device and is connected to a transmission line and performs interface control of the ATM-LAN between a terminal device connected to the terminal device via a transmission line and another terminal device, An ATM-LAN physical layer control chip 9 having a transmitting circuit 10 and a receiving circuit 11 for the LAN physical layer, resistors 33 and 34 for adjusting the output impedance of the transmitting circuit, A coupling transformer 36 for transmitting the output of the filter to the transmission line 3 and a coupling circuit for transmitting the reception signal from the transmission line 4 to the reception circuit 11, Control circuits 202, 203, 204, and 205 for performing protocol processing of transmission and reception for the transformer 47 and the ATM-LAN are provided on the card substrate 201. [ The output driver circuit 50 can be employed for the transmission circuit 10 of the ATM-LAN physical layer control chip. The output driver circuit 50 includes an output circuit 21 and an output control circuit (20 in Fig. 16). The output circuit 21 includes a plurality of CMOS output stages each of which is composed of first and second pairs of a P-channel type MOS transistor and an N-channel type MOS transistor connected in series, and the P-channel type MOS transistor The source of the N-channel type MOS transistor is coupled to the ground voltage Vss and the common drain of the MOS transistor constituting the first pair is connected to one of the transmission terminals TxA And the common drain of the MOS transistor constituting the second pair is connected to the other transmission terminal TxB. Since the output control circuit uses the power supply voltage and the ground voltage as the operation power source, the first pair and the second pair of the CMOS output terminals perform the push-pull operation in opposite phases, and the timing of the push-pull operation of each CMOS output terminal is shifted The turn-on operation of the MOS transistor at a predetermined CMOS output terminal is delayed as compared with the turn-off operation.

PMD _ @ (Physical Medium Dependent) The semiconductor chip 9 satisfies the transmission signal waveform defined by the template for the physical layer of 25 Mb / s ATM-LAN specified in ATM_Forum / 94-1008R5 by the operating power of 3.3 [V] The power consumption of the ATM-LAN physical layer control chip 9 can be suppressed to a low level of about 200 mW, for example. Since the ATM-LAN physical layer control chip 9 is the portion of the ATM-LAN adapter card 200 having the largest power consumption, if the power consumption of the ATM-LAN physical layer control chip 9 can be reduced to about 200 mW, The overall power consumption of the LAN adapter card 200 can be reduced to about 1 watt.

BRIEF DESCRIPTION OF THE DRAWINGS Fig.

System configuration of ATM-LAN physical layer

2 shows an example of the system configuration of the ATM-LAN physical layer. ATM-LAN is a type of LAN before transmission line. LANs of all types of transmission lines connect only one node to each transmission line and collect it on the hub and exchange it. 2, (1), (1a to 1i) are terminal devices such as personal computers or work stations, (2) (2a to 2i) are ATM-LAN interface circuits provided one- (3) (3a to 3i), 4 (4a to 4i) are transmission lines, (5) are transmission lines 3 and 4 are ATM hubs, and (6) and (7) are high-speed transmission cables.

The ATM-LAN interface circuits 2 (2a to 2i) and the hub 5 are connected to a semiconductor chip (hereinafter simply referred to as a PMD semiconductor chip) 9 for a PMD (Physical Media Dependent) Each of the PMD semiconductor chips includes a transmitting circuit 10 and a receiving circuit 11. The PMD semiconductor chip 9 of the ATM-LAN interface circuit 2 (2a to 2i) and the PMD semiconductor chip 9 of the ATM hub 5 are connected to each other via the transmission line 10 3, and 4, and is connected to the input of the other receiving circuit 11. [ Although not shown, the transmission lines 3 and 4 are connected to the transmission circuit 10 and the reception circuit 11 via a transformer (coupling transformer) having an ultra-wideband characteristic.

The ATM hub 5 includes a switch matrix 12 as an ATM exchange and a multiplexing / demultiplexing device 13 for performing transmission between hubs at high speed in addition to a plurality of PMD semiconductor chips 9. Another hub or router (not shown) similar to the hub 5 is connected to the high-speed transmission cables 6 and 7 coupled to the multiple separation apparatus 13. As is clear from the figure, the ATM-LAN does not collide with the output data because transmission and reception are performed in a one-to-one correspondence between the transmission circuit 10 and the reception circuit 11 in at least the physical layer.

When the user data for transmission is added to the ATM-LAN interface circuit 2 in the terminal device 1, the ATM-LAN interface circuit 2 divides the information into 48-byte sectors, A header of 5 bytes is added as header information, and a telegram is transmitted via the transmission line 3 in units of a cell having a fixed length of 53 bytes, which is the sum of 48 bytes and 5 bytes. The ATM hub 5 receives a cell transmitted from the transmission line 3 from the receiving circuit 11 and exchanges or transmits the cell at a high speed by the switch matrix 12 according to the destination header information included in the cell. Then, the cell is transmitted to the destination terminal device 1 on the receiving side. Cells arriving at the ATM-LAN interface circuit 2 for the destination terminal device on the receiving side are checked for the destination header and restored to the original user data. When the terminal device on the receiving side is not connected to the same ATM hub 5 as the transmitting side, the cell is sent out via the multiplexing / separating device 13 via the high-speed transmission cable 6.

PMD semiconductor chip

Fig. 3 shows a block diagram of the PMD semiconductor chip 9. As shown in Fig. The PMD semiconductor chip 9 is formed on one semiconductor substrate such as single crystal silicon by, for example, CMOS integrated circuit manufacturing technology. The PMD semiconductor chip 9 includes a transmission circuit 10 and a reception circuit 11. The PMD semiconductor chip 9 also includes a pair of transmission terminals TxA and TxB, a pair of reception terminals RxA and RxB, a data output terminal RxDATA A data input terminal TxDATA, a clock input terminal TxCLK, and a clock output terminal RxCLK. As an external power supply terminal, a terminal to which a power supply voltage Vdd such as 3.3 [V] is supplied and a terminal to which a ground voltage Vss such as 0 [V] is supplied is shown.

The transmission circuit 10 includes a flip-flop 25 such as a D-type latch, an output control circuit 20, and an output circuit 21. The output control circuit 20 and the output circuit 21 constitute the output driver circuit 50 on the transmission side. The data input at the data input terminal TxDATA is latched by the flip-flop 20 in synchronization with the clock signal TxCLK. The latched data is supplied to the output control circuit 20. The output control circuit 20 adds a control signal in accordance with the logic value of the data supplied thereto to the output circuit 21 so that the output circuit 21 outputs the terminal TxA as the power supply voltage Vdd and the terminal TxB as the ground voltage Vss, or drives the terminals TxA, TxB in the opposite state. Although a detailed description will be described later, the circuit configuration is considered so as to reduce the power source noise caused by the output operation of the output circuit 21 and reduce the penetration current.

The receiving circuit 11 included in the PMD semiconductor chip 9 includes an input buffer 22, a PLL circuit 23, and an output latch 24. The bias voltage VB is supplied to the reception terminals RxA and RxB from the voltage follower circuit 222 via the resistors 220 and 221. [ The signals input to the reception terminals RxA and RxB are supplied to the waveform equalizer 223 and the waveform shaping of the degraded waveform is performed on the transmission line.

The PLL circuit 23 includes a phase comparator PC 230, a frequency comparator FC 231, a signal detection circuit E-Det 232, a selector SEL 234, a charge pump C-Pump 235 and a voltage controlled oscillator VCO 236). The frequency comparator 231 forms an error signal according to the frequency difference between the clock signal input at the clock terminal TxCLK and the clock signal fed back from the voltage controlled oscillator 236. The phase comparator 230 forms an error signal according to the phase difference between the output signal of the waveform equalizer 223 and the clock signal fed back from the voltage controlled oscillator 236. The signal detection circuit 232 detects whether the output of the waveform equalizer 223 includes an effective signal component or not, for example, in accordance with the energy of the signal. The signal detection circuit 232 selects the output of the phase comparator 230 to the selector 234 when a valid signal is detected and selects the output of the frequency comparator 231 when no valid signal is detected. The charge pump 235 generates a current according to an error signal output from the selector 234, and the generated current is converted into a predetermined voltage signal by a low-pass filter in the charge pump. The voltage-controlled oscillator 236 outputs a signal having an oscillation frequency corresponding to the level of the voltage signal supplied thereto.

When the output signal of the waveform equalizer 223 is not a valid signal, the PLL circuit 23 is performing synchronization with the clock signal supplied from the clock terminal TxCLK, and then the output signal of the waveform equalizer 223 The phase lead-in can be effectively performed. When the output signal of the waveform equalizer 223 becomes valid, the output of the voltage controlled oscillator 236 becomes a clock signal synchronized with the output signal of the waveform equalizer 223. Data latch 24 latches the output signal of waveform equalizer 223 in synchronization with the output clock signal at voltage controlled oscillator 236. As a result, the received data is output at the data output terminal RxDATA and at the same time, a clock signal synchronized with it is output at the clock terminal RxCLK.

Combination of PMD semiconductor chip and transmission line

1 shows a PMD semiconductor chip 9 on the transmission / reception side connected in a one-to-one correspondence via transmission lines 3 and 4 together with a detailed example of the output circuit 21. The PMD semiconductor chip 9 for transmission and reception can selectively adopt any one of the three states of the transmission state, the reception state, and the transmission / reception state. Therefore, in the PMD semiconductor chip 9, the transmission circuit 10 and the reception circuit 11 on the same semiconductor substrate are affected by noise alternately. Particularly, since the receiving circuit 11 is easily influenced by the power source noise generated in the transmitting circuit 10, it is important to reduce the noise of the transmitting circuit 10.

1, the transmission line 3 is shown as a twisted pair consisting of (31) and (32), and the transmission line 4 is shown as a twisted pair consisting of (41) and (42). For the twisted pair, use STP (shielded 150 Ω twisted pair), UTP (unshielded 100 Ω twisted pair), FTP (unshielded 120 Ω twisted pair). The transmission terminals TxA and TxB of the transmission circuit 10 in the transmission channel between the transmission circuit 10 and the reception circuit 11 connected by the transmission line 3 are connected to the resistors 33 and 34 for adjusting the input impedance, And the primary side of the transformer 36 is coupled to the output terminal of the filter 35. [ The secondary side of the transformer 36 is coupled to one end of the transmission line 3 (31, 32) and the other end of the transmission line 3 is coupled to the primary side of the transformer 37. The secondary side of the transformer 37 is coupled to the reception terminals RxA and RxB of the reception circuit 11 and the transmission channel between the transmission circuit 10 and the reception circuit 11, (11). Similarly, in the transmission channel between the transmission circuit 10 and the reception circuit 11 connected by the transmission line 4, resistors 43 and 44 for adjusting the output impedance are connected to the transmission terminals TxA and TxB of the transmission circuit 10, And the primary side of the transformer 46 is coupled to the output terminal of the filter 45. [ The secondary side of this transformer 46 is coupled to one end of the transmission line 4 (41, 42) and the other end of the transmission line 4 is coupled to the primary side of the transformer 47. The secondary side of the transformer 47 is coupled to the reception terminals RxA and RxB of the reception circuit 11 and the transmission channel between the transmission circuit 10 and the reception circuit 11, (11). The reception circuit 11 and the transmission circuit 10 of the ATM hub 5 are shown in detail only in the ATM-LAN interface 2 side in Fig. .

Configuration of output driver circuit

1, the output circuit 21 constituting the output driver circuit 50 of the transmission circuit 10 includes, for example, a second output stage 51 and a first output stage 52 connected in parallel . The third CMOS circuit includes a P-channel MOS (simply referred to as PMOS) transistor Q1 and an N-channel MOS (simply NMOS Quot;) transistor Q2, and the fourth CMOS circuit includes a PMOS transistor Q3 and an NMOS transistor Q4 connected in series. The first CMOS circuit includes a PMOS transistor Q5 and an NMOS transistor Q6 connected in series, and the second CMOS circuit includes a series-connected PMOS transistor Q5 and a NMOS transistor Q6. And includes a transistor Q7 and an NMOS transistor Q8. The source terminals of the NMOS transistors Q2, Q4, Q6 and Q8 are coupled to the ground voltage Vss and the source terminals of the PMOS transistors Q1, Q3, Q5 and Q7 are coupled to the power supply voltage Vdd. The common drain of the PMOS transistor Q1 and the NMOS transistor Q2 is coupled to the common drain of the PMOS transistor Q5 and the NMOS transistor Q6, and its coupling point is coupled to one transmission terminal TxA. Similarly, the common drain of the PMOS transistor Q3 and the NMOS transistor Q4 is coupled to the common drain of the PMOS transistor Q7 and the NMOS transistor Q8, and its coupling point is coupled to the other transmission terminal TxB.

The output control circuit 20 includes a CMOS inverter 53 for inverting the logic value of the signal Vs output from the flip-flop 25, a delay circuit 54 for delaying the signal Vs, and a logic value And a CMOS inverter 55 for inverting the inverted signal. The signal Vs is supplied to the gates of the PMOS transistor Q7 and the NMOS transistor Q8, and the output of the CMOS inverter circuit 53 is supplied to the gates of the PMOS transistor Q5 and the NMOS transistor Q6. The output of the delay circuit 54 is supplied to the gates of the PMOS transistor Q3 and the NMOS transistor Q4 and the output of the CMOS inverter circuit 55 is supplied to the gates of the PMOS transistor Q2 and the NMOS transistor Q1. When the logic value of the signal Vs changes, the delay circuit 54 makes the transient response timing of the CMOS circuit constituting the second output stage 51 different from the transient response timing of the CMOS circuit constituting the first output stage 52 . For example, a CMOS inverter of a good stage can be connected in series to obtain a desired delay time.

When the input signal Vs is at the H level (level of the power supply voltage Vdd), the NMOS transistor Q8 and the PMOS transistor Q5 are turned on and the PMOS transistor Q7 and the NMOS transistor Q6 are turned off, Current flows to the primary coil of the transformer 36. Subsequently, when the output of the delay circuit 54 becomes a high level after a predetermined delay time, the NMOS transistor Q4 and the PMOS transistor Q1 are turned on and the PMOS transistor Q3 and the NMOS transistor Q2 are turned off, The current flowing to the primary coil of the transformer 36 toward the transmission terminal TxB is further increased. When the input signal Vs is at the low level (ground voltage Vss level), the PMOS transistor Q7 and the NMOS transistor Q6 are turned on, and the NMOS transistor Q8 and the PMOS transistor Q5 are turned off, Current flows to the primary coil of the transformer 36. Subsequently, when the output of the delay circuit 54 becomes a low level after a predetermined delay time, the PMOS transistor Q3 and the NMOS transistor Q2 are turned on and the NMOS transistor Q4 and the PMOS transistor Q1 are turned off, The current flowing to the primary coil of the transformer 36 toward the transmission terminal TxA is further increased. As a result, when the input signal Vs changes into a pulse shape, a pulse voltage is generated on the primary side of the transformer 36. [ Therefore, a pulse voltage is generated on the secondary side of the transformer 36 in accordance with the winding ratio of the coil. The pulse voltage generated on the secondary side of the transformer 36 is transmitted through the transmission line 3 and the pulse voltage is applied to the reception terminals RxA and RxB of the reception circuit 11 via the transformer 37 on the reception side. The reception terminals RxA and RxB are applied with a bias voltage VB at a connection point between the resistors 220 and 221 connected in series. The pulse voltage signals input to the reception terminals RxA and RxB are waveform-shaped by the waveform equalizer 223 and fetched therein.

Sequentially driving the first output terminal and the second output terminal

In the output driver circuit 50 of FIG. 1, the timing for starting the on-off operation of the MOS transistor constituting the second output stage 51 with respect to the change of the signal Vs, Off operation, the rate of change of the current per unit time in the supply line of the power supply voltage Vdd and the supply line of the ground voltage Vss can be reduced. As a result, the power supply noise of the power supply voltage Vdd inside the PMD semiconductor chip 9 and the power supply line of the ground voltage Vss can be reduced. In the example of Fig. 1, the output stages of two stages are constituted. However, from the viewpoint of reduction of such power source noise, it is also possible to constitute the output driver circuit with three stages or more of output stages.

CMOS output stage

The output circuit 21 constituting the output driver circuit 50 of FIG. 1 was manufactured using the CMOS transistor as described above. Therefore, the gate-source voltage of the MOS transistors Q1 to Q8 is not influenced by the voltages of the transmission terminals TxA and TxB connected to the primary coil of the transformer 36. [ According to the embodiment of FIG. 1, the operating power of each internal circuit of the PMD semiconductor chip 9 becomes the power supply voltage Vdd and the ground voltage Vss. Therefore, the output circuit 21 uses the power supply voltage Vdd and the ground voltage Vss as operating power. Since the MOS transistors Q1 to Q8 of the output circuit 21 are switch-controlled by the power supply voltage Vdd or the ground voltage Vss selectively supplied to the gate, the gate-source voltage of the MOS transistors Q1 to Q8 in the ON state is controlled by the power supply voltage Vdd. This means that the on resistance of the MOS transistors Q1 to Q8 can be made sufficiently small as compared with the impedance of the transformer 36. [

On the other hand, as shown in Fig. 4, the series circuit of the NMOS transistors Q20 and Q21 which use the power supply voltage Vdd and the ground voltage Vss as the operation power supply and the series circuit of the NMOS transistors Q22 and Q23 perform the push- The gate-source voltage of the NMOS transistors Q20 and Q22 depends on the voltage of the transmission terminal TxA. When the output circuit and its control circuit are operated by a single operation power supply, when the NMOS transistors Q20 and Q22 are turned on It is not possible to add the level of the power supply voltage Vdd to the gate-source voltage of the transistor Q1. If the on-resistance of the MOS transistors Q20 and Q22 is set to be sufficiently small by setting the gate-source voltage when the NMOS transistors Q20 and Q22 are turned on to the level of the power supply voltage Vdd, the amplitude of the signal Vs is set to be equal to or higher than the power supply voltage Vdd And the operating power supply voltage of the inverter 56 must be higher than the power supply voltage Vdd.

For example, let? Be an integer defined in the configuration of the MOS transistor, W the gate width of the MOS transistor, L the gate length of the MOS transistor, VGS the gate-source voltage of the MOS transistor, Vth the threshold voltage , And VDS is the drain-source voltage of the MOS transistor, the alternating current resistance Rm of the MOS transistor is approximated by the approximate expression of the drain-source current of the MOS transistor in the non-

Rm = 1 / {? W / L VGS-Vth-VDS}

. In the case of the CMOS output circuit 21 of Fig. 1, even when the operating power of the PMD semiconductor chip 9 becomes a single operating power supply of Vdd and Vss, VGS becomes the level of the power supply voltage Vdd. therefore,

Rm = 1 / {? W / L (Vdd-Vth-VDS)}

. As a result, the ON resistance can be reduced because it is determined only by the level of the power supply voltage Vdd and the ground voltage Vss and the size of the MOS transistor. 4, it is impossible to set the gate-source voltage VGS of the NMOS transistors Q20 and Q22 to the level of the power supply voltage Vdd unless the gate voltages of the NMOS transistors Q20 and Q22 are made higher than the power supply voltage Vdd.

Therefore, when the on-resistance of the MOS transistor constituting the output circuit needs to be reduced, if the operating voltage of the internal circuit constituting the PMD semiconductor chip 9 is to be lowered, the output circuit of the output driver circuit 50 is turned off, Is required.

ATM-LAN Physical Layer Specifications

Next, a case of connecting the circuit configuration described in Fig. 1 to the specification of a specific ATM-LAN will be described. The ATM Forum, which was established in order to make ATM easy to use as a network configuration technology for users, has written technical specifications of ATM, but there is also a working group on ATM-LAN. Recently, an interface specification has been established for an ATM-LAN (a data transfer rate in a physical layer is 32 Mb / s) of 25 Mb / s (Mega-bit / sec). In particular, note the specification of the physical layer of this interface. This specification (hereinafter referred to as the "interest specification") is not yet standardized in the ATM forum.

FIGS. 5 to 9 show a template (pulse mask) described at P, 4-8 of ATM_Forum / 94-1008R5 as a draft of such a physical layer. The draft's copyright is owned by the ATM Forum. In the physical layer interface of the ATM-LAN, in order to improve the transmission efficiency, the number of consecutive bits (the number of symbols) of the logical value 0 or 1 in the transmitted information in terms of scrambling and encoding is limited to 5 symbols. The template is a standard for defining the waveform (output signal waveform of the transformer) for each symbol number of the same logic value. FIG. 6 shows a case of two symbols (repetition of two-bit continuous data); FIG. 7 shows a case of three symbols (repetition of three-bit continuous data) , FIG. 8 shows a case of 4 symbols (4-bit continuous data repetition), and FIG. 9 shows 5-symbol case (5-bit continuous data repetition). The template shown in each figure represents the relative value (%) of the time, and the vertical axis represents the relative value of the amplitude (zero-to-peak) with respect to the waveform of the number of symbols defined by the abscissa. The template defines the upper and lower limit waveforms, and the actual output waveform is in the range between the limits. The actual time of the transverse axis of the waveform defined by the template is determined by the transfer rate and the number of symbols. The actual amplitude of the vertical axis of the waveform defined by the template is determined by the relative value of the amplitude and the vertical axis that is defined according to the type of transmission line. For example, in ATM_Forum / 94-1008R5, the transmission amplitude (TLA) of the peak value (peak-to-peak) at the peak value of the transmission circuit is 2.7 [V] TLA 3.4 [V] for UTP, 3.4 [ 3.3 [V] TLA 4.2 [V] for FTP and 2.95 [V] TLA 3.75 [V] for FTP. Therefore, for each template, the relative value 1 on the vertical axis is the center value of the amplitude range of the zero-to-peak corresponding to 1/2 of the amplitude of the peak-to-peak amplitude defined by the type of transmission line It is taken.

The filters 35 and 45 shown in Fig. 1 are provided to transmit the transmission waveforms satisfying the template shown in Figs. 5 to 9 on the secondary coil side of the transformers 36 and 46. Fig. An example of an equivalent circuit of the filters 35 and 45 is shown in Fig. This filter circuit shapes the substantially rectangular pulse signal output from the transmission terminals TxA and TxB into a waveform satisfying the template.

Regarding the physical layer of ATM-LAN, ATM_Forum / 94-1008R5 also specifies the return loss of the transmitter circuit, TRL (Transmitter Return Loss). The return loss is specified to be more than 14dB in the frequency band of 1 ~ 6MHz, more than 12dB in the frequency band of 6 ~ 17MHz, more than 8dB in the frequency band of 17 ~ 25MHz. Hereinafter, the return loss will be described with reference to Figs. 11 (A) and 11 (B). To facilitate understanding, as shown in Fig. 11A, the signal source Vs, the impedance r0 of the signal source, the transformer, the transmission line, and the impedance RL of the load side are modeled, As an equivalent circuit. 11 (B), L is the inductance of the transformer, rt is the series resistance of the transformer, and k is the coupling coefficient of the transformer. kL is the inductance due to the main flux, and (1-k) L is the leakage inductance. The impedance ZL when the load side is viewed from the signal source Vs

ZL = rt + j? (1-k) L + {? ² kLL (1-k) +

j? kL (rt + RL)} / (rt + RL + j? L)

Lt; / RTI > Here,? = 2? F and f is a frequency.

Assuming that k? 1 and? L "rt + RL in the equation of the impedance ZL, the impedance ZL is

ZL? 2rt + RL

.

The return loss is defined as 10 · log (1 / P ² ), and P (reflectance) is P = | (r0-ZL) / (r0 + ZL) |. Therefore, in order to relatively easily satisfy the return loss defined by the ATM_Forum / 94-1008R3, it is preferable to use a high-performance transformer satisfying the condition of k? 1 and? L "rt + RL. Taking this into consideration, one example of a preferable specification of the transformers 36, 37, 46, 47 actually used is the inductance L = 1 mH, the series resistance rt = 5 ?, the defect coefficient k = 0.999, equivalent capacitance = 5 pF. It is also preferable that the inductance (L) is 1 mH or more, the series resistance (rt) is 5? Or less, the coupling coefficient (k) is 0.999 or more, and the equivalent capacitance is 5 pF or less.

The transformers 36, 37, 46, and 47 used for the ATM-LAN (the data transmission rate in the physical layer is 32 Mb / s) at 25 Mb / s have ultra-wideband characteristics . The lower limit of the band is defined as ATM_Forum / 94-1008R3, and the upper limit of the band is determined by the data transmission rate of the physical layer being 32 Mb / s.

Relationship between specifications of ATM-LAN physical layer and use of CMOS output stage

In order to satisfy the transmission signal waveform defined by the template for the physical layer of the ATM-LAN of 25 Mb / s described in the ATM_Forum / 94-1008R5 as described above, the filters 35 and 45 having the circuit configuration as shown in Fig. And the transmission signal from the transformer 36 ((46)) requires a signal amplitude of zero-to-peak on the order of 2V as specified by the template. In addition, the resistor 33 ((34)) for providing impedance matching on the transmission line side should be provided at the upper end of the filter 35 ((45)) so that the influence of the voltage reflection must be minimized.

Therefore, the signal output from the output circuit 21 generates a voltage loss or a voltage drop due to a filter or a resistor. Therefore, from the viewpoint of satisfying the signal amplitude specified by the template, the output signal of the MOS transistor The smaller the on-resistance, the better. As described above, in this embodiment, the output stage (the output circuit 21) is formed of a CMOS transistor (that is, the ON resistance of the MOS transistor constituting the circuit is small) It is optimal to realize the lowering of the operating voltage. Therefore, in this embodiment, the power supply voltage Vdd is set to 3.3 [V]. Since the output terminal (output circuit 21) is made CMOS, that is, the ON resistance of the MOS transistor connected to the power supply voltage Vdd side is small, the primary coil of the transformer 36 ((46) The output signal amplitude satisfying the template can easily be obtained even if the winding ratio between the secondary coils is 1: 1. In the case where the output stage is composed only of NMOS transistors, it is possible to obtain the output signal amplitude satisfying the template by increasing the number of windings on the secondary side of the transformer even if the ON resistance of the NMOS transistor is increased. However, the amount of current flowing in the output stage increases accordingly, . ≪ / RTI > The inventor of the present invention has actually obtained the result that the output driver circuit 50 is driven at the power supply voltage Vdd of 3.3 [V] to satisfy the transmission waveform of the template.

Non-destruction of PMOS transistor included in output stage

In the N-type well region of the PMOS transistors Q1, Q3, Q5, and Q7 constituting the output terminal of the output driver circuit 50 of the PMD semiconductor chip 9, power is supplied to the PMD semiconductor chip 9, The voltage Vdd is not supplied and the floating state is established. 2 and Fig. 1, since at least the physical layer of the ATM-LAN carries out the transmission and reception in a one-to-one relation, the signal from the other transmission circuit 10 is not inputted to the transmission circuit 10 . Therefore, even when the N-type well region is in the floating state, the drains of the PMOS transistors Q1, Q3, Q5 and Q7 are not supplied at a high level through the transmission line 3, There is no possibility that Q1, Q3, Q5 and Q7 are destroyed. Only the reflected signal of the signal output by the transmitting circuit 10 is input to the transmitting circuit 10. [ Reflection of the output signal can be reduced by providing impedance matching.

Latchup measures at the output stage

12 is a layout diagram of the MOS transistors Q1 to Q4 constituting the second output terminal of FIG. 12, reference numerals 60 and 61 denote N-type well regions (N-WELL), reference numerals 62 and 63 denote P-type well regions (P-WELL) 72 denotes a gate of the MOS transistors Q1 and Q2; 73 denotes a gate of the MOS transistors Q3 and Q4; and 74 and 75 denote gate and drain electrodes of the transistors Q1 to Q4, Electrode. The power supply voltage Vdd is supplied to the electrodes 74 and 75 for supplying the substrates.

13 is a cross-sectional view taken along the line a-a in Fig. As clearly shown in the figure, the electrode 74 dedicated to the substrate feeding is disposed adjacent to the P-WELL 63, and the electrode 75 dedicated to feeding the substrate is disposed adjacent to the P-WELL 62. [ In the layout of Fig. 12, the combination of transistors that are turned on simultaneously is Q1 and Q4 or Q2 and Q3, and a gradient of potential in the Y direction is generated, that is, a potential difference between N-WELL 60 and P- The potential difference between the N-WELL 61 and the P-WELL 62 becomes small. At this time, since the substrate is fed to the N-WELLs 60 and 61 via the electrodes 74 and 75 disposed adjacent to the P-WELLs 62 and 63, .

Reduced through current at the CMOS output stage

Fig. 14 shows another configuration of the output driver circuit 50. Fig. 14, the second output stage 51 constituting the output circuit 21 is connected to the MOS transistors Q1 to Q4 (Q4 to Q4) having a larger size (gate width / gate length) than the MOS transistors Q5 to Q8 constituting the first output stage 52 Respectively. The output control circuit 20 of Fig. 14 changes the output of the second output stage 51 by delaying the change of the output operation of the first output stage 52 as in Fig.

Considering that the MOS transistor size of the second output stage 51 is relatively large, the through current flowing through the second output stage 51 in the transient response is reduced. 1, the delay of the rise of the switch control signals? P1 and? P2 supplied to the PMOS transistors is set to be small (the off timing is relatively fast) for the two, (The ON timing is relatively slow), the delay of the rising change of the switch control signals? N1 and? N2 supplied to the NMOS transistor is made large (the ON timing is relatively slow), and the delay of the falling change Delay circuit 80 (81) which is small (off timing relatively fast) is used. The input of the delay circuit 80 becomes the signal Vs and the input of the delay circuit 81 becomes the output signal of the inverter 53 which is opposite in phase to the input signal Vs.

15 shows an example of the circuit configuration of the delay circuits 80 and 81. In Fig. Between the power supply voltage Vdd and the ground voltage Vss, a series circuit of the PMOS transistor Q30 and the NMOS transistor Q31, a series circuit of the PMOS transistor Q32 and the NMOS transistor Q34, and a series circuit of the PMOS transistor Q35 and the NMOS transistor Q37 are provided. Each of these series circuits operates as an inverter. An NMOS transistor Q33 functioning as a delay element or a resistance element is interposed between the MOS transistors Q32 and Q34. A PMOS transistor Q36 functioning as a delay element or a resistance element is interposed between the MOS transistors Q35 and Q37. The gates of the MOS transistors Q32, Q34, Q35 and Q37 are commonly connected to the coupling points of the MOS transistors Q32 and Q31, the gate of the MOS transistor Q33 is connected to the power supply voltage Vdd and the gate of the MOS transistor Q36 is connected to the ground voltage Vss have. In the delay circuit 80, the signal Vs is supplied to the gates of the MOS transistors Q30 and Q31. In the delay circuit 81, the output of the inverter 53 is supplied to the gates of the MOS transistors Q30 and Q31. The switch control signal? P1 (? P2) is output from the drain of the PMOS transistor Q32, and the switch control signal? N1 (? N2) is output from the drain of the NMOS transistor Q37.

In the delay circuit 80 (81), the change of the input signal Vs (the output of the inverter 53) is delayed by the two-stage series circuit inverter consisting of the MOS transistors Q30 to Q34 to generate the switch control signal? P1 ). It is delayed by the two-stage series circuit inverter composed of the MOS transistors Q30, Q31 and Q35 to Q37 and reflected in the switch control signal? N1 (? N2). At this time, the switch control signal? P1 (? P2) is delayed by the on-resistance of the MOS transistor Q33 to a large extent. In addition, the switch control signal? N1 (? N2) is delayed by the on-resistance of the MOS transistor Q36 to a greater delay than the falling transition. That is, the ON operation is delayed relative to the OFF operation of the MOS transistors Q1 to Q4 of the second output stage 51. [ Therefore, when the second output stage 51 is inverted, the serially connected PMOS transistor and NMOS transistor are not turned on at the same time, so that the through current flowing in the transient response can be reduced. Since the output circuit 21 is required to have a relatively large driving capability or current supply capability, such reduction of the through current can significantly reduce power consumption and power supply noise of the PMD semiconductor chip 9.

Parallel three-stage configuration of CMOS output

FIG. 16 shows an embodiment of an output driver circuit 50 having a CMOS output stage in a parallel three-stage configuration. The output circuit 21 of FIG. 16 is a combination of the output circuit of FIG. 14 and the third output stage 57. The output control circuit 20 of FIG. 16 is a combination of the output control circuit of FIG. 14 and the delay circuits 82 and 83.

The third output terminal 57 has a sixth CMOS circuit including a PMOS transistor Q9 and an NMOS transistor Q10 connected in series and a sixth CMOS circuit including a PMOS transistor Q11 and an NMOS transistor Q12 connected in series and the PMOS transistor Q9 , The source of Q11 is connected to the power supply voltage Vdd and the source of the NMOS transistors Q10 and Q12 is connected to the ground voltage Vss. The common drain of the PMOS transistor Q9 and the NMOS transistor Q10 is connected to one transmission terminal TxA and the common drain of the PMOS transistor Q11 and the NMOS transistor Q12 is connected to the other transmission terminal TxB.

The delay circuits 82 and 83 are configured similarly to the circuit shown in Fig.

The delay circuit 82 supplies the switch control signal? P3 to the gate of the PMOS transistor Q11 and the switch control signal? N3 to the gate of the NMOS transistor Q12. The delay circuit 83 supplies the switch control signal? P4 to the gate of the PMOS transistor Q9 and the switch control signal? N4 to the gate of the NMOS transistor Q10. The relationship between the switch control signal? P3 (? P4) for the PMOS transistor and the switch control signal? N3 (? N4) for the NMOS transistor is similar to the relationship described with reference to Fig. That is, the MOS transistors Q9 to Q12 of the third output stage 57 are arranged so that the ON operation is relatively delayed as compared with the OFF operation. The delay time formed by the delay circuits 82 and 83 becomes larger than the delay time formed by the delay circuits 80 and 81 and the operation of the third output stage 57 is delayed by the second output stage 51, Lt; / RTI > For example, when the signal Vs is changed from the low level to the high level, at the first output stage 52, the MOS transistors Q7 and Q6 are turned on and the MOS transistors Q8 and Q5 are turned off. Then, at the second output stage 51, the MOS transistors Q3 and Q2 are turned on and the MOS transistors Q4 and Q1 are turned off. Finally, at the third output stage 57, the MOS transistors Q11 and Q10 are turned on and the MOS transistors Q9 and Q12 are turned off. At this time, in the second and third output stages 51 and 57, the turn-on operation of the MOS transistor to be turned on is started later than the turn-off operation of the MOS transistor to be turned off. Therefore, it is considered that the parallel three-stage configuration of the CMOS output stage of Fig. 16 can reduce the power source noise more than the parallel two-stage configuration of the CMOS output stage of Fig.

Optimization of Transistor Size Ratio and Delay Time at CMOS Output

Next, a simulation result concerning power supply noise will be described. Fig. 17 shows a circuit in which simulation is performed. The operating power source of the circuit shown in Fig. 17 is set to the power supply voltage Vdd = 3.3 [V] and the ground voltage Vss = 0 [V]. The signal Vs is set to high level = 3.3 [V] and low level = 0 [V]. 16, MB1 = Q5, MB2 = Q6, MB3 = Q7, MB4 = Q8, MB7 = Q1, MB8 = Q2, MB9 = Q3, MB10 = Q4, MB11 = Q9, MB12 = Q10, MB13 = Q11, and MB14 = Q12. And MB5 and MB6 denote MOS transistors constituting the CMOS inverter 53 shown in Fig. 18A and 18B show the configurations of the delay circuit 80 (DEL1) and the delay circuit 81 (DEL2), respectively. 19A and 19B show the configurations of the delay circuit 82 (DEL3) and the delay circuit 83 (DEL4), respectively. The circuit shown in Figs. 18 (A), 18 (B), 19 (A) and 19 (B) is different from the transistor code in Fig. 15, but corresponds to the circuit configuration described in Fig.

20 shows simulation conditions including # 1 to # 10. The condition # 1 is different from that of FIG. 17, and the output circuit is constituted by a single-stage CMOS output stage. For example, an output circuit is formed at the first output terminal 52, although the transistor size differs from that of FIG. Conditions # 2 to # 10 show the case where the circuits shown in FIGS. 17, 18 (A), 18 (B), 19 (A) and 19 (B) are used. 17 to 19 (B), the power supply voltage Vdd is set to 3.3 [V], the ground voltage Vss is set to 0 [V], the high level of the input signal Vs is set to the power supply voltage level, Level.

Conditions # 2 to # 6 shown in FIG. 20 indicate that the delay times of the delay circuits 80 and 81 (DEL1 and DEL2) are 2 ns and the delay times of the delay circuits 82 and 83 (DEL3 and DEL4) 4 ns, and the sizes of the transistors constituting the three stages of the CMOS output stages are made different for each stage in this state. The delay time noted in this simulation refers to the delay time until the gate control signal of the PMOS transistor changes to the low level after the signal Vs changes and the delay time until the gate control signal of the NMOS transistor changes to the high level Delay time. That is, attention is paid to the delay time until the PMOS transistor or the NMOS transistor is turned on after the signal Vs changes. The delay time until the PMOS transistor or the NMOS transistor is turned off after the signal Vs changes does not actively control or pay attention to the delay time. This delay time is not particularly a problem.

B: c: d shown in the item of the transistor size ratio in FIG. 20 means the first CMOS output stage 52: the second CMOS output stage 51: the third CMOS output stage 57. Conditions # 7 to # 10 correspond to the conditions of the transistor size ratio of 1: 2.5: 6.25 (the conditions of # 1 to # 10 that the size ratio of the power source current noise is minimized as described later) The delay times of the delay circuits 80 and 81 (DEL1 and DEL2) and the delays of the delay circuits 82 and 83 (DEL3 and DEL4) Time is different. The transistor size ratio is gate width / gate length (W / L). As described above, the delay times of the delay circuits 80 to 83 (DEL1 to DEL3) depend on the delay time of the fall of the gate control signal for the PMOS transistor with respect to the change of the signal Vs input to the output control circuit, Means the delay time of the rise of the gate control signal for the transistor.

21 shows an example of the conditions of the size of each MOS transistor for obtaining the transistor size and the delay time in the conditions # 1 to # 6. For example, in condition # 8 in FIG. 20, the delay time of the delay circuits DEL1 and DEL2 is 3 ns and the delay time of the delay circuits DEL3 and 4 is 6 ns. This is because the PMOS transistor or NMOS transistor of the second CMOS output stage 51 is turned on at 3 ns after the first CMOS output stage 52 is turned off and the PMOS transistor or NMOS transistor of the third CMOS output stage 57 is turned on at the second CMOS output stage Which is turned on at 3 ns after turning on the transistor.

FIG. 22 shows an example of the transistor size ratio in which the delay time is set for the delay circuits DEL1 to DEL4 under the conditions # 5 and # 7 to # 10. The notation of W / L: MB18: 7 times stated in the remarks column of FIG. 22 means that the W / L value of the MOS transistor MB18 is 7.

In the simulation, the waveform of the power supply current Idd is obtained according to the above-described conditions. For example, FIG. 23A shows the power source current waveform when the simulation is executed under the condition # 1, and FIG. 23B shows the power source current waveform when the simulation is executed under the condition # . To evaluate the power supply noise in the power supply current waveform obtained under various conditions, as shown in Fig. 24A, during the period (t2-t1) corresponding to the transient response period of the output circuit, The evaluation value IX = ISUM / (t2 - t1) is determined by paying attention to the total amount ISUM of values. Therefore, the smaller the value of IX, the smaller the variation of the power supply current (the amount of power supply current noise) in the transient response operation of the output circuit. FIG. 24 (B) shows the evaluation values IX for the conditions # 1 to # 6. According to this, condition # 5 is the smallest amount of power supply current noise. The output voltage waveform from the transformer 36 when using the output driver circuit 50 formed under such conditions was not adversely affected thereby. The evaluation value IX obtained by the same simulation with respect to the conditions # 5 and # 7 to # 10 is shown in FIG. 24C, with the transistor size ratio of the parallel three-stage CMOS output terminal being condition # 5. According to this, condition # 8 is the smallest amount of power supply current noise. Under this condition, the output voltage waveform from the transformer 36 when using the output driver circuit 50 was not adversely affected thereby. Therefore, from the simulation results, it is demonstrated that the power source noise can be made extremely small by using the transistor size ratio and delay time of the condition # 8 in the output driver circuit 50.

ATM-LAN card

Fig. 25 shows an embodiment of an ATM-LAN adapter card. The ATM-LAN adapter card 200 is an IC card configured in accordance with the standard of PCMCIA (Personal Computer Memory Card International Association), and constitutes one example of the ATM-LAN interface circuit 2. In this ATM-LAN adapter card 200, a semiconductor integrated circuit is individually formed on a card substrate 201 having wiring on its front surface and back surface, and a microprocessor 202, a ROM 203 A RAM 204 used as a work area of the microprocessor, an ATM controller 205, a RAM 206 used for a transmission data buffer and a reception data buffer, a PMD semiconductor chip 9 as a physical layer control chip, and a filter / (207). The ATM controller 205 is constituted by an interface specification conforming to the specification of the PCMCIA, and is detachably mounted on the terminal device 1 such as a personal computer. The filter / transformer 207 is connected to a transmission line such as a twisted pair. The filter / transformer 207 is formed as a single chip including the output resistors 33 and 34, the filter 35 and the transformer 36 described in FIG. 14 and the like.

The ATM controller 205 scrambles and encodes the data supplied from the terminal device, forms cells, multiplexes them, and transmits the multiplexed data to the PMD semiconductor chip 9. Upon receiving the information received by the PMD semiconductor chip 9, the ATM controller 205 searches the destination header, and performs processing of decomposing and decoding the cell. The control of the ATM controller 205 is executed by the microprocessor 202 in accordance with the program stored in the ROM 203. [ The microprocessor 202, the ROM 203, the RAM 204, and the ATM controller 205 function as control means for controlling the transfer protocol of the ATM-LAN.

The PMD semiconductor chip 9 is a transmission which is defined by a template for a physical layer for an ATM-LAN of 25 Mb / s described in ATM_Forum / 94-1008R5 by an operating power source of 3.3 [V] Satisfies the signal waveform and also the zero-to-peak signal amplitude of about 2 V defined by the template for the transmitted signal from the transformer 36 ((46)). This can suppress the PMD semiconductor chip 9 to a low power consumption of, for example, about 200 mW. The PMD semiconductor chip 9 is the circuit portion of the ATM-LAN adapter card 200 that has the highest power consumption. According to the calculations by the present inventor, it has become clear that if the power consumption of the PMD semiconductor chip 9 can be reduced to about 200 mW, the overall power consumption of the ATM-LAN adapter card 200 can be reduced to about 1 W.

&Quot; Function and effect of the embodiment "

According to the above-described embodiment, the following operational effects are obtained.

[1] By using the CMOS output circuit 21 of the output driver circuit 50, compared with an output circuit of the type in which an NMOS transistor connected in series is operated in a push-pull operation, the ON resistance And the operating power supply voltage of the internal circuit constituting the PMD semiconductor chip 9 can be lowered.

[2] By using a CMOS output circuit including a small on-resistance MOS transistor, it is possible to satisfy a transmission signal waveform defined by a template for a physical layer for ATM-LAN of 25 Mb / s described in ATM_Forum / 94-1008R5 The signal amplitude defined by the template is set to 5 [V], which is equal to 3.3 [V], even when the filter 35 ((45) for adjusting the output impedance is provided and the resistors 33 and 44 for the output impedance are provided. Can be obtained at a low voltage. Thus, the use of the CMOS output circuit 21 is most suitable for lowering the operating power supply voltage of the PMD semiconductor chip 9 applied to the 25-Mb / s ATM-LAN physical layer described in ATM_Forum / 94-1008R5. This also makes it possible to easily obtain the output signal amplitude satisfying the template even when the ratio of the number of turns of the primary coil of the transformer 36 ((46)) to the number of turns of the secondary coil (turn ratio) is 1: It is not necessary to increase the number of turns (number of turns) on the secondary side of the transformer by increasing the operating current flowing through the circuit. Also in this respect, the use of the CMOS output circuit contributes to the low power consumption of the PMD semiconductor chip 9.

3, PMOS transistors Q1, Q3, Q5, Q7, Q9 and Q11 constituting the output terminal of the output driver circuit 50 of the PMD semiconductor chip 9 are turned off when the power supply to the PMD semiconductor chip 9 is cut off The power supply voltage Vdd is not supplied to the N-type well region, and the N-type well region becomes a floating state. In the ATM-LAN, since the transmission circuit and the reception circuit have a one-to-one relationship and are coupled by the transmission line, even when the N-type well region is in the floating state, the drains of the PMOS transistors Q1, Q3, Q5, Q7, Q9, A high level is not supplied through the transmission line 3 and a large current does not flow from the drain to the N-type well, so that there is no possibility that the PMOS transistors Q1, Q3, Q5 and Q7 are destroyed. On the other hand, when an output driver circuit of a CMOS format is applied to an Ethernet in which the output terminals of a plurality of output driver circuits are commonly connected to one transmission line, when the N type well region of the output driver circuit of a certain node is in the floating state, There is a possibility that the N-type well region of the floating is supplied at a high level by the output operation of the node, which causes a large current to flow from the drain to the N-well, which may destroy the PMOS transistor.

[4] The transmission output driver circuit 50 of the ATM-LAN physical layer is configured by arranging two or more stages of CMOS output terminals 52, 51, and 57 in parallel as described with reference to FIGS. 1, 14, And the rate of change of the current per unit time in the supply line of the power supply voltage Vdd and the supply line of the ground voltage Vss can be reduced by slightly shifting the timing of driving each of them by the output control circuit 20. [ As a result, the power supply noise of the power supply voltage Vdd inside the PMD semiconductor chip 9 and the power supply line of the ground voltage Vss can be reduced.

In this case, as is clear from the simulation conditions of FIG. 20 and the simulation results of FIGS. 24A, 24B, and 24C, the MOS transistor forming the output stage turned on after the output stage that is turned on for the first time, It is possible to reduce the power supply noise by making the size of the output terminal larger than the output terminal that is turned on for the first time.

[6] As shown in FIG. 16, the turn-on operation of the MOS transistor to be turned on at the second and third output stages 51 and 57 is delayed from the turn-off operation of the MOS transistor to be turned off, The through current flowing through the output stages 51 and 57 can be reduced, and power consumption and power supply noise can be further reduced.

As apparent from the simulation result of FIG. 20, in the output circuit having the output stages of the parallel three stages shown in FIG. 16, the first CMOS output stage 52, the second CMOS output stage 51, The delay times of the delay circuits 80 and 81 are set to about 3 ns and the delay times of the delay circuits 82 and 83 are set to about 6 ns The power supply noise can be made very small.

[8] By satisfying the transmission signal waveform defined by the template for the physical layer of 25 Mb / s ATM-LAN described in ATM_Forum / 94-1008R5 by the operating power of 3.3 [V] by the PMD semiconductor chip 9 , The power consumption of the PMD semiconductor chip 9 can be suppressed to as low as about 200 mW. Since the PMD semiconductor chip 9 is the portion of the ATM-LAN adapter card 200 having the largest power consumption, if the power consumption of the PMD semiconductor chip 9 can be reduced to about 200 mW, Can be reduced to about 1W.

Although the invention made by the present inventors has been described concretely according to the embodiments, the present invention is not limited thereto, and it goes without saying that various changes can be made within the scope of not departing from the gist of the present invention.

For example, similarly to the case of Fig. 16, the turn-on operation of the MOS transistor to be turned on may be delayed with respect to the parallel two-stage output circuit of Fig. 1 with delaying the turn-off operation of the MOS transistor to be turned off Do. The output driver circuit may be constituted by a single-stage CMOS output stage. In the configuration of the single stage CMOS output stage, the turn-on operation of the MOS transistor constituting it can be delayed with respect to the turn-off operation.

In the above description, the invention mainly made by the present inventor is applied to the 25-Mb / s physical layer for ATM-LAN described in ATM_Forum / 94-1008R5, which is the field of use thereof, but the present invention is not limited thereto But it is also applicable to other ATM-LAN specifications to be standardized in the future. The present invention can be applied to at least the output stage of the output driver circuit of the ATM-LAN as a CMOS transistor.

Effects obtained by representative ones of the inventions disclosed in the present application will be briefly described as follows.

In the ATM-LAN, the transmission circuit and the reception circuit have a one-to-one relationship and are coupled by a transmission line. For the output driver circuit 50 of the transmission circuit 10, the output terminal of the output circuit 21 is composed of a CMOS transistor Therefore, the gate-source voltage of the P-channel MOS transistor included in the CMOS output terminal and connected to the power supply voltage side can be set substantially at the level of the power supply voltage without depending on the voltage of the transmission terminal. This makes it possible to reduce the ON resistance of the MOS transistors Q1, Q3, Q5, Q7, Q9 and Q11 on the power supply voltage side constituting the output circuit as compared with the output circuit of the type in which the NMOS transistors connected in series are operated in a push-pull operation. Therefore, the operating voltage of the output driver circuit can be reduced, and the operating power voltage of the internal circuit including the output driver circuit and the semiconductor integrated circuit chip 9 used for the ATM-LAN physical layer control can be lowered.

As described above, by using the CMOS output circuit 21 to reduce the on-resistance of the MOS transistor, the ON-resistance of the MOS transistor is regulated by the template for the ATM-LAN physical layer of 25 Mb / s described in, for example, ATM_Forum / 94-1008R5 The signal amplitude defined by the template is set to 3.3 [V] even when the filter 35 ((45) is used to satisfy the requirement of the transmission signal waveform to be used and the resistors 33 and 44 for the output impedance adjustment are arranged, Can be obtained with a relatively low power supply voltage.

The use of the CMOS output circuit 21 is most suitable for lowering the operating power supply voltage of the PMD semiconductor chip 9 applied to the 25-Mb / s ATM-LAN physical layer described in ATM_Forum / 94-1008R5. This makes it possible to easily obtain the output signal amplitude that satisfies the template even if the ratio of the number of turns of the primary coil of the transformer 36 ((46)) to the number of turns of the secondary coil (turn ratio) is 1: Therefore, it is not necessary to increase the number of turns (number of turns) of the secondary winding of the transformer 36 until the operating current flowing through the output circuit is increased. This also contributes to lowering the power consumption of the semiconductor integrated circuit chip 9 for ATM-LAN physical layer control.

Unlike the Ethernet, the ATM-LAN has a one-to-one relationship between the transmitting circuit and the receiving circuit and is coupled by the transmission line. Therefore, even when the N-type well region of the CMOS output terminal is in the floating state, the PMOS transistor Q1 Q3, Q5, Q6, Q7, Q9, and Q11 are not supplied with a high level through the transmission lines 3 and 4 and no large current flows from the drain to the N- , Q9, and Q11) may be destroyed.

Due to the characteristics of the output circuit, the current supply capability (transistor size) of the MOS transistor constituting the CMOS output terminal of the output driver circuit 50 becomes relatively large. At this time, the first timing control means 54 for providing two or more CMOS output stages including the first and second pairs of CMOS transistors in parallel and shifting the timing of the push- Is provided in the circuit (20). Such a configuration can reduce the power source noise because the supply line of the power source voltage Vdd to the CMOS output terminal and the ground voltage Vss can reduce the current change rate per unit time in the supply line.

The output control circuit 20 is provided with the second timing control means 80, 81, 82, 83 for delaying the turn-on operation of the MOS transistor constituting the CMOS output terminal with respect to the turn-off operation, The through current flowing in the CMOS output stage can be reduced. This also contributes to reduction of power noise and low power consumption.

The size of the MOS transistor constituting the first CMOS output stage 52 and the size of the MOS transistor constituting the second CMOS output stage 51 and the size of the MOS transistor constituting the third CMOS output stage 57, Is set to approximately 1: 2.5: 6.25. The turn-on operation of the MOS transistor included in the second CMOS output terminal is delayed by about 3ns with respect to the turn-on operation of the MOS transistor included in the first CMOS output terminal, and the delay (80), (81), (82), and (83)) are provided in the output control circuit (20). This can significantly reduce power supply noise.

Claims (15)

A transmission line driving circuit for an ATM-LAN physical layer, which is connected to a receiving circuit on a one-to-one basis via a transmission line, An output driver circuit having a pair of transmission terminals, Resistor for output impedance adjustment coupled to each pair of transmission terminals. A filter connected in series with the resistor and And a transformer having a primary connected to the output terminal of the filter and a secondary connected to the transmission line, Wherein the output driver circuit includes an output circuit and an output control circuit, Wherein the output circuit includes a CMOS output terminal comprising a first and a second pair each including a P-channel type MOS transistor and an N-channel type MOS transistor connected in series, the first and second pairs of the P- Wherein the transistor has a source connected to a line for a power supply voltage different from the ground potential, the first and second pairs of the N-channel MOS transistors have a source connected to a ground voltage line, Wherein the MOS transistor forming the second pair has a common drain connected to the other side of the transmission terminal, and the MOS transistor forming the second pair has a common drain connected to one side of the transmission terminal, Wherein the output control circuit uses the power supply voltage and the ground voltage as its operating power and push-pulls the first pair and the second pair of the CMOS output terminals in opposite phases. The method according to claim 1, Wherein the output circuit includes two or more stages of CMOS output stages connected in parallel with the first and second pairs, respectively, and the output control circuit includes a first output stage for shifting the timing of the push-pull operation of the CMOS output stages connected in parallel 1 timing control means. The method according to claim 1, And said output control circuit includes second timing control means for delaying the start of the turn-on operation of said P-channel and N-channel MOS transistors of said first and second pairs. The method according to claim 1, Wherein the transformer has an inductance of 1 mH or more, a series resistance of 5 or less, a coupling coefficient of 0.999 or more, and an equivalent capacitance of 5 pF or less and a frequency band of 12 KHz to 16 MHz. The method according to claim 1, Wherein a winding ratio of the primary winding and the secondary winding of the transformer is 1: 1. The method according to claim 1, And the power supply voltage of the output driver circuit is 3.3V. An output driver circuit for an ATM-LAN physical layer, which is connected to a receiving circuit on a one-to-one basis via a transmission line, Output circuit Output control circuit, Wherein the output circuit includes a plurality of CMOS output stages each having a first and a second pair of serially connected P-channel type MOS transistors and N-channel type MOS transistors, and the P- And a source connected to a line for a power supply voltage different from the potential, and the N-channel type MOS transistor of each stage has a source connected to a line for ground voltage, and each of the stages constituting the first pair The MOS transistor having a common drain connected to the first transmission terminal and the MOS transistor at each end constituting the second pair having a common drain connected to the second transmission terminal, Wherein the output control circuit uses the power supply voltage and the ground voltage as an operation power source and performs push-pull operation of the first pair and the second pair of each of the CMOS output terminals in a reverse phase, The timing being shifted from each other. An output driver circuit for an ATM-LAN physical layer, which is connected to a receiving circuit on a one-to-one basis via a transmission line, Output circuit Output control circuit, Wherein the output circuit includes a plurality of CMOS output stages each having a first and a second pair of serially connected P-channel type MOS transistors and N-channel type MOS transistors, and the P- And a source connected to a line for a power supply voltage different from the potential, and the N-channel type MOS transistor of each stage has a source connected to a line for ground voltage, and each of the stages constituting the first pair The MOS transistor having a common drain connected to the first transmission terminal and the MOS transistor at each end constituting the second pair having a common drain connected to the second transmission terminal, Wherein the output control circuit uses the power supply voltage and the ground voltage as operating power, push-pulls the first pair and the second pair of each of the CMOS output terminals in a reverse phase, And delaying the start of the turn-on operation. 9. The method of claim 8, Wherein the output circuit comprises first, second and third parallel connected CMOS output stages each having the first and second pairs, Wherein the output control circuit includes a first delay means and a second delay means, The first delay means delays the start of the turn-on operation of the MOS transistor included in the second CMOS output terminal by the first time length as compared with the start of the turn-on operation of the MOS transistor included in the first CMOS output terminal, Wherein the second delay means delays the first CMOS output terminal by a second time length of the turn-on operation of the MOS transistor included in the third CMOS output terminal as compared to the start of the turn-on operation of the MOS transistor included in the second CMOS output terminal. Circuit. 9. The method of claim 8, Wherein the output circuit comprises first, second and third parallel connected CMOS output stages each having the first and second pairs, The ratio of the size of the MOS transistor forming the first CMOS output stage, the size of the MOS transistor forming the second CMOS output stage, and the size of the MOS transistor forming the third CMOS output stage is approximately 1: 2.5: 6.25, The output control circuit delays the start of the turn-on operation of the MOS transistor included in the second CMOS output terminal by about 3 ns as compared with the start of the turn-on operation of the MOS transistor included in the first CMOS output terminal, And delay means for delaying the onset of the turn-on operation of the included MOS transistor by about 6 ns. An ATM-LAN integrated circuit adapter card mounted on a terminal device and coupled to a transmission line, and performing interface control of the ATM-LAN between other terminal devices connected to the terminal device via the transmission line, An ATM-LAN physical layer control chip having a transmitting circuit and a receiving circuit for an ATM-LAN physical layer, A resistor for adjusting an output impedance of the transmission circuit, A filter connected in series to the resistor and for adjusting the transmitted signal waveform, A transmission coupling transformer for transmitting the output of the filter to a transmission line, A receiving coupling transformer for transmitting a transmission signal from the transmission line to the reception circuit; And control means for executing protocol processing of transmission and reception for the ATM-LAN, The control chip, the resistor, the filter, the transformer, and the control means are all formed on the card substrate, Wherein the transmitting circuit in the ATM-LAN physical layer control chip includes an output driver circuit having a pair of transmitting terminals coupled to the resistor, Wherein the output driver circuit includes an output circuit and an output control circuit, Wherein the output circuit includes a CMOS output terminal comprising first and second pairs each including a P-channel type MOS transistor and an N-channel type MOS transistor connected in series, wherein the P-channel type MOS transistor has a power supply different from the ground potential Wherein the first and second pairs of the N-channel type MOS transistors each have a source connected to a line for ground voltage, and the MOS transistor forming the first pair comprises a source connected to the transmission line, And the MOS transistor forming the second pair has a common drain connected to the other side of the transmission terminal, Wherein the output control circuit uses the power supply voltage and the ground voltage as operating power and push-pulls the first pair and the second pair of the CMOS output terminals in a reverse phase. An ATM-LAN integrated circuit adapter card mounted on a terminal device and coupled to a transmission line, and performing interface control of the ATM-LAN between other terminal devices connected to the terminal device via the transmission line, An ATM-LAN physical layer control chip having a transmitting circuit and a receiving circuit for an ATM-LAN physical layer, A resistor for adjusting an output impedance of the transmission circuit, A filter connected in series to the resistor and for adjusting the transmitted signal waveform, A transmission coupling transformer for transmitting the output of the filter to a transmission line, A receiving coupling transformer for transmitting a transmission signal from the transmission line to the reception circuit; And control means for executing protocol processing of transmission and reception for the ATM-LAN, The control chip, the resistor, the filter, the transformer, and the control means are all formed on the card substrate, Wherein the transmitting circuit in the ATM-LAN physical layer control chip includes an output driver circuit having a pair of transmitting terminals coupled to the resistor, Wherein the output driver circuit includes an output circuit and an output control circuit, Wherein the output circuit includes a plurality of CMOS output stages each having a first and a second pair of serially connected P-channel type MOS transistors and N-channel type MOS transistors, and the P- And a source connected to a line for a power supply voltage different from the potential, wherein the N-channel type MOS transistor of each stage has a source connected to a ground voltage line, and each of the stages forming the first pair Wherein the MOS transistor has a common drain connected to one side of the transmission terminal and each of the MOS transistors forming the second pair has a common drain connected to the other side of the transmission terminal, Wherein the output control circuit uses the power supply voltage and the ground voltage as its operating power, push-pulls the first pair and the second pair of each of the CMOS output terminals in a reverse phase, and the timing of the push- And delays the start of the turn-on operation of the MOS transistor at a predetermined CMOS output terminal. The method of claim 3, Wherein the second timing control means includes means for reducing the delay of the turn-on operation of the first and second pairs of MOS transistors relatively earlier than the turn-off operation of the MOS transistors. 9. The method of claim 8, Wherein the output control circuit reduces the delay of the turn-off operation of the MOS transistor in a predetermined CMOS output terminal relatively earlier than the turn-off operation of the MOS transistor. 13. The method of claim 12, Wherein the output control circuit reduces the delay of the turn-off operation of the MOS transistor in the predetermined CMOS output terminal relatively earlier than the turn-off operation of the MOS transistor.