KR19980037090A - Functional flow pipeline structure with foreseeability - Google Patents

Abstract

The present invention relates to a functional flow pipeline structure having a foresight function, wherein the structure of the present invention includes: a first stage 300-1, a second to transfer input data to each functional unit performing an independent function. In the functional flow pipeline 300 structure consisting of a stage 300-2, a third stage 300-3, and a fourth stage 300-4, the third stage in the first stage 300-1 is provided. First bypass means 400 for bypassing data to stage 300-3; And second bypass means 500 for bypassing data from the first stage 300-1 to the fourth stage 300-4, and according to the present invention as described above, In passing data to the functional unit, by checking other conditions besides the formal path and bypassing the data to a path that satisfies the condition, the bubble phenomenon generated at each stage in the functional flow pipeline is reduced. The result is that the utilization of the functional unit is increased, and the performance can be expected to be improved.

Description

A function flow pipeline structure having lookahead function

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a functional flow pipeline structure having a predictive function. Particularly, in passing data to a plurality of function units (FUs), the present invention satisfies conditions by inspecting various conditions in addition to formal paths. By virtue of bypassing data in a way to improve the efficiency of the overall hardware, the present invention relates to a functional flow pipeline structure having a predictive function.

In general, pipelining provides a means of realizing temporal parallelism in digital computers. The concept of pipeline in a computer is similar to the concept of a production line in a production plant.

In order to perform pipelining, the input process must be subdivided into a sequence of subprocesses, each of which is performed by a particular hardware stage operating concurrently with other stages in the pipeline. do. Successive processes form a flow in the pipe and are performed in an overlapped fashion at the subprocess level. This type of pipe method can dramatically increase the throughput of digital computers.

Subsequently, when classifying pipeline processors, various types of pipeline processors are classified according to processing levels and pipeline configurations and control strategies.

First, Handlers are classified into arithmetic pipelining, instruction pipelining, and processor pipelining according to processing levels.

1 is a diagram for explaining arithmetic pipelining, as shown in FIG. 1, arithmetic logic units of a computer are separated to perform pipeline operations in various data formats. Here, S represents a stage and L represents a latch. Examples of well-known arithmetic pipelines include four-stage pipes used in Star-100, eight-stage pipes used in TI-ASC, 14 or more pipeline stages used in Cray-1, and 26 or more per pipe in Cyber-205. Stage and so on.

2 is a diagram for explaining instruction pipelining, where the performance of the instruction stream is pipelined by superimposing the performance of the current instruction with fetch, decode, and operand fetch of instructions that occur continuously. This technique is also known as instruction lookahead. Almost all high-performance computers have an instruction execution pipeline.

3 is a diagram for explaining processor pipelining, in which processor pipelining refers to pipeline processing of the same data stream by a series of processors, the processors processing each particular task. do. The data stream passes through the first processor with the result stored in the memory block, which can also be accepted by the second processor. At that time, the second processor passes the result performed by the third processor.

And Ramamoorthy and Li have a single function / multifunction pipeline, a static / dynamic pipeline, a scalar / vector pipeline, depending on the pipeline configuration and control strategy. Classified as

Looking at the monofunctional / multifunctional pipeline first, a pipeline unit with a fixed dedicated function is called a unifunctional. Cray-1 has 12 single function pipeline units for various scalar, vector, fixed point and floating point operations. Multifunctional pipes can then perform different functions at different times or simultaneously by interconnecting different subsets of stages in the pipeline. The TI-ASC has four multifunction pipeline processors, each of which can reconfigure many arithmetic logic operations at different times.

And, looking at the static / dynamic pipeline, the static pipeline can only estimate one functional configuration at a time. Static pipelines are single functional or multifunctional. Pipelining is possible in static pipes only if the same type of instruction is executed continuously. Functions performed by static pipelines should not change often. Dynamic pipeline processors, on the other hand, allow for multiple functional configurations to exist simultaneously. In this regard, dynamic pipelines must be multifunctional. Dynamic configuration requires much more sophisticated control and sequencing mechanisms than in static pipelines. Most computers have a single functional or multifunctional static pipe.

In addition, pipeline processors that depend on the instruction or data type are also classified into scalar pipelines and vector pipelines. The scalar pipeline processes a series of scalar operands under the control of a DO loop. Instructions in small DO loops are often prefetched into the instruction buffer. The scalar operands required for repeating scalar instructions are moved to a data cache to continuously supply the operands to the pipeline. The IBM System / 360 Model 91 is a typical example of a device with a scalar pipeline. However, there is no cache in Model 91. On the other hand, the vector pipeline is specially designed to process vector instructions for vector operands. A computer with vector instructions is called a vector processor, and the design of this vector processor extends from the design of a scalar pipeline. The processing of vector operands in the vector pipeline is under the control of firmware and hardware rather than under software control as in the scalar pipeline.

Next, the linear pipelining (linear pipelining) is as follows.

In a pipeline with constant delay, all tasks (the smallest unit of work processed by the computer) have the same processing time in all stations. Stations in an ideal production line run concurrently with sufficient resource usage. However, substantially consecutive stations do not have the same delay. The optimal distribution of a production line is influenced by many factors, including the quality of the working unit (efficiency and acceptability), the required processing speed and the cost of the entire production line.

When a given task, the prior relationship of the set _{{T 1, T 2, ...} , T k} of the sub-task (subtask) of the T, the end of the preceding task T _i (ij) until the succeeding task T _j is It does not start. The interdependencies of all subtasks form a precedence graph, and the linear pipeline can process a series of subtasks according to the linear preceding graph.

4 is a basic structural diagram of a linear pipeline processor, where L is a latch, C is a clock, and S _i is an i-th stage.

The pipeline shown in FIG. 4 consists of a cascade of processing stages, which are pure combinations that perform arithmetic or logic operations on the data stream flowing through the pipe. It is a combinational circuit. The stages are also separated by high speed interface latches. These latches are fast registers to maintain immediate results between stages. The flow of information between adjacent stages is controlled by a common clock applied to all latches simultaneously.

Next, the clock period, speedup, efficiency, and throughput of the linear pipeline will be described.

1) Clock period

The logic circuit in each stage S _i has a time delay, denoted τ _i . If the time delay of each interface latch is τ ₁ , the clock period of the linear pipeline may be expressed as follows.

The inverse of the clock period is represented by the frequency f = 1 / τ of the pipeline processor.

5 is a space-time diagram of a four-stage pipeline processor for explaining the overlapping operation of a linear pipeline, with the X axis representing time, the Y axis representing space, Denotes the j th subtask in the i th task.

Once the pipe is filled, it will output one result per clock period independent of the number of stages. Ideally, a linear pipeline with k stages can handle n tasks within a T _k = k + (n-1) clock period, where k cycles are used to fill the pipeline or to complete the execution of the first task. N-1 cycles are required to complete the remaining n-1 tasks. Such number of tasks may be performed in a nonpipeline processor having the same function within a T ₁ = n * k time delay.

2) Speedup

The speedup of a k-stage linear pipeline processor for the same non-pipeline processor may be defined as follows.

The maximum speed increase a linear pipeline can provide is k, where k is the number of stages in the pipe. This maximum speed increase cannot be achieved completely because of data dependence between instructions, interrupts, program branch and other factors. The wait state caused by unordered instruction execution consumes many pipeline cycles.

After defining the clock period in Equation 1 and defining the speed increase in Equation 2, two units for measuring the performance of the linear pipeline processor will be described. The time interval in the space-time diagram shown in FIG. There is a time interval and a stage space, and a product of the time interval and the stage space is called a time-space span. A given time-space span can exist in a busy or idle state, but not both states at the same time. This concept is used to measure the performance of pipelines.

3) efficiency

The efficiency of a linear pipeline is measured by the percentage of busy time-space span over the total time-space span corresponding to the sum of all busy and idle time-space spans. That is, the efficiency of the pipeline can be defined as follows.

Where n represents the number of tasks (ie, instructions), k represents the number of pipeline stages, and τ represents the clock period of the linear pipeline. When n → ∞, it becomes η → 1, which means that the larger the number of tasks going through the pipeline, the better the efficiency of the pipeline. From Equation 2 and Equation 3, η = S _k / k can be obtained, which provides the efficiency of the linear pipeline from another perspective as the ratio of the actual speed increase to the ideal speed increase k. If n »k at steady state of pipeline, efficiency η should approach 1. However, this ideal case does not hold all the time due to program branches, interrupts, data dependencies and other factors.

4) Throughput

Throughput is defined as the number of results (tasks) that can be completed by the pipeline per unit of time, and this ratio reflects the computational power of the pipeline. That is, the throughput is defined as follows.

Where n is equal to the total number of tasks performed during the observation period kτ + (n-1) τ. Ideally, when η → 1, then ω = 1 / τ = f, which means that the maximum throughput of the linear pipeline is equal to frequency, which corresponds to one output result per clock period.

Fig. 6 is a structural diagram of a pipeline having a conventional function confirmation flow, the conventional pipeline structure comprising: functional unit determining means 100; And a plurality of functional units 200-1 to 200-n.

Here, the functional unit determination means 100 is a pipeline structure in which a plurality of stages are connected in series and is called a function flow pipeline (FFP), and each stage sequentially performs a functional unit selection operation. That is, after extracting a Function Unit Identifier (FU Id.) From a data stream (consisting of functional unit identifiers and data) input from a memory (not shown), and determining which function unit to transfer data to , Output the data.

Each of the functional units among the plurality of functional units 200-1 to 200-n receives data from the functional unit determining means 100 and performs an independent function.

In the first unit 100-1 in the functional unit determination means 100 shown in FIG. 6, the data is D1, the second stage 100-2 is data D2, and the third stage 100-3 is D3. Assume that there is data called D4 in the data and the fourth stage 100-4.

If the data D1 in the first stage 100-1 is data to be used in the fourth functional unit 200-4, the data D3 in the third stage 100-3 is already present in the first functional unit ( If the data is used at 200-1), invalid data currently resides in the fourth stage 100-4. This phenomenon is called bubble.

As described above, the conventional pipeline performs a function unit selection operation sequentially in a plurality of stages in a function flow pipeline (FFP), thereby causing a bubble phenomenon as described above.

Accordingly, the present invention has been made in order to solve the above problems, in the transfer of data to each functional unit, by bypassing the data in a path satisfying the condition by examining several conditions in addition to the formal path. Bypassing, the goal is to provide a functional flow pipeline structure with predictive functionality designed to improve the efficiency of the overall hardware.

A functional flow pipeline structure having a predictive function according to the present invention for achieving the above object includes a first stage, a second stage, and a third to transfer input data to each functional unit performing an independent function. 11. A functional flow pipeline structure comprising a stage and a fourth stage, comprising: first bypass means for bypassing data from the first stage to the third stage; And second bypass means for bypassing data from the first stage to the fourth stage.

According to the present invention as described above, in passing data to each functional unit, by inspecting a number of conditions in another path in addition to the formal path, by bypassing the data in a path that satisfies the conditions, each in the functional flow pipeline Increasing the utilization of functional units by reducing the bubble phenomenon in the stage can be expected to improve performance.

1 is a view for explaining arithmetic pipelining,

2 is a view for explaining instruction pipelining,

3 is a diagram for explaining processor pipelining;

4 is a basic structural diagram of a linear pipeline processor;

5 is a space-time diagram of a four-stage pipeline processor for explaining the overlapping operation of the linear pipeline;

6 is a structural diagram of a pipeline having a conventional functional confirmation flow;

7 is a structural diagram of a functional flow pipeline having a foresight function according to the present invention.

* Explanation of symbols for main parts of the drawings

100: functional unit determining means 100-1 to 100-n: first to nth stages 200-1 to 200-n: plural functional units 300: functional flow pipeline

400: first bypass means 400A: first multiplexer

400B: first selection signal generator 400B-1: first exclusive logic gate

400B-2: First Inverter 400B-3: First Logic Gate

500: second bypass means 500A: second multiplexer

500B: second selection signal generator 500B-1: second exclusive logic gate

500B-2: second inverter 500B-3: second AND gate

600-1 to 600-4: Function unit S _i : i-th stage

L: Latch C: Clock

M _i : i-th memory block Proc. n: nth processor

: j th subtask of the i th task

Hereinafter, the present invention will be described with reference to the accompanying drawings.

7 is a structural diagram of a functional flow pipeline having a predictive function according to the present invention, Figure 7 is a functional flow pipeline 300, the first bypass means 400, the second bypass means 500 and a plurality of It consists of functional units 600-1 to 600-4.

At this time, when looking at the structure of the data stream input to the functional flow pipeline 300, the valid bit (Valid bit) is 1 bit represents the invalid data if 0, and if it is 1 (Valid) Indicates data. In addition, the Function Unit Identifer bit (FU Id bit) is 2 bits, 0 means that data is data required by the first functional unit 600-1, and 1 means data is a second function. Means that the data is required by the unit 600-2, 10 means that the data is required by the third functional unit 600-3, and 11 means that the data is the fourth functional unit 600-4. This means that the data is needed by. On the other hand, data is 16 bits, which is data required for performing an independent function in each functional unit.

The functional flow pipeline 300 includes a first stage 300-1, a second stage 300-2, a third stage 300-3, and a fourth stage 300-4. Each stage delivers data to each functional unit 600-1 to 600-4 in the next stage. At this time, the unique functional unit identifier in the first stage 300-1 is 0, the unique functional unit identifier in the second stage 300-2 is 1, and the unique functional unit identifier in the third stage 300-3 is The unique functional unit identifier is 10 and the unique functional unit identifier in the fourth stage 300-4 is 11. The general pipeline is used to improve the processing of data, but the functional flow pipeline (FFP) here is used for the transfer of data.

The first bypass means 400 includes a first multiplexer 400A and a first selection signal generator 400B. In this case, the first multiplexer 400A includes the first stage 300. Selects one of the data from -1) and the data from the second stage 300-2, and the first selection signal generator 400B functions from the first stage 300-1. After comparing a unit identifier with a unique functional unit identifier from the third stage 300-3, the first multiplexing signal st1 is first multiplexed according to a valid bit present in the third stage 300-3. Output to unit 400A.

The first selection signal generator 400B includes a first exclusive OR gate 400B-1, a first inverter 400B-2, and a first AND gate 400B-3. The OR gate 400B-1 receives the functional unit identifier from the first stage 300-1 and the unique functional unit identifier from the third stage 300-3, and performs an exclusive logic sum. Inverter 400B-2 receives the valid bit from the third stage 300-3 and inverts the result. From first AND gate 400B-3, the result is obtained from the first exclusive OR gate 400B-1. And a result of performing a logical multiplication upon receiving the result from the first inverter 400B-2, and outputting a first selection signal st1.

Meanwhile, the second bypass means 500 includes a second multiplexer 500A and a second selection signal generator 500B. In this case, the second multiplexer 500A includes the first stage 300. Selects one of the data from -1) and the data from the third stage 300-3, and the second selection signal generator 500B functions from the first stage 300-1. After comparing the unit identifier and the unique functional unit identifier from the fourth stage 300-4, the second multiplexing signal st2 is second-multiplied according to the valid bits in the fourth stage 300-4. Output to negative portion 500A.

The second selection signal generator 500B includes a second exclusive OR gate 500B-1, a second inverter 500B-2, and a second AND gate 500B-3, and the second exclusive excitation gate 500B-3 is here. The OR gate 500B-1 receives an exclusive logical unit by receiving a functional unit identifier from the first stage 300-1 and a unique functional unit identifier from the fourth stage 300-4, and performs the second logical sum. Inverter 500B-2 receives the valid bit from the fourth stage 300-4 and inverts the result. From the second AND gate 500B-3, the result from the second exclusive AND gate 500B-1 is determined. And a result of performing a logical multiplication upon receiving the result from the second inverter 500B-2, and outputting a second selection signal st2.

The plurality of functional units 600-1 to 600-4 are arranged in parallel according to the order of latency, in which the latency is represented by the number of clocks and the top of the functional units that require a large number of clocks in order. Arrange on. Each of the functional units 600-1 to 600-4 receives data from each stage of the functional flow pipeline 300 to perform independent functions. Examples of the plurality of functional units 600-1 to 600-4 may include various kinds of adders, multipliers, and dividers.

Next, an operation of an embodiment of the present invention configured as described above will be described with reference to FIG. 7.

1) If the data in the first stage 300-1 in the functional flow pipeline 300 is the data required by the first functional unit 600-1, the data is in the first stage 300-1. The data is transferred directly to the first functional unit 600-1 to perform an independent function.

2) If the data in the first stage 300-1 in the functional flow pipeline 300 is the data required by the second functional unit 600-2, the data in the first stage 300-1 is present. After transferring the data to the next second stage 300-2, the data is transferred from the second stage 300-2 to the second functional unit 600-2 to perform an independent function.

3) The data in the first stage 300-1 in the functional flow pipeline 300 is the data required by the third functional unit 600-3.

The functional unit identifier from the first stage 300-1 and the unique functional unit identifier 10 from the third stage 300-3 are selected by the first selection signal generator 400B of the first bypass means 400. It is input to and compares whether it is the same in the first exclusive logic gate 400B-1. If the data in the first stage 300-1 is the data required by the third functional unit 600-3, the value of the functional unit identifier in the first stage 300-1 is 10 and thus the third stage. Same as the unique functional unit identifier 10 of 300-3. Therefore, the result of the first exclusive logic gate 400B-1 is one. Then, in order to bypass the data in the first stage 300-1 to the third stage 300-3, the valid bit in the third stage 300-3 must be zero. When the valid bit 0 in the third stage 300-3 is inputted by the first inverter 400B-2 and inverted, the result of the first inverter 400B-2 is 1. When the result 1 of the first exclusive logic gate 400B-1 and the result 1 of the first inverter 400B-2 are input to the first AND gate 400B-3 and the AND is performed, the first AND gate is performed. The result of (400B-3) is 1. In this case, the result 1 of the first AND gate 400B-3 becomes the first selection signal st1, and the first selection signal st1 is passed to the first multiplexer 400A of the first bypass unit 400. Is entered. When the first selection signal st1 is 1, the data from the first stage 300-1 of the data from the first stage 300-1 and the data from the second stage 300-2 are the same. It is selected by the first multiplexer 400A and input to the third stage 300-3. (In the case where the first selection signal st1 is 0, the data from the first stage 300-1 may not be used. Among the data from the second stage 300-2, the data from the second stage 300-2 is selected by the first multiplexer 400A and input to the third stage 300-3. In the third stage 300-3, data received from the first stage 300-1 is transferred to the third functional unit 600-3 to perform an independent function.

4) The data in the first stage 300-1 in the functional flow pipeline 300 is the data required by the fourth functional unit 600-4.

The functional unit identifier from the first stage 300-1 and the unique functional unit identifier 11 from the fourth stage 300-4 are selected by the second selection signal generator 500B of the second bypass means 500. It is input to and compares whether it is the same in the second exclusive logic gate 500B-1. If the data in the first stage 300-1 is the data required by the fourth functional unit 600-4, the value of the functional unit identifier in the first stage 300-1 is 11 and thus the fourth stage. Same as the unique functional unit identifier 11 of 300-4. Therefore, the result of the second exclusive logic gate 500B-1 is one. Then, in order to bypass the data in the first stage 300-1 to the fourth stage 300-4, the valid bit in the fourth stage 300-4 must be zero. When the valid bit 0 in the fourth stage 300-4 is inputted by the second inverter 500B-2 and inverted, the result of the second inverter 500B-2 is 1. When the result 1 of the second exclusive logic gate 500B-1 and the result 1 of the second inverter 500B-2 are input to the second AND gate 500B-3 and the AND is performed, the second AND gate is performed. The result of (500B-3) is 1. At this time, the result 1 of the second AND gate 500B-3 becomes the second selection signal st2, and the second selection signal st2 is the second multiplexer 500A of the second bypass unit 500. Is entered. When the second selection signal st2 is 1, the data from the first stage 300-1 of the data from the first stage 300-1 and the data from the third stage 300-3 are displayed. It is selected by the second multiplexer 500A and input to the fourth stage 300-4. (For reference, when the second selection signal st2 is 0, data from the first stage 300-1 and Among the data from the third stage 300-3, the data from the third stage 300-3 is selected by the second multiplexer 500A and input to the fourth stage 300-4. In the fourth stage 300-4, the data received from the first stage 300-1 is transferred to the fourth functional unit 600-4 to perform an independent function.

The embodiments described above are merely illustrative in all respects and should not be construed as limiting, and all modifications that fall within the true spirit and scope of the present invention shall fall within the claims of the present invention.

As described above, according to the present invention, in passing data to each functional unit, the functional flow pipeline is provided by bypassing the data to a path satisfying the condition by checking various conditions with another path besides the formal path. The effect is that the performance improvement can be expected by reducing the bubble occurring at each stage in the stage, thereby increasing the utilization of the functional unit.

Claims (5)

The first stage 300-1, the second stage 300-2, the third stage 300-3 and the fourth stage 300-to transfer the input data to each functional unit performing an independent function. A functional flow pipeline (300) structure comprising: first bypass means (400) for bypassing data from the first stage (300-1) to the third stage (300-3); And a second bypass means 500 for bypassing data from the first stage 300-1 to the fourth stage 300-4. Pipeline structure. The method of claim 1, wherein the first bypass unit 400 selects one of data from the first stage 300-1 and data from the second stage 300-2. 1 multiplexer 400A; And comparing the functional unit identifier from the first stage 300-1 with the unique functional unit identifier from the third stage 300-3 and then applying the valid bit in the third stage 300-3. And a first selection signal generator 400B for outputting a first selection signal to the first multiplexer 400A. 3. The first selection signal generator 400B inputs a functional unit identifier from the first stage 300-1 and a unique functional unit identifier from the third stage 300-3. A first exclusive OR gate 400B-1 that receives and performs an exclusive logical sum; A first inverter 400B-2 for receiving a valid bit from the third stage 300-3 and inverting the valid bit; And a first AND gate that receives a result from the first exclusive OR gate 400B-1 and a result from the first inverter 400B-2, performs an AND, and then outputs a first selection signal. Functional flow pipeline structure having a foresight function, characterized in that consisting of 400B-3). The method of claim 1, wherein the second bypass unit 500 selects one of data from the first stage 300-1 and data from the third stage 300-3. Two multiplexing units 500A; And comparing the functional unit identifier from the first stage 300-1 with the unique functional unit identifier from the fourth stage 300-4, and then applying the valid bit in the fourth stage 300-4. And a second selection signal generator 500B for outputting a second selection signal to the second multiplexer 500A. The method of claim 4, wherein the second selection signal generator 500B inputs a functional unit identifier from the first stage 300-1 and a unique functional unit identifier from the fourth stage 300-4. A second exclusive OR gate 500B-1 that receives and performs an exclusive logic sum; A second inverter 500B-2 that receives the valid bit from the fourth stage 300-4 and inverts the valid bit; And a second AND gate that receives a result from the second exclusive OR gate 500B-1 and a result from the second inverter 500B-2, performs an AND, and then outputs a second selection signal. A functional flow pipeline structure having a foresight function, characterized in that consisting of 500B-3).