KR19980032057A - Probe card and test device using it - Google Patents
Probe card and test device using it Download PDFInfo
- Publication number
- KR19980032057A KR19980032057A KR1019970009246A KR19970009246A KR19980032057A KR 19980032057 A KR19980032057 A KR 19980032057A KR 1019970009246 A KR1019970009246 A KR 1019970009246A KR 19970009246 A KR19970009246 A KR 19970009246A KR 19980032057 A KR19980032057 A KR 19980032057A
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- South Korea
- Prior art keywords
- probe card
- chip
- bonding pad
- glass substrate
- quartz glass
- Prior art date
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- 239000000523 sample Substances 0.000 title claims abstract description 30
- 238000012360 testing method Methods 0.000 title abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims description 20
- 238000003825 pressing Methods 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000001816 cooling Methods 0.000 claims description 3
- 238000007689 inspection Methods 0.000 claims description 3
- 239000011521 glass Substances 0.000 abstract description 8
- 239000004593 Epoxy Substances 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 25
- 238000002788 crimping Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 6
- 230000003287 optical effect Effects 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000012216 screening Methods 0.000 description 2
- 238000010998 test method Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000007688 edging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 210000004907 gland Anatomy 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07314—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/048—Making electrodes
- H01L21/049—Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
- G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
- G01R31/2875—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature related to heating
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
- G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
- G01R31/2877—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature related to cooling
Landscapes
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Crystallography & Structural Chemistry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Measuring Leads Or Probes (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
본 발명은 웨이퍼 상태에서 칩의 번인(burn-in) 시험이 가능한 프로브 카드 및 그것을 이용한 시험장치를 제공하는 것으로서, 본 발명에 의한 프로브 카드(4)는 피측정물인 칩이 형성된 실리콘 웨이퍼와 열팽창 계수가 가까운 석영 유리기판(5)을 이용하여 형성되어 있기 때문에 번인 시험에 있어서 상온에서 고온으로 온도를 변화시켜도 프로빙패드(6)와 본딩패드(3)의 위치 벗어남이 발생되지 않기 때문에 상온에서 위치결정을 행한다. 또한 석영 유리기판(5)은 투명이기 때문에 종래의 유리에폭시 기판의 경우에 위치 맞춤을 위한 구멍을 뚫어둘 필요가 없으며, 프로빙 패드(6)와 본딩 패드(3)의 위치맞춤이 용이하다. 또한, 도전성 고무(10)의 위에 안정성, 도전성이 우수한 Au볼(11)을 형성하는 것에 의해 본딩 패드(3)와의 전기적 도통이 보다 확실하게 이루어진다.The present invention provides a probe card capable of burn-in testing of a chip in a wafer state and a test apparatus using the probe card. The probe card 4 according to the present invention has a silicon wafer and a coefficient of thermal expansion in which a chip as an object to be measured is formed. Is formed by using a quartz glass substrate 5 close to each other, so that the positional deviation between the probing pad 6 and the bonding pad 3 does not occur even if the temperature is changed from normal temperature to high temperature in the burn-in test. Is done. In addition, since the quartz glass substrate 5 is transparent, it is not necessary to drill holes for alignment in the case of the conventional glass epoxy substrate, and the positioning of the probing pad 6 and the bonding pad 3 is easy. In addition, by forming the Au ball 11 having excellent stability and conductivity on the conductive rubber 10, electrical conduction with the bonding pad 3 is more reliably achieved.
Description
본 발명은 반도체 집적회로의 전기적 특성을 측정하는 프로버에 이용되는 프로프 카드에 관한 것으로, 웨이퍼 상태의 복수의 칩에 대하여 번인(burn-in) 시험을 실행 가능한 프로브 카드 및 그것을 이용한 시험장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a probe card for use in a prober for measuring electrical characteristics of a semiconductor integrated circuit. The present invention relates to a probe card capable of performing a burn-in test on a plurality of chips in a wafer state, and a test apparatus using the probe card. It is about.
(종래의 기술)(Conventional technology)
종래부터 반도체 집적회로의 잠재적 불량을 선별하는 스크리닝(screening) 방법의 하나로서 번인 시험을 시행하며, 출하품의 신뢰성을 확보하고 있다. 도 5는 종래의 번인 시험방법을 나타내는 도면이며, 도면에서 부호 31은 조립공정이 완료된 후의 반도체 집적회로, 32는 소켓, 33은 항온조, 34는 전압 인가장치이다. 종래의 번인 시험에서는 반도체 집적회로(31)를 항온조(33)내에서 소켓(32)으로 셋트하며, 전압 인가장치(34)로 부터 실제사용 조건보다도 높은 전원전압을 인가하며, 항온조(33)에 의해 실제 사용조건보다도 높은 분위기 온도를 부여하여 에징을 행한다. 이와같은 실제 사용조건보다도 엄격한 조건아래에서 시험을 행하는 것에 의해 단시간에 잠재적인 고장을 검출하는 것이다.Conventionally, burn-in tests have been conducted as one of the screening methods for screening for potential defects in semiconductor integrated circuits, thereby ensuring the reliability of shipments. 5 is a view showing a conventional burn-in test method, wherein reference numeral 31 denotes a semiconductor integrated circuit after the assembly process is completed, 32 is a socket, 33 is a thermostat, and 34 is a voltage applying device. In the conventional burn-in test, the semiconductor integrated circuit 31 is set to the socket 32 in the thermostat 33, and a power supply voltage higher than the actual use condition is applied from the voltage applying device 34 to the thermostat 33. As a result, an edge temperature higher than actual use conditions is applied to edging. Potential failures can be detected in a short time by conducting tests under conditions that are more stringent than these actual conditions of use.
반면, 최근의 경향으로서 반도체 집적회로의 전기적 특성을 측정하는 프로버를 이용하여 웨이퍼 상태에서 번인 시험을 행하는 방법이 제안되어 있다. 예를들면 일본 특허 공개 평 5-340964호 공보에서는 반도체 웨이퍼 뒷면으로부터 히터로 가열하면서 반도체 웨이퍼위의 칩의 본딩 패드에 대하여 범프(bump)를 접속시켜 모든 칩에 대하여 한번에 전압을 인가하는 것이 가능한 번인 시험장치가 제안되어 있다.On the other hand, as a recent trend, a method of performing burn-in test in a wafer state using a prober for measuring electrical characteristics of a semiconductor integrated circuit has been proposed. For example, Japanese Patent Laid-Open No. 5-340964 discloses a burn-in in which a bump can be connected to a bonding pad of a chip on a semiconductor wafer while being heated by a heater from the back of the semiconductor wafer, and voltage can be applied to all chips at once. A test apparatus has been proposed.
상기와같이 종래의 번인 시험은 조립공정이 완료되며, 팩케이징된 상태로 행해지기 때문에 발생된 고장이 웨이퍼 프로세스에 기인하는 것이 팩케이징에 기인하는 것인지를 구별하는 것이 곤락하다. 또한, 웨이퍼 상태라면 시험시의 온도를 더욱 가속하여 올리는 것이 가능하지만 팩케이지가 있기때문에 온도가속이 제한되어 있다. 또한, 다수의 소켓(32), 항온조(33)등의 설비가 필요하며, 가격이 비싸고, 넓은 공간도 필요한 것이다.As described above, the conventional burn-in test is performed in the packed state after the assembly process is completed, so it is difficult to distinguish whether the failure caused by the wafer process is due to the packaging. In the wafer state, it is possible to further accelerate the temperature during the test, but the temperature acceleration is limited because of the package. In addition, a number of sockets 32, the thermostat 33 and the like is required, expensive, and a large space is also required.
반면, 상기와같은 문제를 해소하기 위해서는 프로버를 이용하여 웨이퍼 상태에서 번인시험을 행하는 방법이 유효하지만 종래의 프로브카드는 불투명한 유리에폭시 기판등으로 형성되어 있기 때문에 칩의 본딩 패드에 대하여 프로빙 침을 접촉시키는 작업이 업려우며, 침의 위치결정 정도가 나쁘며, 또한 침의 본수에도 제한이 있다. 또한 유리에폭시 기판과 실리콘 웨이퍼에서는 열팽창계수에 차이가 있기때문에 상온시에 위치맞춤을 행해도 온도를 상승시키면 벗어남이 발생한다는 문제도 있다. 또한, 일본 특허공개 평5-340964호 공보에서는 반투명형상의 폴리이미드 막에 범프를 형성하며, 폴리이미드 막위의 개구부로부터 광학 현미경에서 얼라이먼트 마크를 이용하여 위치맞춤을 행하는 시험장치가 제안되어 있지만 장기간 사용시 폴리이미드 막의 신뢰성이 문제가 된다.On the other hand, in order to solve the above problem, the method of performing burn-in test in the state of wafer using a prober is effective, but since the conventional probe card is formed of an opaque glass epoxy substrate or the like, the probing needle against the chip bonding pad Contact work is difficult, the position of the needle is bad, and there is a limit to the number of needles. In addition, since the coefficient of thermal expansion is different between glass epoxy substrates and silicon wafers, there is also a problem that deviation occurs when the temperature is raised even when the alignment is performed at normal temperature. Further, Japanese Patent Application Laid-open No. Hei 5-340964 proposes a test apparatus for forming bumps on a semi-transparent polyimide film and aligning using alignment marks in an optical microscope from an opening on the polyimide film. The reliability of the polyimide membrane is a problem.
본 발명은 상기와 같은 문제점을 해소하기 위해 이루어진 것으로서 웨이퍼 상태에서의 칩 번인 시험이 가능한 프로브 카드 및 그것을 이용한 시험장치를 제공하는 것을 목적으로 한다.The present invention has been made to solve the above problems, and an object of the present invention is to provide a probe card capable of testing a chip burn-in in a wafer state and a test apparatus using the same.
(과제를 해결하기 위한 수단)(Means to solve the task)
본 발명에 따른 프로브 카드는, 반도체 웨이퍼위에 형성된 복수의 칩의 전기적 특성을 일괄로 측정하기 위한 프로브 카드에 있어서, 석영 유리기판과, 이 석영 유리기판에 배치되며, 상기 칩의 본딩패드에 접촉되는 접촉전극과, 상기 석영 유리기판에 배치된 검사용의 회로 배선을 구비한 것이다.A probe card according to the present invention is a probe card for collectively measuring electrical characteristics of a plurality of chips formed on a semiconductor wafer, the probe card being disposed on a quartz glass substrate and the quartz glass substrate, and contacting a bonding pad of the chip. The contact electrode and the circuit wiring for inspection arrange | positioned at the said quartz glass board | substrate are provided.
또한, 본 발명에 따른 시험장치는 상기의 프로브 카드를 피측정물인 복수의 칩이 형성된 반도체 웨이퍼위에 위치시키는 고정수단과, 반도체 웨이퍼를 올려놓으며, 프로브 카드와의 위치맞춤을 실행하는 위치 결전수단과, 프로브 카드의 각 접촉전극을 칩의 본딩 패드에 대하여 균일하며, 일정한 압력으로 접촉시키는 압착수단과, 칩에 접촉전극에서 전기신호를 인가하는 신호 인가수단과, 칩을 가열 또는 냉각하는 수단을 구비한 것이다.In addition, the test apparatus according to the present invention includes a fixing means for positioning the probe card on a semiconductor wafer on which a plurality of chips to be measured are formed, a position deciding means for placing the semiconductor wafer and performing alignment with the probe card; Compression means for contacting each contact electrode of the probe card to the bonding pad of the chip at a constant pressure, signal applying means for applying an electrical signal from the contact electrode to the chip, and means for heating or cooling the chip. It is.
도 1은 본 발명의 실시예 1에 따른 프로브 카드를 나타내는 단면도.1 is a cross-sectional view showing a probe card according to Embodiment 1 of the present invention.
도 2는 본 발명의 실시예 2에 따른 프로브 카드를 나타내는 상면도.Fig. 2 is a top view showing a probe card according to Embodiment 2 of the present invention.
도 3a 및 도 3b는 본 발명의 실시예 1에 따른 프로브 카드의 프로빙 패드 구조를 나타내는 단면도.3A and 3B are sectional views showing a probing pad structure of a probe card according to Embodiment 1 of the present invention.
도 4는 본 발명의 실시예 1에 따른 시험장치의 구성을 나타내는 단면도.4 is a cross-sectional view showing a configuration of a test apparatus according to Example 1 of the present invention.
도 5는 종래의 번인 시험방법을 나타내는 설명도.5 is an explanatory diagram showing a conventional burn-in test method.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 : 반도체 웨이퍼2 : 표면 보호막1: semiconductor wafer 2: surface protective film
3 : 본딩 패드4 : 프로브 카드3: bonding pad 4: probe card
5 : 석영 유리기판6 : 프로빙 패드5: quartz glass substrate 6: probing pad
7 : 커넥터8 : 회로배선7 connector 8: circuit wiring
9 : 도금부10 : 도전성 고무9 plating part 10 conductive rubber
11 : Au볼12 : X Y스테이지11: Au ball 12: X Y stage
13 : 하부 압착판14 : 히터13: lower pressing plate 14: heater
15 : 상부 압착판16 : 웨이퍼 압착용 고정판15: upper pressing plate 16: wafer holding plate
17 : 압착용 나사18 : 압착용 모터17: crimping screw 18: crimping motor
19 : 압착용 모터 제어장치20 : 광학 현미경19: crimping motor control device 20: optical microscope
21 : 전압 인가장치31 : 반도체 집적회로21: voltage applying device 31: semiconductor integrated circuit
32 : 소켓33 : 항온조32 socket 33 thermostat
34 : 전압 인가장치34: voltage applying device
실시예 1Example 1
도 1, 도 2는 본 발명의 실시예 1인 프로브 카드를 나타내는 단면도 및 상면도이다. 도면에 있어서 부호 1은 그 주면에 피측정물인 칩이 다수 형성된 반도체 웨이퍼, 2는 표면 보호막, 3은 각각의 칩 회로소자와 외부전극 단자를 접속하는 접속영역인 본딩 패드, 4는 본 발명에 따른 프로브 카드이며, 5는 석영 유리기판, 6은 칩의 본딩 패드(3)와 전기적 커넥터를 취하기위한 접촉전극인 프로빙 패드, 7은 전원 및 그랜드등에 접속되는 커넥터, 8은 검사용의 회로배선을 각각 나타낸다. 또한, 도 3은 프로빙 패드(6)의 구조를 나타내는 단면도이며, 도면에서 9는 도금부, 10은 탄력성이 있는 도전성 고무, 11은 도전성 고무(10)의 위에 형성된 Au볼이다.1 and 2 are a cross-sectional view and a top view showing a probe card according to a first embodiment of the present invention. In the drawing, reference numeral 1 denotes a semiconductor wafer on which a plurality of chips to be measured are formed on a main surface thereof, 2 a surface protective film, 3 a bonding pad which is a connection area for connecting each chip circuit element and an external electrode terminal, and 4 according to the present invention. A probe card, 5 is a quartz glass substrate, 6 is a bonding pad 3 of a chip and a probing pad which is a contact electrode for taking electrical connectors, 7 is a connector connected to a power supply and a gland, and 8 is a circuit wiring for inspection. Indicates. 3 is a sectional view showing the structure of the probing pad 6, in which 9 is a plating portion, 10 is a conductive rubber having elasticity, and 11 is an Au ball formed on the conductive rubber 10. FIG.
본 실시예에 의한 프로브 카드(4)는 피측정물인 칩이 형성된 실리콘 웨이퍼와 열팽창 계수가 가까운 석영 유리기판(5)을 이용하여 형성되어 있기때문에 번인 시험에서 상온에서 고온으로 온도를 변화시켜도, 프로빙 패드(6)와 본딩 패드(3)의 위치 벗어남이 발생되지 않기때문에 상온에서 위치결정을 행할 수 있다. 또한, 석영 유리기판(5)은 투명하기 때문에 종래의 유리 에폭시 기판과 같이 위치 맞춤을 위한 구멍을 마련하여 둘 필요가 없으며, 프로빙 패드(6)와 본딩 패드(3)의 위치맞춤이 용이하다.The probe card 4 according to the present embodiment is formed by using a silicon wafer on which a chip as a measurement target is formed and a quartz glass substrate 5 having a thermal expansion coefficient close to each other. Since the positional deviation of the pad 6 and the bonding pad 3 does not occur, positioning can be performed at normal temperature. In addition, since the quartz glass substrate 5 is transparent, it is not necessary to provide a hole for alignment like a conventional glass epoxy substrate, and the positioning of the probing pad 6 and the bonding pad 3 is easy.
또한, 도 3a에 나타내듯이 프로빙 패드(6)에 탄력성이 있는 예를들면 에폭시 수지를 주성분으로 하여 은구를 포함하는 도전성 고무(10)를 이용하는 것에 의해 종래의 침이 세워진식의 금속 프로버에 비교하여 밀착성이 좋으며, 복수의 본딩 패드(3)에 대하여 균일한 접촉압으로 접촉시키는 것이 가능하다. 또한 도 3b에 나타내듯이 도전성 고무(10)의 위에 도전성이 우수한 Au볼(11)을 형성하는 것에 의해 본딩 패드(3)와의 전기적 도통이 보다 확실하게 된다. 또한, 번인 시험에는 엄격한 사용조건에 견딜수 있는 안정된 부재가 필요하며, Au볼(11)은 고온-저온의 극심한 온도의 상승 하강을 반복하여도 열화되는 일 없이 안정이 우수하다.In addition, as shown in Fig. 3A, by using the conductive rubber 10 containing silver spheres, for example, having an elasticity in the probing pad 6, for example, an epoxy resin as a main component, it is compared with a conventional metal prober with a standing needle. Therefore, adhesiveness is good and it is possible to make contact with the some bonding pad 3 with uniform contact pressure. In addition, as shown in FIG. 3B, by forming the Au balls 11 having excellent conductivity on the conductive rubber 10, electrical conduction with the bonding pads 3 is more secure. In addition, the burn-in test requires a stable member that can withstand the strict use conditions, and the Au ball 11 is excellent in stability without deterioration even after repeated increase and decrease of extreme temperature of high temperature and low temperature.
도 4는 상기의 프로브 카드(4)를 이용한 시험장치의 구성을 나타내는 단면도이다. 도면에 있어서 부호 12는 X Y스테이지, 13은 하부 압착판, 14는 웨이퍼(1)의 가열수단인 히터, 15는 유리제의 상부 압착판, 16은 웨이퍼 압착용 고정판, 17은 웨이퍼 압착용 고정판(16)에 나사 결합됨과 함께 상부 압착판(15)에 회전 자유로이 장착되며, 축 방향으로 이동하여 상부 압착판(15)을 상하운동 시키는 압착용 나사, 18은 압착용 나사(17)를 회전시키는 압착용 모터, 19는 압착용 모터의 제어장치, 20은 광학 현미경, 21은 전압 인가장치이다.4 is a cross-sectional view showing the configuration of a test apparatus using the probe card 4 described above. In the drawing, reference numeral 12 denotes an XY stage, 13 a lower press plate, 14 a heater as a heating means for the wafer 1, 15 an upper press plate made of glass, 16 a wafer press plate, and 17 a wafer press plate 16 Screw is coupled to the upper pressing plate (15) is rotatably mounted, the screw for moving the axial direction to move the upper pressing plate 15 up and down, 18 is a pressing screw for rotating the pressing screw (17) The motor, 19 is a control device for the crimping motor, 20 is an optical microscope, 21 is a voltage applying device.
이어서 동작에 관하여 설명한다. X Y스테이지(12)위에 올려놓여진 하부 압착판(13)위에는 히터(14)가 마련되며, 피 측정물인 복수의 칩이 형성된 웨이퍼(1)를 가열한다. 또한 본 실시예에서는 가열수단으로서 히터(14)를 마련하였지만, 냉각수단을 마련하는 경우도 있다. 압착용 모터 제어장치(19)는 압착용 모터(18)를 구동하며, 압착용 나사(17)를 회전시켜 상부 압착판(15)하면에 마련된 프로브 카드(4)의 프로빙 패드(6)를 반도체 웨이퍼(1)위에 마련한 본딩 패드(3)에 압착시킨다.Next, the operation will be described. A heater 14 is provided on the lower pressing plate 13 placed on the X Y stage 12 to heat the wafer 1 on which the plurality of chips as the object to be measured are formed. In addition, although the heater 14 was provided as a heating means in this embodiment, cooling means may be provided in some cases. The crimping motor controller 19 drives the crimping motor 18, and rotates the crimping screw 17 to semiconductor the probing pads 6 of the probe card 4 provided on the lower surface of the upper crimping plate 15. The bonding pad 3 provided on the wafer 1 is pressed.
프로빙 패드(6)와 본딩 패드(3)의 위치결정 수단으로서는 광학 현미경(20)에 의해 어느측도 투명한 유리제의 상부 압착판(15)과 설영 유리기판(5)을 통하여 양자의 패턴을 인식하며, X Y스테이지(12)를 이동시켜서 중복시킨다. 본 실시예에서는 프로빙 패드(6)는 본딩 패드(3)의 구멍을 내기위한 용도의 마스크를 이용하여 형성되어 있기 때문에 각각의 위치는 완전하게 일치하며, 얼라이먼트 마크는 특히 형성할 필요가 없다. 광할 현미경(20)에 카메라를 접속하며, 화상처리에 의해 위치결정를 행하여도 좋다. 또한, 석영 유리기판(5)위에 형성된 전원공급용의 외로배선(8)은 프로빙 패드(6)의 폭에 비하여 충분하게 가늘기 때문에 얼라이먼트에는 영향이 없다. 또한, 본 실시예에서는 유리제의 상부 압착판(15)을 이용하였지만, 투명 또는 반투명으로 적정한 경도가 있는 안정한 것이라면 다른 재료라도 좋다. 또한 상부 압착판(15)으로서 불투명한 재료를 이용하는 경우에는 패턴을 인식하기 위한 개구부를 마련하면 좋다.As the positioning means of the probing pad 6 and the bonding pad 3, both patterns are recognized by the optical microscope 20 through the upper press plate 15 and the glass substrate 5 of transparent glass, The XY stage 12 is moved and overlapped. In this embodiment, since the probing pad 6 is formed using a mask for drilling holes in the bonding pad 3, the respective positions are perfectly matched, and alignment marks need not be particularly formed. A camera may be connected to the microscope 20 to be lighted, and positioning may be performed by image processing. In addition, since the outward wiring 8 for power supply formed on the quartz glass substrate 5 is sufficiently thin as compared with the width of the probing pad 6, there is no influence on the alignment. In addition, although the upper press plate 15 made of glass was used in the present Example, other materials may be sufficient as long as it is a stable thing with moderate hardness, transparent or translucent. In addition, when using an opaque material as the upper press plate 15, what is necessary is just to provide the opening part for recognizing a pattern.
위치맞춤이 완료되어 균일한 접촉압으로 프로빙 패드(6)를 본딩 패드(3)에 압착시킨후 번인 시험을 개시 한다. 칩은 피터(14)에 의해 가열되기 때문에 가속시험을 행할 수 있다. 시험은 전압 인가장치(21)에서 프로빙 패드(6)를 통해 반도체 웨이퍼(1)위의 본딩 패드(3)에 펄스 신호 또는 직류정류를 인가하며, 칩을 동작시켜 번인 시험이 실시된다.After the alignment is completed, the probing pad 6 is pressed against the bonding pad 3 with a uniform contact pressure and the burn-in test is started. Since the chip is heated by Peter 14, the accelerated test can be performed. In the test, a pulse signal or direct current rectification is applied to the bonding pad 3 on the semiconductor wafer 1 through the probing pad 6 in the voltage applying device 21, and the burn-in test is performed by operating the chip.
본 실시예의 시험장치에 의하면, TEG의 신뢰성 평가등도 다수 실시할 수 있으며, 제품 칩에 적용한 경우 조립후의 번인 시험을 실시할 필요가 없게된다. 또한, 웨이퍼 상태로 번인 시험을 행할 수 있기때문에 종래와 같이 팩케이지의 내열성을 고려할 필요가 없으며, 온도가속을 충분하게 실행할 수 있다. 또한 팩케이징 전에 고장을 발견할 수 있기때문에 불량품을 팩케이징하는 불합리함은 없게된다. 또한 종래의 번인시험과 같이 다수의 소켓(32), 항온도(33)등의 설비도 필요없으며, 저 가격화, 에너지 절감화도 이룰수 있다.According to the test apparatus of this embodiment, the reliability evaluation of the TEG can be performed in many cases, and when applied to a product chip, it is not necessary to perform the burn-in test after assembly. In addition, since the burn-in test can be performed in the wafer state, it is not necessary to consider the heat resistance of the package as in the prior art, and the temperature acceleration can be sufficiently performed. In addition, failures can be detected before packaging, eliminating the irrationality of packaging defective products. In addition, as in the conventional burn-in test, a plurality of sockets 32, a constant temperature 33, and other equipment are not required, and the cost can be reduced and energy can be achieved.
상기와 같이 본 발명에 의하면, 투명하고 반도체 웨이퍼와 열팽창 계수에 가까운 석영 유리기판을 이용하였기 때문에 반도체 웨이퍼상에 형성된 다수 칩과의 위치맞춤이 용이하며, 또한 온도변화에 의해서도 위치벗어남이 발생되지 않기때문에 상온에서 위치맞춤을 실행하여 고온에서 시험할 수 있는 프로브 카드를 얻을 수 있는 효과가 있다.As described above, according to the present invention, since the semiconductor wafer and the quartz glass substrate close to the thermal expansion coefficient are used, alignment with a plurality of chips formed on the semiconductor wafer is easy, and no deviation occurs due to temperature change. Therefore, it is effective to obtain a probe card that can be tested at high temperature by performing alignment at room temperature.
또한, 접촉전극은 본딩 패드 형성용 마스크를 이용하여 형성되기 때문에 각각의 위치가 일치되어 얼라이먼트 마크를 특별히 형성할 필요가 없는 효과가 있다.In addition, since the contact electrodes are formed by using a bonding pad forming mask, the respective positions are coincident with each other, so that there is no need to form alignment marks in particular.
Claims (3)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP96-263970 | 1996-10-04 | ||
| JP8263970A JPH10111315A (en) | 1996-10-04 | 1996-10-04 | Probe card and testing device using the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR19980032057A true KR19980032057A (en) | 1998-07-25 |
Family
ID=17396757
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970009246A KR19980032057A (en) | 1996-10-04 | 1997-03-19 | Probe card and test device using it |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPH10111315A (en) |
| KR (1) | KR19980032057A (en) |
| CN (1) | CN1153269C (en) |
| DE (1) | DE19717369A1 (en) |
| TW (1) | TW313688B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100689180B1 (en) * | 2006-02-07 | 2007-03-02 | 주식회사 코셈 | Prob card for a semiconductor wafer |
| KR101471778B1 (en) * | 2013-07-23 | 2014-12-10 | 세메스 주식회사 | Jig for detecting actual contact position between needles of probe card and wafer and method of detecting the actual contact position using the same |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3326095B2 (en) | 1996-12-27 | 2002-09-17 | 日本発条株式会社 | Conductive contact |
| KR20010021666A (en) * | 1997-07-14 | 2001-03-15 | 마에다 츠구요시 | Conductive contact |
| JP2001033487A (en) | 1999-07-22 | 2001-02-09 | Mitsubishi Electric Corp | Probe card for testing semiconductor integrated circuit and manufacture of this probe card |
| KR20020054914A (en) * | 2000-12-28 | 2002-07-08 | 주식회사 현대 디스플레이 테크놀로지 | Test unit of tft lcd panel |
| DE10308916A1 (en) * | 2003-02-28 | 2004-09-16 | Infineon Technologies Ag | Appliance for electric contacting substrate, containing integrated circuit with exposed contacts and contacting assembly with counter contacts on contacting plate in spacing corresponding to circuit contacts |
| JP3757971B2 (en) * | 2003-10-15 | 2006-03-22 | カシオ計算機株式会社 | Manufacturing method of semiconductor device |
| KR20070010187A (en) * | 2004-04-27 | 2007-01-22 | 제이에스알 가부시끼가이샤 | Sheet-shaped probe, manufacturing method thereof and application thereof |
| DE102004035343A1 (en) * | 2004-07-21 | 2005-09-29 | Infineon Technologies Ag | Contacting card for use in testing integrated circuits, has a substrate carrier with contacts matching those of a wafer substrate to be tested and connects from these contacts to a testing device |
| CN1326225C (en) * | 2004-11-05 | 2007-07-11 | 中国科学院上海微系统与信息技术研究所 | Micro-mechanical chip testing card and producing method thereof |
| US20060109014A1 (en) * | 2004-11-23 | 2006-05-25 | Te-Tsung Chao | Test pad and probe card for wafer acceptance testing and other applications |
| JP2006292727A (en) * | 2005-03-18 | 2006-10-26 | Alps Electric Co Ltd | Semiconductor transfer tray, burn-in board using the same, inspection apparatus for burn-in test, burn-in test method, and semiconductor manufacturing method |
| CN1321320C (en) * | 2005-03-23 | 2007-06-13 | 北京青鸟元芯微系统科技有限责任公司 | Chip degree aging method of thermal diffusion pressure drag type MEMS pressure sensor |
| DE102006054734A1 (en) * | 2005-12-05 | 2007-06-06 | Feinmetall Gmbh | Electrical test device for testing an electrical device under test and corresponding method |
| JP5221118B2 (en) * | 2007-12-14 | 2013-06-26 | 東京エレクトロン株式会社 | Inspection device |
| JP2011095028A (en) * | 2009-10-28 | 2011-05-12 | Optnics Precision Co Ltd | Probe sheet |
| TW201216391A (en) * | 2010-10-11 | 2012-04-16 | Ind Tech Res Inst | Detection method and detection device for LED chips on wafer and transparent probe card thereof |
| JP6218718B2 (en) * | 2014-10-22 | 2017-10-25 | 三菱電機株式会社 | Semiconductor evaluation apparatus and evaluation method thereof |
| CN105044402A (en) * | 2015-08-25 | 2015-11-11 | 贵州航天计量测试技术研究所 | Encapsulated micro-wave voltage-controlled oscillator test device |
| CN112213612A (en) * | 2019-07-09 | 2021-01-12 | 刘小伟 | Automobile electrician and electronic practical training basic circuit testing device |
| CN111090033A (en) * | 2019-12-24 | 2020-05-01 | 淮安芯测半导体有限公司 | Semiconductor device and probe test method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05340964A (en) * | 1992-06-05 | 1993-12-24 | Mitsubishi Electric Corp | Tester for wafer and chip |
-
1996
- 1996-10-04 JP JP8263970A patent/JPH10111315A/en active Pending
-
1997
- 1997-01-31 TW TW086101087A patent/TW313688B/en active
- 1997-03-19 KR KR1019970009246A patent/KR19980032057A/en not_active Application Discontinuation
- 1997-04-24 DE DE19717369A patent/DE19717369A1/en not_active Ceased
- 1997-05-23 CN CNB971113009A patent/CN1153269C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100689180B1 (en) * | 2006-02-07 | 2007-03-02 | 주식회사 코셈 | Prob card for a semiconductor wafer |
| KR101471778B1 (en) * | 2013-07-23 | 2014-12-10 | 세메스 주식회사 | Jig for detecting actual contact position between needles of probe card and wafer and method of detecting the actual contact position using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| TW313688B (en) | 1997-08-21 |
| DE19717369A1 (en) | 1998-04-09 |
| CN1179006A (en) | 1998-04-15 |
| CN1153269C (en) | 2004-06-09 |
| JPH10111315A (en) | 1998-04-28 |
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