KR19980030711A - Data Deformatting Circuit of Image Decoder - Google Patents

Abstract

According to the present invention, in digitally encoding and decoding image information, when a coded data string input from an ECC processing unit of a format processing unit of an encoder is input to a deformatting circuit of a decoder, the data is separated in advance for each component, and the state data is a state data. The STA component data is sent to a separate register and sent to the dequantizer, while the QNO component data and DC component data that are not deformatted are waited in the buffer memory F1 / F2 after the deformatter, and the AC component data is forwarded to the deformatter. Send the data to the memory S1 / S2 and deformat it in the deformatter, and then combine the QNO component data and DC component data and send them to the dequantizer to dequantize the data together with the state data. Formatted images by storing them in their respective memories By de-formatting and deformatting data components in the process of decoding the information, the data access time generated during the reformatting process is shortened, and the actual data format time is also shortened. Has the effect of improving.

Description

Data Deformatting Circuit of Image Decoder

According to the present invention, in digitally encoding / decoding video information, the data is formatted by a format processing unit of a previous encoder and deformatted in advance for each component of the input data so that only the deformatted component data can be deformatted. The present invention relates to a data deformatting circuit in an image decoder which shortens the deformatting time.

Currently, various multimedia devices, such as a high definition TV (HDTV) or a set-top box, including a digital video cassette recorder (hereinafter, referred to as a DVCR), display video images differently from the prior art. It is digitally compressed for transmission and processing.

To this end, after converting a video taken by a video camera or an analog video signal input from various video signal sources into digital information, it is stored in a frame memory (memory that stores one screen of image data). Later, the pixels are decomposed and processed in pixel units. For example, one screen may be represented as 352 x 240 pixels. At this time, each pixel has a luminance (brightness information of the image) and a color difference (color information of the image), and the luminance and the color difference (color) compress the information by the following three methods.

1) In general, images have similar values between adjacent pixels (high correlation), so information is compressed using on-screen (spatial) correlation. (Strictly, compression operation is performed on pixel difference values between screens.) Do it.)

2) The information is compressed using the inter-screen (temporal) correlation by storing the information of the previous screen and representing the current screen as a difference from the previous screen.

3) When hatching by the method of 1) and 2) above, the information is compressed using the different probability of occurrence of the code.

The orthogonal transform (decomposition of image information into frequency components) is widely used among various methods for image compression, among which a discrete cosine transform (DCT) is used for image encoding. It is widely used in international standards. In this DCT, by dividing a single image into square areas of constant size and performing conversion processing on each area, it is possible to obtain a highly precise image of the highest frequency from a screen component (DC) having an average value in the area (the whole area is the same value). It is decomposed into image components of various frequencies up to. This decomposition process is called orthogonal transformation. The advantage of such orthogonal transformation (particularly, DCT) is that pixel values (e.g., luminance) that are irregularly spread on the screen before conversion tend to concentrate toward the low frequency term after conversion. Therefore, good information compression can be achieved with little information loss through the operation of discarding the high frequency terms.

Here, the process of discarding the high frequency terms is quantization. In this case, the pixel value or the component value of each orthogonally transformed frequency is divided by a value (denominator) called a quantization step size, and the rest is rounded off. However, this missing portion is not completely restored to the war state even if it is multiplied by the quantization step size during reproduction. In this case, the larger the denominator, the more many terms become almost zero, and thus the compression ratio can be increased, but the high frequency terms are lost, the fineness is lost, and the low frequency terms become dim due to the quantization error. . On the contrary, the smaller the denominator is, the smaller the cut-off error is. Therefore, the fineness is not impaired at the time of reproduction, so that it is closer to the original picture, but the compression ratio is lowered instead.

In the MPEG II (Motion Picture Experts Group), the second video encoding standard standard, hereinafter referred to as MPEG II, shows the encoding process of the image information using the DCT. Is input to the orthogonal converter 11 and processing starts. In this case, the input of the DCT block may include a frame as it is, or a difference between a frame and a motion compensated frame may be entered. The former is for intra coding and the latter is for inter coding. Motion compensation in MPEG II includes P type and B type, and may also compensate for motion for each field or compensate for motion for each frame. The P type also uses a unique method called dual prime. When such frame data is input, the quadrature converter 11 performs 8 x 8 pixels as one block, performs DCT operation (compression based on intra-screen spatial correlation), and sends the result to the quantizer 12. The quantizer 12 determines the quantization step using a weight matrix variable (weight_matrix) representing the weight of each DCT coefficient and a quantization size code variable (quantizer_scale_code) for determining the step of the quantization step. Each coefficient after quantization is variable length coded (VLC) in the variable length encoder 13, and DC coefficients of an intra block are the magnitudes of DC components of the DCT coefficients. The code is divided into two, a variable (dct_dc_size) indicating a and a variable (dct_dc_differential) indicating a difference between DC components, and the remaining coefficients are coded using a VLC table defined in MPEG II.

Such motion compensation, DCT type, and quantization are performed in units of macro blocks, and the coding type is informed through a variable called macro type. That is, the macro_type alone can determine whether the macroblock has compensated for motion, whether the DCT coefficient is transmitted or not, whether or not the quantization scale code (quantizer_scale _code) is transmitted.

Each macroblock is coded block by block, and a variable used to indicate whether blocks belonging to the macroblock are coded or skipped is coded_block_pattern (). Thereafter, such data are bundled with various headers, extensions, and user data to form a syntax and transmitted to the decoder through the buffer 14. The number of bits generated per picture is variably controlled according to the fullness of the buffer, which is used by the encoder to ensure that the buffer 14 does not underflow or overflow. The state of (14) must be monitored at all times, and the bit generation amount of the next picture must be adjusted.

In addition, the quantized result of the quantizer 12 is also sent to the inverse quantizer 15 and the inverse orthogonal transformer 16 to undergo the inverse quantization and the inverse orthogonal transformation process, and in the first adder 17, The bit stream data is summed with the data sent from the received second adder 18 and averaged and sent to the second adder 18 and the frame memory 21. Then, the motion predictor 19 predicts the motion based on the frame information sent from the frame memory 21 and the variable value sent from the motion calculator 20, and sends the motion to the second adder 18 again to convert the motion to the second adder 18. Repeat the process by feeding back to).

In the decoding process of the data received from the buffer 14 through the encoding process as described above, as shown in FIG. 2, the encoded data coded in the encoding process is transmitted in the form of a bit stream through the buffer 14 of the encoder. After receiving it, the variable length decoder 22 extracts the variable length coded DCT coefficient to obtain QFS [n] through the reverse process. Here, n = 0 indicates a DC coefficient, or an AC coefficient following it. Normally, DC coefficients in inter coding are coded using a different method than other coefficients using the VLC table because the magnitude is very large, unlike normal coefficients. In addition, the absolute size is not transmitted, and only the difference value is transmitted compared with the corresponding value of the previous block. Therefore, a predictor is used, which has the coefficient value of the previous block. In other words, a color component is referred to as cc, and when cc = 0, a luminance signal is represented. If cc = 1, a Cb element is used, and if cc = 2, a Cb element is represented. On the other hand, since there are too many values for variable length encoding of the DC difference of an intra block as it is, the code is divided into two parts, dct_dc_size and dct_dc_differential, without using the VLC table. At this time, dct_dc_size is a variable length code value of 2 to 10 bits for the luminance signal and the color signal, respectively, and has a value ranging from 0 to 63 for the luminance signal and -2047 to +2047 for the color signal.

As described above, the variable length coded signal in the variable length decoder 22 converts the one-dimensional DCT coefficient of QFS [n] into two dimensions according to the scanning method in the inverse scanner 23, which is a zigzag scan. ) Or alternate scan, which can be used arbitrarily. If the value of alternate_scan in Equation 1 is 0, it represents a zigzag scan, and if 1, it represents an alternative scan.

[Equation 1]

QFS [v] [u] = QFS [scan [alternate_scan] [v] [u]]

The two-dimensionalized signal in this inverse scanner 23 restores the actual DCT coefficient value in inverse quantizer 24. In this case, the DC coefficient of the in-block block (the value of the upper left corner of the 8 x 8 block) is obtained by multiplying the received quantization value by 8 (that is, [inverse quantization value = 8 x [quantization value]), and the inverse quantization of other coefficients is The AC coefficients (63 other than the left top edge of an 8 x 8 block) first double the received quantization values (between the screens, plus +1 or -1 away from zero) and then add the quantization MQUANT) multiplies the value of the corresponding position in the quantization matrix by dividing by 16.In this result, the decimal point is truncated, and if the result is an even number, +1 or -1 is added in the direction of approaching zero and close to zero. Make it the odd number of the page. If the result is greater than 2047, it is 2047. If the result is less than -2048, it is -2048. This is to prevent IDCT mismatch in the inverse orthogonal transformation. The quantization characteristic value (MQUANT) used in this operation is initialized at the beginning of the slice and updated once in the middle until the next update. This is used as is.

Next, the inverse orthogonal transformer 25 performs inverse orthogonal transformation (IDCT) by the following equation.

[Equation 2]

f (x, y) =

Where u, v, x, y = 0, 1, 2, 3 ... N-1,

In addition, x and y are spatial coordinates in the same domain, and u and v are coordinates in the transform domain.

That is, C (u), C (v) = (if u, v = 0)

It is represented by 1 (other cases).

For reference, the DCT of the M × N block defined in MPEG is expressed as in Equation 3 below.

[Equation 3]

f (u, v) =

In the IDCT, if the precision on the encoder side and the precision on the decoder side do not coincide, the error accumulates between the encoder and the decoder when the interframe error (DCT operation for the prediction error) is continuous. This is called IDCT mismatch. In MPEG, all values reproduced by inverse quantization of coefficients are limited to odd numbers to avoid this error accumulation. The root cause of this IDCT mismatch is that even though IDCT is a real calculation, the data must be an integer. For example, when the theoretical value of the IDCT pixel is an integer + 0.5, the probability that the result is shifted by 1 by rounding is 1/2 even if the precision of IDCT prescribed by the standard is increased. It is possible to avoid this by the rounding rule, but before the standardization, ICTs for DCT and IDCT are already on the market, and this problem is decided by limiting all the results of IDCT to radix. This solved most IDCT mismatches.

Thereafter, the motion compensator 26 compensates for the motion in the unit of a field or a unit of frame. Accordingly, field prediction may be performed in a field picture, and both frame prediction and field prediction may be used in a frame picture. In a simple frame picture, one motion vector (MV) is required for a P type per 16 × 16 macroblock, and two motion vectors MV are required in the B type, which are forward and backward. Do. In the case of simple field prediction, two movements, one from the top and bottom two fields in the P type per 16 x 16 macroblock, and four moves from the top, bottom, backward, and forward in the B type. Vector MV is needed. In MPEG II, a 16 x 16 prediction mode is specified for a field picture, and a dual prime mode is specified for a P picture. In this dual_prime mode, one MV and one differential motion are performed on the transmitting side. You send a differential motion vector and the decoder uses it to calculate four forward motion vectors. This mode is only used for P pictures. The 16x8 picture mode divides a 16x16 macroblock in one field picture into 16x8 blocks below and transmits one MV for each block below and below. The reason for this is that the vertical distance in the field picture is twice the frame picture, so the vertical axis length is too long to compensate for the motion of the 16 × 16 macroblock.

On the other hand, since field prediction can be used in both a field picture and a frame picture, the top and bottom fields may be respective fields or may indicate the top field and bottom field in one frame. In this case, the first and the second are called second fields in the order in which they are displayed. In MPEG II, the first field is designated whether the field is top or bottom. There is no guarantee that it will be in the top field. That is, field prediction in MPEG II is done by the most recently reconstructed fields. In this prediction process, the data predicted by using the information data of the previous frame is decoded and outputted through data exchange with the frame memory 27.

In the encoding of the video using the DCT method as described above, after the variable length encoding

Before the buffer 14 is sent to the decoder through the buffer 14, an additional process of formatting the data encoded by the variable length encoder 13 is performed.

A configuration of a data formatting circuit for performing this process is shown in FIG. 3, wherein the data encoded by the variable length encoder 13 of the encoder by the format processor 28 is F1 memory 30 and F2 memory which are temporary storage memories. (30 '), the data is divided into code word data and code length data by the format processor 28, and processed according to the video segment format. It transmits to the correction controller 29 to correct the error to send to the decoder.

At this time, the data is processed in units of segments, one segment is composed of five macro blocks, and each macro block is composed of six DCTs. Since one DCT is composed of 8 x 8 = 64 pixels (= pixel = bits), one segment becomes a data stream in the form of a bit stream of 1920 bits in total.

The format processing unit 28 divides data into three stages: path 1, path 2, and path 3.

In pass 1, each DCT block of the VLC data is read and stored in the temporary memories F1 (30) and F2 (30 '), and the corresponding segment data sequence is distributed to the buffer memories S1 (31) and S2 (31'). The remaining data is distributed to the MR 32 which is the auxiliary memory.

In pass 2, the remaining data in the MR memory 32 is distributed to the empty DCT in units of macro blocks, the macro blocks are filled, and the remaining data is stored in the VR memory 33.

In path 3, the remaining data in the VR memory 33 is distributed to the free DCTs in the segments in units of segments.

The remaining data is discarded after the pass 1, pass 2 and pass 3 processes as described above.

Such a series of pass processes are performed for each cycle period of the segment signal as shown in FIG. 4. Referring to this, when the first segment signal is provided to the formatter, the formatter converts the data string coded by the variable length encoder 13 into F1 ( 30) Read to memory and save. Then, when the second segment signal is provided to the formatter, the formatter similarly reads and stores the coded data string into the F2 (30 ') memory. At the same time, the data stored in the F1 30 memory is formatted and transferred to the buffer memory S1 31. When the third segment signal is provided, the recoded data string is read and stored in the F1 30 memory. At the same time, the formatted data transferred to the S1 31 memory is sent to the ECC processing unit 29, while the data stored in the F2 30 'memory is formatted and transferred to the buffer memory S2 31'. When the fourth segment signal is provided, the formatted data transferred to the S1 31 memory is sent to the ECC processing unit 29, while the formatted data transferred to the S2 31 'memory is sent to the ECC processing unit 29. The data stored in the F1 30 memory is formatted again and transferred to the buffer memory S1 31. After that, the above series of processes are repeated.

In this case, the data format configuration state when the data is formatted by the formatting processing unit 28 and transferred to the buffer memories S1 and S2 while the original uncompressed image information is formatted and processed is shown in FIG. 5.

These passes 1, 2 and 3 are processed during one segment signal period.

On the other hand, in encoding the video using the DCT method as described above, after the variable length encoding is performed, the data that has been formatted by the variable length encoder 13 before being sent to the decoder through the buffer 14 is deformatted by the decoder. After the process is finally reproduced, which is sent in the data formatting step in the data formatting step as shown in Figure 6 after correcting the error in the ECC processing unit 29, the deformatting unit 36 receives this data Of these data components, only the AC (AC) component is decoded to generate continuous zero run data and non-zero level data to combine these two data into a pair. QNO data which is a quantization number among these stored data values and input data And DC component values (DC value, mode, class number) are transmitted to the inverse quantizer 39 for processing.

The data processing of this system is processed in units of segments like formatting, one segment is composed of five macro blocks, and each macro block is composed of six DCT blocks.

Since the deformatting unit 36 processes data in accordance with the video segment format while passing through three stages of the path 1, the path 2, and the path 3, the deformatting unit 36 also passes the path 1, the path 2, the path. Processing in 3 steps.

In the pass1 step, data is deformatted in units of DCT blocks, in the pass2 step, in macroblock units, and in the pass3 step, in units of segments.

In this case, the deformatting unit 36 reads the DCT block in step 3 and stores the DCT block in the temporary memories S1 35 and S2 35 ', and then deformats the corresponding segment data string and then buffers F1 ( 37) and F2 (38) are distributed, stored, and sent to the dequantizer 39 in accordance with the signal. At this time, the de-formatting process is an STA component which is a state data composed of four bits indicating whether a data error and an error concealment of a macroblock unit are compressed in the formatted DCT data sent from the ECC processing unit 29. And the QNO component, which is the quantization number data, the DC component, which is the DC value, mode class number data, and the AC component, are put together in the memory.

However, in the data deformatting process in the conventional decoder as described above, each component of each segment coded data in the format of the coded data string in which the data formatted in the encoder is corrected by the ECC processing unit 29 is corrected. By decomposing them separately and processing them all at once without deformatting, the program burden becomes heavy during deformatting process, and the deformatting process is complicated, so the software burden increases and the processing time takes a lot. There was a problem.

In order to solve the above problems, the coded data string inputted by the ECC processing unit between the ECC processing unit and the deformatting unit of the deformatting circuit is pre-divided for each component through a hardware circuit to obtain state data. STA component data is sent to a separate register and sent to the inverse quantizer, while QNO component data and DC component data that are not deformatted are queued in buffer memory F1 / F2 at the rear of the deformatter, and only the AC component data is predecessed. Send the data to the memory S1 / S2 and deformat it in the deformatting unit, and then combine the QNO component data and the DC component data and send them to the dequantizer to dequantize the data together with the state data so that only the deformatted data can be read and processed directly. To minimize the software processing overhead It is an object of the present invention to provide a data deformatting circuit of an image decoder which shortens data access time and overall deformatting time.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block circuit diagram of an encoder generally used in a decitic (DCT) coding scheme.

2 is a block circuit diagram of a decoder generally used in a decidence decoding scheme.

3 is an overall block circuit diagram of a data formatting processing circuit in a diversity incubator.

4 is a timing pattern diagram illustrating a segment cycle used in data format in the data formatting processing circuit of FIG.

FIG. 5 is a data accommodating state diagram of a buffer memory showing an actual data accommodating state in a buffer memory used for data formatting in the data formatting processing circuit of FIG.

6 is an overall block diagram of a deformatting processing circuit of a conventional video demodulator.

7 is an overall block diagram of a deformatting processing circuit of the video decoder of the present invention.

8 is a detailed block circuit diagram of a separation unit in a deformatting processing circuit of the video decoder of the present invention according to FIG. 7;

* Explanation of symbols for the main parts of the drawings *

11: Quadrature Converter 12: Quantizer

13: variable-length encoder 14: buffer

15, 24, 39: inverse quantizer 16, 25: inverse orthogonal converter

17: first adder 18: second adder

19: motion predictor 20: motion calculator

21, 27: frame memory 22: variable length decoder

23: reverse scanner 26: motion compensator

28: format processing unit 29: ECC processing unit

30, 30 ': F1, F2 memory 31, 31': S1, S2 memory

32: MR memory 33: VR memory

34: auxiliary memory section 341: AR memory

342: R / W controller 343: address memory

35, 35 ': S1, S2 buffer memory 36: Deformatting section

37, 37 ': F1, F2 buffer memory 40: separation part

401, 402, 403: R3, R2, R1 Register 404: Counter

405, 406, 407: Controller 408, 409, 410: r1, r2, r3 buffer

In order to achieve the above object, the present invention provides an ECC processing unit for correcting errors in data formatted by an encoding circuit of an encoder, a separating unit for receiving data from the ECC processing unit and separating the data by components of the data; A deformatting unit for deformatting each component data separated from a component, a dequantizer for performing dequantization for restoring actual DCT coefficient values of the deformatted data in the deformatting unit, and the deformatting unit for data A buffer memory for buffering the AC component data separated in the separating unit by the control of the deformatting unit when deformatting the data, and in the separating unit under the control of the deformatting unit when the deformatting unit deformats the data. It includes a buffer memory for buffering the separated DC component data.

In the present invention as described above, when the error of the formatted data is sent by the ECC processing unit of the formatter of the encoder, the data input in the formatting step in the separation unit is separated into respective components (STA, QNO, DC, AC). Then, only the component data to be deformatted is deformatted by the deformatting unit to quantize the deformatted data and the remaining component data together in a subsequent dequantizer to restore the original DCT coefficients.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

The present invention for achieving the above object is sent to the ECC processing unit 29 and the ECC processing unit 29 for correcting errors in the data formatted in the formatter circuit of the encoder in front of the deformatting circuit as shown in FIG. A separating unit 40 which receives the incoming data and separates it for each component of the data, a deformatting unit 36 which deformats each component data in which the components are separated in the separating unit 40, and the deformatting unit ( An inverse quantizer 39 for performing inverse quantization for restoring the actual DCT coefficient value of the data deformatted in 36), and the deformatter 36 of the deformatter 36 when the deformatter 36 deformats the data. A buffer memory S1 / S2 (35, 35 ') for buffering the AC component data separated by the separating unit 40 by control, and the deformatting unit 36 when the deformatting unit 36 deformats the data. DC component separated from the separation unit 40 by the control of Quantized code components (QNO) buffer memory F1 / F2 (37, 38) for buffering the data was configured to include a.

As shown in FIG. 8, the separating unit 40 includes register means for receiving and storing data corrected by an error from data formatted by the ECC processing unit 29 of the formatting circuit on the encoder side of the front end, and stored from the register means. And buffering means for dividing the data for each component and temporarily storing the data in a separate buffer memory, and controlling means for counting a system clock and providing an enable signal for reading each component data to the buffering means.

Also, the register means includes registers R3, R2, and R1 (401, 402, 403) which sequentially receive formatted data from which an error is corrected from the ECC processing unit 29 of the formatter of the encoder. .

The buffering means includes r1 (408) which is a temporary storage buffer for reading and storing state data (STA) from the register R1 (403), and DC component data and quantization number data from the registers R3 to R1 (403 to 401). R2 (409), a temporary storage buffer for reading and storing (QNO), and r3 (410), a temporary storage buffer for reading and storing AC component data (AC) from the registers R3 to R1 (403 to 401). It was configured to include.

The control means includes a counter 404 for counting an enable signal provided by the system and providing a read enable signal for each component, and the registers R3 to R1 according to the enable signal provided by the counter. And controllers 405, 406, and 407 which provide control signals to the buffer memories r1 to r3 to read respective component data from (403 to 401).

According to the present invention configured as described above, as shown in FIG. 7, when the error of the formatted data is sent by the ECC processing unit 29 of the formatting circuit of the encoder before the deformatting circuit, the deformatting circuit according to the present invention is corrected. In the separating unit 40, the input data is separated into each component (STA, QNO, DC, AC) and sent to the deformatting unit 36 to deformat the formatted data, and then dequantized at a later stage. Inverse quantization at the device 39 restores the original DCT coefficients.

At this time, looking at the process of separating into each component (STA, QNO, DC, AC) of the data input from the separator 40 in detail, as shown in Figure 8, first input to the separator 40 The data to be input is input to three registers R3 (401), R2 (402) and R1 (403) of the register means in accordance with the clock provided by the system. At this time, since the input data is input in units of 8 bits, 8 bits of data are sequentially read in each of the three registers.

On the other hand, in the counter of the control means 404 when the data is input to each of the three registers as described above, receives the enable signal (enable) provided from the system to calculate the timing to decode the data temporarily stored in the register means A separate enable signal is provided to each of the three controllers 405, 406, and 407 that provide data read enable signals for each component so that the format processor 36 can read the components separately and store them in each buffer of the buffering means. to provide. Then, the three controllers generate STA-EN signals, DC / QNO-EN signals, and AC-EN signals, and provide them to the deformatter 36 to separate data temporarily stored in the three registers for each component. Read it and transfer it to the buffer memory of the buffering means.

As a result, when the STA-EN signal is input, the deformatting unit 36 reads the most significant four bits (7: 4) of the register R1 (403) and buffers the buffer memory. move to r1 (408). Next, when the DC / QNO-EN signal is input, the compressed DC component and the quantization number (QNO) component data of the data have 12 bits of DC component and 4 bits of QNO, respectively, so that the lower 4 bits (3) of the register R1 (403) are used. Reads: 0) and all 8 4 bits (7: 0) of register R2 (402) and the upper 4 bits (7: 4) of R3 (401) and transfers them to buffer memory r2 (409) of the buffering means. When the AC-EN signal is input, since the AC component data of the compressed data is 16 bits, the lower 4 bits (3: 0) of the next register R1 403 and the entire 8 bits (7) of the register R2 402 are input. The upper 4 bits (7: 4) of: 0) and R3 (401) are read and transferred to the buffer memory r3 (410) of the buffering means.

The data transferred by separating the data for each component of the data is transferred to the R1 408 buffer of the buffering means during the deformatting process performed by the deformatting unit 36. The component data STA is simply the state of the bit stream of the data. It is an unnecessary data element that is not used during the deformatting process because it is the state component data (the data of these 4 bits is 0, which is valid data. AC component data (compressed data representing 63 bits of AC component except the upper left DC component 1 bit of an 8 x 8 DCT block) to be deformatted data is stored in the buffer memory S1 / S2 (35, 35). ') To be deformatted by the deformatting section 36. On the other hand, DC / QNO component data does not need to be decoded (only the upper left 1 bit representing the DC component of an 8 x 8 DCT block is compressed and does not need to be deformatted, and the QNO component data is used in the quantization step). The data is sent to the buffer memory F1 / F2 (37, 38), and then recombined with the deformatted AC component data so as to be used as a whole in the dequantizer 39. Inverse quantization ensures complete deformatting.

As described above, the deformat processing method according to the present invention allows the data to be formatted in the format processing step without being deformatted together in the deformat processing step, so that the data is separated and deformatted by each component through a hardware circuit in advance. When deformatting by the deformatting section 36, only the deformatted data is taken directly from the buffers 35 and 35 'and deformatted, so that the burden of processing by software in the deformatting section 36 is minimized. In addition to shortening the data access time that is generated, the reformat time of the actual data is also shortened.

According to the present invention as described above, in the process of decoding the formatted video information, the data components are separated and deformatted in advance, thereby shortening the data access time generated during the reformatting and the actual data. Deformatting time is also faster, which improves the performance of the system.

Claims (5)

In a data deformatting processing circuit used for a decoder for encoding and decoding DCT processed image data, An ECC processing unit 29 for correcting errors of data formatted in the formatter circuit of the encoder preceding the deformatter circuit; A separation unit 40 which receives the data sent from the ECC processing unit 29 and separates the data by the components of the data; A deformatting unit 36 which deformats each component data from which the components are separated in the separating unit 40; An inverse quantizer (39) for performing inverse quantization for restoring the actual DCT coefficient value of the data deformatted by the deformatter (36); Buffer memory S1 / S2 (35, 35 ') which buffers AC component data separated in separation section 40 under control of deformatting section 36 when the deformatting section 36 deformats data. Wow; Buffer memory F1 / which buffers the DC component and the quantization number component (QNO) data separated by the separating unit 40 under the control of the deformatting unit 36 when the deformatting unit 36 deformats the data. A data deformatting circuit of an image encoder comprising: F2 (37, 38). The data processing apparatus according to claim 1, wherein the separation unit (40) comprises: register means for receiving and storing error-corrected data from the data formatted by the ECC processing unit (29) of the formatting circuit on the encoder side of the front end; Buffering means for dividing the data stored from the register means for each component and temporarily storing the data stored in separate buffer memories; And control means for counting a system clock and providing an enable signal for reading the respective component data to the buffering means. 3. The register according to claim 2, wherein the register means includes registers R3, R2, and R1 (401, 402, 403) which sequentially receive formatted data from which an error is corrected from the ECC processing unit 29 of the formatter of the encoder. And a data deformatting circuit of the video encoder. 3. The apparatus of claim 2, wherein the buffering means comprises: a r1 (408) which is a temporary storage buffer for reading and storing state data (STA) from the register R1 (403); R2 (409) which is a temporary storage buffer which reads and stores DC component data and quantization number data (DC / QNO) from the registers R3 to R1 (403 to 401); And r3 (410) which is a temporary storage buffer for reading and storing AC component data (AC) from said registers R3 to R1 (403 to 401). 3. The apparatus of claim 2, wherein the control means comprises: a counter (404) for counting an enable signal provided by the system and providing a read enable signal for each component; A controller (405, 406, 407) for providing a control signal to the buffer memories r1 to r3 to read respective component data from the registers R3 to R1 (403 to 401) according to the enable signal provided by the counter. A data deformatting circuit of an image encoder, characterized in that it is made.