KR19980023731A - Address generation method of convolutional interleaver / deinterleaver and static RAM using static RAM - Google Patents

Abstract

The present invention relates to a weaving interleaver of a digital channel encoder and a weaving deinterleaver of a channel decoder. More particularly, the present invention relates to a static RAM that reduces the amount of hardware by using a static RAM (SRAM) and efficiently controls access to the static RAM. The present invention relates to an address generation method of a convolutional interleaver / deinterleaver and a static RAM used. The convolutional interleaver / deinterleaver of the present invention includes an input means 41, an address generation means 42, a static RAM 43, and an output means 44. And the control means 45, the address generation method applied to the address generation means 22 is a time corresponding to the delay time to be output after the correct delay in accordance with the input sequence with N symbols as a period The write address (WA) and the read address (RA) are generated for each half period of the clock, and the cyclic address is calculated by modular operation of the total memory size (MEM_SIZE) of the static RAM. By assigning addresses in a correct manner, the same interleaving / deinterleaving as before has been performed.

Therefore, the effect of the present invention uses only a minimum of memory (i.e., (N-1) x (B-1) + 1) (Bytes), and also controls because the various control signals are clock signals and inverted clock signals. The effect is that the means can be easily implemented in simple hardware.

Description

Cnvolutional Interleaver and Deinterleaver using SRAM and a method for generating address of SRAM

The present invention relates to a weaving interleaver of a digital channel encoder and a weaving deinterleaver of a channel decoder. More particularly, the present invention relates to a static RAM that reduces the amount of hardware by using a static RAM (SRAM) and efficiently controls access to the static RAM. It relates to a convolutional interleaver / deinterleaver and static RAM address generation method.

In general, in a typical communication system, errors occurring during transmission include a random error occurring in a random form in one place and a burst error generated by being concentrated in one place.

In this way, error correction techniques are used to handle errors occurring on the channel at the receiving end. Such error correction techniques are mainly used for error correcting coding (ECC) and interleaving of coded data. There is a technique.

Error Correction Coding (ECC) adds a check symbol used to detect or correct an error. The error correction coding (ECC) combines several information symbols into blocks and performs encoding on a block basis. There are a block code and a nonblock code for performing encoding according to an input sequence of an information symbol string.

Interleaving is a rearrangement of the sequence of data strings in a predetermined manner in a coded data sequence, and includes a block interleaver and a convolution interleaver according to the scheme.

FIG. 1 is a block diagram of a general channel encoder. The channel encoder includes a Reed Solomon encoder 11, a first interleaver 12, a convolutional encoder 13, and a second interleaver 14. As shown in FIG.

The Reed Solomon encoder 11 adds a check symbol for error correction to the original information symbol to perform the Reed Solomon encoding function, and the first interleaver 12 performs a readout of the signal output from the Reed Solomon encoder 11. Rearrange the order to randomize.

The convolutional encoder 13 encodes the signal output from the first interleaver 12 into a convolutional code, and the second interleaver 12 rearranges the order of the signals output from the convolutional encoder 13. To randomize them.

2 is a block diagram of a general channel decoder, in which the channel decoder includes a synchronous detector 21, a second deinterleaver 22, a convolutional decoder 23, a second deinterleaver 24, and a Reed Solomon decoder 25. It consists of

The synchronization detector 21 detects synchronization of an input signal, and the second deinterleaver 22 deinterleaves the signal output from the synchronization detector 21 to input an order of the input signal of the second interleaver 14. Rearrange and print.

The convolutional decoder 23 corrects an error generated by Viterbi decoding the signal output from the second deinterleaver 22, and the first deinterleaver 24 outputs the signal output from the convolutional decoder 23. Deinterleaving and rearranges the signals in the order of the input signals of the first interleaver 12 to output them.

The Reed Solomon decoder 25 corrects an error generated by Reed Solomon decoding the signal output from the first deinterleaver 24.

The error correction system using the convolutional / RS concatenated code shown in FIG. 1 and FIG. 2 efficiently rearranges the coded signals to cope with both random and cluster errors, for the following reason.

The error correction code (RS code, convolutional code) can correct a limited number of bit errors in each codeword, so it is efficient for random errors, but can be inefficient when errors occur in groups.

In order to cope with such clustering errors, the transmitting end rearranges (randomizes) the order of the data streams encoded through the interleaver and restores the original data stream order through the deinterleaver at the receiving end even if a cluster error occurs during transmission. This is because the cluster error is transformed into a random error.

On the other hand, the DSS (Direct Satellite System) method, which is one of US digital satellite broadcasts, adopts a (146, 130) lead solomon encoder and rearranges a Reed Solomon-coded signal through a convolutional interleaver.

Here, the (146, 130) Lead Solomon code adds 16 check symbols to 130 information symbols by using 8 bits as a symbol, and has a total codeword length of 146 symbols (= 146 bytes). ) The convolutional interleaver inserts and rearranges 12 random symbols between two neighboring input symbols with an interleaving interval of 13.

Fig. 3 is a block diagram of a conventional convolutional interleaver used in the DSS method, in which the convolutional interleaver includes an input switch 30, a plurality of shift registers 2-0 to 2-145, and a plurality of adders 3-0. 3-145).

The input switch 30 transfers input data by switching from input tap # 0 of the rightmost adder 3-0 to tap # 145 of the leftmost adder 3-145 in the order of byte input. do.

In the plurality of shift registers 2-0 to 2-145, one register 2-0 is connected to the rightmost adder 3-0, and there are 12 registers 2-1 to 2-0 between the remaining two adders. 2-145) is connected, and shifts to the right once per input by a clock synchronized with the input data.

In the plurality of adders 3-0 to 3-145, one input of the leftmost adder 3-145 is always fixed to zero, and an input tap switched to the input switch 30 is fixed to zero. When connected to the switch in the state, input data is received and output in addition to the shifted value from the shift register.

Referring to the operation of the conventional convolutional interleaver configured as described above are as follows.

When the Reed Solomon coded signal is input in byte units, the input switch 30 sequentially selects the 0th adder 3-0 in byte clock units.

Therefore, zero-order data D0 is input in synchronization with the first clock, and zero-order data D0 is output after one clock delay. Primary data D1 is input at the second clock, and primary data D1 is output after a 12 + 1 clock delay. The secondary data D2 is input at the third clock, and the secondary data D2 is output after a 2x12 + 1 clock delay. Subsequently, the 145th order data D145 is input at the 146th clock, and is output after 145x12 + 1 clocks.

As a result, through the N = 146, B = 13 convolutional interleaver configured as described above, 0th to 145th data (Di, 0≤i≤145) are output after a delay as shown in Equation 1 below.

The minimum amount of memory required in the conventional convolutional interleaver of FIG. 3 is given by Equation 2 below.

When the memory is implemented as a shift register as in the prior art, even though it is basically implemented simply, six gates are used per register, and one gate is implemented by four transistors. This requires 24 transistors.

If this is implemented in general logic (LOGIC), it is a very large amount, and even if implemented in an application-specific semiconductor (ASIC), the amount is not negligible, there was a problem of considerable hardware volume or cost burden.

As a solution to this problem, the static RAM can be implemented with only 1.5 gates, or 6 transistors, per static RAM cell. Therefore, when the amount of memory required by the convolutional interleaver is very large, Implementing with static RAM (SRAM) rather than using a shift register will be economical in terms of volume and cost of hardware.

However, in the convolutional interleaver / deinterleaver using static RAM, control logic for accessing the static RAM needs to be added, but there is a problem in that the hardware structure and address generation method are not disclosed.

Accordingly, the present invention has been made to solve the above problems of the prior art, an object of the present invention is to provide a convolutional interleaver / deinterleaver having a simple hardware structure while reducing the memory burden by using a static RAM (SRAM). Its purpose is to.

Another object of the present invention is to provide an address generation method for performing interleaving / deinterleaving in the apparatus by using circular addressing.

Weaving interleaver / deinterleaver using a static RAM to achieve the above object,

Input means for latching input data in byte units and outputting the data to a data bus; Address generating means for generating a read address (RA) and a write address (WA); A static RAM which outputs data stored according to the read address RA to the data bus and simultaneously stores data carried on the data bus according to the write address WA; Output means for latching and outputting data output from the static RAM in units of bytes; The input means enable signal IN_ENA, the static RAM read signal, the static RAM write signal, and the output means enable signal OUT_ENA according to the packet synchronization signal packet_sync and the byte clock signal byte_clock. And control means for generating a control signal, for example.

In order to achieve the above another object, a method of generating an address of a static RAM for the device for interleaving at an interleaving interval B, with a period of N data in a data stream input in bytes,

A first step of initializing a base address (BASE_ADDR) at system initial stage in order to map a static RAM having a memory size of (N-1) × B + 1 (bytes) in a cyclic address designation method; In order to delay the Nth order 0th symbol D (k, 0), the base address BASE_ADDR is generated as the read address RA0 for the first half period of the clock, and the read address RA0 + 1 is after the clock. A second process occurring at the write address WA0 for half a period; For the delay of the remaining symbols of the N period (D (k, i), 1≤i≤N-1), the read address (RAi-1) +1 of the previous clock is read to the read address (RAi) for the first half period of the clock. And a third process of generating the read address (RAi) + symbol order (i) x (B-1) + 1 as a write address (WAi) during a half cycle of the clock.

In order to achieve the above object, the interleaved data string is received in byte units and deinterleaved by N periods (= S (k, 0), S (k, 1), ..., S (k, N-1)). The method of generating a static RAM address for the device,

A first process of determining a switching position of a (N−1) × B + 1 (bytes) static RAM according to an index i of an input symbol to generate a write address WAi; A second process of initializing a base_address to map the static RAM in a cyclic address designation method; For the delay of the Nth order zero symbol S (k, 0), the base address (base_address) is generated as the read address (RA0) for the first half period of the clock, and the read address (RA0) + 1 + switching position x A second process of generating (B-1) to the write address WA0 for a half cycle after the clock; For the delay of the remaining symbols of N periods (S (k, i), 1≤i≤N-1), the read address (RAi-1) +1 of the previous clock is read to the read address (RAi) for the first half period of the clock. And a third process of generating the read address RAi + 1 + switching position × (B-1) to the write address WAi during the last half period of the clock.

The convolutional interleaver applying the address generation method of the present invention as described above performs interleaving according to the same rearrangement order as before, and the deinterleaver also restores the original order.

Therefore, in the convolutional interleaver / deinterleaver applying the static RAM address generation method according to the present invention, only minimal memory (that is, (N-1) × (B-1) +1) (Bytes) needs to be used. Since the control signals are clock signals inverted from the clock signals, the control means can be easily implemented in simple hardware.

1 is a block diagram of a general channel encoder,

2 is a block diagram of a general channel decoder;

3 is a block diagram of a conventional convolutional interleaver used in the DSS scheme;

4 is a block diagram of a convolutional interleaver according to the present invention;

5 is an address mapping diagram of a static RAM for explaining an address allocation method according to the present invention;

6 is a timing diagram for various control signals for explaining the operation of the convolutional interleaver / deinterleaver according to the present invention.

Explanation of symbols on the main parts of the drawings

41: input buffer 42: address generator

43: static RAM 44: output latch

45: control unit

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

4 is a block diagram of a convolutional interleaver using a static RAM according to the present invention. The convolutional interleaver of the present invention includes an input buffer 41, an address generator 42, a static RAM 43, and an output latch 44. And a control unit 45.

The input buffer 41 latches the input data D (k, i) in byte units and outputs them to the data bus.

The address generator 42 generates a read address RA during the first half cycle of the clock, and generates and outputs a write address WA during the second half cycle of the clock.

The static RAM 43 outputs the data S (k, i) stored in accordance with the read address RA generated during the first half period of the clock to the data bus and at the same time generated during the second half period of the clock. The input data D (k, i) is stored according to the write address WA.

The output buffer 44 latches the data S (k, i) output from the static RAM 43 to finally output interleaved data.

The controller 45 may include an input buffer enable signal IN_ENA, a static RAM read signal, a static RAM write signal, and an output buffer according to a packet synchronization signal packet_sync and a byte clock. A control signal such as an enable signal OUT_ENA is generated to control the input buffer 41, the static RAM 43, and the output buffer 44.

5 is an address mapping diagram of a static RAM for explaining an address allocation method according to the present invention.

As shown in FIG. 5, one byte (# 0) indicated by the base address (base_address) is a memory block for implementing the function of shift register 3-0 of FIG. 3, and the next 12 bytes (# 1). ) Is a memory block for implementing the functions of the first shift register 3-1 of FIG. 3, and the shift registers 3-2 to 3-145 of FIG. 3 are also described below in the remaining memory blocks # 2 to # 145. And one-to-one correspondence.

That is, the minimum memory capacity (MEM_SIZE) required is 145 x 12 + 1 (bytes), and the address of memory block 1 composed of 1 byte becomes the lowest address.

The base address (base_address) is increased by 1 (from right to left) every clock in synchronization with the clock of the input symbol, and the data is generated by reading the data by generating the base address (base_address) as a read address during the first half period of the clock. A shift action of 3 is achieved.

The read address (RA) and the write address (WA) for accessing the physical memory are mapped to a circular addressing method by using a modular operation of the total memory size (MEM_SIZE).

Here, the cyclic address designation method is a address designation method in which a address circulates within a predetermined range when the highest address or the lowest address in a predetermined range is reached, and then returns to the first address value.

Comparing the operation of Fig. 5 of the present invention with that of the conventional Fig. 3, a tap input to the adder of Fig. 3 is equivalent to inputting data into a tap selected by an input switch and 0 into another tap. Since the other input value of the adder corresponding to the selected tap becomes 0, it is sufficiently implemented by simply storing the input data in the static RAM as shown in FIG.

Next, the address generation algorithm of the interleaver for accessing the memory of FIG. 5 will be described.

First, the interleaver address generation algorithm is described using the C language, and the switch synchronization and the related synchronization portion are excluded.

Table 1

Interleaver address generation algorithm: C program 1

#define N 146

#define B 13

while (system = ON) {

if (reset = ON) {

base_address = 0 (or arbitrary position);

input_counter = 0;

}

else {

switch_position = input_counter;

RA = base_address;

WA = (base_address + switch_position * (B-1) +1)% MEM_SIZE;

input_counter = (input_count + 1)% N;

base_address = (base_address + 1)% MEM_SIZE;

}

1 system clock delay;

}

In Table 1, RA is a read address of the static RAM, WA is a write address of the static RAM, and switch_position corresponds to the switch tap number of FIG. 3 and is the same value as the index of the input data.

Briefly referring to Table 1, it is determined whether the system is on and reset.

When reset, the base address (base_address) indicating the start address of the static RAM is designated as the lowest address 0, and the counter variable (input_count) indicating the data of the period is initialized to 0.

If not reset, a switch variable (switch_position) indicating a switch position is designated by the counter variable (input_count), a read address (RA) is designated by the base address (base_address), and a write address (WA) is designated by the base address ( base_address) is added to (B-1) multiplied by the switch variable (switch_position) plus 1, and then a modular operation value is designated as a memory size (MEM_SIZE).

The counter variable input_count is increased by 1 and is designated as a value that is modularly calculated by N. The counter variable base_address is increased by 1 and is designated as a value that is modularly calculated by a memory size MEM_SIZE.

The result of applying the address generation algorithm performed as described above to the convolutional interleaver having period 7 and interleaving interval 3 (N = 7, B = 3) is shown in Table 2 below.

TABLE 2

Static RAM Address and Output Data of (7, 3) Convolutional Interleaver According to Period Variable k

Input data D (k, i) Count variable input_count Base address Read Address (RA) Write Address (WA) Output data S (k, i) D (1,0) 0 0 0 One X D (1,1) One One One 4 D (1,0) D (1,2) 2 2 2 7 X D (1,3) 3 3 3 10 X D (1,4) 4 4 4 0 D (1,1) D (1,5) 5 5 5 3 X D (1,6) 6 6 6 6 X D (2,0) 0 7 7 8 D (1,2) D (2,1) One 8 8 11 D (2,0) D (2,2) 2 9 9 One X D (2,3) 3 10 10 4 D (1,3) D (2,4) 4 11 11 7 D (2,1) D (2,5) 5 12 12 10 X D (2,6) 6 0 0 0 D (1,4) D (3,0) 0 One One 2 D (2,2) D (3,1) One 2 2 5 D (3,0) D (3,2) 2 3 3 8 D (1,5) D (3,3) 3 4 4 11 D (2,3)

It is assumed that the static RAM size (= (N-1) × (B-1) +1) of the (7, 3) convolutional interleaver is 13 bytes, the highest address is '12' and the lowest address is '0'. It is about the case.

As shown in Table 2, the read address RA is generated according to the cyclic address designation method while increasing by one from the lowest address 0 during the first half period of the clock.

In addition, the write address WA increases by 3 (= B) from the lowest address (1) of the first stage during the half cycle of the clock, and occurs according to the cyclic address designation method to store data input in the 7 (= N) cycle. The address for storing the 0th order symbol of the next period is generated by incrementing 2 (= B-1) from the address of the last data of the previous period.

Therefore, 2 (= B-1) data is inserted between two neighboring data in the stream of input data to obtain interleaved data.

Subsequently, the data stream output by the (7, 3) convolutional interleaver with N = 7 and B = 3 will be described with reference to the deinterleaving method.

The symbol D (k, i) having the index i (0 ≦ i ≦ 6) is input to the convolutional interleaver with seven symbols in cycles according to the period variable k representing the several periods, and is output in the order shown in Table 2 below.

TABLE 3

Interleaver Output Order

k D (k, i), 0≤i≤5 One D (1,0), X, X, D (1,1), X, X, D (1,2) 2 D (2,0), X D (1,3), D (2,1), X, D (1,4), D (2,2) 3 D (3,0), D (1,5), D (2,3), D (3,1), D (1,6), D (2,4), D (3,2) 4 D (4,0), D (2,5), D (3,3), D (4,1), D (2,6), D (3,4), D (4,2) ： ： ： ： ： ： D (k, 0), D (k, 5), D (k, 3), D (k, 1), D (k, 6), D (k, 4), D (k, 2)

In Table 3 above, X represents any data contained in a register at the beginning of the system. As shown in Table 3 above, in the deinterleaver, when N data is inputted, the interleaver input index i is input in the order of data having 0, 5, 3, 1, 6, 4 and 2.

Therefore, the deinterleaver reversely applies the delay amount according to the index (Equation 1) in the interleaver, thereby making the delay amount according to all the indexes equal, so that the input order of the interleaver and the output order of the deinterleaver are the same. Should be made.

That is, the deinterleaver should have a relative delay amount as shown in Equation 3 according to the index of the interleaver input of the input data.

Therefore, in the deinterleaver N = 7 and B = 3, the interleaver's input index i = 0 is 6 × 2, i = 5 is 1 × 2, i = 3 is 3 × 2, i = 1 is 5 × 2, i = 6 should be delayed by 0x2, i = 4 by 2x2, and i = 2 by 4x2.

Briefly summarizing the above description, when the block diagram of FIG. 3 is applied to the (7,3) interleaver / deinterleaver, the interleaver adder input tab numbers # 0, # 1, # 2, # 3, # 4 , # 5,

Switching action occurs # 6 in turn, and in the deinterleaver, it is equivalent to switching to each tap in the order of # 6, # 1, # 3, # 5, # 0, # 2, # 4.

Next, an algorithm for obtaining the switching order of the deinterleaver will be described.

First, the switching algorithm in the deinterleaver in the case of DSS where N = 146 and B = 12 is described using C language as follows.

TABLE 4

Algorithm to find the switching order of deinterleaver: C program 2

#define N 146

#define B 13

main ()

{

int n, i;

int H [N], G [N];

FILE * outf;

outf = fopen (dsspkg.vhd, w);

for (n = 0; nN; n ++) H [n] = n * B% N;

for (j = 0; jN; j ++)

{for (n = 0; nN; n ++)

{if (H [n] == j)

G [j] = n; }

fprint (outf, #% d,, N-1-G [j]);

}

fclose (outf);

}

In Table 4, the variable n is an input index indicating the input order of the interleaver, and H [n] indicates the number of times of N cycles of output data from the interleaver. The variable j is an input index indicating the input order of the deinterleaver, and G [j] is an inverse function of H [n].

In brief description of Table 4, the output order H [n] of the interleaver is a value calculated by multiplying the input index n and the interleaving interval B by N. The inverse function G [j] of the H [n] value (= n) Corresponds to an input index n indicating the number of input data of N periods in the interleaver in the interleaver. Equation 3 is expressed using the value of the index G [j] = n of the interleaver. Obtain the switching order N-1-G [j] that determines the delay amount as follows.

The results of the program 2 are shown in Table 4.

TABLE 4

Deinterleaver switching order: tap number

# 145, # 100, # 55, # 10, # 111, # 66, # 21, # 122, # 77, # 32, # 133, # 88, # 43, # 144, # 99, # 54, # 9, # 110, # 65, # 20, # 121, # 76, # 31, # 132, # 87, # 42, # 143, # 98, # 53, # 8, # 109, # 64, # 19, # 120, # 75, # 30, # 131, # 86, # 41, ： ： ： ： # 137, # 92, # 47, # 2, # 103, # 58, # 13, # 114, # 69, # 24, # 125, # 80, # 35, # 136, # 91, # 46, # 1, # 102, # 57, # 12, # 113, # 68, # 23, # 124, # 79, # 34, # 135, # 90, # 45, # 0, # 101, # 56, # 11, # 112, # 67, # 22, # 123, # 78, # 33, # 134, # 89, # 44

The address generation algorithm for the deinterleaver was described using the C language using the switching order of the deinterleaver obtained as described above.

TABLE 5

Address generation C program 2 of deinterleaver

constant N = 146;

constant B = 13;

constant switching_orther [N] = {145,100,55,10,111,66,21,122,77,32,133,88,43,

144, 99,54, 9,110,65,20,121,76,31,132,87,42,

143, 98,53, 8,109,64,19,120,75,30,131,86,41,

142, 97,52, 7,108,63,18,119,74,29,130,85,40,

141, 96,51, 6,107,62,17,118,73,28,129,84,39,

140, 95,50, 5,106,61,16,117,72,27,128,83,38,

139, 94,49, 4,105,60,15,116,71,26,127,82,37,

138, 93,48, 3,104,59,14,115,70,25,126,81,36,

137, 92,47, 2,103,58,13,114,69,24,125,80,35,

136, 91,46, 1,102,57,12,113,68,23,124,79,34,

135, 90,45, 0,101,56,11,112,67,22,123,78,33,

134, 89,44}

while (system = ON) {

if (reset = ON) {

base_address = 0 (or arbitrary position);

input_counter = 0;} else {

switch_position = constant (input_counter);

RA = base_address;

WA = (base_address + switch_position * (B-1) +1)% MEM_SIZE;

input_counter = (input_count + 1)% N;

}

base_address = (base_address + 1)% MEM_SIZE;

1 system clock delay;

}

As shown in Table 5, the deinterleaver algorithm differs only in the switching order, and the address generation method is equally applied.

Table 6 shows an example of the (N = 7, B = 3) weaving deinterleaver applying Table 5.

TABLE 6

Static RAM Address and Output Data of (7, 3) Convolutional Deinterleaver According to Period Variable k

As shown in Table 6, the data output after 14 clocks after the system initialization is restored in its original order before interleaving, so that the deinterleaving is performed perfectly.

That is, the hardware structure of the deinterleaver is the same as that of the interleaver shown in FIG. 4, except that the address is changed by only changing the switching order of FIG. 3 corresponding to the input order in generating an address for accessing the static RAM. You just need to create it.

6 is a timing diagram for various control signals for explaining the convolutional interleaver operation of FIG. 4. 6 illustrates the operation of the convolutional interleaver of the DSS method using N = 146 and B = 13 for the interleaving process.

6A is a byte clock signal (byte_clock), 6B is an input data stream (D (k, i)), and is input to the input buffer 41 in synchronization with the byte clock (byte_clock).

6C is an enable signal IN_ENA of the input buffer, which is generated in the same manner as the clock signal in the controller 45 and is an active low signal.

6D is input buffer output data, which is delayed by one clock by the input buffer enable signal IN_ENA, and then loaded on the data bus for the next half cycle of the byte clock.

6E is a static RAM write signal (write), which is generated in the same manner as the clock signal by the controller 45 and is an active low signal.

6F is a static RAM read signal, which is generated by inverting the clock signal by the controller 45 and is an active low signal.

6G is address data for accessing a static RAM loaded on an address bus. The address generator 44 generates a read address RA during the first half cycle of the clock and a write address WA during the half cycle of the clock. do.

6H is data loaded on a data bus, and output data S (k, i) of the static RAM is loaded according to the read address RA during the first half cycle of the clock, and output data of the input buffer during the half cycle of the clock. (D (k, i)) is loaded.

6I is an enable signal OUT_ENA of the output latch, and is generated by inverting the clock signal by the controller 25 and is an active low signal.

6J is output data S (k, i) of the output latch, in which the output data of the static RAM carried in the previous half cycle of the clock is latched.

In addition, since the control signals 6C, 6E, 6F, and 6I of FIG. 6 are equally applied to the deinterleaver, deinterleaving is performed in the original data order.

As described above, in the convolutional interleaver / deinterleaver applying the static RAM address generation method according to the present invention, by using only a minimum of memory (= (N-1) × (B-1) +1) (Bytes), In theory, it has the effect of using optimal memory.

In addition, since the control signals are clock signals inverted from the clock signals, the control means can be easily implemented in simple hardware.

Claims (7)

A convolutional interleaver / deinterleaver for rearranging data streams at an interleaving interval B, transmitting the received data streams, and restoring the data streams in the order of the original data stream. Input means (41) for latching input data in byte units and outputting the data to a data bus; Address generating means 42 for generating a read address RA and a write address WA; A static RAM (43) for outputting data stored according to the read address (RA) to the data bus and simultaneously storing data carried on the data bus according to the write address (WA); Output means (44) for latching and outputting data output from the static RAM (43) in units of bytes; And The input means enable signal IN_ENA, the static RAM read signal, the static RAM write signal, and the output means enable signal OUT_ENA according to the packet synchronization signal packet_sync and the byte clock signal byte_clock. Convolutional interleaver / deinterleaver using a static RAM, characterized in that it comprises a control means for generating a control signal such as. The convolutional interleaver according to claim 1, wherein the control means 45 generates a clock signal byte_clock as an input means enable signal IN_ENA and provides it to the input means 41. Deinterleaver. The convolutional interleaver / de-decier of claim 1, wherein the control means 45 generates a clock signal byte_clock as a static RAM write signal WT and provides the clock signal to the static RAM 43. Interleaver. The convolutional interleaver of claim 1, wherein the control means 45 inverts a clock signal (byte_clock) to generate a static RAM read signal (read) to provide the static RAM 43 to the static RAM 43. Deinterleaver. The convolutional interleaver using a static RAM according to claim 1, wherein the control means (45) generates a clock signal (byte_clock) as an output means enable signal (OUT_ENA) and provides it to the output means (44). Deinterleaver. In interleaving the data stream input in the unit of byte with the interval of N data, at the interleaving interval B, A first step of initializing a base address (BASE_ADDR) at system initial stage in order to map a static RAM having a memory size of (N-1) × B + 1 (bytes) in a cyclic address designation method; In order to delay the Nth order 0th symbol D (k, 0), the base address BASE_ADDR is generated as the read address RA0 for the first half period of the clock, and the read address RA0 + 1 is after the clock. A second process occurring at the write address WA0 for half a period; For the delay of the remaining symbols of the N period (D (k, i), 1≤i≤N-1), the read address (RAi-1) +1 of the previous clock is read to the read address (RAi) for the first half period of the clock. And a third process of generating the read address (RAi) + symbol order (i) x (B-1) + 1 as a write address (WAi) during a later half cycle of the clock. How to generate RAM address. Deinterleaving the interleaved data strings in byte units for N periods (= S (k, 0), S (k, 1), ..., S (k, N-1)), A first process of determining a switching position of a (N−1) × B + 1 (bytes) static RAM according to an index i of an input symbol to generate a write address WAi; A second process of initializing a base_address to map the static RAM in a cyclic address designation method; In order to delay the Nth order symbol S (k, 0), the base address (base_address) is generated as the read address (RA0) for the first half period of the clock, and the read address (RA0) + 1 + switching position x A second process of generating (B-1) to the write address WA0 for a half cycle after the clock; For the delay of the remaining symbols of N periods (S (k, i), 1≤i≤N-1), the read address (RAi-1) +1 of the previous clock is read to the read address (RAi) for the first half period of the clock. And a third process of generating the read address (RAi) + 1 + switching position × (B-1) as a write address (WAi) for a half cycle after the clock. How to produce.