KR102648914B1 - Nonvolatile memory device - Google Patents

Abstract

According to an embodiment of the present invention, the non-volatile memory device includes a first memory block stacked in a direction perpendicular to the substrate and connected to a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines. is connected to a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and corresponds to a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines in response to a block selection signal, respectively. a block selection circuit configured to provide driving voltages, and a block connected only to specific string selection lines among a plurality of string selection lines and configured to provide an off voltage only to specific string selection lines in response to an inverted block selection signal. Contains non-selective circuitry.

Description

Nonvolatile memory device {NONVOLATILE MEMORY DEVICE}

The present invention relates to semiconductor memory, and more specifically to non-volatile memory devices.

Semiconductor memories include volatile memory devices, such as SRAM and DRAM, where the stored data is lost when the power supply is cut off, and flash memory devices, such as PRAM, MRAM, RRAM, and FRAM, which retain the stored data even when the power supply is cut off. It is classified as a volatile memory device.

Flash memory devices are widely used as mass storage media. Recently, as flash memory devices with three-dimensional structures are developed, the integration of flash memory devices is improving, and various techniques for controlling flash memory devices with improved integration are being developed.

An object of the present invention is to provide a non-volatile memory device with reduced cost by reducing the area of peripheral circuits (particularly, row decoders) of the non-volatile memory device.

According to an embodiment of the present invention, the nonvolatile memory device includes a first memory block stacked in a direction perpendicular to the substrate and connected to a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, connected to a plurality of string selection lines, the plurality of word lines, and the plurality of ground selection lines, and in response to a block selection signal, the plurality of string selection lines, the plurality of word lines, and the plurality of ground A block selection circuit configured to provide corresponding driving voltages to selection lines, and connected only to specific string selection lines among the plurality of string selection lines, and in response to an inverted block selection signal, the specific string selection line and a block non-select circuit configured to provide only an off voltage.

According to an embodiment of the present invention, a nonvolatile memory device includes a first cell string connected in series between a common source line and a first bit line and including a plurality of first cell transistors stacked in a direction perpendicular to the substrate, the A second cell string connected in series between a common source line and the first bit line and including a plurality of second cell transistors stacked in a direction perpendicular to the substrate, the first cell string through a plurality of signal lines, and a block selection circuit connected to the second cell string and configured to provide corresponding driving voltages to the plurality of signal lines in response to a block selection signal, and connected to specific signal lines among the plurality of signal lines; , in response to an inverted block selection signal, comprising a block non-selection circuit configured to provide an off voltage to the specific signal lines, and the remaining signal lines excluding the specific signal lines among the plurality of signal lines are the first signal lines. It includes at least one first string selection line connected to a cell string and at least one second string selection line connected to the second cell string.

According to an embodiment of the present invention, a nonvolatile memory device is stacked in a direction perpendicular to the substrate, a first memory block connected to a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and an external memory block. A block decoder configured to output a block selection signal and an inverted block selection signal based on an address received from a device, the plurality of string selection lines, the plurality of word lines, and the plurality of string selection lines in response to the block selection signal. A plurality of pass transistors each configured to provide corresponding driving voltages to ground select lines, and configured to provide an off voltage to specific string select lines among the plurality of string select lines in response to the inverted block select signal. It includes a plurality of unselected pass transistors, and the number of the plurality of unselected pass transistors is smaller than the number of the plurality of string select lines.

According to embodiments of the present invention, the size of the row decoder including the block non-selection circuit can be reduced by connecting the block non-selection circuit to only some of the string selection lines of the memory block. Accordingly, a non-volatile memory device with reduced cost is provided.

In addition, according to embodiments of the present invention, by connecting the block non-selection circuit to only some signal lines (e.g., erase control line, dummy word line, etc.) among various signal lines connected to the memory block, the block non-selection circuit The size of the row decoder including can be reduced. Accordingly, a non-volatile memory device with reduced cost is provided.

1 is a block diagram showing a non-volatile memory device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating a first memory block among a plurality of memory blocks included in the memory cell array of FIG. 1 .
FIG. 3 is a diagram illustrating the row decoder of FIG. 1 by way of example.
FIG. 4 is a flow chart showing the operation of the non-volatile memory device of FIG. 1.
FIG. 5 is a diagram showing the configuration of the row decoder of FIG. 3 in more detail.
FIG. 6 is a diagram illustrating the program bias of the row decoder of FIG. 5.
FIG. 7 is a diagram for explaining the operation of the non-volatile memory device of FIG. 1.
FIG. 8 is a diagram illustrating the row decoder of FIG. 1.
FIG. 9A is a diagram illustrating the row decoder of FIG. 1.
FIG. 9B is a diagram for explaining the configuration of the row decoder of FIG. 9A.
Figure 10 is a circuit diagram exemplarily showing a third memory block according to an embodiment of the present invention.
Figures 11A to 11D are diagrams showing a row decoder according to an embodiment of the present invention.
Figure 12 is a block diagram illustrating a storage system to which a non-volatile memory device according to embodiments of the present invention is applied.

Hereinafter, embodiments of the present invention will be described clearly and in detail so that a person skilled in the art can easily practice the present invention.

1 is a block diagram showing a non-volatile memory device according to an embodiment of the present invention. Referring to FIG. 1 , the nonvolatile memory device 100 may include a memory cell array 110 and a peripheral circuit 120 . Hereinafter, for convenience of explanation, the non-volatile memory device 100 is described as a NAND flash memory device, but the scope of the present invention is not limited thereto.

The memory cell array 110 may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of cell strings. Each of the plurality of cell strings may include a plurality of cell transistors connected in series, and the plurality of cell transistors may be connected to string select lines (SSL), word lines (WL), and ground select lines (GSL), respectively. You can.

In an exemplary embodiment, a plurality of cell transistors of the memory cell array 110 may be stacked in a direction perpendicular to the substrate. That is, the memory cell array 110 may include memory blocks with a three-dimensional structure.

The peripheral circuit 120 may include a row decoder 121, a voltage generator 122, a control logic circuit 123, and an input/output circuit 124. In an exemplary embodiment, the memory cell array 110 may be formed in a cell region of a semiconductor substrate, and the peripheral circuit 120 may be formed in a peripheral region of the semiconductor substrate that is physically separated from the cell region. Alternatively, the peripheral circuit 120 may be formed on a semiconductor substrate, and the memory cell array 110 may be formed by stacking on top of the peripheral circuit 120. That is, the nonvolatile memory device 100 may be formed in a cell-on-peripheral (COP) structure. However, the scope of the present invention is not limited thereto, and the nonvolatile memory device 100 may be implemented in various forms.

The row decoder 121 may be connected to the memory cell array 110 through string select lines (SSL), word lines (WL), and ground select lines (GSL). The row decoder 121 may receive an address (ADDR) from an external device (eg, a memory controller or a host device). In an exemplary embodiment, the address ADDR may include various address information such as a block address, a row address, a column address, etc. The row decoder 121 may decode the received address (ADDR) and control each of the string select lines (SSL), word lines (WL), and ground select lines (GSL).

The voltage generator 122 generates various voltages required for the nonvolatile memory device 100 to operate (e.g., a plurality of program voltages, a plurality of verification voltages, a plurality of pass voltages, a plurality of select read voltages, A plurality of unselected read voltages, a plurality of block selection voltages, etc.) can be generated. Various voltages generated from the voltage generator 122 may be provided to the row decoder 121.

The control logic circuit 123 receives a command (CMD) or control signal (CTRL) from an external device (e.g., memory controller, host device, etc.), and operates based on the received command (CMD) or control signal (CTRL). The row decoder 121, voltage generator 122, and input/output circuit 124 can be controlled.

The input/output circuit 124 may be connected to the memory cell array 110 through a plurality of bit lines BL. The input/output circuit 124 may read data (DATA) stored in the memory cell array 110 through a plurality of bit lines (BL) and transmit the read data (DATA) to an external device. Alternatively, the input/output circuit 124 may receive data DATA from an external device and store the received data DATA in the memory cell array 110 through the bit lines BL.

In an example embodiment, the nonvolatile memory device 100 may operate based on a specific unit (eg, block unit, sub-block unit, word line unit, page unit, etc.). For example, when a page-by-page program operation for the first word line is performed on the non-volatile memory device 100, the row decoder 121 uses an address (ADDR) (particularly a block address) received from an external device. Based on , at least one memory block among a plurality of memory blocks included in the memory cell array 110 may be selected. The row decoder 121 selects string selection lines (SSL) and word lines to perform a program operation on the first word line in the selected memory block based on the address (ADDR) (particularly, the row address) received from an external device. fields (WL), ground selection lines (GSL), and bit lines (BL) can be controlled.

In an exemplary embodiment, a plurality of memory blocks may share bit lines BL with each other. That is, during a program operation, the bit line voltage may be provided to the remaining memory blocks (i.e., unselected blocks) other than the selected block among the plurality of memory blocks. Specific cell transistors (eg, string select transistors) may be turned off in the unselected memory blocks so that the bit line voltage is not applied to the unselected memory blocks. The row decoder 121 may provide a specific voltage to control lines (eg, some of the string select lines (SSL)) connected to specific cell transistors so that the specific cell transistors can be turned off.

In an exemplary embodiment, the row decoder 121 according to an embodiment of the present invention may provide a specific voltage only to a specific string selection line among the string selection lines of an unselected block. In this case, since a specific voltage does not need to be applied to all string selection lines of the unselected block, the size of the row decoder 121 can be reduced. The configuration of the row decoder 121 according to an embodiment of the present invention is described in more detail with reference to the drawings below.

FIG. 2 is a circuit diagram illustrating a first memory block among a plurality of memory blocks included in the memory cell array of FIG. 1 . In an exemplary embodiment, the first memory block BLK1 having a three-dimensional structure is exemplarily described with reference to FIG. 2 , but the scope of the present invention is not limited thereto. For example, the memory cell array 110 may include a plurality of memory blocks, and each of the plurality of memory blocks may have a structure similar to the first memory block BLK1 of FIG. 2 . In an exemplary embodiment, the first memory block BLK1 shown in FIG. 2 may be a physical erase unit of the nonvolatile memory device 100. However, the scope of the present invention is not limited to this, and the physical erase unit may be modified into a page unit, a word line unit, a sub-block unit, etc.

Referring to FIGS. 1 and 2 , the first memory block BLK1 may include a plurality of cell strings CS11, CS12, CS21, and CS22. Each of the plurality of cell strings (CS11, CS12, CS21, CS22) may be arranged in the row direction and column direction. Although for the sake of brevity of the drawing, four cell strings (CS11, CS12, CS21, CS22) are shown in FIG. 2, the scope of the present invention is not limited thereto, and the number of cell strings is in the row or column direction. can be increased or decreased.

Among the plurality of cell strings (CS11, CS12, CS21, CS22), cell strings located in the same column may be connected to the same bit line. For example, the cell strings CS11 and CS21 may be connected to the first bit line BL1, and the cell strings CS21 and CS22 may be connected to the second bit line BL2.

Each of the plurality of cell strings CS11, CS12, CS21, and CS22 may include a plurality of cell transistors. Each of the plurality of cell transistors may be a charge trap flash (CTF) memory cell. A plurality of cell transistors may be stacked in a height direction, which is a direction perpendicular to a plane (eg, a semiconductor substrate (not shown)) formed by the row and column directions.

A plurality of cell transistors may be connected in series between a corresponding bit line (eg, BL1 or BL2) and a common source line (CSL). For example, the plurality of cell transistors may include string selection transistors (SSTb, SSTa), dummy memory cells (DMC1, DMC2), memory cells (MC1 to MC4), and ground selection transistors (GSTa, GSTb). there is. Series-connected string selection transistors SSTb and SSTa may be provided between the series-connected memory cells MC1 to MC4 and the corresponding bit line (eg, BL1 or BL2). Series-connected ground selection transistors (GSTa, GSTb) may be provided between the series-connected memory cells (MC1 to MC4) and the common source line (CSL).

In an exemplary embodiment, a second dummy memory cell DMC2 may be provided between the series-connected string selection transistors SSTb and SSTa and the series-connected memory cells MC1 to MC4, and the series-connected memory cells MC1 to MC4 may be provided. A first dummy memory cell (DMC1) may be provided between MC4) and the ground selection transistors (GSTb and GSTa) connected in series.

Among the memory cells MC1 to MC4 of each of the plurality of cell strings (CS11, CS12, CS21, and CS22), memory cells located at the same height may share the same word line. For example, the first memory cells MC1 of each of the plurality of cell strings CS11, CS12, CS21, and CS22 may be located at the same height from the substrate (not shown) and extend the first word line WL1. You can share it. The second memory cells MC2 of each of the plurality of cell strings CS11, CS12, CS21, and CS22 may be located at the same height from the substrate (not shown) and may share the second word line WL2. . Likewise, each of the third and fourth memory cells MC3 and MC4 of the plurality of cell strings CS11, CS12, CS21, and CS22 may be located at the same height from the substrate (not shown), and the third and fourth memory cells MC3 and MC4, respectively, may be located at the same height from the substrate (not shown). The fourth word lines (WL3, WL4) can be shared.

Among the dummy memory cells DMC1 and DMC2 of the plurality of cell strings CS11, CS12, CS21, and CS22, dummy memory cells located at the same height may share the same dummy word line. For example, the first dummy memory cells DMC1 of each of the plurality of cell strings CS11, CS12, CS21, and CS22 may share the first dummy word line DWL1, and the plurality of cell strings CS11 may share the first dummy word line DWL1. , CS12, CS21, CS22), each of the second dummy memory cells DMC2 may share the second dummy word line DWL2.

Among the string selection transistors SST1b and SST1a of each of the plurality of cell strings CS11, CS12, CS21, and CS22, string selection transistors located in the same row and at the same height may be connected to the same string selection line. For example, the string selection transistors SSTb of the cell strings CS11 and CS12 may be connected to the string selection line SST1b, and the string selection transistors SSTa of the cell strings CS11 and CS12 may be connected to the string selection line SST1b. It can be connected to the selection line (SST1a). The string selection transistors SSTb of the cell strings CS21 and CS22 may be connected to the string selection line SST2b, and the string selection transistors SSTa of the cell strings CS21 and CS22 may be connected to the string selection line SST2a. ) can be connected to.

Although not shown in the drawing, string selection transistors located in the same row among the string selection transistors (SST1b, SST1a) of each of the plurality of cell strings (CS11, CS12, CS21, CS22) may share the same string selection line. there is. For example, the string selection transistors SSTb and SSTa of the cell strings CS11 and CS12 may share the first string selection line, and the string selection transistors SSTb and SSTa of the cell strings CS21 and CS22 may share the first string selection line. SSTa) may share a second string selection line that is different from the first string selection line.

Among the ground selection transistors GST1b and GST1a of each of the plurality of cell strings (CS11, CS12, CS21, and CS22), ground selection transistors located in the same row and at the same height may be connected to the same ground selection line. For example, the ground selection transistors GSTb of the cell strings CS11 and CS12 may be connected to the ground selection line GST1b, and the ground selection transistors GSTa of the cell strings CS11 and CS12 may be connected to the ground selection line. It can be connected to the selection line (GST1a). The ground selection transistors GSTb of the cell strings CS21 and CS22 may be connected to the ground selection line GST2b, and the ground selection transistors GSTa of the cell strings CS21 and CS22 may be connected to the ground selection line GST2a. ) can be connected to.

Although not shown in the drawing, the ground selection transistors GST1b and GST1a of each of the plurality of cell strings CS11, CS12, CS21, and CS22 may share the same ground selection line. Alternatively, among the ground selection transistors GST1b and GST1a of each of the plurality of cell strings (CS11, CS12, CS21, and CS22), ground selection transistors of the same height may share the same ground selection line. Alternatively, ground selection transistors located in the same row among the ground selection transistors GST1b and GST1a of each of the plurality of cell strings CS11, CS12, CS21, and CS22 may share the same ground selection line.

In an exemplary embodiment, the first memory block BLK1 shown in FIG. 2 is an example, and the number of cell strings may be increased or decreased, and the rows and columns constituting the cell string may be adjusted according to the number of cell strings. The number can be increased or decreased. Additionally, the number of cell transistors (GST, MC, DMC, SST, etc.) of the first memory block (BLK1) may be increased or decreased, respectively, and the height of the first memory block (BLK1) may be increased or decreased depending on the number of cell transistors. may increase or decrease. Additionally, depending on the number of cell transistors, the number of lines (GSL, WL, DWL, SSL, etc.) connected to the cell transistors may increase or decrease.

FIG. 3 is a diagram illustrating the row decoder of FIG. 1 by way of example. For brevity of the drawing, the configuration of the row decoder 121 is explained based on one cell string CS11 among the plurality of cell strings CS11, CS12, CS21, and CS22 of the first memory block BLK1. Additionally, unnecessary components in explaining the row decoder 121 are omitted.

Below, in order to clearly explain various embodiments of the present invention, the operation of the nonvolatile memory device 100 on a memory block basis is described. That is, in the following embodiments, the operation of the non-volatile memory device 100 for selected blocks and non-selected blocks is described, but the scope of the present invention is not limited thereto, and the operation types of the non-volatile memory device 100 are not limited thereto. Control operations may be performed on various lines (e.g., GSL, WL, DWL, SSL, etc.) connected to the selected memory block (e.g., program operation, read operation, or erase operation, etc.).

Referring to FIGS. 1 to 3 , the row decoder 121 may include a block decoder 121a, a block selection circuit 121b, a block non-selection circuit 121c, and a line driver 121d.

The block decoder 121a may decode the block address ADDR_BLK (for example, it may be included in the address ADDR) and output the block selection signal SEL_BLK. For example, the block decoder 121a may determine whether the block address ADDR_BLK corresponds to the first memory block BLK1 including the cell string CS11. When the block address (ADDR_BLK) corresponds to the first memory block (BLK1), the first memory block (BLK1) may be a selected block, and when the block address (ADDR_BLK) does not correspond to the first memory block (BLK1) , the first memory block BLK1 may be an unselected block. That is, the block decoder 121a can determine whether the first memory block BLK1 is a selected block or an unselected block based on the block address ADDR_BLK.

When the first memory block BLK1 is the selected block, the block decoder 121a may output a “logic high” block selection signal SEL_BLK. When the first memory block BLK1 is an unselected block, the block decoder 121a may output a “logic low” block selection signal SEL_BLK. However, the scope of the present invention is not limited to this, and the level of the block selection signal (SEL_BLK) may be modified in various ways.

The block selection circuit 121b includes string selection lines (SSL1a, SSL1b), dummy word lines (DWL1, DWL2), and word lines (WL1 to WL4) connected to the cell string (CS11) of the first memory block (BLK1). , and may be connected between the ground selection lines (GSL1a and GSL1b) and the line driver 121d.

The block selection circuit 121b may operate in response to the block selection signal SEL_BLK. For example, the block selection circuit 121b may include a plurality of signal lines (e.g., SSL1a, SSL1b, DWL2, WL4, ..., WL1, DWL1, GSL1b, GSL1a) connected between each of the line drivers 121d. It may include path transistors. A plurality of pass transistors of the block selection circuit 121b may be turned on in response to the block selection signal SEL_BLK of “logic high”. In this case, the driving voltages (e.g., VSSL1a, VSSL1b, VDWL2, VWL4, ..., VWL1, VDWL1, VGSL1b, VGSL1a) from the line driver 121d are applied to each corresponding signal line (e.g., SSL1a). , SSL1b, DWL2, WL4, …, WL1, DWL1, GSL1b, GSL1a).

A plurality of pass transistors of the block selection circuit 121b may be turned off in response to the block selection signal SEL_BLK of “logic low”. In this case, each corresponding line (eg, SSL1a, SSL1b, DWL2, WL4, ..., WL1, DWL1, GSL1b, GSL1a) may be floated.

That is, when the first memory block BLK1 is the selected block, the block selection circuit 121b may provide corresponding driving voltages to various lines connected to the first memory block BLK1, and the first memory block (BLK1) When BLK1) is an unselected block, the block selection circuit 121b may block or float the driving voltage provided to various lines connected to the first memory block BLK1.

In an exemplary embodiment, the driving voltages (e.g., VSSL1a, VSSL1b, VDWL2, VWL4, ..., VWL1, VDWL1, VGSL1b, VGSL1a) from the line driver 121d determine the operation type of the non-volatile memory device 100. (For example, program operation, verification operation, read operation, erase operation, etc.), it may be modified in various ways depending on string selection/non-selection, word line selection/non-selection, etc.

In an exemplary embodiment, when the first memory block BLK1 is an unselected block, string selection transistors are used to prevent the voltage provided to the bit line (eg, BL1) from being applied to the first memory block BLK1. Some of (SSTb, SSTa) may be turned off.

For example, the block non-selection circuit 121c is a non-selection circuit connected between the first string selection line (SSL1b) and the off voltage (VOFF) among the string selection lines (SSL1b, SSL1b) connected to the first memory block (BLK1). It may include an unselected path transistor, and the unselected path transistor may operate in response to an inverted block select signal (/SEL_BLK). In an example embodiment, the off voltage VOFF may be a ground voltage (GND) or a negative voltage.

That is, the block non-selection circuit 121c may be turned off when the first memory block BLK1 is a selected block and may be turned on when the first memory block BLK1 is an unselected block. When the block non-selection circuit 121c is turned on, an off voltage (VOFF) is applied to the first string selection line (SSL1b), and the string selection transistor (SSTb) connected to the first string selection line (SSL1b) is turned on. By being turned off, the voltage of the first bit line BL1 may not be applied to the first memory block BLK1.

In an exemplary embodiment, a conventional nonvolatile memory device is configured to provide an off voltage (VOFF) to all string selection lines connected to a specific memory block when a specific memory block is an unselected block. In this case, the block deselect circuit will include a deselect pass transistor connected to each of all string select lines. In this case, the size of the row decoder may increase.

On the other hand, according to an embodiment of the present invention, the block non-selection circuit 121c is connected only to some string selection lines among a plurality of string selection lines connected to one memory block (i.e., the first memory block (BLK1)). Therefore, the area of the row decoder 121 can be reduced.

FIG. 4 is a flow chart showing the operation of the non-volatile memory device of FIG. 1. Hereinafter, the operation of the nonvolatile memory device 100 according to an embodiment of the present invention will be described based on the first memory block BLK1. However, the scope of the present invention is not limited thereto, and the nonvolatile memory device 100 may perform an operation according to the flowchart of FIG. 4 for each of a plurality of memory blocks.

Referring to FIGS. 1 to 4 , in step S110, the nonvolatile memory device 100 may determine whether the first memory block BLK1 is the selected block. For example, the nonvolatile memory device 100 receives an address (ADDR) from an external device (e.g., memory controller, host device, etc.) and selects one of a plurality of memory blocks based on the received address (ADDR). At least one memory block can be selected. In other words, the nonvolatile memory device 100 may determine whether the first memory block BLK1 is the selected block based on the address ADDR received from the external device.

If the first memory block BLK1 is not a selected block (i.e., an unselected block), in step S120, the nonvolatile memory device 100 turns off the block selection circuit 121b to select the first memory Signal lines connected to the block (BLK1) can be floated. For example, as described with reference to FIG. 3 , when the first memory block BLK1 is an unselected block, the block decoder 121a may output a logic low block selection signal SEL_BLK. The block selection circuit 121b may float signal lines connected to the first memory block BLK1 in response to the logic low block selection signal SEL_BLK. In other words, the block selection circuit 121b may block the connection between the signal lines connected to the first memory block BLK1 and the line driver 121d.

In step S130, the nonvolatile memory device 100 may provide the off voltage VOFF to only some of the string select lines SSL. For example, as described with reference to FIG. 3, when the first memory block BLK1 is an unselected block, the block unselection circuit 121c turns - in response to the inverted block selection signal /SEL_BLK. It is turned on, and accordingly, an off voltage (VOFF) may be provided to some string selection lines (eg, SSL1b). At this time, since the block non-selection circuit 121c is connected to only some of the string selection lines SSL1b and SSL1a, the off voltage VOFF is provided only to some of the string selection lines SSL1b. will be. In this case, the remaining string selection line (eg, SSL1a) may be floating.

When the first memory block BLK1 is the selected block, in step S140, the nonvolatile memory device 100 turns on the block selection circuit 121b and is driven with signals connected to the first memory block BLK1. Voltages can be provided. In step S140, the nonvolatile memory device 100 may control driving voltages provided to a plurality of lines connected to the first memory block BLK1.

For example, as described with reference to FIG. 3 , when the first memory block BLK1 is the selected block, the block decoder 121a may output a logic high block selection signal SEL_BLK. The block selection circuit 121b may be turned on in response to the logic high block selection signal SEL_BLK. Various driving voltages from the line driver 121d may be provided to corresponding signal lines through the turned-on block selection circuit 121b.

In an exemplary embodiment, driving voltages may vary depending on the type of operation of the nonvolatile memory device 100, whether a string is selected, whether a word line is selected, operating conditions, etc. In an exemplary embodiment, when the first memory block BLK1 is a selected block, the block non-selection circuit 121c may be turned off.

FIG. 5 is a diagram showing the configuration of the row decoder of FIG. 3 in more detail. In FIG. 3 , the schematic configuration of the row decoder 121 is described based on one cell string CS11. However, with reference to FIG. 5 , the configuration of the row decoder 121 is briefly described based on the first memory block BLK1. This is explained in more detail. For the sake of brevity of drawings and convenience of explanation, detailed descriptions of components unnecessary for explaining the row decoder 121 and components described above are omitted.

Referring to FIGS. 1 to 5 , the first memory block BLK1 may include a plurality of cell strings CS11, CS12, CS21, and CS22. Each of the plurality of cell strings CS11, CS12, CS21, and CS22 may include string select transistors SSTb and SSTa. Since the remaining components of the first memory block BLK1 have been described with reference to FIG. 2, detailed description thereof will be omitted.

The row decoder 121 may include a block decoder 121a, a block selection circuit 121b, a block non-selection circuit 121c, and a line driver 121d. Since the block decoder 121a and the line driver 121d have been described above, their detailed description will be omitted.

The block selection circuit 121b may be connected to various lines (e.g., SSL1a, SSL1b, SSL2a, SSL2b, etc.) connected to the first memory block BLK1, and may be connected to the line driver in response to the block selection signal SEL_BLK. Driving voltages from 121d can be provided to the corresponding signal lines or blocked (or floated).

In response to the inverted block selection signal (/SEL_BLK), the block non-selection circuit 121c selects some of the string selection lines (SSL1a, SSL1b, SSL2a, SSL2b) connected to the first memory block (BLK1). Off voltage (VOFF) can be provided. For example, as shown in FIG. 5, the block non-selection circuit 121c selects some strings of the string selection lines (SSL1a, SSL1b, SSL2a, and SSL2b) in response to the inverted block selection signal (/SEL_BLK). The off voltage (VOFF) can be applied only to the selection lines (SSL1b and SSL2b).

In an exemplary embodiment, some of the string selection lines (SSL1b, SSL2b) connected to the block non-selection circuit 121c are string selection lines connected to string selection transistors physically adjacent to the bit line among string selection transistors located in the same row. It can be. For example, as shown in FIG. 5, the string selection transistors SSTa and SSTb of the cell strings CS11 and CS12 are located in the same row, and each is connected to the string selection lines SSL1a and SSL1b, respectively. do. At this time, the string selection transistors SSTb may be physically closer to the bit lines BL1 and BL2 than the string selection transistors SSTa. When the first memory block BLK1 is an unselected block, string selection lines (e.g., SSL1b, SSL2b) connected to string selection transistors (e.g., SSTb) physically adjacent to the bit lines BL1. Only the off voltage (VOFF) can be applied.

In an exemplary embodiment, the block non-selection circuit 121c may not be connected to the remaining string selection lines (eg, SSL1a and SSL2a). In other words, when the first memory block (BLK1) is an unselected block, the off voltage (VOFF) is not applied to the remaining string selection lines (SSL1a and SSL2a), and the remaining string selection lines (SSL1a and SSL2a) are floating. It can be.

In an exemplary embodiment, similar to that previously described, the block non-select circuit 121c turns off certain string select lines (e.g., SSL1b, SSL1a) in response to the inverted block select signal (/SEL_BLK). It may include non-selected pass transistors configured to provide voltage VOFF. At this time, the number of non-selected pass transistors (2 in the embodiment of FIG. 5) is equal to the number of the plurality of string selection lines (SSL1a, SSL1b, SSL2a, SSL2b) connected to the first memory block (BLK1) (FIG. 5 In an embodiment, it may be less than 4).

As described above, according to an embodiment of the present invention, the block non-selection circuit 121c configured to provide an off voltage (VOFF) for turning off the string selection transistor of the unselected block selects a plurality of strings connected to the unselected block. It is connected to only some of the string selection lines among the lines, and the remaining string selection lines may be omitted. Therefore, even if the number of string selection transistors included in the memory block or the number of string selection lines connected to the memory block increases, the number of non-select pass transistors included in the block non-selection circuit 121c does not increase, so the row decoder The overall area of (121) may be reduced.

FIG. 6 is a diagram illustrating the program bias of the row decoder of FIG. 5. To clearly describe embodiments of the present invention, program operations for selected blocks and unselected blocks are described. In addition, in order not to obscure the technical idea of the present invention, only the biases of the string selection lines for the selected and unselected blocks are explained, and the biases of the remaining signal lines (e.g., WL, DWL, GSL, CSL, etc.) are explained. Detailed description is omitted.

Referring to FIGS. 5 and 6 , the power supply voltage (VCC) or the ground voltage (VSS) may be applied to the first and second bit lines BL1 and BL2. When the first memory block BLK1 is the selected block, as described above, the block selection circuit 121b is turned on and the block non-selection circuit 121c is turned off, so that the driving voltages VSSL1a, VSSL1b, VSSL2a, VSSL2b) may be provided with corresponding string selection lines (SSL1a, SSL1b, SSL2a, SSL2b). In an exemplary embodiment, the driving voltages VSSL1a, VSSL1b, VSSL2a, and VSSL2b may be varied depending on whether the cell strings CS11, CS12, CS21, and CS22 are selected. For example, when the cell strings CS11 and CS12 are selected strings and the cell strings CS21 and CS22 are unselected strings, the driving voltages VSSL1a and VSSL1b are those of the cell strings CS11 and CS12. It may be a high voltage (e.g., VCC) for turning on the string selection transistors SSTa and SSTb, and the driving voltages VSSL2a and VSSL2b are applied to the string selection transistors of the cell strings CS21 and CS22, respectively. It may be a low voltage to turn off (SSTa, SSTb). In an example embodiment, the driving voltages VSSL2a and VSSL2b may each have different levels.

When the first memory block BLK1 is an unselected block (Unselected BLK), as described above, the block selection circuit 121b is turned off and the block unselection circuit 121c is turned on, thereby partially The off voltage VOFF may be applied only to the string selection lines SSL1b and SSL2b, and the remaining string selection lines SSL1a and SSL2a may be floating.

FIG. 7 is a diagram for explaining the operation of the non-volatile memory device of FIG. 1. Referring to FIG. 7, the operation of the row decoder 121 for selected blocks and the operation for unselected blocks are described. For convenience of explanation, detailed description of the components described above is omitted.

In an exemplary embodiment, the first and second memory blocks BLK1 and BLK2 shown in FIG. 7 may each include a plurality of cell strings arranged in three rows, and cell strings located in the same row are the same. Can be connected to string selection lines. However, the scope of the present invention is not limited thereto.

Referring to FIG. 7, the row decoder 121 includes first and second block selection circuits 121b-1 and 121b-2 and first and second block non-selection circuits 121c-1 and 121c-2. can do. The first block selection circuit 121b-1 may be connected to a plurality of string selection lines SSL1a, SSL1b, SSL2a, SSL2b, SSL3a, and SSL3b of the first memory block BLK1. The first block non-selection circuit 121c-1 may be connected only to some string selection lines (e.g., SSL1b, SSL2b, SSL3b) among the plurality of string selection lines SSL1a to SSL3b of the first memory block BLK1. You can.

The second block selection circuit 121b-2 may be connected to a plurality of string selection lines SSL1a, SSL1b, SSL2a, SSL2b, SSL3a, and SSL3b of the second memory block BLK2. The second block non-selection circuit 121c-2 may be connected only to some string selection lines (e.g., SSL1b, SSL2b, SSL3b) among the plurality of string selection lines SSL1a to SSL3b of the second memory block BLK2. You can.

For brevity of drawings and convenience of description, string selection lines connected to the first and second memory blocks BLK1 and BLK2 are denoted by the same reference numerals, but the scope of the present invention is not limited thereto, and the first and second memory blocks BLK1 and BLK2 are indicated by the same reference numerals. The string selection lines of each of the second memory blocks BLK1 and BLK2 may be lines that are physically distinct from each other.

For brevity of the drawing, only the string selection lines connected to the first and second memory blocks BLK1 are shown, but the scope of the present invention is not limited thereto, and the first memory block BLK1 and the first block selection circuit (121b-1) or the second memory block (BLK2) and the second block selection circuit (121b-2) may be further connected through various lines (eg, DWL, WL, GSL, etc.) described above.

For convenience of explanation, it is assumed that the first memory block BLK1 is a selected block and the second memory block BLK2 is an unselected block. At this time, as described above, the first block selection circuit 121b-1 connected to the first memory block BLK1, which is the selected block, is turned on. In this case, as shown in FIG. 7, it corresponds to the string selection lines (SSL1b, SSL1a, SSL2b, SSL2a, SSL3b, and SSL3a) of the first memory block (BLK1) through the first block selection circuit (121b-1). Voltages (eg, VSSL1b, VSSL1a, VSSL2b, VSSL2a, VSSL3b, VSSL3a) may be provided.

The second block selection circuit 121b-2 connected to the second memory block BLK2, which is an unselected block, may be turned off. In this case, as shown in FIG. 7, the second block selection circuit 121b-2 2), the string selection lines (SSL1b, SSL1a, SSL2b, SSL2a, SSL3b, SSL3a) of the second memory block (BLK1) are floated or the corresponding voltages (e.g., VSSL1b, VSSL1a, VSSL2b, VSSL2a, VSSL3b, VSSL3a) may not be provided or may be blocked.

At this time, the second block non-selection circuit 121c-2 connected to some string selection lines (SSL1b, SSL2b, SSL3b) of the second memory block (BLK2), which is an unselected block, is turned on, thereby An off voltage (VOFF) may be provided to some string selection lines (SSL1b, SSL2b, and SSL3b) of (BLK2). Accordingly, even if the second memory block BLK2, which is an unselected block, shares a bit line with the first memory block BLK1, the voltage of the shared bit line may not be applied to the second memory block BLK2.

In addition, even if various voltages (e.g., VSSL1b, VSSL1a, VSSL2b, VSSL2a, VSSL3b, VSSL3a) provided to the first and second block selection circuits 121b-1 and 121b-2 are shared, the second block selection Because various voltages are blocked by the circuit 121b-2, an operation on the second memory block BLK2 may not be performed.

As described above, according to embodiments of the present invention, the non-volatile memory device applies an off voltage (VOFF) to only some of the string selection lines among the plurality of string selection lines connected to the unselected memory block, thereby Malfunctions can be prevented. Accordingly, since the block non-selection circuit only needs to be connected to some of the string selection lines among the plurality of string selection lines, the area of the row decoder can be reduced even if the number of string selection transistors or the number of string selection lines increases.

In an exemplary embodiment, a string selection line to which an off voltage is applied among a plurality of string selection lines connected to one memory block is connected to a string selection transistor physically adjacent to a bit line among string selection transistors located in the same row. It could be a line. Alternatively, among a plurality of string select lines connected to one memory block, a string select line to which an off voltage is applied may be a string select line connected to a string transistor located at the highest level from the substrate among string select transistors located in the same row.

FIG. 8 is a diagram illustrating the row decoder of FIG. 1. For brevity of drawings and convenience of explanation, detailed descriptions of the components described above are omitted.

1 and 8, the row decoder 121-3 includes a block decoder 121a-3, a block selection circuit 121b-3, a block non-selection circuit 121c-3, and a line driver 121d- 3) may be included. Since the block decoder 121a-3, block selection circuit 121b-3, and line driver 121d-3 have been described above, their detailed description will be omitted.

Unlike previous embodiments, in the embodiment of FIG. 8, the cell string CS11-1 may include a plurality of string select transistors SSTs. Each of the string selection transistors SSTs may be connected to a plurality of string selection lines SSL1a to SSL1k.

The block non-selection circuit 121c-3 may be connected to some of the string selection lines SSL1a to SSLi among the plurality of string selection lines SSL1a to SSL1k. That is, when the memory block containing the cell string CS11-1 is an unselected block, the block unselection circuit 121c-3 selects some of the string selection lines SSL1a to SSL1k among the plurality of string selection lines SSL1a to SSL1k. ~SSLi) may be configured to provide an off voltage (VOFF).

In an exemplary embodiment, the number of some string selection lines (SSL1a to SSLi) connected to the block non-selection circuit 121c-3 (i.e., i, where i is a positive integer) is equal to the number of the remaining string selection lines (SSL1i). +1~SSL1k) (i.e., (k-i) numbers, where (k-i) is a positive integer greater than i).

Although the plurality of string selection transistors (SSTs) and the plurality of string selection lines (SSL1a to SSL1k) are shown as connected 1:1 in FIG. 8, the scope of the present invention is not limited thereto. For example, the number of string selection transistors (SSTs) may be m (where m is a positive integer), and the number of string selection lines (SSL1a to SSL1k) may be k (where k is an amount smaller than m). It can be an integer). That is, one string selection line can be shared with at least two string selection transistors.

FIG. 9A is a diagram illustrating the row decoder of FIG. 1. FIG. 9B is a diagram for explaining the configuration of the row decoder of FIG. 9A. For the sake of brevity of drawings and convenience of explanation, detailed descriptions of components unnecessary for explaining the configuration of the row decoder 121-4 and components described above are omitted.

Referring to FIGS. 1, 2, 9A, and 9B, the row decoder 121-4 includes a block decoder 121a-2, a block selection circuit 121b-4, a block non-selection circuit 121c-4, and a line driver 121d-4. Since the block decoder 121a-2, block selection circuit 121b-4, and line driver 121d-4 have been described above, their detailed description will be omitted.

The block non-selection circuit 121c-4 may be connected to specific string selection lines among the plurality of string selection lines SSL1a, SSL1b, SSL2a, and SSL2b. For example, the block non-selection circuit 121c-4 may be connected to specific string selection lines (eg, SSL1a, SSL2b) among the plurality of string selection lines (SSL1a, SSL1b, SSL2a, and SSL2b). In an exemplary embodiment, the specific string selection lines SSL1a and SSL2b connected to the block non-selection circuit 121c-4 may be determined based on the threshold voltages of the string selection transistors SSTa and SSTb.

As a more detailed example, as shown in FIG. 9B, the string selection transistors connected to the string selection line (SSL1b) may have a first threshold voltage distribution (Vth1), and the string selection transistors connected to the string selection line (SSL1a) may have a second threshold voltage distribution (Vth2). At this time, the second threshold voltage distribution (Vth2) may be at a higher level than the first threshold voltage distribution (Vth1). In other words, the lower or upper limit of the second threshold voltage distribution (Vth2) may be higher than the lower or upper limit of the first threshold voltage distribution (Vth1).

Likewise, the string selection transistors connected to the string selection line (SSL1b) may have a first threshold voltage distribution (Vth1), and the string selection transistors connected to the string selection line (SSL1a) may have a second threshold voltage distribution (Vth2). there is. At this time, the second threshold voltage distribution (Vth2) may be at a higher level than the first threshold voltage distribution (Vth1). In other words, the lower or upper limit of the second threshold voltage distribution (Vth2) may be higher than the lower or upper limit of the first threshold voltage distribution (Vth1).

A string selection line (e.g., SSL1a or SSL2b in the embodiment of FIG. 9B) connected to the string selection transistors having the highest threshold voltage distribution among the string selection lines (e.g., SSL1b/SSL1a) located in the same row. This block may be connected to the non-selection circuit 121c-4.

In other words, the threshold voltages of the string selection transistors connected to the string selection lines connected to the block non-selection circuit 121c-4 may be higher than the threshold voltages of the string selection transistors connected to other string selection lines.

In an exemplary embodiment, string selection transistors connected to the string selection lines connected to the lock non-selection circuit 121c-4 may be programmed to have a threshold voltage higher than a reference value.

Figure 10 is a circuit diagram exemplarily showing a third memory block according to an embodiment of the present invention. For convenience of explanation, detailed description of the components described above is omitted. In an exemplary embodiment, the third memory block BLK3 of FIG. 10 is an exemplary structure of a three-dimensional memory block, and the exemplary embodiment of the present invention is not limited thereto. In an exemplary embodiment, each of the plurality of memory blocks included in the memory cell array may have the structure of the first memory block BLK1 of FIG. 2 or the structure of the third memory block BLK3 of FIG. 10. there is.

Referring to FIG. 10 , the third memory block BLK3 may include a plurality of cell strings CS11, CS12, CS21, and CS22. A plurality of cell strings CS11, CS12, CS21, and CS22 may be arranged in row and column directions. Cell strings located in the same column may be connected to the same bit line. For example, the cell strings CS11 and CS21 may be connected to the first bit line BL1, and the cell strings CS12 and CS22 may be connected to the second bit line BL2.

Each of the plurality of cell strings CS11, CS12, CS21, and CS22 may include a plurality of cell transistors. A plurality of cell transistors may be connected in series between a corresponding bit line and a common source line (CSL). In an exemplary embodiment, the plurality of cell transistors include string select transistors (SSTa, SSTb), memory cells (MC1 to MC4), dummy memory cells (DMC1 to DMC3), ground select transistors (GSTa, GSTb), and erase. It may include control transistors (ECT1, ECT1). Each cell transistor may be connected to corresponding lines (e.g., SSL1a, SSL1b, SSL2a, SSL2b, DWL1 to DWL3, WL1 to WL4, GSL1a, GSL1b, GSL2a, GSL2b, ECL1, ECL2, etc.). The string selection transistors (SSTa, SSTb), memory cells (MC1 to MC4), dummy memory cells (DMC1, DMC2), and ground selection transistors (GSTa, GSTb) are described with reference to FIG. 2, so a detailed description thereof is provided. It is omitted.

Unlike the first memory block BLK1 of FIG. 2 , the third memory block BLK3 of FIG. 10 may further include erase control transistors ECT1 and ECT2 and a third dummy memory cell DMC3.

The first erase control transistor ECT1 may be located between the ground selection transistors GSTa and GSTb connected in series and the common source line CSL, and may be connected to the first erase control line ECL1. The second erase control transistor ECT2 may be located between the string select transistors SSTa and SSTb connected in series and the bit line BL1 or BL2, and may be connected to the second erase control line ECL2. The first and second erase control transistors ECT1 and ECT2 may be controlled by the first and second erase control lines ECL1 and ECL2, respectively. In an exemplary embodiment, the first and second erase control transistors ECT1 and ECT2 are configured to control gate induced drain leakage (GIDL) current during an erase operation for the third memory block BLK3. It can be configured.

The third dummy memory cell DMC1 may be located between the memory cells MC1 to MC4 stacked in a direction perpendicular to the substrate, and may be connected to the third dummy word line DWL3. For example, the third dummy memory cell DMC1 may be located between the second and third memory cells MC2 and MC3. In an exemplary embodiment, when the third memory block BLK3 has a multi-stacked structure, the third dummy memory cell MC3 is configured to include a lower structure (e.g., ECT1, GSTa, GSTb, It may be formed in a connection layer between a structure containing DMC1, MC1, MC2, etc.) and an upper structure (e.g., a structure containing ECT2, SSTa, SSTb, DMC2, MC4, MC3, etc.).

In an exemplary embodiment, the third memory block BLK3 shown in FIG. 10 is illustrative, and the scope of the present invention is not limited thereto. For example, at least one of the components shown in FIG. 10 may be omitted. Alternatively, additional components may be added to FIG. 10. That is, it will be understood that the third memory block BLK3 shown in FIG. 10 is an example, and the structure of the memory block may be modified in various ways.

Figures 11A to 11D are diagrams showing a row decoder according to an embodiment of the present invention. For convenience of explanation, the configuration of the row decoders 221-1, 221-2, 221-3, and 221-4 is described based on the third memory block BLK3 of FIG. 10, and the components described above are included. Detailed description is omitted. In FIGS. 11A to 11D , for clarity of drawing, the line connected to the block non-selection circuit among the various lines connected to the third memory block BLK3 is shown as a thick solid line.

Referring to FIGS. 11A to 11D, the row decoders 221-1, 221-2, 221-3, and 221-4 may be connected to the third memory block BLK3 through various lines, and the block decoder 221a- 1, 221a-2, 221a-3, 221-4), block selection circuit (221b-1, 221b-2, 221b-3, 221b-4), block non-selection circuit (221c-1, 221c-2, 221c) -3, 221c-4), and line drivers (221d-1, 221d-2, 221d-3, 221d-4). Block decoders (221a-1, 221a-2, 221a-3, 221-4), block selection circuits (221b-1, 221b-2, 221b-3, 221b-4), and line drivers (221d-1, 221d) -2, 221d-3, 221d-4) are similar to the components described above, so detailed description thereof is omitted.

As shown in FIG. 11A, the block unselection circuit 221c-1 is connected to the second erase control line ECL2, and when the third memory block BLK3 is an unselected block, the second erase control line ( It can be configured to provide off voltage (VOFF) with ECL2). That is, unlike the previous embodiments, the block non-selection circuit 221c-1 of FIG. 11A applies the off voltage VOFF to the second erase control line ECL2 located above the string selection lines instead of the string selection lines. can be provided. In an exemplary embodiment, the second erase control line ECL2 may indicate a line commonly connected to the bit lines BL1 and BL2 and physically adjacent cell transistors (i.e., the second erase control transistors ECT2). You can.

Next, as shown in FIG. 11B, the block unselection circuit 221c-2 is connected to the second dummy word line DWL2, and when the third memory block BLK3 is an unselected block, the second dummy word line DWL2 is connected to the second dummy word line DWL2. Off voltage (VOFF) can be provided through the word line (DWL2). That is, unlike the previous embodiments, the block non-selection circuit 221c-2 of FIG. 11B applies an off voltage ( VOFF) can be provided.

Next, as shown in FIG. 11C, the block unselection circuit 221c-3 is connected to the third dummy word line DWL3, and when the third memory block is an unselected block, the third dummy word line ( DWL3) can provide off voltage (VOFF). That is, unlike the previous embodiments, the block non-selection circuit 221c-3 of FIG. 11C provides the off voltage VOFF to the third dummy word line DWL3 located between the word lines instead of the string selection lines. You can.

Next, as shown in FIG. 11D, the block unselection circuit 221c-4 is connected to the first erase control line ECL1, and when the third memory block BLK3 is an unselected block, the first erase circuit 221c-4 is connected to the first erase control line ECL1. An off voltage (VOFF) can be provided through the control line (ECL1). That is, unlike the previous embodiments, the block non-selection circuit 221c-4 of FIG. 11D applies the off voltage VOFF to the first erase control line ECL1 located below the ground selection lines instead of the string selection lines. can be provided. In an exemplary embodiment, the first erase control line ECL1 may indicate a line commonly connected to the first erase control transistors ECT1 that are physically adjacent to the common source line CSL.

As described above, the row decoder of the non-volatile memory device according to an embodiment of the present invention may provide an off voltage (VOFF) to only some of the various signal lines connected to the unselected block according to various implementation methods. . In this case, because the number of transistors in the block non-selection circuit included in the row decoder can be reduced, the overall area of the nonvolatile memory device can be reduced. Accordingly, a non-volatile memory device with reduced area or reduced cost is provided.

Figure 12 is a block diagram illustrating a storage system to which a non-volatile memory device according to embodiments of the present invention is applied. Referring to FIG. 12, the storage system 1000 includes a host 1100 and a storage device 1200.

The storage device 1200 exchanges a signal (SIG) with the host 1100 through the signal connector 1201 and receives power (PWR) through the power connector 1202. The storage device 1200 includes a solid state drive (SSD) controller 1210, a plurality of non-volatile memories 1221 to 122n, an auxiliary power supply 1230, and a buffer memory 1240. Exemplarily, each of the plurality of non-volatile memories 1221 to 122n may be one of the non-volatile memory devices described with reference to FIGS. 1 to 11D.

The SSD controller 1210 may control a plurality of non-volatile memories 1221 to 122n in response to a signal SIG received from the host 1100. The plurality of non-volatile memories 1221 to 122n may operate under the control of the SSD controller 1210. The auxiliary power device 1230 is connected to the host 1100 through the power connector 1002. The auxiliary power supply device 1230 can receive power (PWR) from the host 1100 and charge it. The auxiliary power device 1230 may provide power to the SSD 1200 when power supply from the host 1100 is not smooth.

The above-described details are specific embodiments for carrying out the present invention. The present invention will include not only the above-described embodiments, but also embodiments that can be simply changed or easily changed in design. In addition, the present invention will also include technologies that can be easily modified and implemented using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims and equivalents of the present invention as well as the claims described later.

Claims (20)

a first memory block connected to a plurality of ground selection lines, a plurality of word lines, and a plurality of string selection lines stacked in a direction perpendicular to the substrate;
connected to the plurality of string selection lines, the plurality of word lines, and the plurality of ground selection lines, and in response to a block selection signal, the plurality of string selection lines, the plurality of word lines, and the plurality of ground selection lines a block selection circuit configured to provide corresponding driving voltages to each of the ground selection lines; and
A non-volatile memory device comprising a block non-selection circuit connected only to specific string selection lines among the plurality of string selection lines and configured to provide an off voltage only to the specific string selection lines in response to an inverted block selection signal. . According to claim 1,
A non-volatile memory device further comprising a block decoder configured to receive an address from an external device and output the block selection signal and the inverted block selection signal based on the received address. According to claim 2,
If the received address does not correspond to the first memory block, the off voltage is provided to the specific string selection lines, and the remaining string selection lines excluding the specific string selection lines among the plurality of string selection lines are A floating non-volatile memory device. According to claim 1,
A nonvolatile memory device wherein the off voltage is one of a ground voltage and a negative voltage. According to claim 1,
The first memory block includes first and second cell strings stacked in a direction perpendicular to the substrate, between the substrate and the first bit line,
The first cell string is:
a first ground selection transistor stacked in a direction perpendicular to the substrate and connected to a first ground selection line among the plurality of ground selection lines;
a plurality of first memory cells stacked on top of the first ground selection transistor in a direction perpendicular to the substrate and each connected to the plurality of word lines; and
A plurality of first string selection transistors are stacked on top of the plurality of first memory cells in a direction perpendicular to the substrate and each connected to a first string selection line among the plurality of string selection lines,
The second cell string is:
a second ground selection transistor stacked in a direction perpendicular to the substrate and connected to a second ground selection line among the plurality of ground selection lines;
a plurality of second memory cells stacked on top of the second ground selection transistor in a direction perpendicular to the substrate and each connected to the plurality of word lines; and
Nonvolatile memory cells including a plurality of second string selection transistors stacked in a direction perpendicular to the substrate on top of the plurality of second memory cells and each connected to a second string selection line among the plurality of string selection lines. memory device. According to claim 5,
The specific string selection lines include a first portion of the first string select lines and a second portion of the second string select lines. According to claim 6,
The first part of the first string selection lines is physically closer to the first bit line than the rest except the first part of the first string selection lines,
The second portion of the second string select lines is physically closer to the first bit line than the remaining portions of the second string select lines except for the second portion. According to claim 6,
The plurality of first string selection transistors are M (where M is a positive integer), and among the plurality of first string selection transistors, a string selection transistor connected to the first portion of the first string selection lines The number of them is N (where N is smaller than M, and (MN) is a positive integer larger than N),
The plurality of second string selection transistors are M, and the number of string selection transistors connected to the second portion of the second string selection lines among the plurality of second string selection transistors is N. . According to claim 6,
The threshold voltages of the string select transistors connected to the first part of the first string select lines among the plurality of first string select transistors are the first string select lines among the plurality of first string select transistors. Higher than the threshold voltages of the string selection transistors connected to the remaining string selection lines except for the first part,
The threshold voltages of the string selection transistors connected to the second part of the second string selection lines among the plurality of second string selection transistors are the second string selection lines among the plurality of second string selection transistors. A non-volatile memory device that is higher than the threshold voltages of string selection transistors connected to the remaining string selection lines except for the second portion. According to claim 1,
The block unselection circuit includes a plurality of unselection path transistors configured to provide the off voltage to the specific string selection lines in response to the inverted block selection signal,
A nonvolatile memory device wherein the number of the plurality of unselected pass transistors is smaller than the number of the plurality of string select lines. A first cell string connected in series between a common source line and a first bit line and including a plurality of first cell transistors stacked in a direction perpendicular to the substrate;
a second cell string connected in series between the common source line and the first bit line and including a plurality of second cell transistors stacked in a direction perpendicular to the substrate;
a block selection circuit connected to the first cell string and the second cell string through a plurality of signal lines and configured to provide corresponding driving voltages to the plurality of signal lines in response to a block selection signal; and
A block non-selection circuit connected to specific signal lines among the plurality of signal lines and configured to provide an off voltage to the specific signal lines in response to an inverted block selection signal,
Among the plurality of signal lines, the remaining signal lines excluding the specific signal lines include at least one first string selection line connected to the first cell string and at least one second string selection line connected to the second cell string. A non-volatile memory device. According to claim 11,
The specific signal lines are:
a first signal line connected to a cell transistor physically adjacent to the first bit line among the plurality of first cell transistors; and
A nonvolatile memory device including a second signal line connected to a cell transistor physically adjacent to the first bit line among the plurality of second cell transistors. According to claim 12,
The plurality of first cell transistors include a plurality of first string select transistors,
The plurality of second cell transistors include a plurality of second string select transistors,
Among the plurality of first cell transistors, the cell transistor physically adjacent to the first bit line is one of the plurality of first string select transistors,
Among the plurality of second cell transistors, the cell transistor physically adjacent to the first bit line is one of the plurality of second string select transistors. According to claim 12,
The plurality of first cell transistors include a first erase control transistor,
The plurality of second cell transistors include a second erase control transistor,
Among the plurality of first cell transistors, the cell transistor physically adjacent to the first bit line is the first erase control transistor,
Among the plurality of second cell transistors, the cell transistor physically adjacent to the first bit line is the second erase control transistor. According to claim 14,
The first signal line and the second signal line are erase control lines commonly connected to the first erase control transistor and the second erase control transistor. According to claim 11,
When the first memory block including the first cell string and the second cell string is a selected block, the block selection circuit provides the corresponding driving voltages to the plurality of signal lines, and the block non-selection circuit Floats the specific signal lines,
When the first memory block is an unselected block, the block selection circuit floats the plurality of signal lines, and the block non-selection circuit provides the off voltage to the specific signal lines. According to claim 11,
A nonvolatile memory device wherein the off voltage is a ground voltage or a negative voltage. A first memory block stacked in a direction perpendicular to the substrate and connected to a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines;
a block decoder configured to output a block selection signal and an inverted block selection signal based on an address received from an external device;
a plurality of pass transistors configured to provide corresponding driving voltages to the plurality of string selection lines, the plurality of word lines, and the plurality of ground selection lines in response to the block selection signal; and
A plurality of non-select pass transistors configured to provide an off voltage to specific string selection lines among the plurality of string selection lines in response to the inverted block selection signal,
A nonvolatile memory device wherein the number of the plurality of unselected pass transistors is smaller than the number of the plurality of string select lines. According to claim 18,
The first memory block is:
A first cell string connected to a first bit line and including a plurality of first cell transistors connected in series;
a second cell string connected to the first bit line and including a plurality of second cell transistors connected in series;
a third cell string connected to a second bit line and including a plurality of third cell transistors connected in series; and
a fourth cell string connected to the second bit line and including a plurality of fourth cell transistors connected in series;
First string selection lines among the plurality of string selection lines are connected to the first and third cell strings,
Second string selection lines among the plurality of string selection lines are connected to the second and fourth cell strings,
The specific string selection lines include a first portion of the first string select lines and a second portion of the second string select lines. According to claim 19,
The first portion of the first string selection lines is a cell transistor that is most physically adjacent to the first bit line among the plurality of first cell transistors, and the second bit line among the plurality of third cell transistors. and is connected to the most physically adjacent cell transistor,
The second portion of the second string selection lines is a cell transistor that is most physically adjacent to the first bit line among the plurality of second cell transistors, and the second bit line among the plurality of fourth cell transistors. and a non-volatile memory device connected to the most physically adjacent cell transistor.

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