KR102639156B1 - Polishing compositions and methods of using same - Google Patents

Abstract

The present invention provides at least one abrasive; at least one nitride removal rate reducer, acid or base; and a polishing composition comprising water. At least one nitride removal rate reducing agent includes a hydrophobic portion containing C ₁₂ to C ₄₀ hydrocarbon groups; and a hydrophilic portion containing at least one group selected from the group consisting of a sulfinite group, a sulfate group, a sulfonate group, a carboxylate group, a phosphate group, and a phosphonate group, wherein the hydrophilic portion contains The portion and the hydrophilic portion are separated by 0 to 10 alkylene oxide groups. The polishing composition may have a pH of about 2 to about 6.5.

Description

Polishing compositions and methods of using the same {POLISHING COMPOSITIONS AND METHODS OF USING SAME}

This application relates to U.S. Utility Patent Application Serial No. 16/356,669, filed March 18, 2019, which claims priority to U.S. Provisional Application Serial No. 62/781,648, filed December 19, 2018. Priority is claimed, the contents of which are incorporated herein by reference in their entirety.

The semiconductor industry continues to improve chip performance due to further miniaturization of devices through process and direct innovations. Chemical mechanical polishing/planarization (CMP) is a powerful technology because it increases chip density by enabling diverse and complex integration schemes at the transistor level.

Transistors are generally manufactured at the front end of line (FEOL) transistor manufacturing stage. A FEOL material stack typically includes a metal gate and a stack of multiple dielectric materials. Electrical isolation of the billions of active components in each integrated circuit is the goal of FEOL and can be achieved using the shallow trench isolation (STI) process. For illustrative purposes, a portion of the STI process is shown in Figure 1. As can be seen in Figure 1, before the STI CMP process, thermal silicon oxide and SiN are deposited on top of silicon (e.g., a silicon wafer) (1(a) in Figure 1) and then etched. Trench/device isolation and an “active” non-trench region (to form a transistor-containing region) (1(b) in FIG. 1) can be created. Afterwards, these trench/isolation regions are formed by adding silicon oxide (e.g., TEOS) within the trench so that the active non-trench region can be isolated by the silicon oxide within the trench (1(c) in Figure 1). For example, it can be filled by deposition using plasma-enhanced chemical vapor deposition (PECVD). Thereafter, the “overburden/extra” silicon oxide over the active non-trench region can be selectively removed while retaining the silicon oxide in the shallow trench (1(d) in Figure 1). Selective removal of silicon oxide is achieved by the shallow trench isolation (STI) chemical mechanical polishing/planarization (CMP) process, which results in high material removal rates of silicon oxide relative to silicon nitride (e.g., SiN). CMP slurry compositions (such as those described herein) with selectivity (MRR) preferably contain a high percentage of silicon oxide without substantially removing silicon nitride (stop-on layer). It is used to remove After the STI CMP step, silicon is exposed using etching to complete device isolation, and adjacent transistors formed in the active non-trench region are prevented from contacting each other, thereby preventing shorting of the electric circuit.

Dielectric films commonly used in STI include silicon nitride (e.g., SiN), silicon oxide (e.g., TEOS: tetra-ethyl ortho-silicate), poly- Silicon (poly-silicon, P-Si), silicon carbon nitride (e.g., SiCN), and low-k/ultra-low-k dielectric films (e.g. For example, SiCOH). With the introduction of high-k metal gate technology in 45 nm chip production and FinFET technology in 22 nm chip production, SiN, TEOS, SiCN, and P-Si films are starting to be used more in FEOL and in even more applications. did. Additionally, in back end of line (BEOL), the resistivity of existing barrier materials (Ta/TaN; Ti/TiN) is low for advanced 10 nm or less manufacturing nodes. Since they have not been shown to scale effectively, these barrier materials can be replaced by dielectrics such as SiN, TEOS, SiCN, and P-Si for various BEOL material stacks. Therefore, for both FEOL and BEOL, these dielectric films may be used as an etch stop layer, capping material, spacer material, additional liner, diffusion/passivation barrier, hard mask and/or Or it can be used as a stop layer.

In general, dielectric films are becoming increasingly used in advanced semiconductor manufacturing. From a CMP perspective, most of these integrations incorporating dielectrics are slurries that can remove SiN but not TEOS/P-Si, or slurries that can remove TEOS/p-Si but not SiN ( There is a need for a polishing composition (slurry) that can act/polish and/or stop on these films, such as slurries that cannot stop.

The present invention provides a stable material that can selectively polish a variety of materials (e.g., oxides such as silicon oxide) while achieving very low polishing/removal rates on silicon nitride and related silicon and nitrogen-based films such as SiCN (silicon carbon nitride). It concerns aqueous slurries. For example, the polishing composition can polish silicon oxide (e.g., SiO ₂ ) at a relatively high material removal rate (MRR) and suspend silicon nitride (e.g., SiN) or related films at very low rates. It can be polished. For example, silicon oxides that can be removed by the polishing compositions described herein include TEOS, thermal oxide (TOX) (e.g., caused by autoclave induced oxidation of bare silicon) ), silicon oxide formed by plasma enhanced PVD deposition (e.g. high density plasma or high aspect ratio plasma), silicon oxide formed by CVD deposition with post plasma surface cure, carbon doped silicon oxide (SiOC) and silicon oxide formed by liquid application of an oxide precursor followed by light or heat induced curing. In some examples, the target film to be removed with high MRR may be a metal or metal oxide or metal nitride rather than a silicon oxide dielectric. Common examples of metals, metal oxides, and metal nitrides include copper, cobalt, ruthenium, aluminum, titanium, tungsten, and tantalum for metals; For metal oxides, there are hafnium oxide, titanium oxide, aluminum oxide, zirconium oxide and tantalum oxide; and nitrides of ruthenium, aluminum, titanium, tungsten and tantalum. In such cases, the stop-on/low removal rate film may still be a silicon nitride film, so that the desired selectivity can be achieved using a polishing composition containing a nitride removal rate reducing agent from the present invention. You can.

More specifically, the present invention provides a polishing composition comprising an abrasive, a nitride removal rate reducer, an acid or base, water, and optionally a dishing reducer (e.g., an anionic dishing agent). It's about. The pH of the polishing composition described herein can range from 2 to 6.5, more specifically from 2 to 4.5. The compositions of the present invention may also be diluted (e.g., at the point of use) to form a polishing composition without any deterioration in performance. The present invention also discusses methods of polishing semiconductor substrates using the polishing compositions described above.

In one aspect, embodiments disclosed herein relate to a polishing composition comprising at least one abrasive, at least one nitride removal rate reducer, an acid or base, and water. The nitride removal rate reducing agent includes a hydrophobic portion containing a C ₁₂ to C ₄₀ hydrocarbon group; and a hydrophilic portion containing at least one group selected from the group consisting of a sulfinite group, a sulfate group, a sulfonate group, a carboxylate group, a phosphate group, and a phosphonate group, wherein the hydrophobic portion and The hydrophilic portion is separated by 0 to 10 alkylene oxide groups. The polishing composition has a pH of about 2 to about 6.5.

In another aspect, embodiments disclosed herein include at least one abrasive; at least one nitride removal rate reducing agent comprising a hydrophobic portion and a hydrophilic portion; acid or base; and water; wherein the polishing composition has a pH of about 2 to about 6.5; The polishing composition has a removal rate ratio for silicon oxide to a removal rate for silicon nitride of at least about 3:1 while polishing a patterned wafer comprising at least a silicon nitride pattern, wherein the silicon nitride pattern includes at least silicon oxide (and optionally metal or other materials such as dielectrics).

In another aspect, embodiments disclosed herein include at least one abrasive; at least one nitride removal rate reducing agent comprising a hydrophobic portion and a hydrophilic portion; acid or base; and water; wherein the polishing composition has a pH of about 2 to about 6.5; wherein polishing a patterned wafer comprising at least a silicon nitride pattern overlaid with at least silicon oxide using the polishing composition results in less than about 1000 angstroms of silicon oxide dishing, wherein the polishing produces a silicon nitride pattern on the patterned wafer. exposes.

In another aspect, embodiments disclosed herein include at least one abrasive; at least one nitride removal rate reducing agent comprising a hydrophobic portion and a hydrophilic portion; acid or base; and water; wherein the polishing composition has a pH of about 2 to about 6.5; Herein, when polishing a patterned wafer comprising at least a silicon nitride pattern overlaid with at least silicon oxide using the polishing composition, less than about 500 angstroms of silicon nitride erosion occurs, and the polishing produces a silicon nitride pattern on the patterned wafer. expose.

In another aspect, embodiments disclosed herein include applying a polishing composition described herein to a substrate having at least silicon nitride and at least silicon oxide on a surface of the substrate; and contacting the pad with the surface of the substrate and moving the pad relative to the substrate.

The synergistic use of an abrasive, a nitride RR reducer, and an optional dishing reducer in the same composition provides unique advantages not found in currently available slurries. Among others, these advantages include:

1. The compositions described herein can achieve very low silicon nitride (e.g., SiN) removal rates. Excellent silicon nitride protection can be achieved through wise selection and formulation/loading of silicon nitride removal rate reducers. Additionally, low silicon nitride removal rates can be achieved in blanket wafers (i.e. wafers containing only silicon nitride films) and patterned wafers (i.e. silicon nitride films and other films etched with a pattern, e.g. For wafers containing TEOS), it is observed on both sides.

2. Very low silicon nitride removal rates achieve minimal silicon nitride loss on the patterned wafer, resulting in very low silicon nitride post-polish corrosion.

3. The composition can achieve low silicon oxide dishing/step height. Dishing performance can be tuned by judicious selection and loading/concentration of dishing reducer.

4. The composition is compatible with various abrasives. Through particle modification, the zeta potential of the abrasive can be adjusted to further control the removal rate of the target film. Anionic, cationic and neutral abrasives can all form stable slurries with higher silicon oxide removal rates and relatively lower silicon nitride removal rates.

5. The composition can form a stable slurry with high purity colloidal silica as an abrasive. This results in a lower trace metal count and lower large particle count compared to wafers polished with the commonly used ceria abrasive (which typically produces a large amount of defects on the polished wafer). enables the creation of a slurry with a higher particle count, thereby reducing defects on the polished wafer. Additionally, the compositions described herein can overcome certain disadvantages of existing silica-based STI CMP compositions, such as high silicon nitride removal rates and low removal selectivity between silicon oxide and silicon nitride.

6. The composition produces low nitride removal rates over a variety of polishing conditions. For example, silicon nitride removal rates remain low for both hard polish pads (e.g., polyurethane-based pads) and soft polish pads (e.g., porous and low shore D hardness value pads). . Additionally, downforce and speed were observed to have no significant effect on silicon nitride removal rate, which is a good CMP property to have since the stop-on film behavior is non-Prestonian. The fact that the compositions of the present invention show little change in removal rate as a function of pressure and speed results in very good topography and high yields after patterned wafer polishing. In the language of the art, the compositions of the present invention lead to low values for silicon oxide dishing and stepping along with low values for silicon nitride corrosion/loss.

The polishing compositions and concentrates discussed herein provide maintenance of performance for current generation integrated circuit boards while contrasting with currently available modern slurries, while at the same time exhibiting distinct advantages for next generation substrates and integration schemes. The compositions of the present invention can successfully and efficiently remove a variety of metal and dielectric layers with much higher selectivity than those that remove silicon nitride layers. The composition can be used for shallow trench isolation (STI) processes, self-aligned contact processes, or other processes where very low silicon nitride material removal rates are required.

1 is a schematic diagram of the process flow in a shallow trench isolation (STI) process (including STI CMP) in semiconductor manufacturing. Figure 1(a) shows thermal silicon oxide (TOX) and silicon nitride (SiN) being deposited on top of silicon (Si) prior to shallow trench isolation (STI) chemical mechanical planarization (CMP). This is followed by etching to create the active area. Figure 1(b) shows a trench created leaving an active area of silicon covered by TOX and SiN. This is then filled with a dielectric - typically PE-CVD silicon oxide (SiO ₂ ). Figure 1(c) shows the active regions separated by a silica dielectric in a shallow trench. To complete STI, SiO ₂ is selectively removed from the active region while retaining SiO ₂ within the shallow trench. This can be done by STI CMP, which is the subject of this invention, in which SiO ₂ is removed at a high rate and SiN (stop layer) is not removed. Figure 1(d) shows that etching can be used to complete STI by removing SiN and exposing silicon. The active area of silicon will become the transistor once the gate, metal wiring and device fabrication are complete.
Figure 2 is a schematic diagram of an STI patterned wafer film stack before polishing.
Figure 3 is a wafer map showing overall defects after STI CMP using a silica-based polishing composition according to the present invention.
Figure 4 is a wafer map showing overall defects after STI CMP using a commercial ceria abrasive containing composition.

The present invention relates to a polishing composition and a method of polishing a semiconductor substrate using the same. In some embodiments, this invention relates to selectively polishing a silicon oxide surface over a silicon nitride surface. Selectively polishing silicon oxide on silicon nitride is an important process in semiconductor manufacturing and is commonly performed during shallow trench isolation (STI) processing. Typically, STI polishing compositions (slurry) are used to achieve the polishing performance (e.g., selectivity) required in the STI process because compositions using silica abrasives do not perform adequately (e.g., high silicon nitride removal rates). Use ceria abrasive. However, ceria abrasives are known to provide a high rate of defects and scratches when used in polishing compositions due to their “inorganic hard” nature. Additionally, ceria-based polishing compositions have a shorter shelf life (e.g., lower storage capacity, lower useful life, and shorter shelf life) and shorter pot life (e.g., lower shelf life) than silica-based polishing compositions. , activity after opening the container and/or in the storage tank or distribution loop), and ceria has greater price volatility than silica. Additionally, ceria contains rare earth metals and is more expensive than silica. The composition according to the invention allows the use of silica abrasives, which are softer than ceria abrasives, for STI slurries. Silica-containing polishing compositions can provide very good selectivity in material removal rate (MRR) of silicon oxide (e.g., TEOS) over silicon nitride (e.g., SiN), as well as STI processes using ceria abrasives. It also provides a polished wafer surface with comparatively very low defects. Accordingly, the polishing composition according to the present application can increase the device yield of wafers compared to a conventional polishing composition using a ceria abrasive.

The polishing composition described herein comprises (a) an abrasive, (b) a nitride removal rate reducer, (c) an acid or base, (d) water, and optionally (e) a dishing reducer (e.g., an anionic dishing reducer). ) may include. The polishing composition may have a pH of at least about 2 and up to about 6.5. The polishing compositions of the present invention can have high selectivity for polishing dielectrics or metals relative to polishing silicon nitride. The present invention also provides a method of using a polishing composition to polish a semiconductor substrate. In particular, the present invention provides a method for polishing dielectrics or metals with high selectivity for silicon nitride.

In one or more embodiments, the at least one (e.g., two or three) abrasives are selected from cationic abrasives, substantially neutral abrasives, and anionic abrasives. In one or more embodiments, the at least one abrasive is selected from the group consisting of alumina, silica, titania, ceria, zirconia, co-formed products thereof, coated abrasives, surface modified abrasives, and mixtures thereof. . In some embodiments, the at least one abrasive does not include ceria.

In one or more embodiments, the abrasive is a silica-based abrasive, such as selected from the group consisting of colloidal silica, fumed silica, and mixtures thereof. In one or more embodiments, the abrasive has a surface modified with organic groups and/or non-siliceous inorganic groups. For example, a cationic abrasive may include an end group of formula (I):

-O _m -X-(CH ₂ ) _n -Y (I),

Here, m is an integer from 1 to 3; n is an integer from 1 to 10; X is Al, Si, Ti or Zr; and Y is a cationic amino or thiol group. As another example, anionic abrasives may include terminal groups of formula (I):

-O _m -X-(CH ₂ ) _n -Y (I),

Here, m is an integer from 1 to 3; n is an integer from 1 to 10; X is Al, Si, Ti or Zr; And Y is an acidic group. In some embodiments, the at least one abrasive agent is added to the polishing composition described herein in an amount of at least about 0.05% by weight (e.g., at least about 0.1% by weight, at least about 0.5% by weight, at least about 1% by weight) based on the total weight of the composition. % by weight, at least about 2% by weight, at least about 3% by weight or at least about 5% by weight) to up to about 20% by weight (e.g., up to about 15% by weight, up to about 10% by weight, up to about 8% by weight, up to about 6% by weight, up to about 4% by weight, or up to about 2% by weight).

In one or more embodiments, the abrasives described herein have an abrasive thickness of at least about 1 nm (e.g., at least about 5 nm, at least about 10 nm, at least about 20 nm, at least about 40 nm, at least about 50 nm, at least about 60 nm). , at least about 80 nm or at least about 100 nm) to at most about 1000 nm (e.g., at most about 800 nm, at most about 600 nm, at most about 500 nm, at most about 400 nm, or at most about 200 nm). You can have As used herein, mean particle size (MPS) is determined by dynamic light scattering techniques.

In one or more embodiments, at least one (e.g., two or three separate) nitride removal rate reducing agents comprise a C ₁₂ to C ₄₀ hydrocarbon group (e.g., containing an alkyl group and/or alkenyl group). Containing a hydrophobic portion; and a hydrophilic portion containing at least one group selected from the group consisting of a sulfinite group, a sulfate group, a sulfonate group, a carboxylate group, a phosphate group, and a phosphonate group. In one or more embodiments, the hydrophobic moiety and the hydrophilic moiety have 0 to 10 (e.g., 1, 2, 3, 4, 5, 6, 7, 8, or 9) It is separated into alkylene oxide groups (e.g. -(CH ₂ ) _n O- groups, where n may be 1, 2, 3 or 4). In one or more embodiments, the nitride removal rate reducing agent has zero alkylene oxide groups separating the hydrophobic and hydrophilic portions. Without wishing to be bound by theory, it is believed that the presence of alkylene oxide groups in the nitride removal rate reducer may be undesirable in some embodiments because they can cause slurry stability issues and increase silicon nitride removal rates.

In one or more embodiments, the nitride removal rate reducer is present in the polishing compositions described herein in an amount of at least about 0.1 ppm (e.g., at least about 0.5 ppm, at least about 1 ppm, at least about 5 ppm, at least) based on the total weight of the composition. about 10 ppm, at least about 25 ppm, at least about 50 ppm, at least about 75 ppm, or at least about 100 ppm) to up to about 1000 ppm (e.g., up to about 900 ppm, up to about 800 ppm, up to about 700 ppm, up to about 600 ppm, up to about 500 ppm, or up to about 250 ppm).

In one or more embodiments, the nitride removal rate reducing agent has at least 12 carbon atoms (C ₁₂ ) (e.g., at least 14 carbon atoms (C ₁₄ ), at least 16 carbon atoms (C ₁₆ ), at least 18 carbon atoms. (C ₁₈ ), at least 20 carbon atoms (C ₂₀ ) or at least 22 carbon atoms (C ₂₂ )) and/or up to 40 carbon atoms (C ₄₀ ) (e.g. up to 38 carbon atoms (C ₃₈ ), up to 36 carbon atoms (C ₃₆ ), up to 34 carbon atoms (C ₃₄ ), up to 32 carbon atoms (C ₃₂ ), up to 30 carbon atoms (C ₃₀ ), up to 28 carbon atoms (C ₂₈ ), up to 26 carbon atoms (C ₂₆ ), up to 24 carbon atoms (C ₂₄ ) or up to 22 carbon atoms (C ₂₂ )). Hydrocarbon groups referred to herein refer to groups containing only carbon and hydrogen atoms, and include saturated groups (e.g. linear, branched or cyclic alkyl groups) and unsaturated groups (e.g. linear, branched or cyclic alkyl groups). It may include both a nyl group; a linear, branched, or cyclic alkynyl group; or an aromatic group (eg, phenyl or naphthyl). In one or more embodiments, the hydrophilic portion of the nitride removal rate reducer contains at least one group selected from a phosphate group and a phosphonate group. It should be noted that the term “phosphonate group” is meant to include phosphonic acid groups.

In one or more embodiments, the nitride removal rate reducing agent is naphthalenesulfonic acid-formalin condensate, lauryl phosphate, myristyl phosphate, stearyl phosphate, octadecylphosphonic acid, oleyl phosphate, behenyl phosphate, octadecyl sulfate. , raceryl phosphate, oleth-3-phosphate and oleth-10-phosphate.

In one or more embodiments, the polishing compositions described herein optionally further include at least one (e.g., two or three) dishing reducers (e.g., anionic dishing reducers). In one or more embodiments, the at least one dishing reducer comprises at least one group selected from the group consisting of hydroxy, sulfate, phosphonate, phosphate, sulfonate, amine, nitrate, nitrite, carboxylate and carbonate groups. It is a compound containing In one or more embodiments, the at least one dishing reducing agent is at least one selected from the group consisting of polysaccharides and substituted polysaccharides. In one or more embodiments, the at least one dishing reducing agent is at least one selected from the group consisting of carrageenan, xanthan gum, hydroxypropyl cellulose, methyl cellulose, ethyl cellulose, hydroxypropyl methyl cellulose, and carboxymethyl cellulose. In one or more embodiments, the at least one nitride removal rate reducer and the at least one dishing reducer are chemically different from each other.

In one or more embodiments, the dishing reducing agent is present in the polishing composition described herein in an amount of at least about 0.1 ppm (e.g., at least about 0.5 ppm, at least about 1 ppm, at least about 5 ppm, at least about 10 ppm, at least about 25 ppm, at least about 50 ppm, at least about 75 ppm, or at least about 100 ppm) to up to about 1000 ppm (e.g., up to about 900 ppm, up to about 800 ppm, up to about 700 ppm, up to about 600 ppm or up to about 500 ppm).

In one or more embodiments, the acid is formic acid, acetic acid, malonic acid, citric acid, propionic acid, malic acid, adipic acid, succinic acid, lactic acid, oxalic acid, hydroxyethylidene diphosphonic acid, 2-phosphono-1,2,4- Butane tricarboxylic acid, aminotrimethylene phosphonic acid, hexamethylenediamine tetra(methylenephosphonic acid), bis(hexamethylene)triamine phosphonic acid, amino acetic acid, peroxyacetic acid, potassium acetate, phenoxy acetic acid, glycine, bicine, diglycol. Acids, glyceric acid, trisine, alanine, histidine, valine, phenylalanine, proline, glutamine, aspartic acid, glutamic acid, arginine, lysine, tyrosine, benzoic acid, nitric acid, sulfuric acid, sulfurous acid, phosphoric acid, phosphonic acid, hydrochloric acid, periodic acid and mixtures thereof.

In one or more embodiments, the base is potassium hydroxide, sodium hydroxide, cesium hydroxide, ammonium hydroxide, triethanol amine, diethanol amine, monoethanol amine, tetrabutyl ammonium hydroxide, tetramethyl ammonium hydroxide, lithium hydroxide, imidazole, triazole, It is selected from the group consisting of aminotriazole, tetrazole, benzotriazole, tolyltriazole, pyrazole, isothiazole, and mixtures thereof.

In one or more embodiments, the acid or base is present in the polishing composition described herein in an amount of at least about 0.01% by weight (e.g., at least about 0.05% by weight, at least about 0.1% by weight, at least about 0.5% by weight) based on the total weight of the composition. % or at least about 1% by weight) to up to about 10% by weight (e.g., up to about 8% by weight, up to about 6% by weight, up to about 5% by weight, up to about 4% by weight, or up to about 2% by weight). It can exist in quantity. For example, the acid or base can be added in an amount sufficient to adjust the pH of the polishing composition to a desired value.

In one or more embodiments, water is present in the polishing compositions described herein (e.g., as a liquid medium or carrier) at least about 50% by weight (e.g., at least about 55% by weight, at least about 60% by weight, at least about 65% by weight, at least about 70% by weight or at least about 75% by weight) to up to about 99.9% by weight (e.g., up to about 99.5% by weight, up to about 99% by weight, up to about 97% by weight) %, up to about 95% by weight or up to about 90% by weight).

In one or more embodiments, the polishing compositions described herein have a polishing strength of at least about 2 (e.g., at least about 2.5, at least about 3, at least about 3.5, or at least about 4) and up to about 6.5 (e.g., at least about 6, may have a pH of up to about 5.5, up to about 5, or up to about 4.5). Without wishing to be bound by theory, it is believed that polishing compositions with pH exceeding 6.5 reduce silicon oxide/silicon nitride removal rate selectivity and may have stability issues.

In one or more embodiments, polishing described herein may be performed using salts (e.g., halide salts), polymers (e.g., cationic or anionic polymers, or polymers other than dishing reducers), surfactants (e.g. For example, other than nitride removal rate reducers), plasticizers, oxidizers, corrosion inhibitors (e.g., azole or non-azole corrosion inhibitors) and/or certain abrasives (e.g., ceria abrasives or non-ionic abrasives). It may not substantially contain the specific ingredients above. Halide salts that can be excluded from the polishing composition include alkali metal halides (e.g., sodium or potassium halides) or ammonium halides (e.g., ammonium chloride), including chloride, bromide, or iodine. It could be cargo. As used herein, a polishing composition is “substantially free from” components that are not intentionally added to the polishing composition. In some embodiments, the polishing compositions described herein contain up to about 1000 ppm (e.g., up to about 500 ppm, up to about 250 ppm, up to about 100 ppm, up to about 50 ppm, up to about 10 ppm, or up to about 1 ppm). In some embodiments, the described polishing compositions may not include one or more of the above ingredients at all.

In one or more embodiments, the polishing composition described herein has a polishing ratio of at least about 3:1, or at least about 4:1, or at least about 5:1, or at least about 10:1, or at least about 25:1, or at least about 50:1, or at least about 60:1, or at least about 75:1, or at least about 100:1, or at least about 150:1, or at least about 200:1, or at least about 250:1, or at least about 300 :1, or at least about 500:1, or at least about 750:1, or up to about 1000:1, or up to about 5000:1. ) has a ratio of removal rate to . In one or more embodiments, either a blanket wafer or a patterned wafer (i.e., a wafer comprising at least a silicon nitride pattern, in which the silicon nitride pattern is overlaid with at least silicon oxide (and optionally other materials such as metals and dielectrics)). When measuring removal rates for polishing, the rates described above can be applied.

In one or more embodiments, when a patterned wafer (which may include at least a silicon nitride pattern overlaid with silicon oxide) is polished with a polishing composition (e.g., the polishing may expose the silicon nitride pattern on the patterned wafer). (until), up to about 1000 Angstroms, up to about 500 Angstroms, or up to about 375 Angstroms, or up to about 250 Angstroms, or up to about 200 Angstroms, or up to about 100 Angstroms, or up to about 50 Angstroms, and/or at least about 0 Angstroms. Dishing of silicon oxide (e.g., TEOS) occurs. In one or more embodiments, when a patterned wafer (which may include at least a silicon nitride pattern overlaid with silicon oxide) is polished with a polishing composition (e.g., the polishing may expose the silicon nitride pattern on the patterned wafer). up to about 500 Angstroms, or up to about 400 Angstroms, or up to about 300 Angstroms, or up to about 250 Angstroms, up to about 200 Angstroms, up to about 100 Angstroms, or up to about 75 Angstroms, or up to about 65 Angstroms, or Up to about 50 angstroms of silicon nitride corrosion occurs, or up to about 32 angstroms and/or at least about 0 angstroms.

In one or more embodiments, the planarization efficiency (i.e., the change in silicon oxide step divided by the amount of silicon oxide removed during polishing and multiplied by 100) is determined when polishing a patterned wafer using a polishing composition according to the present invention. , at least about 14% (e.g., at least about 20%, at least about 30%, at least about 38%, at least about 40%, at least about 46%, at least about 50%, at least about 60%, at least about 70%, or at least about 74%) and up to about 100% (e.g., up to about 99.9%, up to about 99%, up to about 95%, up to about 90%, up to about 80%, up to about 70%, and up to about 60%) am. In one or more embodiments, the total defect count on a patterned wafer having a diameter of 12 inches (i.e., about 300 mm) is reduced by a polishing composition according to the present invention (e.g., a silica abrasive and a nitride removal rate reducer). When polishing a patterned wafer using a composition comprising), up to 175 (e.g., up to 170, up to 160, up to 150, up to 125, up to 100, up to 75, up to 50, maximum 25, maximum 10, or maximum 5). As described herein, defects counted are those that are at least about 90 nm in size.

In one or more embodiments, the invention provides a method comprising: applying a polishing composition according to the invention to a substrate (e.g., a wafer) having at least silicon nitride and silicon oxide on the surface of the substrate; and contacting the pad with the surface of the substrate and moving the pad relative to the substrate. In some embodiments, the substrate has at least a silicon nitride pattern overlaid with at least silicon oxide (e.g., silicon oxide in the presence of other materials such as silicon-based dielectrics (e.g., silicon carbide, etc.), metals, metal oxides, nitrides, etc.) When comprising, the method may remove at least a portion of the silicon oxide (eg, silicon oxide on the active, non-trench area) to expose silicon nitride. It should be noted that the terms “silicon nitride” and “silicon oxide” as used herein are expressly intended to include both undoped and doped versions of silicon nitride and/or silicon oxide. For example, in one or more embodiments, the silicon nitride and silicon oxide are independently selected from carbon, nitrogen (for silicon oxide), oxygen, hydrogen, or any other known dopant for silicon nitride or silicon oxide. It may be doped with at least one dopant. Some examples of silicon oxide film types include TEOS (tetra-ethyl orthosilicate), SiOC, SiOCN, SiOCH, SiOH, and SiON, to name a few. Some examples of silicon nitride film types include SiN (pure silicon nitride), SiCN, SiCNH, and SiNH, to name a few.

In some embodiments, methods of using the polishing compositions described herein may further include one or more additional steps to fabricate a semiconductor device from a substrate treated by the polishing composition. For example, the method may include one or more of the following steps prior to the polishing method described above: (1) depositing silicon oxide (e.g., thermal silicon oxide) on a substrate (e.g., a silicon wafer); depositing to form a silicon oxide layer, (2) depositing silicon nitride on the silicon oxide layer to form a silicon nitride layer, (3) etching the substrate to form trench and non-trench regions, and (4) ) Depositing silicon oxide on the etched substrate to fill the trench with silicon oxide. As another example, the method includes etching the substrate (e.g., to remove silicon nitride and silicon oxide) after the polishing method described above to expose silicon and/or silicon oxide or other heterogeneous films on the wafer substrate. It may include at least one additional step, such as:

Example

Examples are provided to further illustrate the capabilities of the polishing compositions and methods of the present invention. The provided examples are not intended to limit the scope of the invention and should not be construed as limiting. Any percentages listed are by weight (% by weight) unless otherwise specified. The nitride removal rate reducers described in the examples were obtained from various suppliers and, in some cases, may contain small amounts of similar compounds having carbon chain lengths smaller or larger than those specified in the table below. The carbon chain lengths specified in the table represent the main components of the nitride removal rate reducer.

Example 1: Demonstration of nitride stop

In this example, the polishing composition used in Samples 1A-1F comprised primarily 3 w/w% of a neutral colloidal silica abrasive, malonic acid as a pH adjuster, a nitride removal rate reducer (if present), and water as a liquid carrier. . The pH of the polishing composition was 2.3. 200 mm silicon oxide (TEOS) and silicon nitride (SiN) blanket wafers were polished using an Applied Materials Mirra CMP polisher on a Dow VP6000 pad with a down force of 2 psi and a flow rate of 175 mL/min.

TEOS and SiN removal rates vs. nitride removal rates to reduce surfactant species Sample Nitride removal rate reducer EO group TEOS RR
[Å/min] SiN RR
[Å/min] TEOS RR/
SiN RR control group doesn't exist 0 982 121 8 1A stearyl phosphate 0 816 2 408 1B n-octadecylphosphonate 0 868 One 868 1C oleyl phosphate 0 965 4 241 1D octadecyl sulfate 0 854 One 854 1E Oleth-3 Phosphate 3 790 10 79 1F Oleth-10 Phosphate 10 629 7 90

“EO” stands for ethylene oxide. “RR” stands for removal rate.

The results in Table 1 show that the control polishing composition (without nitride removal rate reducer) has a removal rate selectivity between silicon oxide and silicon nitride of 8, which is suitable for most applications requiring low silicon nitride ratios. Too low for this. However, with the addition of the nitride removal rate reducer, the silicon nitride removal rate of the polishing composition decreased to 1 Å/min, and the removal rate selectivity increased to 868.

Example 2: Demonstration of pH ranges and different polishing surface charges

In this example, the polishing composition used in Samples 2A-2I included 3 w/w% colloidal silica abrasive, an organic acid as a pH adjuster, n-octadecyl phosphonic acid, and water as a liquid carrier. n-Octadecyl phosphonic acid represents a class of nitride removal rate reducers described herein. Additionally, in this example, the colloidal silica charge was varied using neutral, cationic, and anionic silica as shown in Table 2. The pH of the polishing composition varied from about 2.25 to about 4.25. 200 mm silicon oxide (TEOS) and silicon nitride (SiN) blanket wafers were polished using an Applied Materials Mirra CMP polisher on a Dow VP6000 pad with a down force of 2 psi and a flow rate of 175 mL/min.

TEOS and SiN removal rates versus pH using three types of silica Sample abrasive n-octadecylphosphonic acid
relative concentration pH TEOS RR
[Å/min] SiN RR
[Å/min] TEOS RR/
SiN RR 2A neutral silica × 2.25 925 3 308 2B × 2.75 1186 2 593 2C × 3.50 921 3 307 2D × 4.25 587 9 65 2E cationic silica 2× 2.75 389 2 194 2F 2× 3.50 458 2 229 2G 2× 4.25 815 2 407 2H anionic silica 2× 2.25 47 27 2 2I 2× 3.25 44 13 3

As shown in Table 2, the nitride removal rate reducer was able to control the silicon nitride removal rate with neutral, cationic, and anionic silica in a pH range of about 2.25 to about 4.25. Regardless of the surface charge of the silica abrasive, the robust nitride ratio reduction of this system is surprising. For example, it is generally believed that cationic abrasives will have poor compatibility with anionic nitride removal rate reducers. In contrast, in this system the slurry remains stable and the nitride removal rate reducer remains active.

Typically, silicon nitride removal rates when using anionic abrasives are typically very high (~ 400 Å/min) and difficult to control. Importantly, the nitride removal rate reducing agent described herein was capable of significantly reducing silicon nitride removal rate. This type of system may be useful where low TEOS and silicon nitride removal rates are desired with high removal rates on films that have been well polished by anionic abrasives (e.g., silicon carbide films).

Example 3: Demonstrating the effect of chain length and head type of nitride removal rate reducer

In this example, the polishing composition used in Samples 3A-3L included 3 w/w% colloidal silica abrasive, malonic acid as a pH adjuster, a nitride removal rate reducer shown in Table 3, and water as a liquid carrier. The pH of the polishing composition was 2.25. Specifically, the nitride removal rate reducer used in Samples 3A-3L did not contain any alkylene oxide groups and included the head type and hydrophobicity described in Table 3. Additionally, the nitride removal rate reducer used in Samples 3I, 3J, and 3K included a mixture of surfactants in which lauryl/myristyl phosphate, stearyl phosphate, and raceryl phosphate were the major components, respectively.

200 mm silicon oxide (TEOS) and silicon nitride blanket wafers were polished using an Applied Materials Mirra CMP polisher on a Dow VP6000 pad with a down force of 2 psi and a flow rate of 175 mL/min.

Headgroup and hydrophobicity of TEOS and SiN removal versus nitride removal reducers Sample head type hydrophobic substance
(Hydrophobe) TEOS RR
[Å/min] SiN RR
[Å/min] TEOS RR/
SiN RR 3A phosphonate n-hexyl 953 157 6 3B phosphonate n-octyl 906 138 7 3C phosphonate n-decyl 895 146 6 3D phosphonate n-dodecyl 940 3 313 3E phosphonate n-tetradecyl 919 3 306 3F phosphonate n-hexadecyl 855 2 427 3G phosphonate n-octadecyl 811 2 405 3H Phosphate Hexyl (C6) 946 139 7 3I Phosphate Lauryl/Myristel
(C12/C14) 925 4 231 3J Phosphate Stearyl (C18) 835 3 279 3K Phosphate Behenyl (C22) 828 2 414 3L Phosphate Raceryl (C32) 898 23 39

As shown in Table 3, the size of the hydrophobic material in the nitride removal rate reducer plays an important role in determining the effect of reducing the rate of silicon nitride. Table 3 shows that among the drugs tested, chain lengths greater than 12 performed best for effective nitride arrest under the conditions tested. A carbon chain length greater than 12 in the nitride removal rate reducer (see samples 3D, 3E, 3F, 3G, 3I, 3J, 3K, and 3L in Table 3) ensures low SiN RR (typically <5 Å/min); For blanket films, it produces high selectivity ratios for TEOS:SiN RR (>250). Therefore, these polishing compositions are ideally suited for STI CMP processes where a high selectivity ratio of silicon oxide to silicon nitride is required.

Example 4: Demonstration of down force effect

In this example, the polishing composition used in Samples 4A-4C included 3 w/w% colloidal silica abrasive, an organic acid as a pH adjuster, n-octadecyl phosphonic acid, and water as a liquid carrier. The pH of the polishing composition was 2 to 6.5. 200 mm high-density plasma (HDP) silicon oxide, tetraethyl orthosilicate oxide (TEOS), using an Applied Materials Mirra CMP polisher on a Dow IC1010 pad with down forces of 2, 3, and 4 psi and a flow rate of 175 mL/min. , borophosphosilicate glass (BPSG) and silicon nitride coated wafers were polished.

HDP, TEOS, BPSG, and SiN Removal Rate vs. Downforce Sample pressure [psi] HDP RR [Å/min] TEOS RR[Å/min] BPSG RR[Å/min] SiN RR[Å/min] 4A 2 1147 1835 4971 4 4B 3 1506 2324 6675 2 4C 4 1752 3140 8173 One

As shown in Table 4, the silicon oxide films (HDP, TEOS, and BPSG) showed Prestonian behavior, but the silicon nitride removal rate showed non-Prestonian behavior and was well controlled regardless of the applied down force. In CMP language, the Prestonian behavior of the removal rate means that the polishing rate increases linearly with increasing polishing pressure and/or angular velocity/rpm (revolutions per minute) of the polisher. For high rate target films, Prestonian behavior is preferred (silicon oxide films herein). Non-Prestonian behavior means that the removal rate does not change significantly with changes in pressure or speed. Non-Prestonian behavior is somewhat desirable for stop on films (here SiN). As can be seen in Table 4, the removal rate of silicon oxide film increases linearly/Prestonianically with increasing down force (for example, TEOS RR has a down force of 2 to 3 to 4 psi). As it increases, it increases from 1835 to 2324 to 3140 Å/min). In contrast, SiN (static film) removal rates do not change significantly with increasing pressure (i.e., SiN RR varies from 4 to 2 to 1 Å/min as down force increases from 2 to 3 to 4 psi pressure). . This example also demonstrates that the polishing composition has similar behavior on films of the silicon oxide family as previously defined. For greater clarity, Table 4 depicts the silicon oxide films of three examples: HDP, TEOS, and BPSG. The polishing compositions of the present invention work very effectively to provide high material removal rates for all different types of silicon oxide films. Equivalent experiments using examples of different types of silicon nitride films (SiN, SiCN, etc.) showed slurry suspension behavior similar to that achieved on SiN films depicted in Table 4. For simplicity, only the SiN film ratio is shown in Table 4.

Example 5: Demonstration of pad effectiveness

In this example, the polishing composition used in Samples 5A-5C included 3 w/w% colloidal silica abrasive, an organic acid as a pH adjuster, a nitride removal rate reducer, and water as a liquid carrier. The pH of the polishing composition was 2 to 6.5. 200 mm tetraethyl orthosilicate oxide (TEOS) and silicon nitride (SiN) blanket wafers were polished using an Applied Materials Mirra CMP polisher on a Dow VP6000 or Fujibo H800 pad with a down force of 2 psi and a flow rate of 175 mL/min. .

TEOS and SiN removal rates vs. pad and nitride removal rate reducers Sample Pad Nitride removal rate reducer TEOS RR
[Å/min] SiN RR
[Å/min] TEOS RR/
SiN RR 5A Dow VP6000 stearyl phosphate 745 2 373 5B n-octadecyl phosphonate 756 One 756 5C oleyl phosphate 835 3 278 5A Fujibo H800 stearyl phosphate 951 8 119 5B n-octadecyl phosphonate 942 2 471 5C oleyl phosphate 970 61 16

As shown in Table 5, the nitride removal rate reducer affected silicon nitride protection. On Dow VP6000 pads with medium hardness, all samples (5A-5C) provided effective nitride protection as evidenced by low SiN removal rates and high TEOS/SiN removal selectivity. However, on the soft pad Fujibo H800 pad, only samples (5A, 5B) containing a nitride removal rate reducer with a long chain saturated hydrophobe provided effective nitride arrest. Therefore, this example demonstrates that the polishing compositions of the present invention work effectively on all types of polishing pads. Additionally, this example suggests that nitride protection tends to increase when the nitride removal rate reducer includes a longer hydrophobic material and is more saturated and/or more hydrophobic.

Example 6: Demonstration of Dishing Reduction

In this example, the polishing composition used in Samples 6A-6D consisted of 3 w/w% colloidal silica abrasive, an organic acid as a pH adjuster, n-octadecyl phosphonic acid, an anionic dishing reducing polymer (if present), and a liquid carrier. It included water. The pH of the polishing composition was 3.0. A 200 mm STI 1 silicon oxide/silicon nitride patterned wafer was polished using an Applied Materials Mirra CMP polisher on a Dow VP6000 pad with a down force of 2 psi and a flow rate of 175 mL/min. The wafer is endpointed by laser measurement after approximately 50 seconds and over-polished for 20 seconds.

Effect of anionic dishing reducing polymers on oxide dishing Sample anionic
Dish Reducing Polymer Dishing[Å]
5 ㎛ feature │ 50% dense Dishing[Å]
20 ㎛ features │ 50% dense 6A - 1194 1223 6B Carrageenan 96 180 6C xanthan gum 37 1068 6D Carboxymethylcellulose 172 900

As shown in Table 6, the addition of anionic dishing reducing polymers is effective in controlling oxide dishing, especially on small features. Sample 6A contained no dishing reducer, while samples 6B, 6C and 6D contained three different types of dishing reducer. As can be seen in Table 6, the silicon oxide dishing values for both 5 μm and 20 μm features are much smaller for Samples 6B, 6C and 6D compared to Sample 6A.

Example 7: Demonstration of Concentrate

In this example, the polishing composition used in Samples 7A-7C consisted of 3 w/w% neutral colloidal silica abrasive, organic acid and/or potassium hydroxide as pH adjuster, n-octadecyl phosphonic acid, and water as liquid carrier. Concentrates corresponding to the point of use formulation were included. The single pot solution contained all ingredients needed for polishing, while the two-part system contained all ingredients except organic acids. Mean particle size (MPS) is a reliable indicator of slurry stability. In unstable systems, particles aggregated over time, resulting in measurable MPS growth. MPS was measured on a Malvern instrument using dynamic light scattering techniques. The slurry was stored in an oven set at 60°C and measured every 7 days. According to the Arrhenius relationship for accelerated aging testing, a full test run of 21 days corresponds to approximately one year of room temperature aging. That is, if the slurry is kept at 60°C for 21 days and the MPS of silica does not increase significantly, it can be confirmed that the slurry has a real-time shelf life/shelf life of one year.

Accelerated aging of slurry concentrate (60℃) Sample category pH MPS [nm]
0 days MPS [nm]
7 days MPS [nm]
14 days MPS [nm]
21st 7A 2× single port 2.2 68 69 69 69 7B 2× single port 3.0 65 65 66 66 7C 5×2-part 9.5 72 73 73 74

As shown in Table 7, all formulations were stable throughout the entire test run. Stability in acidic regions for neutral silica is typically difficult to achieve. The single pot solution was stable at a pH of about 2 to about 6.5 at 2× concentration (data selection shown in Table 7) and other concentration levels (e.g., 3×, 4× and up to 10× concentration) (not shown). . In the two-part solution (7C), all components except the acid were much more concentrated and could remain stable (up to 10 times more stable). At the point of use, acid and water will be added to reconstitute the slurry prior to grinding on the grinding tool.

Example 8: Demonstration of patterned wafer removal rate selectivity

In this example, a 200 mm STI patterned wafer was polished using the polishing compositions used in Samples 8A, 8B, and 8C containing colloidal silica abrasives and nitride removal rate reducers shown in Tables 1, 3, and 5; Here the patterned silicon nitride is filled with high density silicon oxide as shown in Figure 2. The pattern in silicon nitride was arranged so that multiple arrays of line spaces, squares, checkers and meshes of various pitch and density were aligned across the wafer surface.

Polishing was done on an Applied Materials 200 mm Mirra polishing tool equipped with a DowDupont VP6000 pad, 3M A165 CIP1 conditioning disk, and 2 PSI wafer back pressure. Polishing time was varied based on motor torque and in-situ endpoint detection by red laser (650 nm) absorbance. During polishing, features in the two endpoint signals are observed, indicating that silicon oxide is removed from the active lines of the film stack, exposing the underlying silicon nitride. The patterned silicon oxide removal rate was calculated as the amount of material removed before exposure to silicon nitride divided by the polishing time. In contrast, patterned silicon nitride removal rate was calculated as the amount of material removed divided by the time after exposure to the polishing composition. Once polishing was complete, the wafer was cleaned through a 200 mm OnTrack post-CMP cleaning tool (Lam Research company) using Fujifilm Wako 8901 post-CMP cleaning chemistry. Film thickness measurements (e.g., to determine removal rates) of all wafers were taken using a KLA Tencor F5X ellipsometer.

Patterned wafer removal rate and selectivity in various line space arrays
Sample Array active line width
(㎛) array
pitch
(㎛) Array pattern density
(%) silicon oxide
removal rate
(Å/min) silicon nitride
removal rate
(Å/min)
selectivity 8A 5 50 10 1301 15 86.7 45 50 90 749 8 93.6 0.18 0.36 50 1330 7 190.0 0.50 1.00 50 1072 10 107.2 100 200 50 1920 18.0 106.6 8B 100 200 50 1710 31.8 53.8 8C 0.05 0.5 10 1043 238 4.3

From the data presented in Table 8, the high selectivity between silicon oxide and silicon nitride material removal rates previously observed on blanket wafers is also observed on patterned wafers containing both silicon oxide (top) and silicon nitride (bottom). As can be seen in Table 8, for Sample 8A, the silicon oxide to silicon nitride selectivity varied from 86 to 190 depending on pattern size, density and pitch. For sample 8B, the silicon oxide to silicon nitride selectivity is 54, while for sample 8C the selectivity is 4. Table 8 provides only representative examples of the performance of patterned wafers. In in-house experiments, selectivity ratios were observed to vary from 3 (considered satisfactory for patterned wafers) to about 1000 on patterned test wafers, depending on film complexity. Additionally, the selectivity of the polishing compositions containing the nitride removal rate reducers presented herein exceeds the selectivity of many legacy, industry standard, commercially available ceria-based STI polishing compositions presented in the prior art.

Example 9: Demonstration of Patterned Wafer Dishing and Erosion

In this example, patterned wafers similar to those used in Example 8 were measured on a Park Systems AFM tool to quantify silicon oxide dishing/stepping and silicon nitride corrosion/loss at the endpoints. The polishing compositions used in Samples 9A and 9B contained the nitride removal rate reducers shown in Tables 1, 3, and 5, and the stack was used to polish the patterned wafer shown in Figure 2. Silicon oxide dishing/stepping and silicon nitride corrosion/loss results are shown in Table 9. Planarization efficiency (PE), expressed as a percentage, is equal to the change in silicon oxide step divided by the amount of oxide removed during polishing and multiplied by one hundred (to convert to a percentage).

Patterned Wafer Dishing and Erosion Sample Array active line width (㎛) array pitch
(㎛) Array pattern density (%) oxide dishing
(Å) Silicon Nitride Corrosion (Å) Flattening efficiency
(%) 9A 5 50 10 40 74 46 45 50 90 157 10 38 0.18 0.36 50 48 70 14 0.50 1.00 50 35.6 60 17 100 200 50 245 30 74 9B 100 200 50 375 34 72

As can be seen in Table 9, silicon oxide dishing and silicon nitride corrosion are very small. Typically, for dishing and corrosion, very low values are desirable. The dishing and corrosion values indicate the smoothness of the polish after the final topography CMP of the patterned wafer. Therefore, low values (in Angstroms) of these values are desirable because they measure the separation in the peaks and valleys of the films of wafers containing different film types on patterned wafers. The lower the number, the smaller the gap between peaks and troughs, which means a flatter wafer surface, which is the overall goal of the CMP process step in semiconductor manufacturing. Ideally, a dishing and corrosion value of zero is desirable (implying a perfectly flat wafer surface). However, typically, these numbers are typically hundreds or thousands of Å on actual device/product patterned wafers. Accordingly, the data presented in Table 9 indicates that the polishing composition provides unique/excellent performance in providing very low dishing and corrosion values, and thus very good topography of the patterned wafer. As can be seen in Table 9, silicon oxide dishing can be as low as 35 Å and as high as 375 Å. With corrosion values as low as 30Å and as high as 74Å, SiN corrosion is much better than dishing. Additionally, these are representative examples, and these dishing and corrosion values were found in this experiment to be as high as 1000 Å and as low as 1 Å, which is still satisfactory for the purposes of the present invention and acceptable to semiconductor manufacturers.

Regarding planarization efficiency (PE), the higher the value, the better the result. Ideally, a PE of 100% is desirable because that value means that the entire wafer is planarized and flat, i.e., there are no steps between peaks and valleys. From the data in Table 9, it can be seen that PE varies from a low of 14% to 74%. Accordingly, these polishing compositions provide good planarization efficiency on patterned wafers.

Additionally, the data presented in Table 9 show that the polishing compositions presented herein exceed the oxide dishing, silicon nitride corrosion and planarization efficiencies of commercially available ceria-based STI polishing compositions.

Example 10: Demonstration of patterned wafer defects after polishing

In this example, defects in patterned wafers similar to those used in Examples 8 and 9 were treated with a commercially available ceria-based STI formulation and Composition 8A described in Example 8, which is a silica-based polishing composition containing a nitride removal rate reducer. ) was measured on a KLA-AIT XUV defect counter tool. A wafer map for a wafer polished using composition 8A is shown in Figure 3. A wafer map for a wafer polished using a commercially available ceria-based STI polishing composition is presented in Figure 4.

As evidenced by Figure 4, ceria-based formulations cause heavy arc scratching with many defects throughout the wafer (total number of defects exceeds 10,000) due to the relative hardness and size of the abrasive. It was easy. A closer examination of the defects shows that there were many macro and micro scratches accompanied by a lot of residue, many of which could be considered overall device killing defects. However, Figure 3 shows that polishing composition 8A containing high purity colloidal silica as an abrasive has significantly fewer scratches than the ceria-based composition ( Figure 4 ). In fact, silica polishing compositions exhibit virtually “defect-free” and clean surfaces. The total number of defects is approximately 175 for defects at least 90 nm in size. Defects are key to final device yield and production of salable chips. For the patterned wafer shown in Figure 4, assume there are 1000 dies (each square) per patterned wafer. Each defective die may turn out to be unsaleable if the defect is a device killer defect. Therefore, since ceria-based polishing compositions exhibit a large amount of defects, the yield of salable chips per wafer will be lower. In contrast, with the polishing compositions of the present invention, defects are significantly lower and the yield of salable chips per wafer is significantly higher.

Therefore, the low defects achieved by using the polishing compositions of the present invention are very attractive to semiconductor companies because it increases the upper and lower limits of their profits. From a technical standpoint, ceria abrasives are inorganic in nature (e.g., cerium lanthanide metal-based oxide), are generally hard, and are larger in size than silica abrasives, making them prone to providing a large number of scratches and defects on the wafer surface. In contrast, colloidal silica abrasives are organic in nature (they are non-metallic oxides of silicon and are in colloidal dispersion form) and are generally soft, so they do not cause scratches or defects during polishing.

Those skilled in the art have not been able to develop silica-based STI polishing compositions with satisfactory removal selectivity of silicon oxide over silicon nitride. As disclosed herein, the inventors have discovered a synergistic combination of silica and silicon nitride removal rate reducers that can provide the industry with silica-based STI polishing compositions. Additionally, the invention described herein can also be applied to abrasives other than silica (alumina, titania, etc.).

Although the invention has been described with respect to the embodiments described herein, it is understood that other modifications and variations are possible without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

As a polishing composition,
at least one abrasive;
As at least one nitride removal rate reducing agent
A hydrophobic portion containing a C ₁₂ to C ₄₀ hydrocarbon group; and
A hydrophilic portion containing at least one group selected from the group consisting of a sulfinite group, a sulfate group, a carboxylate group, a phosphate group, and a phosphonate group.
At least one nitride removal rate reducer comprising: wherein the hydrophobic portion and the hydrophilic portion are separated by 0 to 10 alkylene oxide groups;
acid or base; and
water
wherein the polishing composition is free of salts and oxidizing agents, and the polishing composition has a pH of 2 to 6.5. According to paragraph 1,
further comprising at least one dishing reducing agent;
wherein the at least one dishing reducing agent is a compound comprising at least one group selected from the group consisting of hydroxyl, sulfate, phosphonate, phosphate, sulfonate, amine, nitrate, nitrite, carboxylate and carbonate groups. A polishing composition. According to paragraph 2,
A polishing composition, wherein the at least one dishing reducing agent is at least one selected from the group consisting of polysaccharides and substituted polysaccharides. According to paragraph 2,
A polishing composition, wherein the at least one dishing reducing agent comprises carrageenan, xanthan gum, hydroxypropyl cellulose, methyl cellulose, ethyl cellulose, hydroxypropyl methyl cellulose, or carboxymethyl cellulose. According to paragraph 1,
A polishing composition wherein the hydrophobic portion includes a C ₁₂ to C ₃₂ hydrocarbon group. According to paragraph 1,
A polishing composition wherein the hydrophobic portion includes a C ₁₆ to C ₂₂ hydrocarbon group. According to paragraph 1,
A polishing composition wherein the hydrophilic portion includes a phosphate group or a phosphonate group. According to paragraph 1,
At least one nitride removal rate reducing agent is lauryl phosphate, myristyl phosphate, stearyl phosphate, octadecylphosphonic acid, oleyl phosphate, behenyl phosphate, octadecyl sulfate, raceryl phosphate, oleth-3-phosphate and oleth. A polishing composition selected from the group consisting of -10-phosphate. According to paragraph 1,
A polishing composition, wherein the at least one nitride removal rate reducer has zero alkylene oxide groups separating the hydrophobic portion and the hydrophilic portion. According to paragraph 2,
A polishing composition wherein the at least one nitride removal rate reducer and the at least one dishing reducer are chemically different from each other. According to paragraph 1,
The polishing composition has a removal rate for silicon oxide to removal rate for silicon nitride of at least 3:1. According to paragraph 1,
The polishing composition has a removal rate for silicon oxide to removal rate for silicon nitride of at least 100:1. According to paragraph 1,
A polishing composition, wherein the at least one abrasive is selected from the group consisting of cationic abrasives, neutral abrasives, and anionic abrasives. According to paragraph 1,
The at least one abrasive is selected from the group consisting of alumina, silica, titania, ceria, zirconia, co-formed products thereof, coated abrasives, surface modified abrasives, and mixtures thereof. Composition. According to paragraph 1,
Acids include formic acid, acetic acid, malonic acid, citric acid, propionic acid, malic acid, adipic acid, succinic acid, lactic acid, oxalic acid, hydroxyethylidene diphosphonic acid, 2-phosphono-1,2,4-butane tricarboxylic acid, aminotri Methylene phosphonic acid, hexamethylenediamine tetra(methylenephosphonic acid), bis(hexamethylene)triamine phosphonic acid, amino acetic acid, peroxyacetic acid, phenoxy acetic acid, glycine, bicine, diglycolic acid, glyceric acid, tricine, selected from the group consisting of alanine, histidine, valine, phenylalanine, proline, glutamine, aspartic acid, glutamic acid, arginine, lysine, tyrosine, benzoic acid, nitric acid, sulfuric acid, sulfurous acid, phosphoric acid, phosphonic acid, hydrochloric acid, periodic acid, and mixtures thereof. A polishing composition that is. According to paragraph 1,
Bases include potassium hydroxide, sodium hydroxide, cesium hydroxide, ammonium hydroxide, triethanol amine, diethanol amine, monoethanol amine, tetrabutyl ammonium hydroxide, tetramethyl ammonium hydroxide, lithium hydroxide, imidazole, triazole, aminotriazole, and tetrazole. A polishing composition selected from the group consisting of benzotriazole, tolyltriazole, pyrazole, isothiazole, and mixtures thereof. According to paragraph 1,
The polishing composition is a polishing composition that does not include an anionic polymer. Applying the polishing composition of any one of claims 1 to 17 to a substrate having at least silicon nitride and at least silicon oxide on the surface of the substrate; and
contacting a pad with the surface of the substrate and moving the pad relative to the substrate
A polishing method comprising: According to clause 18,
A polishing method wherein at least one of silicon nitride and silicon oxide is doped with at least one dopant selected from the group consisting of carbon, nitrogen, oxygen, and hydrogen. According to clause 18,
A polishing method further comprising forming a semiconductor device from the substrate.