KR102634315B1 - Memory device comprising parity error detect circuit - Google Patents

Abstract

A memory device according to an embodiment of the present invention may include a parity check unit and a mask unit. The parity check unit may perform a parity check of sampled data according to a strobe signal. The mask unit may generate a parity error signal that is output for a time determined according to the burst length of the data, based on the parity check result. The strobe signal may not include a post-amble.

Description

Memory device including a parity error detection circuit {MEMORY DEVICE COMPRISING PARITY ERROR DETECT CIRCUIT}

The present invention relates to a semiconductor memory device, and more specifically, to a memory device including a parity error detection circuit.

Memory devices are the voice of information devices such as computers, mobile phones, smartphones, PDAs, digital cameras, camcorders, voice recorders, MP3 players, personal digital assistants (PDAs), handheld computers (Handheld PCs), game consoles, fax machines, scanners, printers, etc. and is widely used as a video data storage medium. As memory devices are used as storage media for various devices, consumer demands for memory devices are diversifying.

Accordingly, technologies for increasing capacity, speed, and low power consumption of memory devices are being actively researched. As the processing data of devices supporting various functions increases, the capacity and speed of memory devices are accelerating. However, as the operation of memory devices becomes faster, the probability of errors occurring in the reception of signals may increase. In other words, a problem may occur in which stable operation of the memory device is not guaranteed.

To ensure stable operation of a memory device operating at high speed, the memory device can exchange data with the memory controller using a parity method. The memory device uses a parity error detection circuit to check whether data transmitted by the parity method has been received without distortion.

An object of the present invention is to provide a memory device including a parity error detection circuit that performs a parity check in a memory system that uses a data strobe signal that does not include a post-amble.

A memory device according to an embodiment of the present invention may include a parity check unit and a mask unit. The parity check unit may perform a parity check of sampled data according to a strobe signal. The mask unit may generate a parity error signal that is output for a time determined according to the burst length of the data, based on the parity check result. The strobe signal may not include a post-amble.

A memory device according to another embodiment of the present invention may include an aligner and a parity error detection circuit. The aligner may sample data by means of a data strobe signal that does not include a post-amble. The parity error detection circuit performs a parity check on the data sampled by the aligner, and based on the parity check result, a parity error signal is output for a time determined according to the burst length of the data and indicates whether a parity error has occurred in the data. can be created.

A memory device including a parity error detection circuit according to an embodiment of the present invention can output a parity output signal for a time determined according to the burst length even when receiving a data strobe signal without a post-amble.

1 is a block diagram showing a memory system according to an embodiment of the present invention.
FIG. 2 is a block diagram showing the memory device shown in FIG. 1.
FIG. 3 is a block diagram showing the first DQS aligner shown in FIG. 2.
FIG. 4 is a block diagram showing the first clock aligner shown in FIG. 2.
FIG. 5 is a block diagram showing the parity error detection unit shown in FIG. 2.
FIG. 6 is a circuit diagram showing the parity check unit shown in FIG. 5.
FIG. 7 is a block diagram showing the second parity latency unit shown in FIG. 5.
FIG. 8 is a block diagram showing the mask signal generator shown in FIG. 5.
FIG. 9 is a block diagram showing the error signal generator shown in FIG. 5.
FIG. 10 is a timing diagram showing signals generated according to the operation of the memory system of FIG. 1.
FIG. 11 is a timing diagram showing signals generated when the parity error detection unit shown in FIG. 1 operates.
Figure 12 is a block diagram showing a user system to which a memory device according to an embodiment of the present invention is applied.

Below, embodiments of the present invention will be described clearly and in detail so that those skilled in the art can easily practice the present invention.

1 is a block diagram showing a memory system according to an embodiment of the present invention. Referring to FIG. 1 , the memory system 1000 may include a host 1100 and a memory device 1200. For example, the memory system 1000 may be a single system including both the host 1100 and the memory device 1200. Alternatively, the host 1100 and the memory device 1200 of the memory system 1000 may be implemented as separate devices.

The host 1100 may be a processor circuit or system including a general-purpose processor or an application processor. Alternatively, the host 1100 may be a computing device (e.g., personal computer, peripheral device, digital camera, PDA (Personal Digital Assistant), PMP (Portable Media Player), smartphone) including one or more processors. , tablet, wearable device, etc.).

The host 1100 may perform training on the memory device 1200 during booting or under specific circumstances. Through training, the host 1100 can increase the reliability of data or signal exchange with the memory device 1200. For example, the host 1100 can determine optimal clock timing or reference level by writing or reading training data (TD) from the memory device 1200 under various conditions.

The memory device 1200 may store data provided from the host 1100 or data to be provided to the host 1100. The memory device 1200 may be implemented as any storage medium including volatile memory or non-volatile memory. For example, if the memory device 1200 includes volatile memory, the memory device 1200 may include dynamic random access memory (DRAM), static random access memory (SRAM), thyristor RAM (TRAM), and zero memory (Z-RAM). capacitor RAM), TTRAM (Twin transistor RAM), MRAM, etc. The present invention can be applied to any storage medium including volatile memory. For example, the memory device 1200 includes Unbuffered Dual In-Line Memory Module (UDIMM), Registered DIMM (RDIMM), Load Reduced DIMM (LRDIMM), Non Volatile DIMM (NVDIMM), High Bandwidth Memory (HBM), etc. can do.

For example, if the memory device 1200 includes non-volatile memory, the memory device 1200 may include electrically erasable programmable read-only memory (EPROM), flash memory, magnetic RAM (MRAM), and spin transfer torque. MRAM (Spin-Transfer Torque MRAM), Conductive bridging RAM (CBRAM), FeRAM (Ferroelectric RAM), PRAM (Phase change RAM), Resistive RAM (RRAM), Nanotube RRAM (Nanotube RRAM), Polymer RAM RAM: PoRAM), Nano Floating Gate Memory (NFGM), holographic memory, Molecular Electronics Memory Device, or Insulator Resistance Change Memory. can do. One or more bits can be stored in a unit cell of nonvolatile memory. The above-described examples are not intended to limit the invention.

Hereinafter, for convenience of explanation, it is assumed that the memory device 1200 includes a single memory device. However, as described above, it will be easily understood that the present invention can be applied to various storage devices.

The memory device 1200 may communicate with the host 1100. For example, the memory device 1200 may include Universal Serial Bus (USB), Small Computer System Interface (SCSI), PCIe, Mobile PCIe (M-PCIe), Advanced Technology Attachment (ATA), Parallel ATA (PATA), and SATA ( Various wired communication protocols such as Serial ATA), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), TCP/IP (Transmission Control Protocol/Internet Protocol), and LTE (Long Term Evolution), WiMax, GSM (Global System for Mobile communication), CDMA (Code Division Multiple Access), HSPA (High Speed Packet Access), Bluetooth, NFC (Near Field Communication), WiFi, RFID (Radio Frequency Identification), etc. It may communicate with the host 1100 based on one or more of various wireless communication protocols. The above-described examples are not intended to limit the invention.

The memory device 1200 receives command/address signals (CMD/ADDR) synchronized to the clock signal (CLK) from the host 1100 and reads data (DATA) synchronized to the data strobe signal (DQS). You can perform operations and write operations. The read and write operations of the memory device 1200 are as follows.

In the case of a read operation, the memory device 1200 receives an active command and row address information along with a clock signal CLK from the host 1100. After the reference time, the memory device 1200 receives a column address from the host 1100. Thereafter, after a reference time, the memory device 1200 provides the requested data (DATA) to the host 1100.

In the case of a write operation, first, the memory device 1200 receives a clock signal CLK, an active command, and a row address from the host 1100. After the reference time, the memory device 1200 receives a write command and column address information from the host 1100. Afterwards, the memory device 1200 receives data to be written (DATA) from the host 1100. The memory device 1200 writes the provided data (DATA) into the memory area at a designated address.

The memory device 1200 of the present invention can receive data (DATA) and a data strobe signal (DQS) from the host 1100. The data strobe signal (DQS) is a type of clock signal. Data (DATA) received by the memory device 1200 is synchronized by the data strobe signal (DQS). The data strobe signal DQS is provided from the memory device 1200 to the host 1100 when the memory device 1200 provides data (DATA) to the host 1100. Additionally, the data strobe signal DQS is provided from the host 1100 to the memory device 1200 when the host 1100 provides data (DATA) to the memory device 1200.

The data strobe signal (DQS) may include a pre-amble and a post-amble. The preamble and postamble are generated by the memory device 1200 before or after the memory device 1200 receives data (DATA) from the host 1100, such as the input buffer (not shown) and the clock. This is a signal for synchronizing a buffer (not shown), etc. to the data strobe signal (DQS). It is assumed that the data strobe signal (DQS) of the present invention does not include a post amble and includes only a preamble.

The memory device 1200 of the present invention may include a parity error detection unit 1220. The parity error detection unit 1220 performs a parity check of data (DATA) to be written to the memory device 1200 through a write operation. Hereinafter, data to be written to the memory device 1200 through a write operation is referred to as write data DATA. Write data (DATA) may be synchronized within the memory device 1200 by the data strobe signal (DQS) provided from the host 1100.

Additionally, the parity error detection unit 1220 may receive a parity signal (PRT) from the host 1100 and perform an additional parity check of the write data (DATA) using the parity signal (PRT). Additional parity check of data (DATA) using the parity signal (PRT) will be described with reference to FIG. 9. The parity error detection unit 1220 provides the parity check result to the host 1100 as a parity output signal (P_out).

The parity error detection unit 1220 performs a parity check on the sorted data (DATA) based on the data strobe signal (DQS) and outputs the parity check result as a parity output signal (P_out). When the data strobe signal (DQS) includes a post amble, the parity error detection unit 1220 operates in synchronization with the data strobe signal (DQS), so it includes the parity check result for the last bit of the data (DATA). The parity output signal (P_out) can be reset by the post amble of the data strobe signal (DQS).

However, as described above, the data strobe signal (DQS) of the present invention does not include a post amble. Accordingly, the parity output signal P_out including the parity check result for the last bit of the data DATA is not reset by the data strobe signal DQS. Accordingly, the parity output signal P_out including the parity check result of the last bit of the data DATA is maintained without being reset. That is, the parity output signal (P_out) is not reset at the edge of the data strobe signal (DQS). For this reason, the memory device 1200 may not comply with the communication protocol of the memory system 1000 defined by the Joint Electron Device Engineering Council (JEDEC) standard document.

The parity error detection unit 1220 of the present invention adjusts the time at which the parity output signal (P_out) is output according to the burst length (BL) based on the data strobe signal (DQS) that does not include the post amble. Here, the burst length refers to the number of bits of data (DATA) continuously exchanged between the memory device 1200 and the host 1100.

In the above, the configuration of the parity error detection unit 1220, which adjusts the output time of the parity output signal (P_out) according to the burst length, and the memory device 1200 including the same was briefly described. Through this configuration, the memory device 1200 can output the parity output signal (P_out) for a time determined by the burst length (BL) even when receiving a data strobe signal (DQS) without a post amble. As a result, the memory device 1200 can comply with the communication protocol of the memory system 1000 defined by the Joint Electron Device Engineering Council (JEDEC) standard document.

FIG. 2 is a block diagram showing the memory device shown in FIG. 1. The block diagram of FIG. 2 will be explained with reference to FIG. 1. Referring to FIG. 2, the memory device 1200 includes a data input driver 1210, first and second DQS aligners 1211 and 1213, first and second clock aligners 1212 and 1214, and parity error detection. It may include a unit 1220, a mode register 1230, a clock buffer 1240, a memory cell array 1250, a command/address latch 1260, a command decoder 1270, and a data output driver 1280. .

When the memory device 1200 performs a write command, the data input driver 1210 receives write data (DATA) and data strobe signal (DQS) from the host 1100 through the DQS pad (DQS_p) and the DQ pad (DQ_p). receives. As described above, the data strobe signal (DQS) does not include a post amble. The data input driver 1210 outputs the received data (DATA) and the data strobe signal (DQS) as internal data (DQ_i) and internal DQS signal (DQS_i), respectively.

The first DQS aligner 1211 aligns the internal data (DQ_i) with the internal DQS signal (DQS_i). That is, the first DQS aligner 1211 samples the internal data (DQ_i) from the rising and falling edges of the internal DQS signal (DQS_i), and stores the internal data (DQ_i) in each internal DQS. It is output separately into odd data and even data sorted by the signal (DQS_i). Odd data refers to odd-numbered data of the internal data (DQ_i), and even data refers to even-numbered data of the internal data (DQ_i).

The first clock aligner 1212 samples and aligns odd data and even data of the internal data (DQ_i) using the internal clock signal (CLK_i). The first clock aligner 1212 outputs data sorted by the internal clock signal CLK_i as odd sort data D_od and even sort data D_ev, respectively. Odd alignment data (D_od) and even alignment data (D_ev) are provided to the parity error detection unit 1220 and the sense amplifier 1251, respectively.

The second DQS aligner 1213 samples and sorts the parity signal (PRT) provided from the host 1100 through the parity pad (PRT_p) by the internal DQS signal (DQS_i). Although not shown, the memory device 1200 may further include an input driver for receiving a parity signal (PRT). The second clock aligner 1214 sorts the parity signal (PRT) sampled by the internal DQS signal (DQS_i) by sampling it by the internal clock signal (CLK_i). The second clock aligner 1214 outputs the parity signal PRT aligned by the internal clock signal CLK_i as the internal parity signal PRTi.

The parity error detection unit 1220 performs a parity check of odd-aligned data (D_od) and even-aligned data (D_ev) using the internal clock signal (CLK_i). The parity error detection unit 1220 receives the internal parity signal (PRTi) and performs an additional parity check of the data (DATA) using the parity signal (PRT).

Additionally, the parity error detection unit 1220 receives a pulse write command (PWY), parity latency (PL), and burst length (BL) from the command decoder 1270 and the mode register 1230, respectively. The parity error detection unit 1220 generates a mask signal (not shown) that adjusts the time at which the parity output signal (P_out) is output based on the pulse write command (PWY) and the burst length (BL) of data. The output time of the parity output signal (P_out) is adjusted by a mask signal (not shown). According to the parity latency (PL), the parity error detection unit 1220 adjusts the output timing of the parity output signal (P_out).

The mode register 1230 may store information provided from the command decoder 1270. For example, the mode register 1230 may receive parity latency (PL) and burst length (BL) from the command decoder 1270 and store them. Additionally, the mode register 1230 may provide stored parity latency (PL) and burst length (BL) to the parity error detection unit 1220.

The clock buffer 1240 receives the clock signal (CLK) and clock bar signal (CLKb) from the host 1100 through the clock pad (CLK_p) and clock bar pad (CLKb_p). For example, clock buffer 1240 may be configured as a differential input buffer. The clock buffer 1240 generates an internal clock signal (CLK_i) based on the provided clock signal (CLK) and clock bar signal (CLKb). The generated internal clock signal CLK_i is provided to the parity error detection unit 1220, the first and second clock aligners 1212 and 1214, and the command decoder 1270.

The memory cell array 1250 may provide stored data to the data output driver 1280 through the sense amplifier 1251. Alternatively, odd sort data (D_od) and even sort data (D_ev) may be stored in the memory cell array 1250 by the sense amplifier 1251. The address of the memory cell in which data provided from the host 1100 will be stored may be provided to the memory cell array 1250 through the command/address latch 1260, row decoder 1252, and column decoder 1253.

The command/address latch 1260 receives a command (CMD) and an address (ADDR) from the host 1100. The command/address latch 1260 provides the received command (CMD) to the command decoder 1270. Additionally, the command/address latch 1260 provides the address of the received memory cell to the row decoder 1252 and the column decoder 1253. The command decoder 1270 receives various commands through the command/address latch 1260. The command decoder 1270 provides decoded commands with components such as a parity error detection unit 1220, a mode register 1230, a row decoder 1252, and a column decoder 1253.

The data output driver 1280 may output data stored in the memory cell array 1250 to the host 1100 through the DQ pad (DQ_p). At this time, the row decoder 1252 and the column decoder 1253 may provide the address of the memory cell in which data to be output is stored to the memory cell array 1250. Additionally, when the data output driver 1280 outputs data to the host 1100, the data output driver 1280 may provide a data strobe signal (DQS) to the host 1100 through the DQS pad (DQS_p). .

FIG. 3 is a block diagram showing the first DQS aligner shown in FIG. 2. The block diagram of FIG. 3 will be explained with reference to FIG. 2. Referring to FIG. 3, the first DQS aligner 1211 may include first and second flip-flops FF1 and FF2.

The first flip-flop (FF1) receives internal data (DQ_i) as a data input (D) and a data strobe signal (DQS) as a clock input (CK). The first flip-flop (FF1) samples the internal data (DQ_i) by the rising edge of the data strobe signal (DQS). Odd data of the internal data (DQ_i) is sampled by the rising edge of the data strobe signal (DQS), and the first flip-flop (FF1) outputs the sampled data as odd data (DD_od).

The second flip-flop (FF2) receives internal data (DQ_i) as a data input (D) and the bar signal of the data strobe signal (DQS) as a clock input (CK). The second flip-flop (FF2) samples the internal data (DQ_i) by the falling edge of the data strobe signal (DQS). The even-numbered data of the internal data (DQ_i) is sampled by the falling edge of the data strobe signal (DQS), and the second flip-flop (FF2) outputs the sampled data as even data (DD_ev).

As a result, the first and second flip-flops FF1 and FF2 sample and align the internal data DQ_i by the rising edge and falling edge of the data strobe signal DQS, respectively. The first and second flip-flops FF1 and FF2 separate the sampled data into odd data DD_od and even data DD_ev and output them.

The second DQS aligner 1213 shown in FIG. 2 may include the same configuration as the first DQS aligner 1211. The second DQS aligner 1213 receives the parity signal (PRT) from the host 1100 through the parity pad (PRT_p), and receives the parity signal (PRT) by the rising edge and falling edge of the data strobe signal (DQS). You can sample. The second DQS aligner 1213 outputs the sampled signals as an odd parity signal (not shown) and an even parity signal (not shown), respectively.

FIG. 4 is a block diagram showing the first clock aligner shown in FIG. 2. The block diagram of FIG. 4 will be explained with reference to FIG. 2. Referring to FIG. 4, the first clock aligner 1212 may include first and second flip-flops FF1 and FF2.

The first flip-flop (FF1) receives odd data (DD_od) as a data input (D) and receives the internal clock signal (CLK_i) as a clock input (CK). The first flip-flop (FF1) samples odd data (DD_od) by the rising edge of the internal clock signal (CLK_i). The first flip-flop (FF1) outputs the sampled data as odd-aligned data (D_od).

The second flip-flop (FF2) receives even data (DD_ev) as a data input (D) and receives the internal clock signal (CLK_i) as a clock input (CK). The second flip-flop (FF2) samples the even data (DD_ev) by the rising edge of the internal clock signal (CLK_i). The second flip-flop (FF2) outputs the sampled data as even sort data (D_ev).

As a result, the first and second flip-flops (FF1, FF2) sample and align the odd data (DD_od) and even data (DD_ev) by the rising edge of the internal clock signal (CLK_i), respectively, and sample the sampled data, respectively. It is output separately into odd sort data (D_od) and even sort data (D_ev).

The second clock aligner 1214 shown in FIG. 2 may include the same configuration as the first clock aligner 1212. The second clock aligner 1214 receives an odd parity signal (not shown) and an even parity signal (not shown) from the second DQS aligner 1213, and odd parity is determined by the rising edge of the internal clock signal (CLK_i). A signal (not shown) and an even parity signal (not shown) can be sampled. The second clock aligner 1214 outputs the sampled signals as an odd-aligned parity signal (not shown) and an even-aligned parity signal (not shown), respectively.

FIG. 5 is a block diagram showing the parity error detection unit shown in FIG. 2. The block diagram of FIG. 5 will be explained with reference to FIGS. 1 and 2. Referring to FIG. 5 , the parity error detection unit 1220 may include a parity check unit 1221, first and second parity latency units 1222 and 1223, and a mask unit 1224.

The parity check unit 1221 receives odd-aligned data (D_od[N:0]) and even-aligned data (D_ev[N:0]) from the first clock aligner 1212. Here, the number of bits 'N' varies depending on the data bus size of the memory device 1200. That is, if the memory device 1200 includes a data bus composed of M DQ pads (DQ_p), the number of bits may be 'M'.

Hereinafter, it is assumed that the number of bits 'N' is 3. Accordingly, the memory device 1200 includes first to fourth DQ pads (DQ_p[3:0]). Odd alignment data (D_od[0]) and even alignment data (D_ev[0]) are data provided through the first DQ pad (DQ_p[0]) by the internal DQS signal (DQS_i) and internal clock signal (CLK_i). This is sorted data. Similarly, odd-aligned data (D_od[3:1]) and even-aligned data (D_ev[3:1]) are data provided through the second to fourth DQ pads (DQ_p[3:1]), respectively, and are internal DQS This is data sorted by the signal (DQS_i) and the internal clock signal (CLK_i).

The parity check unit 1221 performs a parity check of provided data. The parity check unit 1221 outputs parity check results as a first odd error signal (ERR1_od) and a first even error signal (ERR1_ev), respectively. The configuration of the parity check unit 1221 will be described with reference to FIG. 6.

The first parity latency unit 1222 receives an internal clock signal (CLK_i) from the clock buffer 1240. The first parity latency unit 1222 delays the first odd error signal (ERR1_od) and the first even error signal (ERR1_ev) according to the parity latency (PL) by a multiple of the period of the internal clock signal (CLK_i). The first parity latency unit 1222 outputs delayed signals as a delay odd error signal (ERRd_od) and a delay even error signal (ERRd_ev).

The second parity latency unit 1223 receives an internal clock signal (CLK_i) from the clock buffer 1240. Additionally, the second parity latency unit 1223 receives the decoded pulse write command (PWY) from the command decoder 1270. The second parity latency unit 1223 delays the pulse write command (PWY) by a multiple of the period of the internal clock signal (CLK_i) according to the parity latency (PL). The second parity latency unit 1223 outputs the delayed command as a delayed pulse write command (PWYd). The configuration of the second parity latency unit 1223 will be described with reference to FIG. 7.

The mask unit 1224 is provided with a delay odd error signal (ERRd_od), a delay even error signal (ERRd_ev), a delay pulse write command (PWYd), an internal clock signal (CLK_i), and a burst length (BL). The mask unit 1224 generates a parity output signal (P_out) that indicates whether a parity error has occurred in data based on the provided signals. The mask unit 1224 outputs the parity output signal (P_out) for a time determined according to the burst length (BL).

The mask unit 1224 may include a mask signal generator 1225 and an error signal generator 1226. The mask signal generator 1225 is provided with a delay pulse write command (PWYd) and a burst length (BL). The mask signal generator 1225 generates a mask signal (MASK) signal by adjusting the pulse of the delay pulse write command (PWYd) according to the burst length (BL). The configuration of the mask signal generator 1225 will be described with reference to FIG. 8.

The error signal generator 1226 receives a delay odd error signal (ERRd_od), a delay even error signal (ERRd_ev), and a mask signal (MASK). Additionally, the error signal generator 1226 may further receive an internal parity signal (PRTi). The internal parity signal (PRTi) may include an odd parity signal (PRTi_od) and an even parity signal (PRTi_ev). The error signal generator 1226 can analyze whether the parity error of the write data (DATA) is a parity error of odd data or even data based on the odd parity signal (PRTi_od) and the even parity signal (PRTi_ev). .

The error signal generator 1226 performs a parity check of the write data (DATA) based on the delay odd error signal (ERRd_od), the delay even error signal (ERRd_ev), and the internal parity signal (PRTi). The error signal generator 1226 outputs the parity check result as a parity output signal (P_out) during the activation period of the mask signal (MASK). The configuration of the error signal generator 1226 will be described with reference to FIG. 9.

FIG. 6 is a circuit diagram showing the parity check unit shown in FIG. 5. The circuit diagram of FIG. 6 will be explained with reference to FIGS. 1 and 5. Referring to 6, the parity check unit 1221 may include first to sixth exclusive OR logic (XOR1 to XOR6).

As described above, the parity check unit 1221 checks the parity of odd-sorted data (D_od[3:0]) and even-sorted data (D_ev[3:0]). For example, the memory device 1200 may receive data from the host 1100 in an even parity method. In this case, odd-aligned data (D_od[3:0]) will be provided from the host 1100 so that each bit at the same position (hereinafter referred to as a bit string) includes an even number of logical '1's. Additionally, even sort data (D_ev[3:0]) will be provided from the host 1100 so that each bit string includes an even number of logical '1's.

For example, when data is provided from the host 1100 in the even parity method, '1011' is provided to the even sort data (D_ev[0]), and '1001' is provided to the even sort data (D_ev[1]). '1100' may be provided in the even sort data (D_ev[2]), and '1111' may be provided in the even sort data (D_ev[3]). In this case, the data of the first bit string of the even sort data (D_ev[3:0]) is '1111'. Since the number of logic '1's is even, parity error does not occur. Additionally, the data of the second and third bit strings of the even sort data (D_ev[3:0]) are '0011' and '1001', respectively. Since the number of logic '1's in the data of the second and third bit strings is even, parity errors do not occur. However, the data of the fourth bit string of the even sort data (D_ev[3:0]) is '1101', and since the number of logic '1's in the data in the bit string is odd, a parity error occurs.

The above example describes a case where the memory device 1200 receives data (DATA) from the host 1100 in an even parity method. The memory device 1200 may receive data (DATA) from the host 1100 using an odd parity method. In this case, the odd sort data (D_od[3:0]) and the even sort data (D_ev[3:0]) will be provided so that the bit strings at the same position each include an odd number of logic '1'. Hereinafter, it is assumed that the memory system 1000 of FIG. 1 exchanges data (DATA) using an even parity method.

The first, second, and fifth exclusive OR logic (XOR1, XOR2, XOR5) checks the parity of odd aligned data (D_od[3:0]). The checked parity result is output as a first odd error signal (ERR1_od). The third, fourth and sixth exclusive OR logic (XOR3, XOR4, XOR6) checks the parity of the even sort data (D_ev[3:0]). The checked parity result is output as a first even error signal (ERR1_ev).

For example, if there is a parity error in the odd sort data (D_od[3:0]), logic '1' will be output as the first odd error signal (ERR1_od). Additionally, if there is a parity error in the even sort data (D_ev[3:0]), the first even error signal (ERR1_ev) will output logic '1'.

On the other hand, when a parity error occurs in odd-sorted data (D_od[3:0]) or even-sorted data (D_ev[3:0]) in the memory system 1000 using the odd parity method, the first odd error The signal ERR1_od or the first even error signal ERR1_ev will output a value opposite to that when using the even parity method (eg, 0).

FIG. 7 is a block diagram showing the second parity latency unit shown in FIG. 5. The block diagram of FIG. 7 will be explained with reference to FIG. 5 . Referring to FIG. 7, the second parity latency unit 1223 may include first to fourth multiplexers (MUX1 to MUX4) and first to fourth flip-flops (FF1 to FF4).

The first multiplexer (MUX1) selects and outputs either the pulse write command (PWY) or the output signal of the second flip-flop (FF2) according to the parity latency (PL[0]). The output signal of the first multiplexer (MUX1) is provided to the first flip-flop (FF1). The first flip-flop (FF1) samples the output signal of the first multiplexer (MUX1) using the internal clock signal (CLK_i), and outputs the sampled signal as a signal with a length of one cycle of the internal clock signal (CLK_i). . The output signal is provided to the mask signal generator 1225 as a delay pulse write command (PWYd).

Similarly, the second multiplexer (MUX2) selects and outputs either the pulse write command (PWY) or the output signal of the third flip-flop (FF3) according to the parity latency (PL[1]), and the third multiplexer (MUX3) selects and outputs either the pulse write command (PWY) or the output signal of the third flip-flop (FF3) according to the parity latency (PL[2]). The output signal of the second multiplexer (MUX2) is provided to the second flip-flop (FF2), and the output signal of the third multiplexer (MUX3) is provided to the third flip-flop (FF3). The second and third flip-flops (FF2, FF3) sample the output signals of the second and third multiplexers (MUX2, MUX3) by the internal clock signal (CLK_i), respectively, and output the sampled signals to the internal clock signal (CLK_i). ) is output as a signal with the length of one cycle.

The fourth multiplexer (MUX4) selects either the pulse write command (PWY) or the ground voltage (GND) according to the parity latency (PL[3]) and provides it to the fourth flip-flop (FF4). The fourth flip-flop (FF4) samples the output signal of the fourth multiplexer (MUX4) using the internal clock signal (CLK_i), and outputs the sampled signal as a signal with a length of one cycle of the internal clock signal (CLK_i). .

When the parity latency (PL[0]) is activated, the pulse write command (PWY) is sent to the first flip-flop (FF1) through the first multiplexer (MUX1) without going through the second to fourth flip-flops (FF2 to FF4). ) is provided. Therefore, the pulse write command (PWY) is not delayed, but is sampled by the first rising edge of the internal clock signal (CLK_i). The sampled pulse write command (PWY) is converted into a pulse signal with a length of one cycle of the internal clock signal (CLK_i) without delay, and the converted signal is output as a delayed pulse write command (PWYd).

When the parity latency (PL[1]) is activated, the pulse write command (PWY) is selected by the second multiplexer (MUX2) and provided to the second flip-flop (FF2). The pulse write command (PWY) is converted into a pulse signal with a length of one cycle of the internal clock signal (CLK_i) by the second flip-flop (FF2) and output. The output signal passes through the first multiplexer (MUX1) and the first flip-flop (FF1) and is output as a delay pulse write command (PWYd). That is, since the pulse write command (PWY) passes through the first and second flip-flops (FF1 and FF2), it is delayed by one cycle of the internal clock signal (CLK_i) and is output as a delayed pulse write command (PWYd).

Similarly, when the parity latency (PL[2]) is activated, the pulse write command (PWY) is selected by the third multiplexer (MUX3) and provided to the third flip-flop (FF3). The pulse signal sampled by the third flip-flop (FF3) passes through the second multiplexer (MUX2), the second flip-flop (FF2), the first multiplexer (MUX1), and the first flip-flop (FF1) to produce a delay pulse It is output as a write command (PWYd). Therefore, since the pulse write command (PWY) passes through the first to third flip-flops (FF1 to FF3), it is delayed by two cycles of the internal clock signal (CLK_i) and is output as a delayed pulse write command (PWYd).

Additionally, when the parity latency (PL[3]) is activated, the pulse write command (PWY) is selected by the fourth multiplexer (MUX4) and provided to the fourth flip-flop (FF4). The pulse signal sampled by the fourth flip-flop (FF4) is connected to the third multiplexer (MUX3), the third flip-flop (FF3), the second multiplexer (MUX2), the second flip-flop (FF2), and the first multiplexer. (MUX1), and is output as a delay pulse write command (PWYd) through the first flip-flop (FF1). Accordingly, since the pulse write command (PWY) passes through the first to fourth flip-flops (FF1 to FF4), it is delayed by three cycles of the internal clock signal (CLK_i) and is output as a delayed pulse write command (PWYd).

The configuration of the first parity latency unit 1222 is similar to that of the second parity latency unit 1223. The first parity latency unit 1222 receives a first odd error signal (ERR1_od) and a first even error signal (ERR1_ev), respectively, and generates the first odd error signal (ERR1_od) and the first even error signal (ERR1_od) according to the parity latency (PL). The error signal (ERR1_ev) is delayed by a multiple of the period of the internal clock signal (CLK_i). The first parity latency unit 1222 outputs delayed signals as a delay odd error signal (ERRd_od) and a delay even error signal (ERRd_ev). Those skilled in the art will understand that the first parity latency unit 1222 can be configured with reference to the configuration of the second parity latency unit 1223 shown in FIG. 7.

FIG. 8 is a block diagram showing the mask signal generator shown in FIG. 5. The block diagram of FIG. 8 will be explained with reference to FIGS. 2 and 5. Referring to FIG. 8, the mask signal generator 1225 may include a divider 1225_1 and a multiplexer (MUX).

The divider 1225_1 is provided with a delay pulse write command (PWYd) and an internal clock signal (CLK_i). Based on the internal clock signal (CLK_i) and the delayed pulse write command (PWYd), the divider (1225_1) converts the delayed pulse write command (PWYd) into a pulse signal with a length twice the period of the internal clock signal (CLK_i). do.

Depending on the burst length (BL), the multiplexer (MUX) generates a delay pulse write command (PWYd) with one cycle of pulses of the internal clock signal (CLK_i) and a delay pulse write command (PWYd) of the internal clock signal (CLK_i) converted by the divider (1225_1). One of the signals having two pulse periods is output as a mask signal (MASK). For example, when the burst length (BL) is '2', the multiplexer (MUX) outputs a delay pulse write command (PWYd) with one cycle of pulses of the internal clock signal (CLK_i) as a mask signal (MASK). can do. In addition, when the burst length (BL) is '4', the multiplexer (MUX) outputs a signal with two pulse cycles of the internal clock signal (CLK_i) converted by the divider (1225_1) as the mask signal (MASK). can do.

FIG. 9 is a block diagram showing the error signal generator shown in FIG. 5. The block diagram of FIG. 9 will be explained with reference to FIGS. 2 and 5. Referring to FIG. 9, the error signal generator 1226 may include first and second exclusive OR logic (XOR1, XOR2), negation OR logic (NOR), and negation OR logic (ND).

The first exclusive OR logic (XOR1) performs the exclusive OR of the delay odd error signal (ERRd_od) and the odd parity signal (PRTi_od). The second exclusive OR logic (XOR2) performs exclusive OR of the delay even error signal (ERRd_ev) and the even parity signal (PRTi_ev). As described above, the error signal generator 1226 determines whether the parity error of the write data (DATA) is a parity error of odd data or a parity error of even data based on the odd parity signal (PRTi_od) and the even parity signal (PRTi_ev). Cognition can be analyzed.

For example, when a parity error occurs in odd data of the write data (DATA), the delay odd error signal (ERRd_od) may output logic '1'. The parity output signal (P_out) outputs logic '1' due to the delay odd error signal (ERRd_od) of logic '1'. However, the host 1100 cannot know which signal among the delay odd error signal (ERRd_od) and the delay even error signal (ERRd_ev) output logic '1'. In this case, the host 1100 may sequentially provide an odd parity signal (PRTi_od) of logic '1' and an even parity signal (PRTi_ev) of logic '1' to the error signal generator 1226. The parity output signal (P_out) will output logic '0' due to the odd parity signal (PRTi_od) of logic '1'. As a result, the host 1100 can determine that a parity error has occurred in odd data of the write data (DATA).

The negation OR logic (NOR) performs the negation OR of the first and second exclusive OR logic (XOR1, XOR2). That is, the negative OR logic (NOR) outputs the result of logical sum of the delayed odd error signal (ERRd_od), odd parity signal (PRTi_od), delayed even error signal (ERRd_ev), and even parity signal (PRTi_ev). As a result, the negative OR logic (NOR) outputs a parity check result obtained by additionally performing a parity check result of the write data (DATA) using a parity signal (PRT).

The negation logic (ND) performs a negation logical product of the mask signal (MASK) and the output signal of the negation logic (NOR). As a result, the negative logical sum logic (ND) outputs an inverted signal of the output signal of the negative logical sum logic (NOR) as long as the pulse width of the mask signal (MASK). As described above, the pulse width of the mask signal MASK is adjusted according to the burst length BL. Accordingly, the negative logical sum logic (ND) outputs an inverted signal of the output signal of the negative logical sum logic (NOR) for a period of time determined according to the burst length (BL).

FIG. 10 is a timing diagram showing signals generated according to the operation of the memory system of FIG. 1. The timing diagram of FIG. 10 will be explained with reference to FIGS. 1, 2, and 5. Referring to FIG. 10, the parity output signal (P_out) generated based on the data strobe signal (DQS) that does not include the post amble maintains its output even after the second data (D2) is provided. Here, it is assumed that the burst length (BL) is '2' and the parity latency (PL) is '0'.

At time t1, the memory device 1200 receives a preamble signal of a write command (WR), clock signals (CLK, CLKb), and a data strobe signal (DQS) from the host 1100. The command/address latch 1260 samples the write command (WR) by the clock signals (CLK, CLKb). The memory device 1200 performs a write operation using a sampled write command (WR). Since the write latency (CWL) is '1', the first data (D1) is provided at time t2, which is one cycle of the clock signal CLK from time t1.

Then, at time t2, the memory device 1200 receives first data D1 from the host 1100. The first DQS aligner 1211 of the memory device 1200 samples the first data D1 based on the rising edge of the data strobe signal DQS and outputs it as odd data DD_od. Next, at time t3, the memory device 1200 receives second data D2 from the host 1100. The first DQS aligner 1211 of the memory device 1200 samples the second data D2 based on the falling edge of the data strobe signal DQS and outputs it as even data DD_ev.

At time t4, the first clock aligner 1212 of the memory device 1200 samples odd data DD_od and even data DD_ev at the rising edge of the clock signal CLK, and odd-aligns the sampled data, respectively. Output as data (D_od) and even sort data (D_ev). The parity error detection unit 1220 generates a parity output signal (P_out) based on the provided odd-aligned data (D_od) and even-aligned data (D_ev). In the example of FIG. 10, when the mask unit 1224 of the parity error detection unit does not operate, the parity output signal P_out maintains and outputs the same parity error result even after time t5.

FIG. 11 is a timing diagram showing signals generated when the parity error detection unit shown in FIG. 1 operates. The timing diagram of FIG. 11 will be explained with reference to FIGS. 1, 2, 5, and 10. In the example of FIG. 11 , like the example of FIG. 10 , the memory device 1200 receives a data strobe signal (DQS) that does not include a post amble from the host 1100. In the example of FIG. 11, it is assumed that the burst length (BL) is '2' and the parity latency (PL) is '0'.

Compared to the example of FIG. 10, in the example of FIG. 11, the parity output signal (P_out) generated based on the data strobe signal (DQS) not including the post amble is the mask signal (MASK) generated by the mask unit 1224. ) is output for one cycle of the clock signal (CLK). Since the operation of the memory device 1200 from time t1 to t3 is the same as described in FIG. 10, description thereof is omitted.

At time t4, the parity error detection unit 1220 generates a delay error signal (ERRd) based on the odd-aligned data (D_od) and the even-aligned data (D_ev). As described above, the delay error signal ERRd may include a delay odd error signal ERRd_od and a delay even error signal ERRd_ev. The pulse write command (PWY) is provided to the second parity latency unit 1223, is delayed by the second parity latency unit 1223, and is output as a delayed pulse write command (PWYd). However, in the example of FIG. 11, the parity latency (PL) is '0', so the delayed pulse write command (PWYd) is output at time t4 without delay.

Next, the mask signal generator 1225 generates a mask signal (MASK) based on the delay pulse write command (PWYd) and the burst length (BL). In the example of FIG. 11, since the burst length BL is '2', the mask signal MASK includes a pulse having the length of one cycle of the clock signal CLK. Next, the error signal generator 1226 generates a parity output signal (P_out) based on the delay odd error signal (ERRd_od) and the delay even error signal (ERRd_ev), and outputs parity for the time of the pulse width of the mask signal (MASK). Outputs a signal (P_out). After time t5, the error signal generator 1226 does not output the parity output signal (P_out).

As a result, the memory device 1200 of the present invention can output the parity output signal (P_out) for a time determined by the burst length (BL) even when receiving a data strobe signal (DQS) without a post amble.

Figure 12 is a block diagram showing a user system to which a memory device according to an embodiment of the present invention is applied. Referring to FIG. 12 , the user system 10000 may include an application processor 11000, a memory module 12000, a network module 13000, a storage module 14000, and a user interface 15000.

The application processor 11000 may drive components included in the user system 10000 and an operating system (OS). For example, the application processor 11000 may include controllers, interfaces, graphics engines, etc. that control components included in the user system 10000. The application processor 11000 may be provided as a system-on-chip (SoC).

The memory module 12000 may operate as the main memory, operation memory, buffer memory, or cache memory of the user system 10000. The memory module 12000 is a volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDARM, LPDDR3 SDRAM, LPDDR3 SDRAM, HBM, etc., or a non-volatile random access memory such as PRAM, ReRAM, MRAM, FRAM, etc. may include.

For example, the controller and memory module 12000 included in the application processor 11000 may be configured with the memory system 1000 of the present invention described with reference to FIGS. 1 to 11 . That is, the controller included in the application processor 11000 may correspond to the host 1100 shown in FIG. 1, and the memory module 12000 may include the memory device 1200 shown in FIG. 1. That is, the memory module 12000 includes the parity error detection unit 1220 shown in FIG. 1 and can perform a parity error detection operation by the parity error detection unit 1220.

The network module 13000 can communicate with external devices. For example, the network module 13000 supports Code Division Multiple Access (CDMA), Global System for Mobile communication (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), and Long Term Evolution (LTE). ), Wimax, WLAN, UWB, Bluetooth, WI-DI, etc. can be supported. Here, the network module 13000 may be included in the application processor 11000.

The storage module 14000 can store data. For example, the storage module 14000 may store data received from the application processor 11000. Alternatively, the storage module 14000 may transmit data stored in the storage module 14000 to the application processor 11000. For example, the storage module 14000 is a non-volatile semiconductor memory device such as PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), NAND flash, NOR flash, and three-dimensional NAND flash. It can be implemented.

The user interface 15000 may include interfaces for inputting data or commands into the application processor 11000 or outputting data to an external device. For example, the user interface 15000 may include user input interfaces such as a keyboard, keypad, button, touch panel, touch screen, touch pad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, piezoelectric element, etc. there is. The user interface 15000 may include user output interfaces such as a Liquid Crystal Display (LCD), Organic Light Emitting Diode (OLED) display, Active Matrix OLED (AMOLED) display, LED, speaker, motor, etc.

The contents described above are specific examples for carrying out the present invention. The present invention will include not only the embodiments described above, but also embodiments that can be simply changed or easily modified. In addition, the present invention will also include technologies that can be easily modified and implemented in the future using the embodiments described above.

Claims (12)

a parity check unit that performs a parity check of sampled data according to a data strobe signal; and
A mask unit that generates a parity error signal output for a time determined according to the burst length of the data based on the parity check result,
The data strobe signal does not include a post-amble,
The mask unit is,
A mask signal generator that generates a mask signal that is activated for a time determined according to the burst length of the data, based on a write command, and
A memory device comprising an error signal generator that receives a parity signal from a host and generates the parity error signal based on the parity signal, the mask signal, and the parity check result. According to claim 1,
The parity check unit includes exclusive OR logic,
The exclusive OR logic is a memory device that processes even data and odd data of the data through an exclusive OR operation. According to claim 1,
The memory device further includes a parity latency unit that delays the write command and provides the delay to the mask signal generator according to the parity latency. According to claim 1,
A memory device in which the mask unit receives a parity signal from a host and generates the parity error signal by additionally performing a plurality of operations on the parity signal and the parity check result. According to claim 4,
The memory device further includes a parity latency unit that delays the parity check result and provides the delayed parity check result to the mask unit according to the parity latency. According to claim 4,
The mask unit is configured to receive the parity check result delayed according to the parity signal and parity latency. According to claim 4,
The mask unit is,
a mask signal generator that generates a mask signal including a pulse signal that is activated for a time determined according to the burst length of the data, based on a write command; And includes an error signal generator,
The error signal generator,
A first exclusive OR logic (XOR) for processing the parity check result of odd data among the data and the odd parity signal of the parity signal through an exclusive OR operation among the plurality of operations, and
A second exclusive OR logic (XOR) for processing the parity check result of the even data among the data and the even parity signal of the parity signal through an exclusive OR operation among the plurality of operations, and
The error signal generator generates the parity error signal based on the mask signal and output signals of each of the first and second exclusive OR logic (XOR) logic.
a parity check unit configured to perform a first parity check of data sampled by a data strobe signal not including a post amble;
a mask signal generator that generates a mask signal that is activated for a time determined according to the burst length of the data, based on a write command; and
Includes an error signal generator,
The error signal generator,
A memory device that receives a parity signal from a host, performs a plurality of operations on the parity signal and the first parity check result, and generates a parity error signal based on the mask signal and the plurality of operation results. According to claim 8,
sample the data by the data strobe signal, and
A memory device further comprising an aligner configured to provide the sampled data to a parity check unit. According to claim 8,
a first parity latency unit that delays the write command and provides the delay to the mask signal generator according to parity latency; and
The memory device further includes a second parity latency unit that delays the first parity check result and provides it to the error signal generator according to the parity latency. According to claim 10,
The error signal generator,
A memory device configured to receive a first parity check result delayed by a second parity latency unit according to parity latency. According to claim 10,
The error signal generator,
A first exclusive OR logic (XOR) for processing the first parity check result of odd data among the data and the odd parity signal of the parity signal through an exclusive OR operation among the plurality of operations, and
A second exclusive OR logic (XOR) for processing the first parity check result of the even data among the data and the even parity signal of the parity signal through an exclusive OR operation among the plurality of operations, and
The error signal generator generates the parity error signal based on the mask signal and output signals of each of the first and second exclusive OR logic (XOR) logic.

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