KR102598361B1 - Organic light emitting display device and method for driving it - Google Patents

Abstract

Embodiments of the present invention relate to an organic light emitting display device and driving method. According to an embodiment of the present invention, an organic light emitting display device and a driving method that can solve uneven brightness by improving the charging rate for subpixels of a display panel can be provided. According to an embodiment of the present invention, an organic light emitting display device and driving method capable of compensating the charging rate by instantaneously increasing the current flowing through the organic light emitting diode by applying a reference voltage in the opposite direction to a section where the charging rate of the data voltage decreases. can be provided.

Description

Organic light emitting display device and driving method {ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD FOR DRIVING IT}

Embodiments of the present invention relate to an organic light emitting display device and driving method.

As the information society develops, various demands for display devices that display images are increasing, and various types such as Liquid Crystal Display (LCD), Organic Light Emitting Diode Display (OLED Display), etc. of display devices are being used.

Among these display devices, organic light emitting display devices use organic light emitting diodes that emit light on their own, so they have advantages in terms of fast response speed, contrast ratio, luminous efficiency, luminance, and viewing angle.

This organic light emitting display device includes organic light emitting diodes arranged in each of a plurality of sub-pixels (SP) arranged on a display panel, and each organic light emitting diode emits light by controlling the current flowing through the organic light emitting diodes. An image can be displayed by controlling the luminance expressed by the subpixels (SP).

These subpixels (SP) are driven by the scan signal (SCAN) applied through the gate line (GL), and the data voltage (Vdata) applied through the data line (DL) in accordance with the timing when the scan signal (SCAN) is applied. ) to display the image by expressing the gradation according to the gradation. At this time, the data line DL to which the data voltage Vdata is applied may be arranged one by one for each column of the subpixel SP.

Meanwhile, recently, one data line (DL) has been installed between two adjacent subpixels (SP) to reduce the number of source driver integrated circuits (SDIC) that drive the data line (DL). A DRD (Double Rate Driving) structure is being applied in which one data line (DL) drives two subpixels (SP) arranged on both sides.

In the DRD-type subpixel (SP) structure, a data voltage (Vdata) for driving two subpixels (SP) is applied through the data line (DL) during one horizontal period. At this time, a display device driven by the DRD method may apply a data voltage (Vdata) whose polarity is reversed to each row of the subpixel (SP) in order to minimize flicker and reduce power consumption. Accordingly, the data voltage Vdata applied to the subpixel SP may be a signal having the same polarity as the data voltage Vdata applied to the previous subpixel SP, or a signal with the polarity reversed may be applied. It may be possible.

For example, in the case of an organic light emitting display device with a resolution of 2,160 ) will be placed at each point where subpixels (SP) intersect.

At this time, the organic light emitting display device may output a scan signal (SCAN) sequentially from the first gate line (GL1) to the 2,160th gate line (GL2,160) for the 2,160 gate lines (GL), and may output a scan signal (SCAN) sequentially for the 2,160 gate lines (GL). For the pixel SP, the scan signal SCAN is sequentially output from the first gate line GL1 to the fourth gate line GL4, and then, after a certain period of time, from the fifth gate line GL5 to the eighth gate As in the case of sequentially outputting the scan signal SCAN up to the line GL8, the scan signal SCAN may be sequentially output for each of the four gate lines GL.

In the above case, the case of sequentially outputting the scan signal (SCAN) from the first gate line (GL1) to the 2,160th gate line (GL2,160) as one group is called 2,160 phase driving, The case of sequentially outputting the scan signal SCAN from the first gate line GL1 to the fourth gate line GL4 as one group is called 4-phase driving. Of course, the group of gate lines (GL) that sequentially output the scan signal (SCAN) can be changed to 4, 8, or 256 groups. In other words, the case where the scan signal (SCAN) is sequentially output for each of the N gate lines (GL) can be referred to as N-phase driving.

This N-phase driving can be changed in various ways depending on the size or performance of the display device, the frame time for displaying an image on the display panel varies, and taking into account afterimages that appear in the user's field of view or deterioration of circuit elements, etc.

At this time, in N-phase driving in which the subpixels (SP) that continuously output the scan signal (SCAN) are divided into N subpixel groups and driven, the subpixels (SP) are charged within the same group. In this case and in the case of charging a new group of subpixels (SP), the charging rate is different because the time at which the data voltage (Vdata) is applied to the subpixel (SP) is different. As a result, a problem of non-uniform luminance may occur between a subpixel group composed of N subpixels (SP) and a subpixel group.

The purpose of embodiments of the present invention is to provide an organic light emitting display device and a driving method that can solve uneven brightness by improving the charging rate for subpixels of a display panel.

The purpose of an embodiment of the present invention is to provide an organic light emitting display device and driving method that can compensate for the charging rate by instantaneously increasing the current flowing through the organic light emitting diode by applying a reference voltage in the opposite direction to a section where the charging rate of the data voltage decreases. It is provided.

In one aspect, an organic light emitting display device according to an embodiment of the present invention includes a display panel on which a plurality of gate lines, a plurality of data lines, and a plurality of subpixels are arranged, driving the plurality of gate lines, and N rows of subpixels. A gate driving circuit that sequentially applies scan signals by dividing pixels into subpixel groups, a data driving circuit that drives a plurality of data lines, and a driving voltage applied to the gate driving circuit and the data driving circuit are controlled, and the subpixel group It may include a timing controller that controls the reference voltage generation circuit to apply a first reference voltage while the data voltage is applied to the first subpixel and to apply a second reference voltage while the data voltage is applied to the remaining subpixels. there is.

The subpixel includes an organic light emitting diode, a driving transistor that drives the organic light emitting diode, a switching transistor electrically connected between the gate node of the driving transistor and the data line, and an electrical connection between the source node or drain node of the driving transistor and the reference voltage line. It may include a storage capacitor electrically connected between a sensing transistor connected to a gate node of the switching transistor, and a source node or a drain node.

N may be any natural number.

The first reference voltage may have a negative value.

The reference voltage generator circuit receives a control signal from the timing controller through the gate node, the source node is connected to a first transistor to which the first reference voltage is applied, the gate node of the first transistor and the gate node are connected, and the source node is connected to the first transistor. Two reference voltages are applied, and the first transistor and the drain node may be connected to each other to include a second transistor that transmits the first or second reference voltage to the data driving circuit.

The reference voltage generation circuit may be disposed within a power management integrated circuit.

The data line may operate in a double rate driving (DRD) method in which one data line is placed between two adjacent subpixels, and two subpixels placed on both sides are driven by one data line.

The power management integrated circuit of the present invention includes a display panel in which a plurality of gate lines, a plurality of data lines, and a plurality of subpixels are arranged, drives the plurality of gate lines, and scans N rows of subpixels as subpixel groups. It includes a gate driving circuit that sequentially applies signals, a data driving circuit that drives a plurality of data lines, and a timing controller that controls the driving voltage applied to the gate driving circuit and the data driving circuit, according to the control of the timing controller. , the first reference voltage may be applied while the data voltage is applied to the first subpixel of the subpixel group, and the second reference voltage may be applied while the data voltage is applied to the remaining subpixels.

The power management integrated circuit receives a control signal from the timing controller through a gate node, a first transistor to which a first reference voltage is applied to the source node, the gate node of the first transistor and the gate node are connected, and the source node is connected to the gate node. A second reference voltage (Vref2) is applied, and the first transistor and the drain node may be connected to each other and may include a second transistor that transmits the first or second reference voltage to the data driving circuit.

The driving method of the organic light emitting display device of the present invention includes a plurality of data lines and a plurality of gate lines, a plurality of subpixels arranged in an area where the plurality of data lines and gate lines intersect, and a plurality of subpixels. An organic light emitting device including a display panel, a data driving circuit for driving a plurality of data lines, a gate driving circuit for driving a plurality of gate lines, and a timing controller for controlling driving signals applied to the gate driving circuit and the data driving circuit. A method of driving a display device, comprising: sequentially applying a scan signal to N rows of subpixels as a subpixel group through a gate driving circuit; and applying a data voltage to the first subpixel of the subpixel group. It may include applying a first reference voltage while the data voltage is being applied to the remaining subpixels of the subpixel group, and applying a second reference voltage while the data voltage is being applied to the remaining subpixels in the subpixel group.

According to an embodiment of the present invention, an organic light emitting display device and a driving method that can solve uneven brightness by improving the charging rate for subpixels of a display panel can be provided.

According to an embodiment of the present invention, an organic light emitting display device and driving method capable of compensating the charging rate by instantaneously increasing the current flowing through the organic light emitting diode by applying a reference voltage in the opposite direction to a section where the charging rate of the data voltage decreases. can be provided.

Figure 1 is a diagram showing the schematic configuration of an organic light emitting display device according to an embodiment of the present invention.
Figure 2 is a system diagram of an organic light emitting display device according to an embodiment of the present invention.
Figure 3 is an example of a circuit structure diagram of a subpixel (SP) arranged in an organic light emitting display device according to an embodiment of the present invention.
FIG. 4 is a diagram illustrating an exemplary compensation circuit that senses and compensates for characteristic values of a driving transistor in an organic light emitting display device according to an embodiment of the present invention.
Figure 5 is a diagram showing an example of a subpixel structure when driven in the DRD method in an organic light emitting display device according to an embodiment of the present invention.
FIG. 6 shows a 4-phase DRD driving method of continuously applying a scan signal (SCAN) to four rows of subpixels (SP) as one group in an organic light emitting display device and the resulting charging state of the subpixels (SP). This is a drawing showing .
FIG. 7 shows the scan signal (SCAN) and data voltage (Vdata) of a 4-phase DRD driving method in which a scan signal (SCAN) is continuously applied to four rows of subpixels (SP) as a group in an organic light emitting display device. ) This is a diagram showing the waveform.
Figure 8 shows that in an organic light emitting display device, according to a 4-phase DRD driving method that continuously applies a scan signal (SCAN) to four rows of subpixels (SP) as a group, the first subpixel (SP) is approximately This is a circuit diagram showing charging.
FIG. 9 is a diagram illustrating an example screen in which blurring (Dim) occurs in every gate line from the first to the fourth gate line in the case of four-phase driving in an organic light emitting display device driving DRD.
FIG. 10 is a diagram illustrating signal waveforms of a data voltage and a reference voltage applied to secure a charging rate of a weakly charged subpixel in an organic light emitting display device according to an embodiment of the present invention.
FIG. 11 is a diagram illustrating a process of determining the size of the first reference voltage (Vref1) for a weakly charged subpixel in an organic light emitting display device according to an embodiment of the present invention.
Figure 12 is a diagram showing the configuration of a circuit for improving luminance deviation in an organic light emitting display device according to an embodiment of the present invention.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. The present embodiments only serve to ensure that the disclosure of the present invention is complete and that common knowledge in the technical field to which the present invention pertains is not limited. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

In addition, the shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, it may also include the plural, unless specifically stated otherwise.

Additionally, when interpreting the components in the embodiments of the present invention, it should be interpreted to include a margin of error even if there is no separate explicit description.

Additionally, when describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the components are not limited by the term. When a component is described as being “connected,” “coupled,” or “connected” to another component, that component may be directly connected or connected to that other component, but there are no other components between each component. It should be understood that may be “interposed” or that each component may be “connected,” “combined,” or “connected” through other components. In the case of a description of a positional relationship, for example, if the positional relationship of two parts is described as 'on top', 'on the top', 'on the bottom', 'next to', etc., 'immediately' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

Additionally, the components in the embodiments of the present invention are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

In addition, the features (configurations) in the embodiments of the present invention can be partially or fully combined, combined, or separated from each other, and various technological interconnections and drives are possible, and each embodiment is implemented independently of each other. It may be possible, or it may be possible to implement them together due to a related relationship.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

Figure 1 is a diagram showing the schematic configuration of an organic light emitting display device according to an embodiment of the present invention.

Referring to FIG. 1, an organic light emitting display device 100 according to an embodiment of the present invention includes a display panel 110 in which a plurality of subpixels (SP) are arranged in a row, and a gate for driving the display panel 110. It may include a driving circuit 120 and a data driving circuit 130, and a timing controller 140 for controlling the gate driving circuit 120 and the data driving circuit 130.

In the display panel 110, a plurality of gate lines (GL) and a plurality of data lines (DL) are arranged, and a subpixel (SP) is arranged in an area where the gate line (GL) and the data line (DL) intersect. . For example, in the case of an organic light emitting display device with a resolution of 2,160 A subpixel (SP) will be placed at each point where DL) intersects.

The gate driving circuit 120 is controlled by the timing controller 140, and sequentially outputs a scan signal (SCAN) to a plurality of gate lines (GL) disposed on the display panel 110 to generate a plurality of subpixels (SP). Controls the driving timing for . In the organic light emitting display device 100 with a resolution of 2,160 The case of outputting can be called 2,160 phase driving. Alternatively, the scan signal SCAN is sequentially output from the first gate line GL1 to the fourth gate line GL4, and then the scan signal SCAN is output from the fifth gate line GL5 to the eighth gate line GL8. ), the case of sequentially outputting a scan signal (SCAN) on four gate lines as a unit is called 4-phase driving. In other words, the case of sequentially outputting a scan signal (SCAN) for each N gate lines can be called N-phase driving.

At this time, the gate driving circuit 120 may include one or more gate driver integrated circuits (GDIC). Depending on the driving method, it may be located only on one side of the display panel 110 or on both sides. It may be located. Alternatively, the gate driving circuit 120 may be built into the bezel area of the display panel 110 and implemented in a GIP (Gate In Panel) form.

Meanwhile, the data driving circuit 130 receives image data from the timing controller 140 and converts the received image data into an analog data voltage (Vdata). Then, the data voltage (Vdata) is output to each data line (DL) in accordance with the timing at which the scan signal (SCAN) is applied through the gate line (GL), so that each subpixel ( SP) displays a light emitting signal of corresponding brightness according to the data voltage (Vdata).

Likewise, the data driving circuit 130 may include one or more source driver integrated circuits (SDICs), which may use a Tape Automated Bonding (TAB) method or a Chip On (COG) method. It may be connected to a bonding pad of the display panel 110 using a glass method or may be placed directly on the display panel 110. In some cases, each source driver integrated circuit (SDIC) may be integrated and disposed on the display panel 110. In addition, each source driver integrated circuit (SDIC) may be implemented in a COF (Chip On Film) method. In this case, each source driver integrated circuit (SDIC) is mounted on a circuit film and displays the display panel through the circuit film. It may be electrically connected to the data line (DL) of (110).

The timing controller 140 supplies various control signals to the gate driving circuit 120 and the data driving circuit 130, and controls the operations of the gate driving circuit 120 and the data driving circuit 130. That is, the timing controller 140 controls the gate driving circuit 120 to output a scan signal (SCAN) according to the timing implemented in each frame, and on the other hand, the externally received image data is transmitted to the data driving circuit 130. ) and transmits the converted image data to the data driving circuit 130.

At this time, the timing controller 140 operates various timing signals including a vertical synchronization signal (VSYNC), a horizontal synchronization signal (HSYNC), a data enable signal (Data Enable; DE), and a clock signal (CLK) along with the image data. Receive signals from outside (e.g. host system). Accordingly, the timing controller 140 generates a control signal using various timing signals received from the outside and transmits it to the gate driving circuit 120 and the data driving circuit 130.

For example, the timing controller 140 uses a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (Gate Start Pulse) to control the gate driving circuit 120. Outputs various gate control signals including Output Enable (GOE), etc. Here, the gate start pulse (GSP) controls the timing at which one or more gate driver integrated circuits (GDIC) constituting the gate driving circuit 120 start operating. Additionally, the gate shift clock (GSC) is a clock signal commonly input to one or more gate driver integrated circuits (GDIC), and controls the shift timing of the scan signal (SCAN). Additionally, the gate output enable signal (GOE) specifies timing information of one or more gate driver integrated circuits (GDIC).

In addition, the timing controller 140 uses a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (Source Output Enable signal) to control the data driving circuit 130. Outputs various data control signals including ; SOE), etc. Here, the source start pulse (SSP) controls the timing at which one or more source driver integrated circuits (SDICs) constituting the data driving circuit 130 start sampling data. The source sampling clock (SSC) is a clock signal that controls the timing of sampling data in the source driver integrated circuit (SDIC). The source output enable signal (SOE) controls the output timing of the data driving circuit 130.

This organic light emitting display device 100 is a power management integrated circuit that supplies various voltages or currents to the display panel 110, the gate driving circuit 120, the data driving circuit 130, etc., or controls the various voltages or currents to be supplied. may further include.

Meanwhile, the subpixel SP is located at a point where the gate line GL and the data line DL intersect, and a light emitting device may be disposed in each subpixel SP. For example, the organic light emitting display device 100 includes a light emitting device such as a light emitting diode (LED) or an organic light emitting diode (OLED) in each subpixel (SP), and emits light to the light emitting device according to the data voltage (Vdata). Images can be displayed by controlling the flowing current.

Figure 2 is a system diagram of an organic light emitting display device according to an embodiment of the present invention.

In the organic light emitting display device 100 of FIG. 2, the source driver integrated circuit (SDIC) included in the data driving circuit 130 is implemented in a COF (Chip On Film) method among various methods (TAB, COG, COF, etc.). , This shows a case where the gate driving circuit 120 is implemented in a GIP (Gate In Panel) form among various methods (TAB, COG, COF, GIP, etc.).

A plurality of source driver integrated circuits (SDICs) included in the data driving circuit 130 may each be mounted on a source-side circuit film (SF), and one side of the source-side circuit film (SF) is connected to the display panel 110 and the Can be electrically connected. Additionally, wires for electrically connecting the source driver integrated circuit (SDIC) and the display panel 110 may be disposed on the source side circuit film SF.

This organic light emitting display device 100 includes at least one source printed circuit board (SPCB), control components, and It may include a control printed circuit board (CPCB) for mounting various electrical devices.

At this time, the other side of the source side circuit film (SF) on which the source driver integrated circuit (SDIC) is mounted may be connected to at least one source printed circuit board (SPCB). That is, one side of the source side circuit film (SF) on which the source driver integrated circuit (SDIC) is mounted may be electrically connected to the display panel 110, and the other side may be electrically connected to the source printed circuit board (SPCB).

A timing controller 140 and a power management integrated circuit (Power Management IC (PMIC) 210) may be mounted on a control printed circuit board (CPCB). The timing controller 140 may control the operations of the data driving circuit 130 and the gate driving circuit 120. The power management integrated circuit 210 supplies various voltages or currents, including driving voltages, to the display panel 110, the data driving circuit 130, and the gate driving circuit 120, or controls the supplied voltages or currents. You can.

At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be connected circuitously through at least one connecting member, for example, a flexible printed circuit (FPC). , it may be made of a flexible flat cable (FFC), etc. Additionally, at least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be integrated and implemented as one printed circuit board.

The organic light emitting display device 100 may further include a set board 230 electrically connected to a control printed circuit board (CPCB). At this time, the set board 230 may also be referred to as a power board. This set board 230 may include a main power management circuit (M-PMC, 220) that manages the overall power of the organic light emitting display device 100. The main power management circuit 220 may be interconnected with the power management integrated circuit 210.

In the case of the organic light emitting display device 100 configured as above, the driving voltage EVDD is generated on the set board 230 and transmitted to the power management integrated circuit 210 in the control printed circuit board (CPCB). The power management integrated circuit 210 transmits the driving voltage (EVDD) required for the image driving section or sensing section to the source printed circuit board (SPCB) through a flexible printed circuit (FPC) or flexible flat cable (FFC). The driving voltage (EVDD) delivered to the source printed circuit board (SPCB) is supplied to emit or sense a specific subpixel (SP) in the display panel 110 through the source driver integrated circuit (SDIC).

At this time, each subpixel (SP) arranged on the display panel 110 in the organic light emitting display device 100 includes a light emitting device, an Organic Light Emitting Diode (OLED), and a driving transistor (Driving) for driving the organic light emitting diode (OLED). It may be composed of circuit elements such as transistors.

The type and number of circuit elements constituting each subpixel (SP) may be determined in various ways depending on the provided function and design method.

Figure 3 is an example of a circuit structure diagram of a subpixel (SP) arranged in an organic light emitting display device according to an embodiment of the present invention.

Referring to FIG. 3, a subpixel (SP) disposed in the organic light emitting display device 100 of the present invention may include one or more transistors and a capacitor, and an organic light emitting diode (OLED) may be disposed as a light emitting device. . For example, the subpixel (SP) may include a driving transistor (DRT), a switching transistor (SWT), a sensing transistor (SENT), a storage capacitor (Cst), and an organic light emitting diode (OLED).

At this time, the switching transistor (SWT) is controlled on-off by receiving the scan signal (SCAN) to the gate node through the corresponding gate line, and the sensing transistor (SENT) receives the scan signal (SCAN) and other signals through the corresponding gate line. On-off can be controlled by receiving a sense signal (SENSE) to the gate node.

The driving transistor DRT has a first node N1, a second node N2, and a third node N3. The first node N1 of the driving transistor DRT may be a gate node to which the data voltage Vdata is applied through the data line DL when the switching transistor SWT is turned on. The second node N2 of the driving transistor DRT may be electrically connected to the anode electrode of the organic light emitting diode (OLED) and may be a source node or a drain node. The third node N3 of the driving transistor DRT is electrically connected to the driving voltage line DVL to which the driving voltage EVDD is applied, and may be a drain node or a source node.

Here, the driving voltage (EVDD) required for image driving may be supplied through the driving voltage line (DVL) in the image driving section. For example, the driving voltage (EVDD) required for image driving may be 27V.

The switching transistor (SWT) is electrically connected between the first node (N1) of the driving transistor (DRT) and the data line (DL), and the gate line (GL) is connected to the gate node and supplied through the gate line (GL). It operates according to the scan signal (SCAN). In addition, when the switching transistor (SWT) is turned on, the operation of the driving transistor (DRT) is controlled by transferring the data voltage (Vdata) supplied through the data line (DL) to the gate node of the driving transistor (DRT). I do it.

The sensing transistor (SENT) is electrically connected between the second node (N2) of the driving transistor (DRT) and the reference voltage line (RVL), and the gate line (GL) is connected to the gate node to transmit data through the gate line (GL). It operates according to the supplied sense signal (SENSE). When the sensing transistor (SENT) is turned on, the sensing reference voltage (VpreS) supplied through the reference voltage line (RVL) is transmitted to the second node (N2) of the driving transistor (DRT). That is, by controlling the switching transistor (SWT) and the sensing transistor (SENT), the voltage of the first node (N1) and the voltage of the second node (N2) of the driving transistor (DRT) are controlled, which causes the organic light emitting diode Ensure that current to drive (OLED) is supplied.

In the image driving section where the data voltage (Vdata) is applied, the current (Id) flowing through the organic light emitting diode (OLED) is equal to the voltage difference (Vgs) between the gate node (N1) and the source node (N2) of the driving transistor (DRT). It becomes proportional. At this time, with the switching transistor (SWT) and the sensing transistor (SENT) turned on, the voltage difference (Vgs) between the gate node (N1) and the source node (N2) of the driving transistor (DRT) is the data voltage (Vdata). It will have a difference value (Vdata - Vref) between the and reference voltage (Vref).

These switching transistors (SWT) and sensing transistors (SENT) may be connected to the same gate line (GL) or may be connected to different signal lines. Here, a structure in which the switching transistor (SWT) and the sensing transistor (SENT) are connected to different gate lines (GL) is shown as an example. In this case, switching is performed by a scan signal (SCAN) transmitted through the gate line (GL). The transistor (SWT) is controlled, and the sensing transistor (SENT) is controlled by the sense signal (SENSE).

Meanwhile, the transistor disposed in the subpixel SP may be made of not only an n-type transistor but also a p-type transistor, and here, the case of being made of an n-type transistor is shown as an example.

The storage capacitor Cst is electrically connected between the first node N1 and the second node N2 of the driving transistor DRT and maintains the data voltage Vdata for one frame.

This storage capacitor Cst may be connected between the first node N1 and the third node N3 of the driving transistor DRT depending on the type of the driving transistor DRT. The anode electrode of the organic light emitting diode (OLED) may be electrically connected to the second node (N2) of the driving transistor (DRT), and the base voltage (EVSS) may be applied to the cathode electrode of the organic light emitting diode (OLED). You can. Here, the base voltage (EVSS) may be ground voltage or a voltage higher or lower than the ground voltage. Additionally, the electromotive voltage (EVSS) may vary depending on the driving state. For example, the base voltage (EVSS) at the time of image driving and the base voltage (EVSS) at the time of sensing driving may be set differently.

The structure of the subpixel (SP) described above as an example is a 3T (Transistor) 1C (Capacitor) structure, which is only an example for explanation, and may further include one or more transistors or, in some cases, one or more capacitors. More may be included. Alternatively, each of the multiple subpixels (SP) may have the same structure, or some of the multiple subpixels (SP) may have a different structure.

Image driving that causes the subpixel (SP) to emit light may proceed through an image data recording step, a boosting step, and a light emitting step.

In the image data recording step, the image driving data voltage (Vdata) corresponding to the image signal is applied to the first node (N1) of the driving transistor (DRT), and the image driving data voltage (Vdata) is applied to the second node (N2) of the driving transistor (DRT). The reference voltage VpreR may be applied as the reference voltage Vref. Here, due to the resistance component between the second node (N2) of the driving transistor (DRT) and the reference voltage line (RVL), the reference voltage (VpreR) for image driving is applied to the second node (N2) of the driving transistor (DRT). A voltage similar to may be applied. In the image data recording stage, the storage capacitor (Cst) may be charged with a charge corresponding to the potential difference (Vdata - Vref) between both ends.

Applying the image driving data voltage (Vdata) to the first node (N1) of the driving transistor (DRT) is called image data writing. In the boosting step after the image data recording step, the first node N1 and the second node N2 of the driving transistor DRT may be electrically floating. To this end, the switching transistor (SWT) may be turned off by the scan signal (SCAN) at the turn-off level. Additionally, the sensing transistor SENT may be turned off by the sense signal SENSE at the turn-off level.

In the boosting step, while the voltage difference between the first node (N1) and the second node (N2) of the driving transistor (DRT) is maintained, the first node (N1) and the second node (N2) of the driving transistor (DRT), respectively The voltage can be boosted. Through the boosting step, the voltage of the first node (N1) and the second node (N2) of the driving transistor (DRT) is boosted, and then the voltage of the second node (N2) of the driving transistor (DRT) is maintained at a constant voltage, that is, organic light emission. When the voltage exceeds the voltage that can turn on the diode (OLED), it enters the light emission stage.

In the light emission stage, a driving current flows to the organic light emitting diode (OLED), so that the organic light emitting diode (OLED) can emit light.

At this time, the driving transistor (DRT) disposed in the plurality of subpixels (SP) has unique characteristic values such as threshold voltage and mobility. However, the driving transistor (DRT) has a driving time Since deterioration may occur depending on, the unique characteristic value of the driving transistor (DRT) may change depending on the driving time.

If the characteristic value of the driving transistor (DRT) changes, the on-off timing may change or the driving ability of the organic light emitting diode (OLED) may change. That is, as the characteristic value of the driving transistor (DRT) changes, the timing of supplying current to the organic light-emitting diode (OLED) and the amount of current supplied to the organic light-emitting diode (OLED) may vary. As a result, the characteristic value of the driving transistor (DRT) may change, and the actual luminance of the corresponding subpixel (SP) may vary. In addition, since the driving times of the plurality of subpixels (SP) arranged in the display panel 110 may be different, the characteristic value deviation (threshold voltage deviation, and mobility deviation) may occur.

This deviation in characteristic values between driving transistors (DRT) may cause luminance deviation between subpixels (SP), and the luminance uniformity of the display panel 110 may deteriorate, leading to deterioration of image quality.

The organic light emitting display device 100 according to an embodiment of the present invention includes a storage capacitor in the sensing section of the driving transistor (DRT) in order to effectively sense the characteristic value of the driving transistor (DRT), for example, threshold voltage or mobility. A method of measuring the voltage charged at (Cst) can be used. Accordingly, the organic light emitting display device 100 according to an embodiment of the present invention includes a compensation circuit capable of compensating for a deviation in the characteristic value of the driving transistor (DRT), and can provide a compensation method using the same.

That is, by measuring the voltage charged in the storage capacitor (Cst) in the sensing section of the driving transistor (DRT), the characteristic value or change in characteristic value of the driving transistor (DRT) in the subpixel (SP) can be found. At this time, the reference voltage line (RVL) not only serves to transmit the reference voltage (Vref), but also serves as a sensing line to sense the characteristic value of the driving transistor (DRT) in the subpixel (SP), so the reference voltage The line (RVL) can be called a sensing line.

For example, in the organic light emitting display device 100 according to an embodiment of the present invention, the characteristic value or change in characteristic value of the driving transistor (DRT) is determined by the voltage of the first node (N1) of the driving transistor (DRT) and the second node (N1) of the driving transistor (DRT). It may correspond to the difference in voltage (e.g., Vdata - Vref) of the two nodes (N2).

FIG. 4 is a diagram illustrating an exemplary compensation circuit that senses and compensates for characteristic values of a driving transistor in an organic light emitting display device according to an embodiment of the present invention.

Referring to FIG. 4, the organic light emitting display device 100 according to an embodiment of the present invention senses the characteristic value or change in characteristic value of each driving transistor (DRT) in order to compensate for the deviation in characteristic value of the driving transistor (DRT). Needs to be. To this end, the compensation circuit of the organic light emitting display device 100 according to an embodiment of the present invention includes a driving transistor in the subpixel (SP) in the sensing section for the subpixel (SP) having a 3T1C structure or a modified structure based thereon. It may include components for sensing characteristic values of (DRT) or changes in characteristic values.

The organic light emitting display device 100 according to an embodiment of the present invention senses the voltage of the reference voltage line (RVL) in the sensing section, and determines the characteristic value or characteristic of the driving transistor (DRT) in the subpixel (SP) from the sensed voltage. Changes in value can be detected. The reference voltage line (RVL) not only delivers the reference voltage (Vref), but also serves as a sensing line to sense the characteristic value of the driving transistor (DRT) in the subpixel (SP). can do. Therefore, the reference voltage line RVL may be referred to as a sensing line.

Specifically, the characteristic value or change in the characteristic value of the driving transistor (DRT) in the sensing section of the organic light emitting display device 100 according to an embodiment of the present invention is the voltage of the second node (N2) of the driving transistor (DRT) Example: It can be reflected as Vdata - Vth). The voltage of the second node N2 of the driving transistor DRT may correspond to the voltage of the reference voltage line RVL when the sensing transistor SENT is turned on. In addition, the line capacitor Cline on the reference voltage line RVL may be charged by the voltage of the second node N2 of the driving transistor DRT, and the reference voltage line (Cline) may be charged by the charged line capacitor Cline. RVL) may have a voltage corresponding to the voltage of the second node N2 of the driving transistor DRT.

The compensation circuit of the organic light emitting display device 100 according to an embodiment of the present invention controls the on-off of the switching transistor (SWT) and the sensing transistor (SENT) in the subpixel (SP) that is the sensing target, and controls the data voltage By controlling the supply of (Vdata) and reference voltage (Vref), the second node (N2) of the driving transistor (DRT) changes the characteristic value (threshold voltage, or mobility) or characteristic value of the driving transistor (DRT). It can be driven to reflect the voltage state.

The compensation circuit of the organic light emitting display device 100 according to an embodiment of the present invention measures the voltage of the reference voltage line (RVL) corresponding to the voltage of the second node (N2) of the driving transistor (DRT) and converts it to a digital value. It may include an analog-to-digital converter (ADC) and a switch circuit (SAM, SPRE) for sensing characteristic values.

The switch circuit (SAM, SPRE) that controls the sensing operation is a sensing reference switch (SPRE) that controls the connection between each reference voltage line (RVL) and the sensing reference voltage supply node (Npres) to which the reference voltage (Vref) is supplied. ) and a sampling switch (SAM) that controls the connection between each reference voltage line (RVL) and the analog-to-digital converter (ADC). Here, the sensing reference switch (SPRE) is a switch that controls the sensing operation, and the reference voltage (Vref) supplied to the reference voltage line (RVL) by the sensing reference switch (SPRE) is the sensing reference voltage (VpreS). This happens.

Additionally, the switch circuit for sensing the characteristic value of the driving transistor (DRT) may include an image driving reference switch (RPRE) that controls image driving. The image driving reference switch (RPRE) can control the connection between each reference voltage line (RVL) and the image driving reference voltage supply node (Nprer) to which the reference voltage (Vref) is supplied. The image driving reference switch (RPRE) is a switch used for image driving. The reference voltage (Vref) supplied to the reference voltage line (RVL) by the image driving reference switch (RPRE) is the image driving reference voltage (VpreR). corresponds to

At this time, the reference switch for sensing (SPRE) and the reference switch for image driving (RPRE) may be provided separately or may be integrated and implemented as one. The reference voltage for sensing (VpreS) and the reference voltage for image driving (VpreR) may be the same voltage value or may be different voltage values.

The compensation circuit of the organic light emitting display device 100 according to an embodiment of the present invention stores the sensing value output from the analog-to-digital converter (ADC) or a memory (MEM) that stores the reference sensing value in advance, and the sensing value and the memory. A compensator (COMP) that compares the reference sensing value stored in the (MEM) and calculates a compensation value that compensates for the deviation of the characteristic value may be included in the timing controller 140. At this time, the compensation value calculated by the compensator (COMP) may be stored in the memory (MEM).

The timing controller 140 changes the data voltage (Data) in the form of a digital signal to be supplied to the data driving circuit 130 using the compensation value calculated by the compensator (COM), and applies the changed data voltage (Data_comp) to the data driving circuit ( 130). Accordingly, the data driving circuit 130 converts the changed data voltage (Data_comp) into a data voltage (Vdata_comp) in the form of an analog signal through a digital-to-analog converter (DAC), and stores the converted data voltage (Vdata_comp) in the output buffer (BUF). ) can be output to the corresponding data line (DL). As a result, the characteristic value deviation (threshold voltage deviation, or mobility deviation) for the driving transistor (DRT) within the corresponding subpixel (SP) can be compensated.

Meanwhile, the data driving circuit 130 may include a data voltage output circuit 400 including a latch circuit, a digital-to-analog converter (DAC), and an output buffer (BUF), and in some cases, an analog-to-digital converter. (ADC) and various switches (SAM, SPRE, RPRE) may be further included. On the other hand, the analog-to-digital converter (ADC) and various switches (SAM, SPRE, RPRE) may be located outside the data driving circuit 130.

Additionally, the compensator (COMP) may exist outside of the timing controller 140, but may also be included inside the timing controller 140, and the memory (MEM) may be located outside of the timing controller 140, and may be located outside of the timing controller 140. It may also be implemented in the form of a register inside the controller 140.

Figure 5 is a diagram showing an example of a subpixel structure when driven in the DRD method in an organic light emitting display device according to an embodiment of the present invention.

Referring to FIG. 5, the subpixels (SP) of the organic light emitting display device 100 according to an embodiment of the present invention include a red subpixel (R), a green subpixel (G), a blue subpixel (B), and a white subpixel (SP). This shows a case composed of subpixels (W).

In the organic light emitting display device 100 driven by the DRD method, the display panel 110 has one data line (DL) arranged in each of two subpixel (SP) columns, and two subpixels (SP) in each row at the top and bottom. Gate lines (GL) may be arranged. Here, the red subpixel (G) and green subpixel (G) share one data line (DL11), and the blue subpixel (B) and white subpixel (W) share one data line (DL12). This shows the case where it is being done. Additionally, the red subpixel (R) and blue subpixel (B) share the same gate line (GL11, GL21, GL31, GL41, GL51, ?), and the green subpixel (G) and white subpixel (W) They share the same gate lines (GL12, GL22, GL32, GL42, ?).

The subpixel (SP) structure sharing the data line (DL) and gate line (GL) can be changed in various ways, such as white subpixel (W) and red subpixel (R), or green subpixel (G) and blue. Each subpixel (B) may share a data line (DL), or the white subpixel (W) and the green subpixel (G) may share one gate line (GL).

In the case of this DRD driving method, the data voltage (Vdata) is supplied to two subpixels (SP) through one data line (DL) during one horizontal period (Horizontal Time), and the gate line (GL) is It is driven at twice the frequency compared to driving, so a scan signal (SCAN) can be applied to each subpixel (SP).

In addition, in order to minimize the occurrence of flicker and reduce power consumption, the scan signal (SCAN) is controlled so that the data voltage (Vdata) is applied alternately to the subpixels (SP) arranged on both sides of one data line (DL). You might be able to do it.

FIG. 6 shows a 4-phase DRD driving method of continuously applying a scan signal (SCAN) to four rows of subpixels (SP) as one group in an organic light emitting display device and the resulting charging state of the subpixels (SP). , and FIG. 7 is a diagram showing the waveforms of the scan signal (SCAN) and the data voltage (Vdata) at this time.

Referring to FIGS. 6 and 7, after scan signals (SCAN_GL11 and SCAN_GL21) are sequentially applied to the red subpixel (R1) in the first row and the red subpixel (R2) in the second row for 4-phase driving, Scan signals (SCAN_GL12, SCAN_GL22, SCAN_GL32, and SCAN_GL42) may be sequentially applied from the adjacent green subpixel (G1) in the first row to the green subpixel (G4) in the fourth row. At this time, the timing interval of the scan signals (SCAN_GL11, SCAN_GL21, SCAN_GL31, SCAN_GL41, SCAN_GL12, SCAN_GL22, SCAN_GL32, SCAN_GL42) can be set to 1 horizontal period (1H). Then, the scan signals (SCAN_GL31, SCAN_GL41, SCAN_GL51, and SCAN_GL61) may be applied sequentially from the red subpixel (R3) in the third row to the red subpixel (R6) in the sixth row.

At the point when the scan signal (SCAN) is applied to the red subpixels (R1, R2) in the first and second rows or the green subpixels (G1, G2, G3, G4) in the first to fourth rows, the first When the data voltage (Vdata_DL11) is transmitted through the data line (DL11), the subpixel (SP) corresponding to the section where the scan signals (SCAN_GL11, SCAN_GL21, SCAN_GL12, SCAN_GL22, SCAN_GL32, SCAN_GL42) and the data voltage (Vdata_DL11) overlaps. The color corresponding to the data voltage (Vdata_DL11) will be displayed.

For example, consider the case where the green subpixel (G1) in the first row to the green subpixel (G4) in the fourth row emits light in the display panel 110. At this time, the data voltage (Vdata_DL11) is not supplied in the section where the scan signals (SCAN_GL11, SCAN_GL21) are applied at a high level to the red subpixel (R1) in the first row and the red subpixel (R2) in the second row. In the section where the scan signals (SCAN_GL12, SCAN_GL22, SCAN_GL32, SCAN_GL42) are applied from the green subpixel (G1) in the first row to the green subpixel (G4) in the fourth row, the data voltage (Vdata_DL11) will be supplied at a high level. .

In the case of the organic light emitting display device 100 with a resolution of 2,160 Since (Vdata) is supplied, in order to drive the entire frame of the display panel 110 once, a scan signal (SCAN) must be applied to 2,160 + 2,160 subpixels (SP). At this time, if the organic light emitting display device 100 is driven at a frequency of 120 Hz, one horizontal period (1H) of the scan signal (SCAN) has a time of 1/[120*(2,160+2,160)] = 1.8 μs. It will be.

That is, in the section where the scan signal (SCAN_GL12) is applied to the green subpixel (G1) in the first row after the scan signal (SCAN_GL21) is applied to the red subpixel (R24) in the second row, one horizontal period (1H) The data voltage (Vdata_DL11) will be supplied for 2 horizontal periods (2H) in the section where the scan signal (SCAN_GL22) is applied to the green subpixel (G2) in the second row. Additionally, in the section where the scan signal (SCAN_GL32) is applied to the green subpixel (G3) in the third row, the data voltage (Vdata_DL11) is supplied for 3 horizontal periods (3H), and to the green subpixel (G4) in the fourth row. In the section where the scan signal (SCAN_GL42) is applied, the data voltage (Vdata_DL11) will be supplied for 4 horizontal periods (4H).

In the case of the organic light emitting display device 100 that is driven at a frequency of 120 Hz and has a resolution of 2,160 It will charge the storage capacitor (Cst) for 1H). That is, because the green subpixel (G1) in the first row takes a shorter time to charge the storage capacitor (Cst) than the green subpixels (G2) in the second row to the green subpixels (G4) in the fourth row, the storage capacitor (Cst) becomes the weak charge section where charge is relatively weak. As a result, since the charging rate of the story capacitor Cst is relatively low in the section driving the green subpixel G1 in the first row, blurring phenomenon Dim occurs in the corresponding gate line GL.

For example, as shown in FIG. 8, when the data voltage (Vdata) is applied at 10V and the time for which the switching transistor (SWT) remains in the turn-on state is short as 1 horizontal period (1H), the driving Since sufficient current is not supplied to the storage capacitor (Cst) through the gate node (N1) of the transistor (DRT), the voltage charged to the storage capacitor (Cst) is lower than the data voltage (Vdata) of 10V, for example, only up to 9.8V. This phenomenon occurs.

As a result, in the display panel 110, the subpixel connected to the first gate line GL1, the subpixel connected to the fifth gate line GL5, and the subpixel connected to the ninth gate line GL9 , when there is a transition of the scan signal (SCAN) between a random subpixel group consisting of 4 subpixels and another subpixel group distinguished from it, a storage capacitor (Cst) for each 4th gate line (GL4N+1) Due to the low charging rate, blurring (Dim) occurs.

FIG. 9 is a diagram illustrating an example screen in which blurring (Dim) occurs in every gate line from the first to the fourth gate line in the case of four-phase driving in an organic light emitting display device driving DRD.

In the case of FIG. 9, due to 4-phase driving, the image quality is improved in the first gate line (GL1), the fifth gate line (GL5), the ninth gate line (GL9) to the 4N+1 gate line (GL4N+1). It shows a deterioration phenomenon.

This blurring phenomenon (Dim) is a quality degradation phenomenon that occurs in N-phase driving of the DRD method. In the case of 8-phase driving, the 9th gate line (GL9), the 17th gate line (GL17) to the 8N+1 gate line ( Such blurring may occur in GL8N+1). In the case of N-phase driving, N can be any natural number.

As explained above, this phenomenon occurs in N-phase driving, which sequentially applies a scan signal (SCAN) to N rows of subpixels (SP) as one subpixel group, and the scan signal is transmitted to subpixels (SP) of different colors. In the process of switching (SCAN), it can be seen as a phenomenon that occurs due to insufficient charging of the storage capacitor (Cst) that constitutes the first subpixel (SP) among the subpixel group to which the scan signal (SCAN) is first applied. there is.

To solve this problem, an overdriving method is used to secure the charging rate by shortening the rising time when applying the data voltage (Vdata) to a random subpixel group. However, this overdriving method has the disadvantage of having to increase the size of the data driving circuit 130, and because it requires the process of measuring luminance and setting the overdriving voltage for each data line DL, the subpixel (SP) ), a problem arises in which compensation time takes a long time.

In addition, the charging rate for the subpixels (SP) can be set evenly by alternately driving the subpixels (SP) connected to one data line (DL) one by one. However, this driving method uses a scan signal between the subpixels (SP). Because (SCAN) switching occurs too frequently, there is a problem in which excessive heat is generated in the display panel (DP).

The present invention is an N-phase driving DRD driving method in which a scan signal (SCAN) is sequentially applied to N rows of subpixels (SP) as a subpixel group, and in N rows during the section in which the data voltage (Vdata) is applied. To secure the charging rate for the subpixel (SP) in the corresponding section by applying the reference voltage (Vref) in the opposite direction to the data voltage (Vdata) to the first subpixel (SP) in which weak charging occurs among the subpixel groups. do.

FIG. 10 is a diagram illustrating signal waveforms of a data voltage and a reference voltage applied to secure a charging rate of a weakly charged subpixel in an organic light emitting display device according to an embodiment of the present invention.

Referring to FIG. 10, the organic light emitting display device 100 of the present invention reduces the data voltage (Vdata) during a section in which weak charging occurs among the sections in which the data voltage (Vdata) is applied to the subpixel (SP) through DRD driving. Controls to apply the reference voltage (Vref) in the opposite direction. Since the reference voltage (Vref) is output from the power management integrated circuit 210 under the control of the timing controller 140, the reference voltage (Vref) is generated according to the timing of the data voltage (Vdata) inside the power management integrated circuit 210. You may be able to configure the circuit to swing this way.

Therefore, the organic light emitting display device 100 of the present invention has a first reference voltage (Vref1) applied in the weak charging section and a second reference voltage applied in the strong charging section, based on the time when the data voltage (Vdata) is applied. (Vref2) will swing between.

Since the data voltage (Vdata) has a positive value depending on the brightness displayed by the subpixel (SP), the first reference voltage (Vref1) applied in the weak charging section where the subpixel (SP) is weakly charged has a negative value. You can have

Here, the current (Id) flowing through the organic light emitting diode (OLED) is proportional to the voltage difference (Vgs) between the gate node (N1) and the source node (N2) of the driving transistor (DRT). At this time, the voltage difference (Vgs) between the gate node (N1) and the source node (N2) of the driving transistor (DRT) in the weak charge section is the absolute value of the data voltage (Vdata) and the absolute value of the first reference voltage (Vref1). Since it becomes the sum of the values, the current (Id) flowing through the organic light emitting diode (OLED) ultimately increases, making it possible to improve the charging rate for the subpixel (SP) that is weakly charged in N-phase driving.

In addition, in N-phase DRD driving, the time for which the data voltage (Vdata) is applied to the first subpixel (SP) where weak charging occurs among the N subpixels (SP) to which the scan signal (SCAN) is sequentially applied is 1 horizontal cycle. Since it corresponds to (1H), in the organic light emitting display device 100 driven at a frequency of 120 Hz and having a resolution of 2,160 It will be possible to have a time interval of .

Meanwhile, the second reference voltage Vref2 applied in the strong charging section in which the subpixel SP is strongly charged may be the ground voltage or a voltage higher or lower than the ground voltage.

At this time, the magnitude of the first reference voltage (Vref1) applied to the first subpixel (SP) where weak charging occurs is determined by determining the luminance of the first subpixel (SP) emitted in the weak charging section to be equal to that of the remaining subpixels (SP). By setting the luminance to be most similar, it will be possible to minimize the charging rate deviation between N subpixel groups.

FIG. 11 is a diagram illustrating a process of determining the size of the first reference voltage (Vref1) for a weakly charged subpixel in an organic light emitting display device according to an embodiment of the present invention.

Referring to FIG. 11, in the DRD driving method of 4-phase driving in which the scan signal (SCAN) is sequentially applied using four rows of subpixels (SP) as a subpixel group, the section where the data voltage (Vdata) is applied The subpixel (SP) in which the weak charge is performed may be the first subpixel (SP1). The remaining second to fourth subpixels SP2 to SP4 will have relatively higher charging rates than the first subpixel SP1.

For example, if the luminance of the first subpixel (SP1), which is weakly charged, is 22.4 nit, and the luminance of the second to fourth subpixels (SP2), which are strongly charged, is 30.4 nit, the Due to the luminance difference (8 nit) between subpixel 1 and the remaining subpixels (SP2, SP3, and SP4), blurring (Dim) appears on the gate line GL1 where the first subpixel (SP1) is located. .

Therefore, in order to resolve this blurring phenomenon (Dim), the first reference voltage (Vref1) is set so that the luminance of the first subpixel (SP1) appears at the same level as the luminance of 30.4 nits, which is the luminance of the remaining subpixels (SP2, SP3, and SP4). You just need to decide the value of . For this purpose, the luminance of the first subpixel (SP1) is measured after applying the first reference voltage (Vref1) to a constant value, for example, -1V, and the luminance of the remaining subpixels (SP2, SP3, and SP4) is measured. Compare. - When the luminance of the first subpixel (SP1) is lower than the luminance of the remaining subpixels (SP2, SP3, and SP4) while applying the first reference voltage (Vref1) of 1V, the value of the first reference voltage (Vref1) increases in the negative direction, and conversely, when the luminance of the first subpixel (SP1) is higher than the luminance of the remaining subpixels (SP2, SP3, SP4), the value of the first reference voltage (Vref1) increases in the positive direction. While doing so, the first reference voltage Vref1 may be determined until the luminance of the first subpixel SP1 and the luminance of the remaining subpixels SP2, SP3, and SP4 are at the same level.

By applying the first reference voltage (Vref1) determined in this way to the weak charge section, the luminance of the first subpixel (SP1) and the remaining subpixels (SP2, SP3, and SP4) are unified to 30.4 nit, thereby preventing blurring due to luminance deviation. (Dim) can be resolved.

Figure 12 is a diagram showing the configuration of a circuit for improving luminance deviation in an organic light emitting display device according to an embodiment of the present invention.

Referring to FIG. 12, in the organic light emitting display device of the present invention, a reference voltage generator circuit for applying different reference voltages to specific subpixels in an image driving section may be disposed within the power management integrated circuit 210.

To this end, the power management integrated circuit 210 may be composed of a first transistor and a second transistor through which a gate node is connected and which receives a control signal from the timing controller 140. The drain node or source node of the first transistor and the second transistor may be electrically connected to each other, and through this, the reference voltage (Vref) may be supplied to the reference voltage supply node (Nprer) of the data driving circuit 130. A first reference voltage (Vref1) may be applied to the source node or drain node of the first transistor, and a second reference voltage (Vref2) may be applied to the source node or drain node of the second transistor. Meanwhile, the first transistor may be an n-type transistor, and the second transistor may be a p-type transistor.

Meanwhile, this reference voltage generation circuit may be implemented inside the power management integrated circuit 210, but may also be configured in a module form outside the power management integrated circuit 210, for example, inside the data driving circuit 130. There will be.

Therefore, according to the control signal applied from the timing controller 140, the power management integrated circuit 210 may supply the first reference voltage (Vref1) or the second reference voltage (Vref2) to the reference voltage supply node (Nprer), In an N-phase DRD driven organic light emitting display device, the first reference voltage (Vref1) is supplied to the section in which the data voltage (Vdata) is applied to the first subpixel in which weak charging occurs among the N subpixel groups, and to the remaining subpixels. The second reference voltage (Vref2) may be supplied to the section where the data voltage (Vdata) is applied. Accordingly, in the organic light emitting display device of the present invention, different reference voltages (Vref) are applied depending on the positions of subpixels in the image driving section, so the reference voltage (Vref) can be considered to correspond to the AC voltage.

As previously explained, the current (Id) flowing through the organic light emitting diode (OLED) is proportional to the voltage difference (Vgs) between the gate node (N1) and the source node (N2) of the driving transistor (DRT). In the weak charge section, Since the first reference voltage (Vref1) in the opposite direction (negative value) is applied to the data voltage (Vdata) having a positive value, the voltage of the gate node (N1) and the source node (N2) of the driving transistor (DRT) The difference (Vgs) increases, and eventually the current (Id) flowing through the organic light emitting diode (OLED) increases, making it possible to improve the charging rate for the subpixel (SP) that is weakly charged.

The above description is merely an illustrative explanation of the technical idea of the present invention, and various modifications and variations will be possible to those skilled in the art without departing from the essential characteristics of the present invention. In addition, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but rather to explain it, and therefore the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of the present invention.

100: Organic light emitting display device 110: Display panel
120: gate driving circuit 130: data driving circuit
140: timing controller 210: power management integrated circuit
220: main power management circuit 230: set board
400: data voltage output circuit

Claims (13)

A display panel in which a plurality of gate lines, a plurality of data lines, and a plurality of subpixels are arranged, the plurality of subpixels are divided into a plurality of subpixel groups, and each of the plurality of subpixel groups includes N subpixels. ;
a gate driving circuit that drives the plurality of gate lines and sequentially applies a scan signal to N subpixels included in each of the plurality of subpixel groups;
a data driving circuit that drives the plurality of data lines; and
Controlling the driving voltage applied to the gate driving circuit and the data driving circuit, and applying a first reference voltage while the data voltage is applied to the first subpixel among the N subpixels included in each of the plurality of subpixel groups and a reference voltage to apply a second reference voltage higher than the first reference voltage while the data voltage is applied to the remaining subpixels excluding the first subpixel among the N subpixels included in each of the plurality of subpixel groups. It includes a timing controller that controls the generation circuit,
An organic light emitting display device in which N subpixels included in each of the plurality of subpixel groups emit light of the same color.
According to paragraph 1,
The subpixel is
organic light emitting diode;
A driving transistor driving the organic light emitting diode;
a switching transistor electrically connected between the gate node of the driving transistor and the data line;
A sensing transistor electrically connected between the source node or drain node of the driving transistor and a reference voltage line; and
An organic light emitting display device comprising a storage capacitor electrically connected between a gate node of the switching transistor and a source node or drain node.
According to paragraph 1,
An organic light emitting display device where N is any natural number.
According to paragraph 1,
The organic light emitting display device wherein the first reference voltage has a negative value.
According to paragraph 1,
The reference voltage generation circuit is
a first transistor that receives a control signal from the timing controller through a gate node and has a first reference voltage applied to the source node; and
The gate node of the first transistor is connected to the gate node, a second reference voltage is applied to the source node, and the first transistor and the drain node are connected to each other to use the first or second reference voltage to drive the data. An organic light emitting display device comprising a second transistor that transmits power to the circuit.
According to clause 5,
An organic light emitting display device wherein the reference voltage generating circuit is disposed within a power management integrated circuit.
According to paragraph 1,
The data line is
An organic light emitting display device operating in a DRD method in which one data line is disposed between two adjacent subpixels and the two subpixels disposed on both sides are driven by one data line.
A display panel having a plurality of gate lines, a plurality of data lines, and a plurality of subpixels, a gate driving circuit for driving the plurality of gate lines, a data driving circuit for driving the plurality of data lines, and driving the gate. In the power management integrated circuit of an organic light emitting display device including a circuit and a timing controller for controlling the data driving circuit,
Under the control of the timing controller,
A first reference voltage is applied while a data voltage is applied to the first subpixel among the N subpixels included in each of the plurality of subpixel groups into which the plurality of subpixels are divided, and included in each of the plurality of subpixel groups. Applying a second reference voltage higher than the first reference voltage while a data voltage is applied to the remaining subpixels except the first subpixel among the N subpixels,
A power management integrated circuit in which N subpixels included in each of the plurality of subpixel groups emit light of the same color.
According to clause 8,
a first transistor that receives a control signal from the timing controller through a gate node and has a first reference voltage applied to the source node; and
The gate node of the first transistor is connected to the gate node, a second reference voltage is applied to the source node, and the first transistor and the drain node are connected to each other to use the first or second reference voltage to drive the data. A power management integrated circuit including a second transistor that delivers power to the circuit.
A display panel including a plurality of data lines and a plurality of gate lines, a plurality of subpixels arranged in an area where the plurality of data lines and the gate lines intersect, a plurality of subpixels, and the plurality of data lines. A method of driving an organic light emitting display device comprising a data driving circuit for driving, a gate driving circuit for driving the plurality of gate lines, and a timing controller for controlling the gate driving circuit and the data driving circuit,
sequentially applying a scan signal to N subpixels included in each subpixel group into which the plurality of subpixels are divided, through the gate driving circuit;
applying a first reference voltage while a data voltage is applied to a first subpixel among N subpixels included in each of the plurality of subpixel groups; and
Applying a second reference voltage higher than the first reference voltage while a data voltage is applied to the remaining subpixels excluding the first subpixel among the N subpixels included in each of the plurality of subpixel groups; ,
A method of driving an organic light emitting display device in which N subpixels included in each of the plurality of subpixel groups emit light of the same color.
According to clause 10,
A method of driving an organic light emitting display device, wherein N is an arbitrary natural number.
According to clause 10,
A method of driving an organic light emitting display device in which the first reference voltage has a negative value.
According to clause 10,
The data line is
A driving method of an organic light emitting display device operating in a DRD method in which one data line is disposed between two adjacent subpixels and the two subpixels disposed on both sides are driven by one data line.

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