KR102598152B1 - Asynchronous non-volatile memory module with self-diagnosis function - Google Patents

Abstract

The present invention relates to a semiconductor memory. According to the present invention, it has a volatile memory and a non-volatile memory, so that data can be preserved even when the power is turned off, but data can be read and written. To solve the problem of non-volatile SRAM (NVSRAM) in the prior art, which had limitations in preventing data loss due to errors occurring in the process, the voltage charged in the super capacitor is used when the power is turned off. Data from pseudo-static RAM (PSRAM) is stored in NAND flash memory. At this time, bad blocks are avoided through BBT (Bad Block Table) and stored in valid blocks, and ECC (Error Correction Code) data is stored in valid blocks. After saving CRC (Cyclic Redundancy Code)32 and Data Check Sum data together, when the power is turned on again, the saved data is read and the CRC32 and Data Checksum data stored together are compared. If there is a difference, the error is detected through ECC. An asynchronous non-volatile memory module having a self-diagnosis function is provided that is configured to perform data correction processing, thereby preventing data loss and further increasing the reliability and accuracy of error detection and correction.

Description

Asynchronous non-volatile memory module with self-diagnosis function}

The present invention relates to a semiconductor memory module and a design method thereof. More specifically, the present invention relates to a semiconductor memory module and a method of designing the same. Conventionally, in general, it is provided with two memories, a volatile memory and a non-volatile memory, so that the power can be turned off. Saving data that was being worked on in volatile memory to non-volatile memory has the advantage of preserving data even when the power is turned off, but it also prevents data loss due to errors that occur in the process of reading and writing data. In order to solve the problems of non-volatile SRAM (NVSRAM) in the prior art, which had limitations, it was necessary to determine the state of the memory through self-diagnosis and correctly correct data errors that occur during reading and writing. It relates to an asynchronous non-volatile memory module with a self-diagnosis function that is configured to minimize data loss and increase memory reliability and stability.

In addition, the present invention uses an ECC (Error Correction Code) algorithm to solve the problem of the NVSRAM of the prior art, which had limitations in preventing data loss due to errors occurring in the process of reading and writing data as described above. And, by applying CRC (Cyclic Redundancy Code) 32, BBT (Bad Block Table) and Data Check Sum, when the power is turned off, the voltage charged in the super capacitor is used to control the Pseudo SRAM (PSRAM). Data is stored in NAND flash memory. At this time, bad blocks are avoided through BBT, stored in valid blocks, ECC data, CRC32, and data checksum data are stored together, and the stored data is restored when the power is turned on again. The CRC32 and data checksum data read and stored together are compared to determine whether the read content is accurate. If the read content is different, the data is configured to correct the correct data by finding and recovering the incorrect data through ECC. It relates to an asynchronous non-volatile memory module with a self-diagnosis function configured to prevent loss and further increase the reliability and accuracy of error detection and correction.

In general, memory is roughly divided into volatile memory, which retains data only while power is supplied, and non-volatile memory, which can store data even when power is not supplied.

In addition, non-volatile memory has the advantage of being able to keep data even when power is not supplied compared to volatile memory, in which all data is erased without power, but has the disadvantage of being more expensive and much slower than volatile memory. , Generally, when configuring a system, volatile memory is used while the system is operating, and data is stored in non-volatile memory only when data storage is necessary.

Here, if the equipment suddenly breaks down or the power is turned off, you may lose all of your work and have to recover the data from the beginning. Therefore, even if a situation occurs where data may be lost, you must lose as much data as possible. A method to reduce is required.

Accordingly, conventionally, NVSRAM (Non-Volatile Memory) is configured to preserve data by having both a volatile memory and a non-volatile memory and saving the data being worked on in the volatile memory to the non-volatile memory when the power is turned off. SRAM) has been presented.

That is, examples of the prior art for NVSRAM as described above include, for example, “Flash memory-based 6T non-volatile SRAM and operating method thereof” as presented in Korean Patent Publication No. 10-2330018. .

More specifically, the above-mentioned Korean Patent Publication No. 10-2330018 describes a first pull-down connected to a first pull-up transistor in a 6T non-volatile SRAM (Static Random Access Memory). A first inverter formed of a (pull down) transistor; a second inverter formed by a second pull-down transistor connected to a second pull-up transistor; A first pass gate made of a non-volatile memory element connected between the output of the first inverter and the bit line bar node; and a second pass gate made of a non-volatile memory element connected between the output of the second inverter and the bit line node, wherein the non-volatile memory element forming the first pass gate or the second pass gate is a precharge of the SRAM. HEI (Hot electron) due to the voltage difference between the voltage applied to the bit line node or bit line bar node through (Precharge) and the output voltage of the first or second inverter using the voltage applied to the word line node of SRAM. Injection occurs, the floating gate of the non-volatile memory device is charged with charge, and data storage of the non-volatile memory device is achieved, and a voltage of opposite polarity is applied to the word line node to charge the floating gate. By being configured to remove accumulated charges, it is composed of six transistors and has a faster operating speed than existing DRAM, NAND memory, and flash memory, but as a volatile memory, information is not maintained and is lost after the power is turned off or deactivated. This relates to a 6T non-volatile SRAM based on flash memory that solves the shortcomings of the 6T SRAM of the prior art and maintains the fast operation speed of 6T SRAM and retains information even after the power is turned off.

In addition, another example of the prior art for NVSRAM as described above is, for example, “6T non-volatile SRAM incorporating 3D flash memory” as presented in Korean Patent Publication No. 10-2222813.

More specifically, the above-mentioned Korean Patent Publication No. 10-2222813 discloses a 6T nonvolatile SRAM (Static Random Access Memory), comprising: a substrate; A repeat block consisting of a first pull-down transistor connected to a first pull-up transistor and a second pull-down transistor connected to a second pull-up transistor and stacked on a substrate; and an access block composed of two non-volatile memory elements and vertically stacked on a repeat block, wherein the access block is a HEI generated through the precharge voltage of a 6T non-volatile SRAM cell. By using hot electron injection to charge the floating gate of the non-volatile memory device, information disappears even after the power is turned off while maintaining the fast operation speed of 6T SRAM. It is about 6T non-volatile SRAM with 3D flash memory that is maintained without loss and the structure of the cell (Bit_Cell) forming the memory array is composed of 6 transistors to improve the integration of 6T SRAM, which has low integration. .

As mentioned above, various technical details regarding NVSRAM have been proposed in the past, but the contents of the prior art as described above have the following limitations.

In other words, as mentioned above, NVSRAM detects the risk of data loss when the system power is turned off and transfers data from pseudo-static RAM (PSRAM: Pseudo SRAM), a volatile memory, to NAND flash memory, a non-volatile memory. By proceeding with the backup procedure, using NVSRAM can prevent data loss even in fields with unstable voltage supply.

However, NVSRAM still has disadvantages such as being vulnerable to electrical shock, being expensive, and having a low capacity compared to the high price, so continued research is needed to solve these problems.

Moreover, the NVSRAMs of the prior art as described above do not have the function of self-diagnosing the state of the memory and correctly correcting data errors that occur during reading and writing, so data may be damaged due to errors that occur during reading and writing. There were also limitations in preventing losses.

Therefore, in order to solve the limitations of the NVSRAM of the prior art as described above, data loss is minimized and the reliability of the memory is improved by self-identifying the state of the memory and correcting data errors that occur during reading and writing. It would be desirable to propose a memory module structure and design method with a self-diagnosis function of a new configuration configured to increase stability, but no device or method that satisfies all such requirements has yet been proposed.

Korean Patent Publication No. 10-2330018 (2021.11.24.) Korean Patent Publication No. 10-2222813 (2021.03.05.)

The present invention seeks to solve the problems of the prior art as described above. Therefore, the purpose of the present invention is to provide a memory device that can be turned off by providing two memories, a volatile memory and a non-volatile memory. Saving data that was being worked on in volatile memory to non-volatile memory has the advantage of preserving data even when the power is turned off, but it also prevents data loss due to errors that occur in the process of reading and writing data. In order to solve the problems of non-volatile SRAM (NVSRAM) in the prior art, which had limitations, it was necessary to determine the state of the memory through self-diagnosis and correctly correct data errors that occur during reading and writing. The aim is to present an asynchronous non-volatile memory module with a self-diagnosis function that is configured to minimize data loss and increase memory reliability and stability.

In addition, another object of the present invention is to solve the problem of the NVSRAM of the prior art, which had limitations in preventing data loss due to errors occurring in the process of reading and writing data, as described above, by using ECC (Error Correction Code) algorithm, CRC (Cyclic Redundancy Code)32, BBT (Bad Block Table), and Data Check Sum are applied to use the voltage charged in the super capacitor when the power is turned off. PSRAM) data is stored in NAND flash memory. At this time, bad blocks are avoided through BBT and stored in valid blocks, and ECC data, CRC32, and data checksum data are stored together, and then when the power is turned on again. It reads the stored data and compares the CRC32 and data checksum data stored together to determine whether the read content is accurate. If the read content is different, processing is performed to correct the correct data by finding and recovering the incorrect data through ECC. By doing so, the aim is to present an asynchronous non-volatile memory module with a self-diagnosis function that prevents data loss and simultaneously improves the reliability and accuracy of error detection and correction.

In order to achieve the above object, according to the present invention, in an asynchronous non-volatile memory module having a self-diagnosis function, a first memory unit for data processing when power is turned on (ON) ; a second memory unit for storing data when the power is turned off; and a self-diagnosis control unit that controls the operations of the first memory unit and the second memory unit, respectively, and performs a process to correct data errors through self-diagnosis. An asynchronous non-volatile memory module is provided.

Here, the first memory unit is characterized by including PSRAM (Pseudo SRAM) for data processing when power is turned on.

In addition, the second memory unit is characterized by including a NAND flash memory for storing data when the power is turned off.

In addition, the self-diagnosis control unit controls the operations of the PSRAM of the first memory unit and the NAND flash memory of the second memory unit, respectively, and uses an Error Correction Code (ECC) algorithm, Cyclic Redundancy Code (CRC)32, and a preset BBT ( It is characterized by comprising a CPU that diagnoses the state of each memory through self-diagnosis using the Bad Block Table and Data Check Sum and performs processing to correct data errors.

Moreover, when the power is turned off, the self-diagnosis control unit stores the data of the PSRAM in the NAND flash memory using the voltage charged in the supercapacitor, and at this time, avoids bad blocks through the BBT and stores ECC data and CRC32 in valid blocks. and data checksum data, and then, when the power is turned on again, the data stored in the NAND flash memory and the CRC32 and the data checksum data stored together are read, and the CRC32 portion of the read data and the CRC32 inside the CPU are read. Compare, and if there is no error as a result of CRC32 comparison, the read data checksum data and the data checksum data inside the CPU are compared again. If the data contents are different as a result of comparison of CRC32 or data checksum data, an error is made using the ECC algorithm. It is characterized in that it is configured to perform a process of modifying the correct data by finding and recovering the data in which the error has occurred.

In addition, according to the present invention, in the self-diagnosis method of NVSRAM (Non-Volatile SRAM) configured to prevent data errors in NVSRAM (Non-Volatile SRAM), when the power is turned off, the data of PSRAM is stored in NAND flash using the voltage charged in the supercapacitor. A data storage step in which the data is stored in memory, and processing is performed to avoid bad blocks through a preset BBT and store ECC data, CRC32, and data checksum data in valid blocks together; When the power is turned on again, the data stored in the NAND flash memory and the CRC32 and the data checksum data stored together are read, and a CRC comparison step is performed to compare the CRC32 portion of the read data with the CRC32 inside the CPU; A first data recovery step in which, if the content of the data as a result of the CRC comparison step is different, processing to correct the data with correct data by finding and recovering the data in error using an ECC algorithm is performed; If there is no abnormality as a result of the CRC comparison step, a data checksum comparison step is performed to compare the read data checksum data and the data checksum data inside the CPU; If the contents of the data are different as a result of the comparison of the data checksum comparison step, the second data recovery step is performed to correct the correct data by finding and recovering the erroneous data using the ECC algorithm. A self-diagnosis method of the featured NVSRAM is provided.

As described above, according to the present invention, by applying the ECC algorithm, CRC32, BBT, and data checksum, when the power is turned off, the data of the PSRAM is stored in the NAND flash memory using the voltage charged in the super capacitor, and at this time, the BBT It saves in valid blocks to avoid bad blocks, stores ECC data, CRC32, and data checksum data together, and then reads the saved data when the power is turned on again and compares the CRC32 and data checksum data stored together to ensure that the read content is accurate. An asynchronous non-volatile memory module is provided with a self-diagnosis function configured to determine and, if the read content is different, process to correct the correct data by finding and recovering incorrect data through ECC. While preventing data loss due to errors occurring in the process, the reliability and accuracy of error detection and correction can be further improved.

In addition, according to the present invention, it is possible to minimize data loss and increase reliability and stability of memory by identifying the state of the memory through self-diagnosis and correctly correcting data errors that occur during reading and writing, as described above. An asynchronous non-volatile memory module with a self-diagnosis function is provided, so that it has two memories, a volatile memory and a non-volatile memory, so that when the power is turned off, the data working in the volatile memory is provided. There is the advantage of preserving data even when the power is turned off by storing data in non-volatile memory, but it has the limitation of not being able to prevent data loss due to errors that occur during the process of reading and writing data. The problem of NVSRAM can be solved.

Figure 1 is a diagram schematically showing the overall configuration of a prior art NVSRAM.
Figure 2 is a diagram schematically showing the overall configuration of an asynchronous non-volatile memory module with a self-diagnosis function according to an embodiment of the present invention.
Figure 3 is a table showing the NAND flash memory structure for self-diagnosis applied to an asynchronous non-volatile memory module with self-diagnosis function according to an embodiment of the present invention.
Figure 4 is a flowchart schematically showing the operation when the power is turned off during the overall processing of the self-diagnosis algorithm for improving the reliability of NVSRAM data applied to an asynchronous non-volatile memory module with a self-diagnosis function according to an embodiment of the present invention.
Figure 5 is a flow chart schematically showing the operation when power is turned on during the overall processing of the self-diagnosis algorithm for improving the reliability of NVSRAM data applied to an asynchronous non-volatile memory module with a self-diagnosis function according to an embodiment of the present invention.
Figure 6 is a diagram showing the overall processing process of the algorithm that verifies whether the read data is accurate through CRC32 and data checksum during the data reading process.
Figure 7 is a diagram showing the overall processing process of the algorithm for finding erroneous data and correcting it with correct data using the ECC algorithm.
Figure 8 is a diagram showing the operation waveform of NVSRAM when the power is turned off.
Figure 9 is a diagram showing the operation waveform of NVSRAM when power is turned on.
Figure 10 is a diagram showing the waveforms of the data read/write operator CS pin, RD, and WR pins, respectively.

Hereinafter, with reference to the attached drawings, a specific embodiment of an asynchronous non-volatile memory module with a self-diagnosis function according to the present invention will be described.

Here, it should be noted that the content described below is only one embodiment for carrying out the present invention, and the present invention is not limited to the content of the embodiment described below.

In addition, in the description of the embodiments of the present invention below, parts that are the same or similar to the contents of the prior art or that are judged to be easily understood and implemented at the level of those skilled in the art will be described in detail to simplify the explanation. It should be noted that is omitted.

That is, as will be described later, the present invention is provided with two memories, a volatile memory and a non-volatile memory, so that when the power is turned off, the data being worked on in the volatile memory is stored in the non-volatile memory. Non-volatile SRAM (Non-volatile RAM) of the prior art has the advantage of preserving data even when the power is cut off, but has limitations in preventing data loss due to errors that occur in the process of reading and writing data. In order to solve problems with Volatile SRAM (NVSRAM), we minimize data loss and increase memory reliability and stability by identifying the state of the memory through self-diagnosis and correctly correcting data errors that occur during reading and writing. It relates to an asynchronous non-volatile memory module having a self-diagnosis function configured to enable

In addition, as will be described later, the present invention uses ECC (Error Correction Code) to solve the problem of the NVSRAM of the prior art, which has limitations in preventing data loss due to errors occurring in the process of reading and writing data. By applying the algorithm, CRC (Cyclic Redundancy Code) 32, BBT (Bad Block Table), and Data Check Sum, the voltage charged in the super capacitor is used to create pseudo-static RAM (PSRAM) when the power is turned off. Data is stored in NAND flash memory. At this time, bad blocks are avoided through BBT, stored in valid blocks, ECC data, CRC32, and data checksum data are stored together, and then when the power is turned on again, the saved data is stored. It is configured to read and compare the CRC32 and data checksum data stored together to determine whether the read content is accurate. If the read content is different, processing is performed to correct the correct data by finding and recovering the incorrect data through ECC. It relates to an asynchronous non-volatile memory module with a self-diagnosis function configured to prevent data loss and further increase the reliability and accuracy of error detection and correction.

Continuing, with reference to the drawings, specific details of the asynchronous non-volatile memory module with a self-diagnosis function according to the present invention will be described.

More specifically, referring first to FIG. 1, FIG. 1 is a diagram schematically showing the overall configuration of a prior art NVSRAM.

That is, the NVSRAM structure shown in FIG. 1 represents the currently commercialized NVSRAM structure of Cypress. When the power is turned off, the data of the static RAM (SRAM) is stored in a quantum trap, a non-volatile memory. It is configured in a way that is controlled through software.

Here, generally, data consists only of binary numbers 0 and 1, and in the CPU, if it is close to 0, it is recognized as LOW (0), and if it is close to 1, it is recognized as HIGH (1), depending on the value of the voltage. It can be easily distorted and errors occur due to noise or electrical shock.

Therefore, in order to minimize data loss, an auxiliary power stabilization circuit to reliably control the voltage level and a program to recognize the voltage accurately and precisely are required. In addition, to eliminate data errors, an asynchronous non-volatile memory is required. The memory module itself collects various data about the CRC (Cyclic Redundancy Code)32 processing by applying the ECC (Error Correction Code) algorithm to the data, BBT (Bad Block Table) management, power status, and the operation status of the memory module. It is required to design a memory module to determine whether there is an abnormality, reduce errors occurring during operation, and improve data reliability.

In other words, ECC is an algorithm that finds and corrects data with errors and restores the original data. It can be implemented in various ways through software or hardware, and CRC is the most commonly used received data error detection method in communication systems. It is well known.

In addition, bad blocks are bad blocks that exist in NAND flash memory and can occur during production or during use. Using these bad blocks can cause data errors, so do not use bad blocks and use them to ensure normal operation. A method is needed to allow data to be stored only in blocks.

In addition, BBT is a method that connects the physical block number of NAND flash memory with the logical block number to be accessed. Implementation of this BBT is difficult, but if implemented properly, random access is possible. This has the advantage of greatly increasing stability and increasing efficiency of memory management.

Accordingly, in the present invention, to enable the system to operate more efficiently, the data logging algorithm is improved to store BBT, CRC32, data checksum, valid data block, etc. in NAND flash, and through this, the status and relationship of the module are stored. We designed the memory module so that it can operate immediately without any additional power, and in addition, since quick power detection is required when the power is unstable, we designed a Low Power Voltage Detect circuit to immediately transfer PSRAM data to the NAND flash memory when the power is unstable. We proposed a new memory module structure with a self-diagnosis function that allows data to be preserved even in situations where a failure or power is suddenly turned off, thereby providing a significant advantage in terms of time and cost.

That is, referring to FIG. 2, FIG. 2 is a block diagram schematically showing the overall configuration of the asynchronous non-volatile memory module 10 with a self-diagnosis function according to an embodiment of the present invention.

As shown in FIG. 2, the asynchronous nonvolatile memory module 10 with a self-diagnosis function according to an embodiment of the present invention is roughly divided into a first module including a PSRAM for fast data processing when power is turned on. A memory unit 11, a second memory unit 12 including a NAND flash memory for storing data when the power is turned off, and the first memory unit 11 and the second memory unit 12 described above. The operations of the PSRAM and NAND flash memory of the memory unit 12 are controlled respectively, and the status of each memory is diagnosed through a self-diagnosis system as described later to correct errors. It may be configured to include a self-diagnosis control unit 13 including a CPU (STM32H750: 480 MHz) 13.

More specifically, referring to FIG. 3, FIG. 3 shows in a table the NAND flash memory structure for self-diagnosis applied to the asynchronous non-volatile memory module 10 having a self-diagnosis function according to an embodiment of the present invention. It is a drawing.

As shown in FIG. 3, the NAND flash memory structure applied to the present invention has a bad block table on page 0, CRC32 data for bad blocks, CRC32 data for SRAM, and reservation data, respectively. Bad blocks are managed without using the allocated pages, and valid blocks and CRC32 data and self-diagnosis data for each page are allocated and managed in the remaining pages, so when storing data, only normal blocks are used without using bad blocks. It can be configured to prevent data loss due to bad blocks.

Here, the above-mentioned self-diagnosis data may be composed of a CRC error code, a BBT error code, and checksum data, respectively, as shown in FIG. 3.

Also, referring to FIGS. 4 and 5, first, FIG. 4 shows a self-diagnosis algorithm for improving the reliability of NVSRAM data applied to the asynchronous non-volatile memory module 10 having a self-diagnosis function according to an embodiment of the present invention. It is a flowchart schematically showing the operation when the power is turned off during the overall processing process, and Figure 5 is a flowchart schematically showing the operation when the power is turned on.

As shown in Figures 4 and 5, in the existing self-diagnosis method, only the ECC algorithm was applied, but in the present invention, in addition to the ECC algorithm, CRC32, BBT, and Data Check Sum inside the CPU were added to perform self-diagnosis and It is designed to further increase the reliability and accuracy of error correction.

More specifically, first, as shown in FIG. 4, when the power is turned off, an operation is performed to store PSRAM data in NAND flash using the voltage charged in the supercapacitor. At this time, bad blocks are avoided through BBT and effective ECC data, CRC32, and data checksum data are stored together in the block.

Afterwards, as shown in FIG. 5, when the power is turned on again, the data stored in the NAND flash memory and the CRC32 and data checksum data stored together are read, the CRC32 portion of the read data is compared with the CRC32 inside the CPU, and the CRC32 of the CRC32 is compared. If there are no abnormalities as a result of the comparison, compare the read data checksum data and the data checksum data inside the CPU again.

Subsequently, if the contents of the data are different as a result of comparing the CRC32 or data checksum data, the ECC algorithm can be used to find and restore the erroneous data and correct it into correct data.

That is, referring to FIGS. 6 and 7, FIG. 6 is a diagram showing the overall processing process of the algorithm that verifies whether the read data is accurate through CRC32 and data checksum during the data reading process, and FIG. 7 is an ECC algorithm. This is a diagram showing the overall processing process of the algorithm that uses to find erroneous data and correct it with correct data.

As mentioned above, when the power is turned on, the read data is compared with the CRC32 part of the stored data using the CRC32 inside the CPU, the read data is compared again through the data checksum, and finally, the ECC algorithm is used to compare the read data. The reliability of the data can be further improved by checking where the error occurred and correcting the corresponding part of the data with accurate data.

Here, in the embodiment of the present invention described above, for more specific details of the process of detecting and correcting errors using the ECC algorithm, CRC32, and data checksum, those skilled in the art can refer to error correction methods of the prior art. Since this is a matter that can be appropriately configured, it should be noted that in the present invention, detailed description of content that can be easily understood and implemented by a person skilled in the art with reference to prior art literature, etc., has been omitted as described above.

Next, the results of verifying through experiment the actual performance of the asynchronous non-volatile memory module with a self-diagnosis function and the self-diagnosis algorithm according to the embodiment of the present invention configured as described above will be described.

In other words, the present inventors implemented a test bed and conducted experiments to verify the self-diagnosis algorithm proposed in the present invention, and for this purpose, they checked whether the power status and read/write operations were normal through the waveform of the oscilloscope. .

In more detail, first, referring to FIG. 8, FIG. 8 is a diagram showing the operation waveform of the NVSRAM when the power is turned off.

The waveform shown in Figure 8 shows the result that the voltage IVCC supplied to the CPU is maintained at 3.3V even if the external voltage EVCC becomes 0V when the power is turned off. Even if the external voltage is turned off, the voltage supplied to the CPU remains at 3.3V. It provides sufficient time to store PSRAM data in NAND flash.

Also, referring to FIG. 9, FIG. 9 is a diagram showing the operation waveform of the NVSRAM when the power is turned on.

The result shown in Figure 9 is a waveform that reads data in order to reload the data stored in the NAND flash to PSRAM when the power is turned on. When the power is turned on, the data just before turning off is retrieved and the correct data is restored through a self-diagnosis algorithm. This makes it possible to work again.

In addition, referring to FIG. 10, FIG. 10 is a diagram showing the waveforms of the data read/write operator CS pin and RD and WR pins, respectively.

Through the above-described experimental results, it can be confirmed that even if the power supply becomes unstable, the CPU's voltage is normalized and data is preserved, and when power is supplied again, the preserved data can be retrieved and worked again.

As mentioned above, the memory essential to drive the system is mainly volatile memory due to its speed and price difference, but in the field, the voltage can be unstable at any time and it can easily break down. In this case, volatile memory is used for all If the data is erased and all the data is erased without being saved, the data must be recovered from the beginning again at the cost of time and cost.

To solve this problem, NVSRAM was proposed by combining the advantages of non-volatile memory, which is slow but retains data even when the power is turned off, and volatile memory, which is fast but loses data when the power is turned off. It is vulnerable to shock, so data can be easily damaged.

Accordingly, in the present invention, a self-diagnosis algorithm was applied to minimize data loss. To this end, not only ECC, which detects damage to data through self-diagnosis and corrects the damaged data to the original correct data, but also ensures that the data is normal. The reliability and accuracy of writing/reading data were improved by using the CRC32 inside the CPU to check the reliability and adding a data check sum, and the possibility of commercialization was suggested.

Therefore, as described above, an asynchronous non-volatile memory module having a self-diagnosis function according to an embodiment of the present invention can be implemented, whereby, according to the present invention, by applying the ECC algorithm, CRC32, BBT, and data checksum, When the power is turned off, the PSRAM data is stored in the NAND flash memory using the voltage charged in the super capacitor. At this time, bad blocks are avoided through BBT and stored in valid blocks, and ECC data, CRC32, and data checksum data are stored together. When the power is turned on again, the saved data is read and compared with the CRC32 and data checksum data stored together to determine whether the read content is accurate. If the read content is different, the correct data is restored by finding and recovering the incorrect data through ECC. By providing an asynchronous non-volatile memory module with a self-diagnosis function configured to perform correction processing, data loss due to errors occurring in the process of reading and writing data is provided, while ensuring reliability and accuracy of error detection and correction. It can be raised even further.

In addition, according to the present invention, it is possible to minimize data loss and increase reliability and stability of memory by identifying the state of the memory through self-diagnosis and correctly correcting data errors that occur during reading and writing, as described above. An asynchronous non-volatile memory module with a self-diagnosis function is provided, so that it has two memories, a volatile memory and a non-volatile memory, so that when the power is turned off, the data working in the volatile memory is provided. There is the advantage of preserving data even when the power is turned off by storing data in non-volatile memory, but it has the limitation of not being able to prevent data loss due to errors that occur during the process of reading and writing data. The problem of NVSRAM can be solved.

Above, the details of the asynchronous non-volatile memory module having a self-diagnosis function according to the present invention have been described through the embodiments of the present invention as described above. However, the present invention is not limited to the contents described in the above-described embodiments. Therefore, it is natural that the present invention can be modified, changed, combined, and replaced in various ways by those skilled in the art according to design needs and various other factors.

10. Asynchronous non-volatile memory module with self-diagnosis function
11. First memory unit
12. Second memory unit
13. Self-diagnosis control unit

Claims (6)

In an asynchronous non-volatile memory module with a self-diagnosis function,
A first memory unit including PSRAM (Pseudo SRAM) for data processing when power is turned on (ON);
a second memory unit including NAND flash memory for storing data when the power is turned off;
It controls the operation of the PSRAM of the first memory unit and the NAND flash memory of the second memory unit, respectively, and uses an Error Correction Code (ECC) algorithm, Cyclic Redundancy Code (CRC)32, a preset Bad Block Table (BBT), and a data checksum ( It is configured to include a self-diagnosis control unit including a CPU that diagnoses the state of each memory through self-diagnosis using (Data Check Sum) and performs processing to correct data errors,
The self-diagnosis control unit,
When the power is turned off, the data of the PSRAM is stored in the NAND flash memory using the voltage charged in the supercapacitor. At this time, bad blocks are avoided through the BBT and ECC data, CRC32, and data checksum data are stored together in the valid block. ,
Afterwards, when the power is turned on again, the data stored in the NAND flash memory and the CRC32 and the data checksum data stored together are read, and the CRC32 portion of the read data is compared with the CRC32 inside the CPU,
If there is no abnormality as a result of CRC32 comparison, the read data checksum data and the data checksum data inside the CPU are compared again.
If the data contents are different as a result of comparing CRC32 or data checksum data, the ECC algorithm is used to find and restore the erroneous data and correct it with the correct data.
In addition to being able to preserve data even when the power is turned off, it is designed to prevent data loss due to errors that occur in the process of reading and writing data when the power is turned off, and to increase the reliability and accuracy of error detection and correction. An asynchronous non-volatile memory module with a self-diagnosis function.
According to clause 1,
The NAND flash memory is,
The Bad Block Table, CRC32 data for bad blocks, CRC32 data for SRAM, and reservation data are allocated to page 0, respectively, to manage bad blocks without using the page, and are valid for the remaining pages. Self-diagnosis data including CRC32 data, CRC error code, BBT error code, and checksum data for each block and each page are allocated and managed, respectively.
An asynchronous non-volatile memory module with a self-diagnosis function, which is configured to prevent data loss due to bad blocks by using only normal blocks instead of bad blocks when storing data.
delete delete delete In the NVSRAM self-diagnosis method configured to prevent data errors in NVSRAM (Non-Volatile SRAM),
When the power is turned off, the data in the PSRAM is stored in the NAND flash memory using the voltage charged in the supercapacitor. At this time, processing is performed to avoid bad blocks through preset BBT and store ECC data, CRC32, and data checksum data together in valid blocks. A data storage step is performed;
When the power is turned on again, the data stored in the NAND flash memory and the CRC32 and the data checksum data stored together are read, and a CRC comparison step is performed to compare the CRC32 portion of the read data with the CRC32 inside the CPU;
A first data recovery step in which, if the content of the data as a result of the CRC comparison step is different, processing to correct the data with correct data by finding and recovering the data in error using an ECC algorithm is performed;
If there is no abnormality as a result of the CRC comparison step, a data checksum comparison step is performed to compare the read data checksum data and the data checksum data inside the CPU;
If the contents of the data are different as a result of the comparison of the data checksum comparison step, the second data recovery step is performed to correct the correct data by finding and recovering the erroneous data using the ECC algorithm. Characteristic self-diagnosis method of NVSRAM.