KR102570581B1 - Storage device set including storage device and reconfigurable logic chip, and storage system including storage device set - Google Patents

Abstract

The present disclosure discloses a set of storage devices. The set of storage devices includes: a storage device including a controller that encrypts data to generate encrypted input data and is capable of communicating with a host; receives encrypted input data from the storage device; and receives encrypted input data according to a predetermined configuration. It includes a reconfigurable logic chip that generates processed data by processing the data and encrypts the processed data to generate encrypted output data.

Description

Storage device set including storage device and reconfigurable logic chip, and storage system including storage device set}

The technical idea of the present disclosure relates to a storage device, and more particularly, to a storage device set including a storage device and a reconfigurable logic chip, a storage system including the storage device set, and a method of operating the storage device. will be.

In order to improve the processing speed of the storage system, an accelerator assisting the operation of the host by performing some of the operations performed by the host may be added to the storage system. Accelerators can be classified into dedicated hardware accelerators that perform set functions and reconfigurable accelerators according to design files such as FPGA (Field Programmable Gate Array) images. Recently, since a host performs various applications and high-speed processing for each application is required, a demand for a reconfigurable accelerator such as an FPGA that can be reconfigured to correspond to various applications is increasing.

Technical features of the present disclosure provide a storage device set including a storage device and a reconfigurable logic chip, a storage system including the storage device set, and a method of operating the storage device to reduce overhead of a host.

A storage device according to the technical idea of the present disclosure includes a controller that encrypts data to generate encrypted input data, a storage device capable of communicating with a host, and receiving the encrypted input data from the storage device, and a reconfigurable logic chip generating processed data by processing the encrypted input data according to a configuration and generating encrypted output data by encrypting the processed data.

A storage system according to technical features of the present disclosure includes a host, a reconfigurable logic chip, and a storage device configured to communicate with the host through a first port and communicate with the reconfigurable logic chip through a second port, The storage device transmits encrypted input data to the reconfigurable logic chip through the second port and receives encrypted output data from the reconfigurable logic chip through the second port.

According to the technical idea of the present disclosure, a method of operating a storage device includes receiving a host command including a data processing request from a host through a first port of the storage device, encrypting data through a second port of the storage device. Transmitting a command instructing data processing of the encrypted data and the encrypted data to a reconfigurable logic chip, and receiving encrypted processing data from the reconfigurable logic chip through the second port of the storage device. Include steps.

A storage device set according to technical features of the present disclosure may improve security of the storage device set by performing encrypted communication between the storage device and the reconfigurable logic chip. In addition, the storage device includes a buffer memory, the buffer memory can buffer data to be processed in the reconfigurable logic chip and data processed in the reconfigurable logic chip, and the host and the reconfigurable logic chip can access the buffer memory. there is. Accordingly, data can be exchanged even though the host and the reconfigurable logic chip are not directly connected. In addition, the storage device does not have to directly provide the data processed in the reconfigurable logic chip to the host.

1 schematically illustrates a storage system according to an embodiment of the present disclosure.
2 is a detailed block diagram of a storage device set according to an exemplary embodiment of the present disclosure.
3 is a flowchart illustrating a method of operating a storage device according to an exemplary embodiment of the present disclosure.
FIG. 4 is a flowchart illustrating an example of an operation between a host, a storage device, and a reconfigurable logic chip of FIG. 2 .
FIG. 5 is a flowchart illustrating another example of an operation between a host, a storage device, and a reconfigurable logic chip of FIG. 2 .
6 illustrates an example of an operation of the storage device set of FIG. 2 .
FIG. 7 is a flowchart illustrating operations between the controller, buffer memory and reconfigurable logic chip of FIG. 6 .
FIG. 8 shows another example of an operation of the storage device set of FIG. 2 .
9 is a flowchart illustrating operations among the nonvolatile memory, the controller, the buffer memory and the reconfigurable logic chip of FIG. 8 .
10 is a block diagram showing the controller of FIG. 2 in detail.
FIG. 11 is a block diagram illustrating a modified example of the controller of FIG. 10 .
12 is a detailed block diagram of a storage device set according to an exemplary embodiment of the present disclosure.
13 illustrates an example of an operation of the storage device set of FIG. 12 .
14 is a flowchart illustrating an example of an operation between the controller of FIG. 13 and a reconfigurable logic chip.
15 illustrates another example of an operation of the storage device set of FIG. 12 .
FIG. 16 is a flowchart illustrating an example of an operation between the nonvolatile memory of FIG. 15 , a controller, and a reconfigurable logic chip.
17 illustrates an example of an operation of a storage device set according to an embodiment of the present disclosure.
18 is a flowchart illustrating an example of an operation between the controller of FIG. 17 and a reconfigurable logic chip.
19 illustrates another example of an operation of a storage device set according to an embodiment of the present disclosure.
FIG. 20 is a flowchart illustrating an example of an operation between the nonvolatile memory of FIG. 19 , a controller, and a reconfigurable logic chip.
21 illustrates a storage system according to an embodiment of the present disclosure.
22 shows a network system according to an embodiment of the present disclosure.
23 shows a network system according to an embodiment of the present disclosure.

1 schematically shows a storage system SS according to an embodiment of the present disclosure.

Referring to FIG. 1 , a storage system (SS) includes a storage device set 10 and a host 300, and the storage device set 10 includes a storage device 100 and a reconfigurable logic chip (reconfigurable logic chip). logic chip) (200). The storage device 100 may include a first port PT1 and a second port PT2 , and thus the storage device 100 may be referred to as a dual port storage device.

In one embodiment, the storage device 100 may be implemented as a first chip, and the reconfigurable logic chip 200 may be implemented as a second chip, and the first chip and the second chip may be mounted on a single board and electrically electrical to each other. can be connected to In one embodiment, the storage device 100 may be implemented as a first chip, the reconfigurable logic chip 200 may be implemented as a second chip, and the first chip and the second chip may be implemented as a POP (Package-On-Package) ) can be configured. However, the present invention is not limited thereto, and the storage device 100 and the reconfigurable logic chip 200 may be electrically connected to each other through an arbitrary configuration to configure the storage device set 10 .

In one embodiment, the reconfigurable logic chip 200 may be a Field Programmable Gate Array (FPGA) chip. However, the present invention is not limited thereto, and the reconfigurable logic chip 200 may be a programmable logic device (PLD) or a complex PLD (CPLD). The reconfigurable logic chip 200 may be used as an accelerator assisting the operation of the host 300 by performing some of the operations performed by the host 300 .

The storage device 100 may communicate with the host 300 through the first port PT1. Specifically, the storage device 100 may communicate with the host 300 through the first port PT1 according to the first interface protocol. For example, the first interface protocol may be Peripheral Component Interconnect Express (PCIe). However, the present invention is not limited thereto, and the first interface protocol is USB (Universal Serial Bus), PCI, ATA (AT Attachment), SATA (Serial AT Attachment), PATA (Parallel AT Attachment), SCSI (Small Computer System Interface) ), SAS (Serial Attached SCSI), ESDI (Enhanced Small Disk Interface), IDE (Integrated Drive Electronics), etc.

In one embodiment, the first port PT1 may be connected to a PCIe bus, and the host 300 may include a root complex (RC) connected to the PCIe bus. The root complex RC may manage transactions between the host 300 and the storage device 100 . For example, a root complex (RC) may route messages related to a transaction. A root complex (RC) may include a logical aggregation of root ports, root complex register blocks, or endpoints into which the root complex is integrated.

In one embodiment, the root complex RC may be directly connected to the storage device 100 . In one embodiment, the root complex RC may be connected to the storage device 100 through at least one interface switch. In one embodiment, the root complex (RC) may be implemented as a device separate from a central processing unit (CPU) included in the host 300 . In one embodiment, the root complex (RC) may be implemented to be integrated with a CPU included in the host 300 .

The storage device 100 may communicate with the reconfigurable logic chip 200 through the second port PT2 . Specifically, it may communicate with the reconfigurable logic chip 200 through the second port PT2 according to the second interface protocol. As such, the reconfigurable logic chip 200 does not include a port directly connected to the host 300, and the host 300 may communicate with the reconfigurable logic chip 200 through the storage device 100. .

In this embodiment, the storage device 100 and the reconfigurable logic chip 200 may perform encrypted communication. The storage device 100 may transmit encrypted data to the reconfigurable logic chip 200 through the second port PT2, and transmit the encrypted data to the reconfigurable logic chip 200 through the second port PT2. can be received from Specifically, the storage device 100 may include an encryption/decryption module 111, and the encryption/decryption module 111 may generate encrypted data by encrypting data. Also, the reconfigurable logic chip 200 may include an encryption/decryption module 210, and the encryption/decryption module 210 may decrypt encrypted data received from the storage device 100 and may be reconfigurable. Data processed in the logic chip 200 may be encrypted.

In one embodiment, the storage device 100 may be a block storage device that manages data in block units. In one embodiment, the storage device 100 may be an object storage device that manages data in object units. For example, the storage device 100 may be a key-value storage device. A key-value storage device is a device that quickly and simply processes data using a key-value pair. Here, a "key-value pair" is a pair of a key having uniqueness and a value that is data corresponding to the key, and may be referred to as a "tuple" or a "key-value tuple". In a key-value pair, the key is represented by an arbitrary string such as a file name, Uniform Resource Identifier (URI), or hash, and the value is represented by any kind of image, user-preferred file, or document. can be data.

The storage system SS may be implemented as, for example, a personal computer (PC), a data server, a network-attached storage, an Internet of Things (IoT) device, or a portable electronic device. Portable electronic devices include laptop computers, mobile phones, smart phones, tablet PCs, personal digital assistants (PDAs), enterprise digital assistants (EDAs), digital still cameras, digital video cameras, audio devices, portable multimedia players (PMPs), and PNDs. (personal navigation device), MP3 player, handheld game console, e-book, wearable device, and the like.

In some embodiments, the storage device 100 may be an internal memory embedded in an electronic device. For example, the storage device 100 may be an SSD, an embedded universal flash storage (UFS) memory device, or an embedded multi-media card (eMMC). In some embodiments, the storage device 100 may be an external memory removable from an electronic device. For example, the storage device 100 may include a UFS memory card, Compact Flash (CF), Secure Digital (SD), Micro Secure Digital (Micro-SD), Mini Secure Digital (Mini-SD), extreme Digital (xD), or It may be a memory stick.

2 is a detailed block diagram of a storage device set 10 according to an exemplary embodiment of the present disclosure.

Referring to FIG. 2 , the storage device 100 may include a controller 110, a buffer memory 120, and a non-volatile memory (NVM) 130, and the controller 110 may encrypt/ A decryption module 111 may be included. In one embodiment, the controller 110, buffer memory 120 and non-volatile memory 130 may each be implemented as separate chips. In one embodiment, the controller 110 and the buffer memory 120 may perform encrypted communication. In one embodiment, the controller 110 and the non-volatile memory 130 may perform encrypted communication. In one embodiment, the controller 110 and the reconfigurable logic chip 200 may perform cryptographic communication.

The reconfigurable logic chip 200 may include an encryption/decryption module 210 and an accelerator 220 . The encryption/decryption module 210 may receive encrypted input data from the storage device 100 and decrypt the encrypted input data to generate decrypted data. Also, the encryption/decryption module 210 may receive processed data from the accelerator 220 and encrypt the processed data to generate encrypted output data. In some embodiments, the reconfigurable logic chip 200 may further include a root complex, and data received from the storage device 100 may be delivered to the encryption/decryption module 210 through the root complex.

The accelerator 220 may perform a data processing operation according to a predetermined configuration. The reconfigurable logic chip 200 may be reconfigured during operation, and accordingly, the accelerator 220 may operate as a first accelerator and change to a second accelerator. For example, the accelerator 220 may perform multimedia transcoding or eraser coding. For example, the accelerator 220 may perform machine learning algorithms such as convolutional neural networks (CNNs) and recurrent neural networks (RNNs).

Further, for example, the accelerator 220 may perform inline processing, pre-processing, pre-filtering, cryptography, compression, protocol bridging, and the like. can For example, the accelerator 220 may perform one or more of a sorting operation, a searching operation, a logic operation, or four arithmetic operations. The logic operation may represent an operation performed by various logic gates such as an AND gate, an OR gate, an XOR gate, a NOR gate, and a NAND gate, or an operation operation combining two or more of these operations. The calculation operation performed by the accelerator 220 is not limited to the example described above, and may be any calculation corresponding to some of the calculations performed by the host 300 .

The host 300 may transmit a host command including a data processing request to the storage device 100 . The storage device 100 may transmit a command instructing data processing to the reconfigurable logic chip 200 in response to a host command. Also, the storage device 100 may transmit data to be processed to the reconfigurable logic chip 200 . In one embodiment, the encryption/decryption module 111 may generate encrypted input data by encrypting data to be processed, and the controller 110 may transmit the encrypted input data to the reconfigurable logic chip 200 .

The reconfigurable logic chip 200 may receive commands and data, generate processed data by performing data processing on the received data, and transmit the processed data to the storage device 100 . In one embodiment, the encryption/decryption module 210 may generate decrypted data by decrypting the encrypted input data, and may provide the decrypted data to the accelerator 220 . The accelerator 220 may generate processed data by performing data processing on the decrypted data and provide the processed data to the encryption/decryption module 210 . The encryption/decryption module 210 may generate encrypted output data by encrypting processed data.

Also, the host 300 may transmit a host command including a write request or a read request to the storage device 100 , and the storage device 100 reads data from the nonvolatile memory 130 in response to the read request. In response to a write request, data may be written to the non-volatile memory 130 . The controller 110 writes data into the non-volatile memory 130 in response to a write request received from the host 300, or data from the non-volatile memory 130 in response to a read request received from the host 300. It is possible to control the non-volatile memory 130 to read.

The buffer memory 120 may buffer input data (ID) to be processed in the reconfigurable logic chip 200 . In one embodiment, the input data ID may be encrypted data. However, the present invention is not limited thereto, and in some embodiments, the input data ID may be unencrypted normal data. Also, the buffer memory 120 may buffer data processed by the reconfigurable logic chip 200, for example, first output data OD1 and second output data OD2. In one embodiment, the first and second output data OD1 and OD2 may be encrypted data. However, the present invention is not limited thereto, and in some embodiments, the first and second output data OD1 and OD2 may be normal data. For example, the buffer memory 120 may be a volatile memory such as Dynamic Random Access Memory (DRAM).

In one embodiment, the buffer memory 120 may be a Control Memory Buffer (CMB). The host 300 and the reconfigurable logic chip 200 may access the buffer memory 120 . Accordingly, the host 300 and the reconfigurable logic chip 200 may exchange data through the buffer memory 120 even though they are not directly connected to each other.

For example, the host 300 may load data to be processed in the reconfigurable logic chip 200 into the buffer memory 120, and the reconfigurable logic chip 200 may load the data loaded into the buffer memory 120. can be processed For example, the reconfigurable logic chip 200 may load processing data into the buffer memory 120 , and the host 300 may read the processing data loaded into the buffer memory 120 . As such, since the host 300 can access the buffer memory 120, the storage device 100 does not provide processing data to the host 300 after data processing of the reconfigurable logic chip 200, and data processing A response message indicating completion of the process may be transmitted to the host 300 .

The non-volatile memory 130 may include a memory cell array including a plurality of memory cells. In one embodiment, the non-volatile memory 130 may include a flash memory device, for example, a NAND flash memory device. However, the present invention is not limited thereto, and the nonvolatile memory 130 may include a resistive memory device such as a resistive RAM (ReRAM), a phase change RAM (PRAM), or a magnetic RAM (MRAM).

3 is a flowchart illustrating a method of operating a storage device according to an exemplary embodiment of the present disclosure. Referring to FIG. 3 , the operating method of the storage device according to the present embodiment may include steps sequentially performed in the storage device 100 of FIG. 2 . Hereinafter, it will be described with reference to FIGS. 2 and 3 together.

In operation S110 , the storage device 100 receives a host command including a data processing request from the host 300 . In one embodiment, the storage device 100 may receive data along with a host command. In one embodiment, the storage device 100 may receive data from the host 300 after receiving a host command. In one embodiment, the storage device 100 may read data from the buffer memory 120 or the non-volatile memory 130 .

In step S130 , the storage device 100 transmits a command instructing data processing and encrypted data to the reconfigurable logic chip 200 . In one embodiment, the storage device 100 first transmits a command to the reconfigurable logic chip 200, and then, in response to a read request from the reconfigurable logic chip 200, the storage device 100 transmits encrypted data to the reconfigurable logic chip 200. ) can be transmitted. In one embodiment, the storage device 100 may transmit a command and encrypted data to the reconfigurable logic chip 200 together.

In one embodiment, between steps S110 and S130, the storage device 100 may perform a data encryption operation. For example, the encryption/decryption module 111 may encrypt data to be processed in the reconfigurable logic chip 200 . In one embodiment, the storage device 100 may read encrypted data from the buffer memory 120 or the nonvolatile memory 130 . In one embodiment, the storage device 100 may receive encrypted data from the host 300 .

In step S150 , the storage device 100 receives encrypted processed data from the reconfigurable logic chip 200 . In one embodiment, the storage device 100 may store encrypted processed data in the buffer memory 120 or the non-volatile memory 130 . In one embodiment, the storage device 100 may transmit encrypted processing data to the host 300 . In one embodiment, the storage device 100 may decrypt encrypted processed data. In one embodiment, the storage device 100 may store the decrypted processed data in the buffer memory 120 or the non-volatile memory 130 . In one embodiment, the storage device 100 may transmit decrypted processed data to the host 300 .

FIG. 4 is a flowchart illustrating an example of an operation between the host 300 of FIG. 2 , the storage device 100 and the reconfigurable logic chip 200 .

Referring to FIG. 4 , the host 300 generates a host command including a data processing request (S200). For example, the host 300 may generate a host command instructing the reconfigurable logic chip 200 a CNN required for image recognition in response to a user input instructing execution of an image recognition application. The host 300 transmits a host command to the storage device 100 (S210).

The storage device 100 encrypts data to be processed in the reconfigurable logic chip 200 to generate encrypted input data (S220). For example, the storage device 100 may generate encrypted input data by encrypting an image file that is an image recognition target. For example, the storage device 100 may encrypt data received from the host 300 and data read from the buffer memory 120 or the non-volatile memory 130 . In one embodiment, the storage device 100 may receive encrypted data, and in this case, S220 may be omitted.

The storage device 100 transmits a command instructing data processing to the reconfigurable logic chip 200 (S230). The storage device 100 transmits the encrypted input data to the reconfigurable logic chip 200 (S235). The reconfigurable logic chip 200 generates decrypted data by decrypting the encrypted input data (S240). The reconfigurable logic chip 200 generates processed data by processing the decoded data according to a predetermined configuration (S250). The reconfigurable logic chip 200 generates encrypted output data by encrypting the processed data (S260). The reconfigurable logic chip 200 transmits the encrypted output data to the storage device 100 (S270).

The storage device 100 performs a write operation on encrypted output data. For example, the storage device 100 may write encrypted output data into the buffer memory 120 or the nonvolatile memory 130 . In one embodiment, the storage device 100 may decrypt encrypted output data and perform a write operation on the decrypted output data. The storage device 100 transmits a response message indicating that data processing has been completed to the host 300 .

FIG. 5 is a flowchart illustrating another example of an operation between the host 300 , the storage device 100 and the reconfigurable logic chip 200 of FIG. 2 .

Referring to FIG. 5 , the present embodiment corresponds to the modified example of FIG. 4 , and hereinafter, differences from the operation illustrated in FIG. 4 will be mainly described. The host 300 generates a host command including a multi-data set processing request, that is, a host command instructing processing of the multi-data set (S300). Here, the multi-data set refers to a plurality of data related to the host command. In addition, a host command including a multi-data set processing request may instruct the reconfigurable logic chip 200 to output a plurality of data, ie, a multi-data set, by performing a plurality of data processing operations in response to the host command. there is. For example, a host command containing a multi-data set processing request may be a transcoding command. The host 300 transmits a host command to the storage device 100 (S310).

The storage device 100 encrypts data to be processed in the reconfigurable logic chip 200 to generate encrypted input data (S320). For example, the storage device 100 may generate encrypted input data by encrypting a multimedia file to be transcoded. The storage device 100 transmits a command instructing data processing to the reconfigurable logic chip 200 (S330). The storage device 100 transmits the encrypted input data to the reconfigurable logic chip 200 (S335). For example, the encrypted input data may be encrypted data for a multimedia file having a scalable format. The reconfigurable logic chip 200 generates decrypted data by decrypting the encrypted input data (S340). For example, the reconfigurable logic chip 200 may generate a multimedia file having a scalable format by decrypting encrypted input data.

The reconfigurable logic chip 200 generates first processed data by processing the decrypted data according to a predetermined configuration, and generates encrypted first output data by encrypting the first processed data (S350). For example, the reconfigurable logic chip 200 may generate a first multimedia file having a first format by transcoding a multimedia file having a scalable format. Subsequently, the reconfigurable logic chip 200 may generate an encrypted first multimedia file by encrypting the first multimedia file.

The reconfigurable logic chip 200 transmits the encrypted first output data to the storage device 100 (S355). For example, the reconfigurable logic chip 200 may transmit the encrypted first multimedia file to the storage device 100 . The storage device 100 performs a write operation on the encrypted first output data (S360). For example, the storage device 100 may write the encrypted first multimedia file into the buffer memory 120 or the nonvolatile memory 130 .

The reconfigurable logic chip 200 generates second processed data by processing the decrypted data according to a predetermined configuration, and generates encrypted second output data by encrypting the second processed data (S370). For example, the reconfigurable logic chip 200 may generate a second multimedia file having a second format by transcoding a multimedia file having a scalable format. Subsequently, the reconfigurable logic chip 200 may generate an encrypted second multimedia file by encrypting the second multimedia file. In one embodiment, step S370 may be performed while steps S355 and S360 are performed. However, the present invention is not limited thereto, and step S370 may be performed before step S355.

The reconfigurable logic chip 200 transmits the encrypted second output data to the storage device 100 (S375). For example, the reconfigurable logic chip 200 may transmit the encrypted second multimedia file to the storage device 100 . The storage device 100 performs a write operation on the encrypted second output data (S380). For example, the storage device 100 may write the encrypted second multimedia file into the buffer memory 120 or the non-volatile memory 130 . The storage device 100 transmits a response message indicating that data processing has been completed to the host 300 (S390).

FIG. 6 shows an example of an operation of the storage device set 10 of FIG. 2 .

Referring to FIG. 6 , the host 300 may transmit a data write request and a host command including data to the storage device 100 . In one embodiment, the encryption/decryption module 111 may encrypt data and load the encrypted data into the buffer memory 120 . Subsequently, the reconfigurable logic chip 200 may read the encrypted data loaded into the buffer memory 120 . In another embodiment, the storage device 100 may load data received from the host 300 into the buffer memory 120 . Subsequently, when a read request is received from the reconfigurable logic chip 200, the encryption/decryption module 111 encrypts the data loaded into the buffer memory 120 and transmits the encrypted data to the reconfigurable logic chip 200. may be

The encryption/decryption module 210 may decrypt encrypted data and provide the decrypted data to the accelerator 220 . The accelerator 220 may generate processed data by processing data according to a predetermined configuration. Next, the encryption/decryption module 210 may encrypt processed data and write the encrypted data into the buffer memory 120 . Subsequently, the host 300 may read processing data from the buffer memory 120 .

FIG. 7 is a flowchart illustrating operations between the controller 110, the buffer memory 120 and the reconfigurable logic chip 200 of FIG. 6 .

Referring to FIG. 7 , the controller 110 receives a data write request and a host command including data from the host 300 (S400). The encryption/decryption module 111 included in the controller 110 generates encrypted input data by encrypting the received data (S410). The controller 110 transmits the encrypted input data to the buffer memory 120 (S420). The buffer memory 120 loads the encrypted input data (S430). When loading of the encrypted input data is completed, the buffer memory 120 transmits a response message to the controller 110 (S435).

The controller 110 transmits a command instructing data processing to the reconfigurable logic chip 200 (S440). The reconfigurable logic chip 200 transmits a read command to the buffer memory 120 (S445). The buffer memory 120 performs a read operation (S450) and transmits the encrypted input data to the reconfigurable logic chip 200 (S460). The reconfigurable logic chip 200 decrypts the encrypted input data to generate decrypted data, processes the decrypted data to generate processed data, and encrypts the processed data to generate encrypted output data (S470). The reconfigurable logic chip 200 transmits the encrypted output data to the buffer memory 120 (S475). The buffer memory 120 loads the encrypted output data (S480). The buffer memory 120 transmits a response message indicating completion of writing to the reconfigurable logic chip 200 (S485). The reconfigurable logic chip 200 transmits a response message indicating that data processing is finished to the controller 110 (S490).

FIG. 8 shows another example of an operation of the storage device set 10 of FIG. 2 .

Referring to FIG. 8 , the host 300 may transmit a host command including a data processing request to the storage device 100 . The controller 110 may read data stored in the nonvolatile memory 130 and load the read data into the buffer memory 120 . In one embodiment, the encryption/decryption module 111 may encrypt the read data and provide the encrypted data to the buffer memory 120 . In one embodiment, the controller 110 may read encrypted data from the nonvolatile memory 130 and load the read encrypted data into the buffer memory 120 .

The reconfigurable logic chip 200 may read encrypted data loaded into the buffer memory 120 . The encryption/decryption module 210 may decrypt encrypted data and provide the decrypted data to the accelerator 220 . The accelerator 220 may generate processed data by processing data according to a predetermined configuration. Next, the encryption/decryption module 210 may encrypt processed data and write the encrypted data into the buffer memory 120 . Subsequently, the host 300 may read processing data from the buffer memory 120 .

FIG. 9 is a flowchart illustrating operations among the non-volatile memory 130 , the controller 110 , the buffer memory 120 and the reconfigurable logic chip 200 of FIG. 8 .

Referring to FIG. 9 , the controller 110 receives a host command including a data processing request from the host 300 (S500). The controller 110 transmits a read command to the non-volatile memory 130 (S505). In an embodiment, the controller 110 may check a physical address at which data to be processed is stored by referring to the mapping table, and may transmit a read command including the physical address to the nonvolatile memory 130 . The non-volatile memory 130 performs a read operation (S510) and transmits data to the controller 110 (S515).

The encryption/decryption module 111 included in the controller 110 generates encrypted input data by encrypting the received data (S520). The controller 110 transmits the encrypted input data to the buffer memory 120 (S525). The buffer memory 120 loads encrypted input data (S530). When loading of the encrypted input data is completed, the buffer memory 120 transmits a response message to the controller 110 (S535).

The controller 110 transmits a command instructing data processing to the reconfigurable logic chip 200 (S540). The reconfigurable logic chip 200 transmits a read command to the buffer memory 120 (S545). The buffer memory 120 performs a read operation (S550) and transmits the encrypted input data to the reconfigurable logic chip 200 (S560). The reconfigurable logic chip 200 decrypts the encrypted input data to generate decrypted data, processes the decrypted data to generate processed data, and encrypts the processed data to generate encrypted output data (S570). The reconfigurable logic chip 200 transmits the encrypted output data to the buffer memory 120 (S575). The buffer memory 120 loads the encrypted output data (S580). The buffer memory 120 transmits a response message indicating completion of writing to the reconfigurable logic chip 200 (S585). The reconfigurable logic chip 200 transmits a response message indicating that data processing is finished to the controller 110 .

FIG. 10 is a block diagram showing the controller 110 of FIG. 2 in detail.

Referring to FIG. 10, the controller 110 includes an encryption/decryption module 111, a processor 112, a memory 113, a host interface 114, an FPGA interface 115, a volatile memory interface 116, and a non-volatile memory interface 116. memory interface 117, which can communicate with each other via a bus 118. For example, reconfigurable logic chip 200 may be an FPGA. In one embodiment, the encryption/decryption module 111 may be implemented in software or firmware and may be loaded into the memory 113 . However, the present invention is not limited thereto, and the encryption/decryption module 111 may be implemented in hardware.

The processor 112 may include a central processing unit or a microprocessor, and may control overall operations of the controller 110 . In one embodiment, processor 112 may be implemented as a multi-core processor, such as a dual-core processor or quad-core processor. The memory 113 operates under the control of the processor 112 and may be used as an operating memory, a buffer memory, a cache memory, and the like. For example, the memory 113 may be implemented as a volatile memory such as DRAM or SRAM or a non-volatile memory such as PRAM or flash memory.

The host interface 114 may provide an interface between the host 300 and the controller 110 and may include, for example, the first port PT1 of FIG. 1 . The FPGA interface 115 may provide an interface between the controller 110 and the FPGA, that is, the reconfigurable logic chip 200, and may include, for example, the second port PT2 of FIG. 1 . In one embodiment, the FPGA interface 115 may receive encrypted data from the encryption/decryption module 111 and provide the encrypted data to the reconfigurable logic chip 200 . Also, the FPGA interface 115 may receive encrypted data from the reconfigurable logic chip 200 and provide the encrypted data to the encryption/decryption module 111 .

Volatile memory interface 116 may provide an interface between controller 110 and volatile memory, such as buffer memory 120 of FIG. 2 . In one embodiment, the volatile memory interface 116 may receive encrypted data from the encryption/decryption module 111 and provide the encrypted data to the buffer memory 120 . Also, the volatile memory interface 116 may receive encrypted data from the buffer memory 120 and provide the encrypted data to the encryption/decryption module 111 .

The non-volatile memory interface 117 may provide an interface between the controller 110 and the non-volatile memory 130 . In one embodiment, the non-volatile memory interface 117 may receive encrypted data from the encryption/decryption module 111 and provide the encrypted data to the non-volatile memory 130 . Also, the nonvolatile memory interface 117 may receive encrypted data from the nonvolatile memory 130 and provide the encrypted data to the encryption/decryption module 111 . In one embodiment, the number of non-volatile memory interfaces 117 may correspond to the number of non-volatile memory chips included in the storage device 100 or the number of channels between the controller 110 and the non-volatile memory 130. there is.

FIG. 11 is a block diagram illustrating a modified example 110' of the controller of FIG. 10 .

Referring to FIG. 11, the controller 110' includes a processor 112, a memory 113, a host interface 114, an FPGA interface 115', a volatile memory interface 116', and a non-volatile memory interface 117'. ), which may communicate with each other via the bus 118. Hereinafter, differences between the controller 110' according to the present embodiment and the controller 110 of FIG. 10 will be mainly described.

The FPGA interface 115' may include an encryption/decryption module 115a. The encryption/decryption module 115a encrypts data received from the memory 113, the host 300, the buffer memory 120 or the nonvolatile memory 130, and transfers the encrypted data to the reconfigurable logic chip 200. can provide In addition, the encryption/decryption module 115a receives encrypted data from the reconfigurable logic chip 200 and decrypts the encrypted data so that the memory 113, the host 300, the buffer memory 120 or the non-volatile memory (130).

The volatile memory interface 116' may include an encryption/decryption module 116a, and the encryption/decryption module 116a may be selectively activated. In one embodiment, the encryption/decryption module 116a may encrypt data received from the memory 113, the host 300, or the non-volatile memory 130 and provide the encrypted data to the buffer memory 120. there is. In addition, the encryption/decryption module 116a may receive encrypted data from the buffer memory 120, decrypt the encrypted data, and provide the data to the memory 113, the host 300, or the non-volatile memory 130. . In one embodiment, the volatile memory interface 116 ′ may store encrypted data received from the reconfigurable logic chip 200 in the buffer memory 120 without passing through the encryption/decryption module 116a, and the buffer memory ( The encrypted data received from 120) may be provided to the reconfigurable logic chip 200 without passing through the encryption/decryption module 116a.

The non-volatile memory interface 117' may include an encryption/decryption module 117a, and the encryption/decryption module 117a may be selectively activated. In one embodiment, the encryption/decryption module 117a may encrypt data received from the memory 113, the host 300, or the buffer memory 120 and provide the encrypted data to the non-volatile memory 130. there is. In addition, the encryption/decryption module 117a may receive encrypted data from the non-volatile memory 130, decrypt the encrypted data, and provide the data to the memory 113, the host 300, or the buffer memory 120. . In one embodiment, the non-volatile memory interface 117' may store the encrypted data received from the reconfigurable logic chip 200 in the non-volatile memory 130 without going through the encryption/decryption module 116a, and Encrypted data received from the volatile memory 130 may be provided to the reconfigurable logic chip 200 without passing through the encryption/decryption module 117a.

12 is a block diagram illustrating a storage device set 10a according to an exemplary embodiment.

Referring to FIG. 12 , the storage device 100a may include a controller 110a and a non-volatile memory 130, and the controller 110a may include an encryption/decryption module 111 and a buffer memory 120a. . According to this embodiment, the buffer memory 120a may be embedded in the controller 110a. In one embodiment, the encryption/decryption module 111 may be disposed in front of the buffer memory 120a. Accordingly, the buffer memory 120a may buffer encrypted data.

The encryption/decryption module 111 may encrypt input data received from the host 300 or the nonvolatile memory 130 and provide the encrypted input data to the buffer memory 120a. Accordingly, the buffer memory 120a may buffer encrypted input data. Also, the encryption/decryption module 111 may decrypt encrypted output data received from the reconfigurable logic chip 200 and provide the decrypted output data to the buffer memory 120a. Accordingly, the buffer memory 120a may buffer the decoded output data. However, the present invention is not limited thereto, and the buffer memory 120a may buffer encrypted output data received from the reconfigurable logic chip 200 .

FIG. 13 shows an example of an operation of the storage device set 10a of FIG. 12 .

Referring to FIG. 13 , the host 300 may transmit a data write request and a host command including data to the storage device 100a. The encryption/decryption module 111 may encrypt data and load the encrypted data into the buffer memory 120a. Subsequently, the reconfigurable logic chip 200 may read the encrypted data loaded in the buffer memory 120a. The encryption/decryption module 210 may decrypt encrypted data and provide the decrypted data to the accelerator 220 . The accelerator 220 may generate processed data by processing data according to a predetermined configuration. Subsequently, the encryption/decryption module 210 may encrypt processed data and write the encrypted data into the buffer memory 120a. Subsequently, the host 300 may read processing data from the buffer memory 120a.

FIG. 14 is a flowchart illustrating an example of an operation between the controller 110a and the reconfigurable logic chip 200 of FIG. 13 .

Referring to FIG. 14 , the controller 110a receives a data write request and a host command including data from the host 300 (S600). The encryption/decryption module 111 included in the controller 110a generates encrypted input data by encrypting the received data (S610). The controller 110a loads the encrypted input data into the buffer memory 120 (S620).

The controller 110a transmits a command instructing data processing to the reconfigurable logic chip 200 (S630). The reconfigurable logic chip 200 transmits a read command to the controller 110a (S640). The controller 110a transmits the encrypted input data to the reconfigurable logic chip 200 (S650). The reconfigurable logic chip 200 decrypts the encrypted input data to generate decrypted data, processes the decrypted data to generate processed data, and encrypts the processed data to generate encrypted output data (S660). The reconfigurable logic chip 200 transmits the encrypted output data to the controller 110a (S670).

The controller 110a writes the encrypted output data into the buffer memory 120a or the non-volatile memory 130 (S680). In one embodiment, the encryption/decryption module 111 may decrypt encrypted output data to generate decrypted output data, and the controller 110a may store the decrypted output data in a buffer memory 120a or a non-volatile memory ( 130) can also be entered. Subsequently, the controller 110a may transmit a response message indicating that data processing is finished to the host 300 .

FIG. 15 shows another example of an operation of the storage device set 10a of FIG. 12 .

Referring to FIG. 15 , the host 300 may transmit a host command including a data processing request to the storage device 100a. The controller 110a may read data stored in the nonvolatile memory 130 and load the read data into the buffer memory 120a. In one embodiment, the encryption/decryption module 111 may encrypt the read data and provide the encrypted data to the buffer memory 120a. In one embodiment, the controller 110a may read encrypted data from the non-volatile memory 130 and load the read encrypted data into the buffer memory 120a.

The reconfigurable logic chip 200 may read encrypted data loaded in the buffer memory 120a. The encryption/decryption module 210 may decrypt encrypted data and provide the decrypted data to the accelerator 220 . The accelerator 220 may generate processed data by processing data according to a predetermined configuration. Subsequently, the encryption/decryption module 210 may encrypt processed data and write the encrypted data into the buffer memory 120a. Subsequently, the host 300 may read processing data from the buffer memory 120a.

FIG. 16 is a flowchart illustrating an example of an operation between the non-volatile memory 130 of FIG. 15 , the controller 110a and the reconfigurable logic chip 200 .

Referring to FIG. 16 , the controller 110a receives a host command instructing data processing from the host 300 (S700). The controller 110a transmits a read command to the non-volatile memory 130 (S710). In an embodiment, the controller 110a may check a physical address at which data to be processed is stored by referring to the mapping table, and may transmit a read command including the physical address to the nonvolatile memory 130 . The non-volatile memory 130 performs a read operation (S720) and transmits data to the controller 110a (S725). The encryption/decryption module 111 included in the controller 110a generates encrypted input data by encrypting the received data (S730). The controller 110a loads the encrypted input data into the buffer memory 120 (S740).

The controller 110a transmits a command instructing data processing to the reconfigurable logic chip 200 (S750). The reconfigurable logic chip 200 transmits a read command to the controller 110a (S760). The controller 110a transmits the encrypted input data to the reconfigurable logic chip 200 (S765). The reconfigurable logic chip 200 decrypts the encrypted input data to generate decrypted data, processes the decrypted data to generate processed data, and encrypts the processed data to generate encrypted output data (S770). The reconfigurable logic chip 200 transmits the encrypted output data to the controller 110a (S780).

The controller 110a writes the encrypted output data into the buffer memory 120a or the non-volatile memory 130 (S790). In one embodiment, the encryption/decryption module 111 may decrypt encrypted output data to generate decrypted output data, and the controller 110a may store the decrypted output data in a buffer memory 120a or a non-volatile memory ( 130) can also be entered. Subsequently, the controller 110a may transmit a response message indicating that data processing is finished to the host 300 .

17 illustrates an example of an operation of the storage device set 10b according to an embodiment of the present disclosure.

Referring to FIG. 17 , the storage device 100b may include a controller 110b and a non-volatile memory 130, and the controller 110b may include an encryption/decryption module 111 and a buffer memory 120b. . According to this embodiment, the buffer memory 120b may be embedded in the controller 110b. In one embodiment, the encryption/decryption module 111 may be disposed after the buffer memory 120a. Accordingly, the buffer memory 120b may buffer unencrypted normal data.

The host 300 may transmit a data write request and a host command including data to the storage device 100b. Data received from the host 300 may be loaded into the buffer memory 120b. Subsequently, the encryption/decryption module 111 may encrypt data loaded into the buffer memory 120b and provide the encrypted data to the reconfigurable logic chip 200 .

The encryption/decryption module 210 may decrypt encrypted data and provide the decrypted data to the accelerator 220 . The accelerator 220 may generate processed data by processing data according to a predetermined configuration. Next, the encryption/decryption module 210 may encrypt processed data and provide the encrypted data to the controller 110b. The encryption/decryption module 111 may decrypt encrypted data, and the decrypted data may be loaded into the buffer memory 120b. Subsequently, the host 300 may read processing data from the buffer memory 120b.

FIG. 18 is a flowchart illustrating an example of an operation between the controller 110b and the reconfigurable logic chip 200 of FIG. 17 .

Referring to FIG. 18 , the controller 110b receives a data write request and a host command including data from the host 300 (S800). The controller 110b loads the received data into the buffer memory 120b (S810). The controller 110b transmits a command instructing data processing to the reconfigurable logic chip 200 (S820). The reconfigurable logic chip 200 transmits a read command to the controller 110b (S830).

The encryption/decryption module 111 included in the controller 110b generates encrypted input data by encrypting data loaded into the buffer memory 120b (S840). The controller 110b transmits the encrypted input data to the reconfigurable logic chip 200 (S850). The reconfigurable logic chip 200 decrypts the encrypted input data to generate decrypted data, processes the decrypted data to generate processed data, and encrypts the processed data to generate encrypted output data (S860). The reconfigurable logic chip 200 transmits the encrypted output data to the controller 110b (S870).

The controller 110b writes the encrypted output data into the buffer memory 120b or the non-volatile memory 130 (S880). In one embodiment, the encryption/decryption module 111 may decrypt encrypted output data to generate decrypted output data, and the controller 110b may store the decrypted output data in a buffer memory 120b or a non-volatile memory ( 130) can also be entered. Subsequently, the controller 110b may transmit a response message indicating that data processing is finished to the host 300 .

19 illustrates another example of an operation of the storage device set 10b according to an embodiment of the present disclosure.

Referring to FIG. 19 , the host 300 may transmit a host command instructing data processing to the storage device 100b. The controller 110b may read data stored in the non-volatile memory 130 and load the read data into the buffer memory 120b. The encryption/decryption module 111 may encrypt data loaded into the buffer memory 120b and provide the encrypted data to the reconfigurable logic chip 200 .

The encryption/decryption module 210 may decrypt encrypted data and provide the decrypted data to the accelerator 220 . The accelerator 220 may generate processed data by processing data according to a predetermined configuration. Subsequently, the encryption/decryption module 210 may encrypt processed data and transmit the encrypted data to the controller 110b. The encryption/decryption module 111 may decrypt encrypted data, and the decrypted data may be loaded into the buffer memory 120b. Subsequently, the host 300 may read processing data from the buffer memory 120b.

FIG. 20 is a flowchart illustrating an example of an operation between the nonvolatile memory 130 of FIG. 19 , the controller 110b and the reconfigurable logic chip 200 .

Referring to FIG. 20 , the controller 110b receives a host command instructing data processing from the host 300 (S900). The controller 110b transmits a read command to the non-volatile memory 130 (S910). In an embodiment, the controller 110b may check a physical address at which data to be processed is stored by referring to the mapping table, and may transmit a read command including the physical address to the nonvolatile memory 130 . The nonvolatile memory 130 performs a read operation (S920) and transmits data to the controller 110b (S925).

The controller 110b loads data into the buffer memory 120b (S930). The encryption/decryption module 111 generates encrypted input data by encrypting the data loaded into the buffer memory 120b (S940). The controller 110b transmits a command instructing data processing to the reconfigurable logic chip 200 (S950). The reconfigurable logic chip 200 transmits a read command to the controller 110b (S960). The controller 110b transmits the encrypted input data to the reconfigurable logic chip 200 (S965). The reconfigurable logic chip 200 decrypts the encrypted input data to generate decrypted data, processes the decrypted data to generate processed data, and encrypts the processed data to generate encrypted output data (S970). The reconfigurable logic chip 200 transmits the encrypted output data to the controller 110b (S980).

The controller 110b writes the encrypted output data into the buffer memory 120b or the non-volatile memory 130 (S990). In one embodiment, the encryption/decryption module 111 may decrypt encrypted output data to generate decrypted output data, and the controller 110b may store the decrypted output data in a buffer memory 120b or a non-volatile memory ( 130) can also be entered. Subsequently, the controller 110b may transmit a response message indicating that data processing is finished to the host 300 .

21 illustrates a storage system SS' according to an embodiment of the present disclosure.

Referring to FIG. 21 , the storage system SS′ may include a storage device set 10c, a host 300, and a hardware accelerator 400, which may communicate with each other through a bus 500. For example, the storage system SS' may be a server or a data center. The storage device set 10c may include the storage device 100 and a reconfigurable accelerator (RA). As such, the storage system SS′ may include both the hardware accelerator 400 and the reconfigurable accelerator RA. In this case, the reconfigurable accelerator RA may be implemented in the storage device set 10c.

The hardware accelerator 400 may assist the operation of the host 300 by performing a predetermined specific operation among operations performed by the host 300 . For example, the hardware accelerator 400 may be a graphic processing unit (GPU). The reconfigurable accelerator (RA) may perform an operation corresponding to an application currently executed in the host 300 by being reconfigured in real time according to the type of operation performed by the host 300 . As such, while the operation performed by the hardware accelerator 400 does not change during the operation of the storage system SS′, the operation performed by the reconfigurable accelerator RA may change during the operation of the storage system SS′. there is.

According to this embodiment, the storage device 100 may perform the role of an existing storage device by including storage such as a non-volatile memory chip, and furthermore, the storage device 100 includes a reconfigurable accelerator (RA) and a storage device. A set of devices 10c may be configured. Accordingly, the host 300 and the reconfigurable accelerator RA may exchange data through a buffer memory included in the storage device 100, for example, CMB, even though they are not directly connected to each other. Accordingly, data processing speed between the storage device 100 and the reconfigurable accelerator RA may be further improved.

22 illustrates a network system 1000 according to an embodiment of the present disclosure.

Referring to FIG. 22 , a network system 1000 may include a server system 1100 and a plurality of terminals 1210 to 1230 communicating with the server system 1100 through a network NET. The server system 1100 may include a server 1110 and an SSD 1120 . In this case, the SSD 1120 may correspond to the storage devices 100, 100a, and 100b of the above-described embodiments. In some embodiments, SSD 1120 may be implemented using the embodiments described above with reference to FIGS. 1-21 .

23 illustrates a network system 2000 according to an embodiment of the present disclosure.

Referring to FIG. 23 , a network system 2000 may include a client group 2100 and a data center 2200 . The client group 2100 may include client devices C communicating with the data center 2200 through a first network NET1, for example, the Internet. The data center 2200 is a facility that collects various data and provides services, and includes an application server group 2210 and a database that communicate with each other through a second network (NET2), for example, a local area network (LAN) or an intranet. A server group 2220 and an object cache server group 2230 may be included.

The application server group 2210 may include application server devices (AS), and the application server devices (AS) process requests received from the client group 2100, and according to requests from the client group 2100. The database server group 2220 or the object cache server group 2230 can be accessed. The database server group 2220 may include database server devices DS that store data processed by the application server devices AS. The object cache server group 2230 may include object cache server devices (OCS) that temporarily store data stored in the database server devices DS or data read from the database server devices DS, Accordingly, a cache function may be performed between the application server devices AS and the database server devices DS. In one embodiment, the database server devices DS may be implemented using the embodiments described above with reference to FIGS. 1 to 21 .

As above, exemplary embodiments have been disclosed in the drawings and specifications. Although the embodiments have been described using specific terms in this specification, they are only used for the purpose of explaining the technical idea of the present disclosure, and are not used to limit the scope of the present disclosure described in the claims. . Therefore, those of ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims.

Claims (20)

a first port configured to communicate according to a first interface protocol;
a second port configured to communicate according to a second interface protocol;
A reconfigurable logic chip that receives encrypted input data, processes the encrypted input data according to a predetermined configuration to generate processed data, and encrypts the processed data to generate encrypted output data. (reconfigurable logic chip); and
a storage device communicating with a host through the first port, communicating with the reconfigurable logic chip through the second port, and including a buffer memory and a controller;
The buffer memory,
storing unencrypted input data received from the host through the first port;
storing the encrypted output data received from the reconfigurable logic chip through the second port;
The controller,
reading the unencrypted input data from the buffer memory;
generating the encrypted input data by encrypting the unencrypted input data;
Transmitting the encrypted input data to the reconfigurable logic chip through the second port;
receiving the encrypted output data from the reconfigurable logic chip through the second port;
and transmitting decrypted output data generated by decrypting the encrypted output data stored in the buffer memory to the host through the first port. According to claim 1,
The storage device set characterized in that the storage device buffers the encrypted input data or the encrypted output data in the buffer memory. According to claim 1,
The controller receives the unencrypted input data and a write command from the host, encrypts the received unencrypted input data to generate the encrypted input data, and transfers the generated encrypted input data to the buffer A set of storage devices characterized by loading into memory. The method of claim 1, wherein the storage device,
Further comprising a non-volatile memory for storing the unencrypted input data,
The controller reads the unencrypted input data from the non-volatile memory in response to a host command received from the host, encrypts the read unencrypted input data, and generates the encrypted input data; and loading the encrypted input data into the buffer memory. According to claim 1,
The storage device set of claim 1 , wherein the controller transmits a command instructing processing of the encrypted input data to the reconfigurable logic chip when loading of the encrypted input data into the buffer memory is completed. According to claim 1,
The storage device set of claim 1 , wherein the controller is implemented in a first chip and the buffer memory is implemented in a second chip. According to claim 1,
The storage device set, characterized in that the controller and the buffer memory are implemented on the same chip. According to claim 1,
The controller decrypts the encrypted output data to generate the decrypted output data;
Wherein the storage device buffers the unencrypted input data or the decrypted output data in the buffer memory. The storage device set of claim 1 , wherein the reconfigurable logic chip is indirectly connected to the host through the storage device. delete According to claim 1,
The storage device set, characterized in that the storage device and the reconfigurable logic chip are mounted on a single board. According to claim 1,
The storage device and the reconfigurable logic chip are implemented as a package-on-package (POP). According to claim 1,
The storage device set, characterized in that the reconfigurable logic chip is a Field Programmable Gate Array (FPGA). a first port configured to communicate according to a first interface protocol;
a second port configured to communicate according to a second interface protocol;
host;
reconfigurable logic chips; and
a storage device configured to communicate with the host through the first port and communicate with the reconfigurable logic chip through the second port;
The storage device,
non-volatile memory to store unencrypted input data;
a buffer memory storing encrypted output data provided from the reconfigurable logic chip; and
Reading the unencrypted input data from the non-volatile memory, encrypting the unencrypted input data to generate encrypted input data, and sending the encrypted input data to the reconfigurable logic chip through the second port. and a controller for transmitting and receiving the encrypted output data from the reconfigurable logic chip through the second port. 15. The method of claim 14, wherein the reconfigurable logic chip,
Receive the encrypted input data from the storage device, generate processed data from the encrypted input data according to a predetermined configuration, encrypt the processed data to generate the encrypted output data, and generate the encrypted output data. and transmitting output data to the storage device. The method of claim 14, wherein the controller,
and generating decrypted output data by decrypting the encrypted output data stored in the buffer memory, and transmitting the decrypted output data to the host through the first port. According to claim 14,
The buffer memory further stores the encrypted input data,
The storage system of claim 1 , wherein the reconfigurable logic chip is indirectly connected to the host through the storage device. As a method of operating a storage device,
receiving a host command including a data processing request from a host through a first port of the storage device;
storing unencrypted input data received from the host through the first port of the storage device in a buffer memory;
reading the unencrypted input data from the buffer memory;
generating encrypted input data by encrypting the unencrypted input data;
transmitting the encrypted input data and a command instructing data processing of the encrypted input data to a reconfigurable logic chip through a second port of the storage device;
receiving encrypted output data from the reconfigurable logic chip through the second port of the storage device; and
and transmitting decrypted output data generated by decrypting the encrypted output data to the host through the first port of the storage device. According to claim 18,
The method of claim 1 , wherein the reconfigurable logic chip is indirectly connected to the host through the storage device. According to claim 18,
The storage device includes a non-volatile memory,
The method,
receiving read data from the non-volatile memory; and
Further comprising encrypting the read data,
The method of claim 1 , wherein the transmitting to the reconfigurable logic chip comprises transmitting the encrypted read data to the reconfigurable logic chip.

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