KR102509646B1 - Storage device - Google Patents

Abstract

The present invention relates to a storage device that communicates with a host device using a defined interface protocol and supports a method of setting internal parameters indicating connection characteristics with the host upon request from the host. The storage device comprises: a main non-volatile memory; and a controller that communicates with a host according to a predetermined interface protocol and controls the main non-volatile memory. The controller includes a special function register (SFR) that stores parameters indicating connection characteristics with the host, receives a parameter change command according to the interface protocol from the host, extracts, from the parameter change command one or more descriptors, each containing an SFR address and a parameter value corresponding to a target parameter to be changed, and tunes the interface by executing the one or more descriptors and writing the parameter value to the SFR.

Description

Storage device {STORAGE DEVICE}

The present invention relates to a storage device including a non-volatile memory.

Semiconductor memories are classified into volatile memory devices and non-volatile memory devices. A volatile memory device loses stored data when power is cut off, but a non-volatile memory device can preserve stored data even when power is cut off. Non-volatile memory includes read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), Resistive RAM (RRAM), Ferroelectric RAM (FRAM), and the like.

Non-volatile memory is used as a storage device in a computing system. In a computing system, a storage device may communicate with a host device using a defined interface protocol.

SUMMARY OF THE INVENTION An object of the present invention is to provide a storage device that communicates with a host device using a predetermined interface protocol and supports a method of setting internal parameters indicating connection characteristics with the host at the request of the host.

A storage device according to an embodiment of the present invention includes a main non-volatile memory; and a controller communicating with a host according to a predetermined interface protocol and controlling the main non-volatile memory, wherein the controller includes a special function register (SFR) storing parameters representing connection characteristics with the host, Receiving a parameter change command according to the interface protocol from a host, extracting one or more descriptors including SFR addresses and parameter values corresponding to target parameters to be changed from the parameter change command, and executing the one or more descriptors, Tune the interface by writing the parameter values to the SFR.

A storage device according to an embodiment of the present invention includes a main non-volatile memory; and a controller communicating with a host according to a predetermined interface protocol and controlling the main non-volatile memory, wherein the controller includes a special function register (SFR) storing parameters representing connection characteristics with the host, The interface is tuned by changing parameter values included in the SFR in response to a parameter change command from the host, and the SFR is an area that does not support access by the host in the interface protocol.

A storage device according to an embodiment of the present invention includes a main non-volatile memory; a controller including a special function register (SFR) that communicates with a host using a predetermined interface protocol, controls the main non-volatile memory, and stores parameters representing connection characteristics with the host; a buffer memory buffering data read from the main non-volatile memory and providing the data to the controller; and a sub non-volatile memory that stores data necessary for the operation of the controller and is directly accessed by the controller using an address, wherein the controller boots stored in a boot area of the main non-volatile memory when power supply is sensed. Loading a loader into the buffer memory, initializing the SFR using the boot loader loaded into the buffer memory, acquiring one or more descriptors each including an SFR address and a parameter value from the sub non-volatile memory, and Tune the interface by executing the obtained descriptor to update the SFR.

A computing system according to an embodiment of the present invention includes a host; and a storage device including a register configured to communicate with the host through a predetermined interface protocol to store data of the host and to store parameters representing connection characteristics of the protocol, wherein the host determines a value of a target parameter whose value is to be changed. A parameter change command including one or more descriptors each including a register address and a parameter value is provided to the storage device, the storage device receives the parameter change command through an interface with the host, and changes the received parameter. Tune the interface by decrypting a command, extracting the one or more descriptors from the decrypted command, and executing the extracted descriptors to write the parameter values to the registers.

A storage device according to an embodiment of the present invention may support a parameter change command to externally change a parameter value stored in a special function register (SFR) that cannot be accessed through an interface protocol with a host. Accordingly, the storage device can easily perform interface tuning by applying an externally provided parameter value.

A storage device according to an embodiment of the present invention may store a parameter change command in a sub nonvolatile memory directly accessible by a storage controller instead of storing it in a boot region of a main nonvolatile memory. Accordingly, the storage device may perform interface tuning by quickly loading the parameter change command from the sub nonvolatile memory upon power-on reset.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

1 is a block diagram illustrating a computing system according to an embodiment of the present invention.
2 is a flowchart illustrating the operation of a computing system according to an embodiment of the present invention.
3 is a block diagram illustrating a storage device according to an exemplary embodiment of the present invention.
4 to 6 are diagrams for explaining a parameter change command according to an embodiment of the present invention.
7 is a flowchart illustrating an operation of a storage device according to an exemplary embodiment of the present invention.
8 is a block diagram illustrating a storage device according to an exemplary embodiment of the present invention.
9 to 10 are flowcharts illustrating operations of a storage device according to an embodiment of the present invention.
11 is a block diagram illustrating a computing system according to an embodiment of the present invention.
FIG. 12 is an exemplary block diagram illustrating a main non-volatile memory of FIG. 11 .
13 is a diagram for explaining a 3D V-NAND structure applicable to a storage device according to an embodiment of the present invention.
14 is a diagram illustrating a system to which a storage device according to an embodiment of the present invention is applied.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a computing system according to an embodiment of the present invention.

The computing system 10 may include a host 100 and a storage device 200 .

The host 100 may include electronic devices, for example, portable electronic devices such as mobile phones, MP3 players, and laptop computers, or various types of electronic devices such as desktop computers, game consoles, TVs, and projectors.

The storage device 200 may communicate with the host 100 and perform operations under the control of the host 100 . The storage device 200 may include non-volatile memory such as flash memory, PRAM, MRARM, and RRAM. For example, the storage device 200 may include a solid state drive (SSD), MMC, embedded MMC (eMMC), reduced size MMC (RS-MMC), and a multi-media card (MMC) in the form of micro-MMC. Media Card), Secure Digital (SD) card in the form of SD, mini-SD, and micro-SD, USB (Universal Serial Bus) storage device, UFS (Universal Flash Storage) device, CF (Compact Flash) card, smart It may be implemented as one of various types of storage devices such as a smart media card, a memory stick, and the like.

The storage device 200 may communicate with the host 100 according to a predetermined interface protocol. For example, the storage device 200 and the host 100 may communicate according to a Peripheral Component Interconnect Express (PCIe) protocol. The host 100 may include a storage interface 111 for communicating with the storage device 200 according to a predetermined interface protocol, and the storage device 200 communicates with the host 100 according to a predetermined interface protocol. It may include a host interface 211 to perform.

Various types of electronic devices and storage devices may communicate according to a defined interface protocol. Optimal connection characteristics may vary according to various connection environments of the host 100 and the storage device 200 communicating with each other. For example, a pre-emphasis level and a de-emphasis level at which a signal to noise ratio (SNR) of a signal transmitted from the storage device 200 to the host 100 can be optimized. (De-Emphasis) level may vary depending on the connection environment.

The storage device 200 may have various parameters defining connection characteristics with the host 100 . The storage device 200 may optimize connection characteristics with the host 100 by optimizing parameter values. An operation of optimizing connection characteristics of the storage device 200 may be referred to as an interface tuning operation.

If the storage device 200 acquires externally optimized parameter values and applies the obtained parameter values to internal parameters as they are, the storage device 200 can quickly and easily perform interface tuning. For example, a vendor of the storage device 200 may find optimal parameter values according to a connection environment. In addition, if the storage device 200 receives the optimal parameter values from the outside and applies them to the internal parameters, the storage device 200 can optimize the connection characteristics without directly finding the optimized parameter values.

The storage device 200 may include registers for storing parameter values. An interface protocol for communication between the host 100 and the storage device 200 may not provide an interface for the host 100 to access registers. If, in order to apply the optimal parameter value to the storage device 200, a manufacturer has to produce firmware to which the optimized parameter value is applied and support firmware update to the storage device 200, it is difficult to apply the optimal parameter value. there is.

According to an embodiment of the present invention, the storage device 200 may support a parameter change command. For example, when the storage device 200 complies with the Non-Volatile Memory Express (NVMe) standard, the parameter change command may be an NVMe Admin command. The parameter change command may include one or more descriptors including a register address corresponding to a target parameter to be changed and a parameter value.

When receiving a parameter change command from the host 100, the storage device 200 may tune the interface by recording a parameter value in a register address area included in the parameter change command. Accordingly, even when the host 100 cannot access the register according to the interface protocol, the storage device 200 may tune the interface using an external optimal parameter value.

2 is a flowchart illustrating the operation of a computing system according to an embodiment of the present invention.

In step S11, the host may provide a parameter change command including one or more descriptors. As described above, each descriptor may include a register address and a parameter value corresponding to a target parameter to be changed.

Meanwhile, the optimized parameter value may be determined by the manufacturer. A manufacturer may generate a parameter change command including an optimized parameter value and transmit the command to the host so that the host can tune an interface with the storage device.

Depending on the implementation, the manufacturer may improve the security of parameters and parameter values by transmitting the parameter change command to the host in an encrypted state. For example, when the storage device complies with the NVMe standard, the host may provide an encrypted parameter change command to the storage device according to a security protocol supported by the NVMe standard. When the storage device receives the encrypted parameter change command, the storage device may decrypt the parameter change command in step S12.

In step S13, the storage device may extract one or more descriptors from the parameter change command by parsing the parameter change command.

In step S14, the storage device may perform interface tuning by executing the extracted descriptor and writing a parameter value to a register. For example, the storage device may apply an optimal parameter value to the target parameter by recording the parameter value included in the descriptor in a register area indicated by a register address included in the descriptor.

Hereinafter, a storage device and a parameter change command according to an embodiment of the present invention will be described in more detail with reference to FIGS. 3 to 6 .

3 is a block diagram illustrating a storage device according to an exemplary embodiment of the present invention.

The storage device 200 may correspond to the storage device 200 described with reference to FIG. 1 . The storage device 200 may include a storage controller 210 and a main non-volatile memory 240 .

The storage controller 210 may control the main nonvolatile memory 240 according to a request of the host 100 . The storage controller 210 may transmit a control signal to the main nonvolatile memory 240 and exchange data with the main nonvolatile memory 240 .

The storage controller 210 may include a special function register (SFR) 219. The SFR 219 may include a storage area capable of storing parameter values representing connection characteristics with the host 100 according to an interface protocol. Meanwhile, access by the host 100 to the SFR 219 may not be supported in the interface protocol.

The main nonvolatile memory 240 may perform read, program, and erase operations under the control of the storage controller 210 . The main non-volatile memory 240 may include a NAND flash memory. However, the present invention is not limited to the main non-volatile memory 240 including a NAND flash memory, and the main non-volatile memory 240 includes at least one of various non-volatile memories such as PRAM, MRAM, RRAM, and FeRAM. can include

According to an embodiment of the present invention, the storage device 200 may receive a parameter change command from the host 100 through an interface protocol for communication with the host 100 . The storage controller 210 may perform interface tuning by storing parameter values in a storage area of the SFR 219 in response to a parameter change command received from the host 100 .

4 to 6 are diagrams for explaining a parameter change command according to an embodiment of the present invention.

4 is a diagram illustrating a data structure of a parameter change command.

The parameter change command may have a form supported by an interface protocol for communication between the storage device and the host. For example, the parameter change command may have a packet form, for example.

Referring to FIG. 4 , the parameter change command may include a signature field, a target power cycle field, and a descriptor field.

The signature field may indicate the validity of the parameter change command. For example, the storage device may perform interface tuning using the parameter change command only when the signature field of the parameter change command includes a valid signature.

The target power cycle field may indicate an expiration condition of the parameter change command. Specifically, when a parameter change command is received from the host, the storage device internally stores the parameter change command, and performs interface tuning by optimized parameters using the parameter change command even when the storage device is powered on and reset. can

According to an embodiment of the present invention, the target power cycle field may include power cycling number information as an expiration condition of a parameter change command. A power cycle may refer to one cycle in which power of the storage device is turned off and then turned on, and the number of times of power cycling may refer to the number of times the power of the storage device is turned off and then turned on.

After receiving the parameter change command, the storage device may expire the parameter change command when power cycles are repeated as many times as the number of power cycles included in the target power cycle field. Expiration of the parameter change command may indicate that interface tuning is not performed according to the parameter change command any more even after the storage device is powered-on reset.

When the storage device performs interface tuning using a parameter change command including incorrect parameter values, normal communication between the storage device and the host may become impossible. According to an embodiment of the present invention, a parameter change command including invalid parameter values may expire under an expiration condition. Accordingly, communication between the storage device and the host may be resumed after the parameter change command expires.

Meanwhile, FIG. 4 illustrates a case in which two target power cycle fields have a size of 4 bytes and each indicates values of upper 4 bytes and lower 4 bytes of the number of power cycling. However, the size and number of target power cycle fields are not limited to the example of FIG. 4 .

In the example of FIG. 4 , the parameter change command may include N (N is a natural number) descriptor fields. Each descriptor field may include information for specifying a target parameter to be changed and a value of the target parameter to be changed. That is, the parameter change command illustrated in FIG. 4 may change values of N target parameters.

5 is a diagram for explaining in detail a descriptor included in a parameter change command.

Referring to FIG. 5 , the descriptor field may include a group field, an address field, and a value field. The group field and the address field may specify a target parameter, and the value field may indicate a value to be changed of the target parameter.

Specifically, the group field may refer to a code block affected by the target parameter. A code block may refer to a set of firmware source code, for example a function. The target parameter may be a local parameter applied within a specific function, and the group field may specify a code block to which the target parameter is applied.

The address field may include an address of an area where the target parameter is stored in the SFR, that is, an SFR address. Depending on implementation, the SFR address may be a memory map address, which is an address allocated by a storage controller to access the SFR.

The value field may include a value of the target parameter to be written to the SFR address area.

Referring back to FIG. 4 , the parameter change command may include a plurality of descriptor fields. When the parameter change command includes a plurality of descriptor fields, the storage device may change values of a plurality of target parameters by sequentially executing a plurality of descriptors in response to the parameter change command.

6 is a diagram for explaining an execution sequence of descriptors according to an embodiment of the present invention.

FIG. 6 illustrates N (N is a natural number) descriptors included in the parameter change command of FIG. 4 and groups, addresses, and parameter values included in each descriptor.

According to an embodiment of the present invention, the storage device may execute descriptors in the order listed in the packet. In the example of FIG. 6 , the storage device changes the value of target parameters included in groups 0 by first executing descriptors 1 and 2, and the value of target parameters included in group 1 by executing descriptor 3. You can execute from descriptor 1 to descriptor N in the order of changing the .

In the parameter change command, a plurality of descriptors may be listed in an order capable of efficiently changing a plurality of target parameters. For example, a plurality of descriptors may be arranged in group order. For example, the group order may be the order in which code blocks are executed in the firmware source code that controls the connection to the host. The storage device may simply execute a plurality of descriptors listed in group order in order to change target parameters applied to code blocks executed in a predetermined order. Accordingly, the amount of computation required to change a plurality of target parameters can be reduced.

7 is a flowchart illustrating an operation of a storage device according to an exemplary embodiment of the present invention.

In step S21, the storage controller included in the storage device may receive a parameter change command from the host. As described with reference to FIG. 4 , the parameter change command may include validity information, an expiration condition, and one or more descriptors.

In step S22, the storage controller may extract one or more descriptors from the parameter change command. As described with reference to FIG. 5 , one or more descriptors may include a group including a target parameter, an address indicating a region in which the target parameter is stored in the SFR, and a value of the target parameter.

In step S23, the storage controller may record parameter values in the SFR by executing the one or more extracted descriptors in the listed order. As described with reference to FIG. 6 , one or more descriptors within the parameter change command may be listed in group order.

According to embodiments of the present disclosure described with reference to FIGS. 3 to 7 , a storage device may support a parameter change command. The host may control the storage device to change a parameter value included in an SFR that the host cannot access through an interface protocol by using the parameter change command. The storage device may perform interface tuning by obtaining optimal parameter values determined outside the manufacturer and recording them in the SFR area, and the storage device and the host may exchange signals quickly and accurately.

Meanwhile, as described above, the storage device may internally store the parameter change command received from the host, and may perform interface tuning using the parameter change command when the storage device is powered on and reset. According to an embodiment of the present invention, the storage device may store data necessary for the operation of the storage controller in a sub nonvolatile memory instead of storing a parameter change command in a boot area of the main nonvolatile memory. Hereinafter, a storage device according to an embodiment of the present invention will be described in more detail with reference to FIGS. 8 to 10 .

8 is a block diagram illustrating a storage device according to an exemplary embodiment of the present invention.

The storage device 200 may include a storage controller 210 , a sub nonvolatile memory 220 , a buffer memory 230 and a main nonvolatile memory 240 . The storage controller 210 and the main nonvolatile memory 240 may correspond to the storage controller 210 and the main nonvolatile memory 240 described with reference to FIG. 3 .

The storage controller 210 may include a SFR 219 . As described with reference to FIG. 3, the SFR 219 may include parameters defining connection characteristics with the host.

The main nonvolatile memory 240 may further include a boot area 241 as well as a normal area for storing data from the host. The boot area 241 may store a boot loader, which is data necessary for booting the storage device 200 . The boot area 241 may be accessed by the storage controller 210 when the storage device 200 is powered on and reset. The boot area 241 may also be referred to as a boot block or boot sector, and may have a limited size, for example, about 4 KB.

The sub nonvolatile memory 220 may store data necessary for the operation of the storage controller 210 . For example, the sub nonvolatile memory 220 may include EEPROM, NOR flash memory, SNOR (Serial NOR) flash memory, and the like. Depending on the implementation, the sub non-volatile memory 220 may have a size of several megabytes.

The buffer memory 230 may buffer data to be programmed into the main nonvolatile memory 240 or data read from the main nonvolatile memory 240 . The buffer memory 230 may be implemented as a volatile memory. For example, the buffer memory 230 may be implemented as static random access memory (SRAM) or dynamic random access memory (DRAM).

Meanwhile, when the main nonvolatile memory 240 is a NAND flash memory, it may be difficult to read and write data to an arbitrary address of the main nonvolatile memory 240 by the storage controller 210 . For example, in a NAND flash memory, data may be read in units of a page, which is a set of memory cells connected to one word line. The storage controller 210 may control data stored in the main nonvolatile memory 240 to be read in page units, and the data stored in the main nonvolatile memory 240 is buffered in the buffer memory 230, and then the storage controller ( 210) can be used.

On the other hand, in the sub nonvolatile memory 220 , data reading and writing to an arbitrary address may be possible by the storage controller 210 . Specifically, the storage controller 210 may select one memory cell by specifying a row address and a column address of the sub nonvolatile memory 220 using an external address.

As described above, a parameter change command is stored in the storage device 200, and interface tuning may be performed using the parameter change command during a power-on reset of the storage device 200, that is, during a booting operation. It is desirable that the parameter change command can be quickly accessed at boot time. However, the size of the boot area 241 may be limited, and in order to alleviate the size limitation of the boot area 241, the firmware design of the storage device may need to be significantly modified.

Accordingly, it may be difficult to store the parameter change command together with the boot loader in the boot area 241 and load the boot loader and parameter change command together during a booting operation. In addition, storing the parameter change command in the normal area of the non-volatile memory device 240 and accessing the normal area as well as the boot area 241 during a booting operation may delay booting completion time.

According to an embodiment of the present invention, the storage controller 210 may store a parameter change command in the sub nonvolatile memory 220 and obtain the parameter change command from the sub nonvolatile memory 220 during a booting operation. . While the main nonvolatile memory 240 is difficult to directly access by the storage controller 210 , the sub nonvolatile memory 220 can be easily accessed by the storage controller 210 using an address. Accordingly, the storage controller 210 can quickly obtain a parameter change command and quickly perform interface tuning during a booting operation.

Hereinafter, a method of storing a parameter change command in the storage device 200 and using the parameter change command during a power-on reset according to an embodiment of the present invention will be described in detail with reference to FIGS. 9 to 10 .

9 to 10 are flowcharts illustrating operations of a storage device according to an embodiment of the present invention.

9 is a flowchart illustrating an operation performed by a storage device in response to a parameter change command. Steps S31 to S33 of FIG. 9 may be similar to steps S21 to S23 described with reference to FIG. 7 .

After performing interface tuning using the parameter change command, the storage controller may store the parameter change command in the sub nonvolatile memory in step S34. The stored parameter change command can be used for interface tuning at power-on reset.

10 is a flowchart illustrating an operation performed by a storage device upon power-on reset.

In step S41, the storage device may detect power supply and perform power-on reset operations of steps S42 to S47.

In step S42, the storage device may load the boot loader stored in the main non-volatile memory into the buffer memory. For example, a processor included in the storage controller may control the main nonvolatile memory to load data having a predetermined size from a predetermined address of the main nonvolatile memory into a buffer memory.

In step S43, the storage device may initialize the SFR using the boot loader loaded into the buffer memory. For example, the boot loader may include initial parameter values before interface tuning is performed, and the storage controller may initialize connection characteristic parameters by recording the initial parameter values in the SFR.

In step S44, the storage device may determine whether a parameter change command is stored in the sub nonvolatile memory. For example, the storage controller may directly access the sub nonvolatile memory using an address without going through a buffer memory. Since the parameter change command can be stored in the sub non-volatile memory, the storage controller can quickly determine whether the parameter change command has been stored.

In step S45, the storage device may determine whether it is necessary to change the initialized connection characteristic parameters. For example, when a parameter change command including a valid signature is stored in the sub nonvolatile memory, the storage controller may determine that parameters need to be changed if the parameter change command has not expired. On the other hand, the storage controller may determine that parameters do not need to be changed when the parameter change command is not stored in the sub nonvolatile memory, the stored command is invalid, or the stored command has expired.

If parameters need to be changed (Yes in step S45), the storage controller may extract one or more descriptors from the parameter change command in step S46. In step S47, the storage controller may overwrite the optimal parameter value in the area where the initial parameter value of the SFR is stored by executing the one or more descriptors in the listed order.

According to an embodiment of the present invention, a storage device may support a parameter change command conforming to a predetermined interface protocol. The storage device may change parameter values of SFRs to which the host is not allowed to access by acquiring optimal parameter values by receiving the parameter change command. Accordingly, the host and the storage device can exchange signals quickly and accurately.

The storage device may store parameter change commands in secondary non-volatile memory directly accessible by the controller. Even when it is difficult for the storage device to store the parameter change command in the boot region of the main nonvolatile memory, the storage controller can quickly access the parameter change command during power-on reset. Accordingly, interface tuning can be quickly performed upon power-on reset of the storage device.

Hereinafter, an example of a computing system to which an embodiment of the present invention is applied will be described in detail with reference to FIGS. 11 to 14 .

11 is a block diagram illustrating a computing system according to an embodiment of the present invention.

The computing system 30 may include a host 300 and a storage device 400 . Also, the storage device 400 may include a storage controller 410 , a sub main nonvolatile memory 440 , a buffer memory 430 and a main nonvolatile memory 440 . The host 300 and the storage device 400 may be similar to the host 100 and the storage device 200 described with reference to FIG. 1 . Also, the storage controller 410, the sub main nonvolatile memory 440, the buffer memory 430, and the main nonvolatile memory 440 are the storage controller 210 and the sub nonvolatile memory 220 described with reference to FIG. 8 . ), the buffer memory 230 and the main non-volatile memory 240 may be similar.

The storage device 400 may include storage media for storing data according to a request from the host 300 . As an example, the storage device 400 may include at least one of a solid state drive (SSD), an embedded memory, and a removable external memory. When the storage device 400 is an SSD, the storage device 400 may be a device conforming to the non-volatile memory express (NVMe) standard. When the storage device 400 is an embedded memory or an external memory, the storage device 400 may be a device conforming to a universal flash storage (UFS) standard or an embedded multi-media card (eMMC) standard. The host 300 and the storage device 400 may respectively generate and transmit packets according to adopted standard protocols.

The main non-volatile memory 440 may retain stored data even when power is not supplied. The main nonvolatile memory 440 may store data provided from the host 300 through a program operation, and output data stored in the main nonvolatile memory 440 through a read operation.

When the main nonvolatile memory 440 includes a flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the storage device 400 may include other various types of non-volatile memories. For example, the storage device 400 includes magnetic RAM (MRAM), spin-transfer torque MRAM (Spin-Transfer Torgue MRAM), conductive bridging RAM (CBRAM), ferroelectric RAM (FeRAM), phase RAM (PRAM), resistive memory ( Resistive RAM) and other various types of memory may be applied.

The storage controller 410 may control the main nonvolatile memory 440 in response to a request from the host 300 . For example, the storage controller 410 may provide data read from the main nonvolatile memory 440 to the host 300 and store the data provided from the host 300 in the main nonvolatile memory 440 . For this operation, the storage controller 410 may support read, program, and erase operations of the main nonvolatile memory 440 .

The sub nonvolatile memory 420 may store data necessary for the operation of the storage controller 410 . The sub nonvolatile memory 420 may be directly accessed by the storage controller 410 using an address. The sub nonvolatile memory 420 may include EEPROM, NOR flash memory, SNOR (Serial NOR) flash memory, and the like.

The buffer memory 430 may buffer data to be programmed into the main nonvolatile memory 440 or data read from the main nonvolatile memory 440 .

The storage controller 410 may include a host interface 411 , a main memory interface 412 , and a central processing unit (CPU) 413 . In addition, the storage controller 410 includes a packet manager 414, a sub memory interface 415, a buffer memory interface 416, an error correction code (ECC) engine 417 and an advanced encryption standard (AES) engine 418. can include more. The storage controller 410 may further include a working memory (not shown) into which a flash translation layer (FTL) is loaded, and the CPU 413 executes the flash translation layer so that the memory for the main non-volatile memory 440 is stored. Data writing and reading operations can be controlled.

The host interface 411 may transmit/receive packets with the host 300 through a predetermined interface protocol. A packet transmitted from the host 300 to the host interface 411 may include a command or data to be written to the main non-volatile memory 440, and is transmitted from the host interface 411 to the host 300. The packet may include a response to a command or data read from the main nonvolatile memory 440 .

The main memory interface 412 may transmit data to be written in the main nonvolatile memory 440 to the main nonvolatile memory 440 or may receive data read from the main nonvolatile memory 440 . Such a main memory interface 412 may be implemented to comply with standards such as Toggle or Open NAND Flash Interface (ONFI).

The flash conversion layer driven by the CPU 413 may perform various functions such as address mapping, wear-leveling, and garbage collection. The address mapping operation is an operation of changing a logical address received from the host 300 into a physical address used to actually store data in the main nonvolatile memory 440 . Wear-leveling is a technique for preventing excessive deterioration of a specific block by uniformly using blocks in the main non-volatile memory 440. For example, firmware balancing erase counts of physical blocks It can be realized through technology. Garbage collection is a technique for securing usable capacity in the main non-volatile memory 440 by copying valid data of a block to a new block and then erasing the old block.

Meanwhile, the CPU 413 may include an SFR 419 for storing parameter values used for the operation of the storage device 400 . For example, the SFR 419 may store parameters representing connection characteristics with the host.

The packet manager 414 may generate a packet according to an interface protocol negotiated with the host 300 or parse various types of information from a packet received from the host 300 .

The sub memory interface 415 may transmit/receive data with the sub nonvolatile memory 420 disposed outside the storage controller 410 . Also, the buffer memory interface 416 may transmit and receive data to and from the buffer memory 430 disposed outside the storage controller 410 . In the example of FIG. 11 , the sub nonvolatile memory 420 and the buffer memory 430 may be disposed outside the storage controller 410 , but may be disposed inside the storage controller 410 .

The ECC unit 417 may perform error detection and correction functions for read data read from the main nonvolatile memory 440 . More specifically, the ECC unit 417 may generate parity bits for write data to be written in the main non-volatile memory 440, and the parity bits generated in this way are used together with the write data in the main non-volatile memory 440. may be stored in memory 440 . When data is read from the main non-volatile memory 440, the ECC unit 417 corrects an error in the read data using parity bits read from the main non-volatile memory 440 together with the read data, and the error is corrected. Read data can be output.

The AES engine 418 may perform at least one of an encryption operation and a decryption operation on data input to the storage controller 410 using a symmetric-key algorithm. . For example, the AES engine 418 may decrypt a command received by the storage controller 410 according to a security protocol.

Meanwhile, the storage controller 410 may further include an encryption engine for encrypting data stored in the main nonvolatile memory 440 . However, the storage controller 410 may store data stored in the sub nonvolatile memory 420 in plain text without encryption. According to an embodiment of the present invention, the storage controller 410 may store a command received according to a security protocol in the sub nonvolatile memory 420 as it is.

Since the command received according to the security protocol may be an encrypted command, even if the command is stored as it is in the sub non-volatile memory 420 without additional encryption, security of the descriptor included in the command may be maintained. The storage controller 410 may obtain the encrypted command from the sub nonvolatile memory 420 during power-on reset, decrypt the encrypted command, and perform interface tuning using the decrypted command.

FIG. 12 is an exemplary block diagram illustrating a main non-volatile memory of FIG. 11 . Referring to FIG. 12 , the main nonvolatile memory 500 may include a control logic circuit 520, a memory cell array 530, a page buffer 540, a voltage generator 550, and a row decoder 560. there is. Although not shown in FIG. 15, the main non-volatile memory 500 may further include the memory interface circuit 510 shown in FIG. 12, and may also include a column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, and the like. may further include.

The control logic circuit 520 may generally control various operations within the main nonvolatile memory 500 . The control logic circuit 520 may output various control signals in response to the command CMD and/or the address ADDR from the memory interface circuit 510 . For example, the control logic circuit 520 may output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

The memory cell array 530 may include a plurality of memory blocks BLK1 to BLKz (where z is a positive integer), and each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. there is. The memory cell array 530 may be connected to the page buffer unit 540 through bit lines BL, and may include word lines WL, string select lines SSL, and ground select lines GSL. It can be connected to the row decoder 560 through

In an exemplary embodiment, the memory cell array 530 may include a 3D memory cell array, and the 3D memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells respectively connected to word lines vertically stacked on a substrate. U.S. Patent Publication No. 7,679,133, U.S. Patent Publication No. 8,553,466, U.S. Patent Publication No. 8,654,587, U.S. Patent Publication No. 8,559,235, and U.S. Patent Application Publication No. 2011/0233648 are incorporated herein by reference. are combined In an exemplary embodiment, the memory cell array 530 may include a 2D memory cell array, and the 2D memory cell array may include a plurality of NAND strings disposed along row and column directions.

The page buffer 540 may include a plurality of page buffers PB1 to PBn (where n is an integer greater than or equal to 3), and the plurality of page buffers PB1 to PBn may be configured through a plurality of bit lines BL. Each of the memory cells may be connected. The page buffer 540 may select one or more bit lines from among the bit lines BL in response to the column address Y-ADDR. The page buffer 540 may operate as a write driver or a sense amplifier according to an operation mode. For example, during a program operation, the page buffer 540 may apply a bit line voltage corresponding to data to be programmed to a selected bit line. During a read operation, the page buffer 540 may detect data stored in a memory cell by sensing a current or voltage of a selected bit line.

The voltage generator 550 may generate various types of voltages for performing program, read, and erase operations based on the voltage control signal CTRL_vol. For example, the voltage generator 550 may generate a program voltage, a read voltage, a program verify voltage, an erase voltage, and the like as the word line voltage VWL.

The row decoder 560 may select one of the plurality of word lines WL and select one of the plurality of string select lines SSL in response to the row address X-ADDR. For example, during a program operation, the row decoder 560 may apply a program voltage and a program verify voltage to a selected word line, and during a read operation, may apply a read voltage to the selected word line.

13 is a diagram for explaining a 3D V-NAND structure applicable to a storage device according to an embodiment of the present invention.

When the non-volatile memory of the storage device is implemented as a 3D V-NAND type flash memory, each of a plurality of memory blocks constituting the non-volatile memory may be expressed as an equivalent circuit as shown in FIG. 13 .

The memory block BLKi shown in FIG. 13 represents a three-dimensional memory block formed in a three-dimensional structure on a substrate. For example, a plurality of memory NAND strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate.

Referring to FIG. 13 , the memory block BLKi may include a plurality of memory NAND strings NS11 to NS33 connected between the bit lines BL1 , BL2 , and BL3 and the common source line CSL. Each of the plurality of memory NAND strings NS11 to NS33 may include a string select transistor SST, a plurality of memory cells MC1, MC2, ..., MC8, and a ground select transistor GST. 13 shows that each of the plurality of memory NAND strings NS11 to NS33 includes eight memory cells MC1, MC2, ..., MC8, but is not necessarily limited thereto.

The string select transistor SST may be connected to corresponding string select lines SSL1 , SSL2 , and SSL3 . The plurality of memory cells MC1 , MC2 , ..., MC8 may be connected to corresponding gate lines GTL1 , GTL2 , ... , and GTL8 , respectively. The gate lines GTL1 , GTL2 , ..., GTL8 may correspond to word lines, and some of the gate lines GTL1 , GTL2 , ... , GTL8 may correspond to dummy word lines. The ground select transistor GST may be connected to corresponding ground select lines GSL1 , GSL2 , and GSL3 . The string select transistor SST may be connected to corresponding bit lines BL1 , BL2 , and BL3 , and the ground select transistor GST may be connected to the common source line CSL.

Word lines (eg, WL1) having the same height may be commonly connected, and ground select lines GSL1, GSL2, and GSL3 and string select lines SSL1, SSL2, and SSL3 may be separated from each other. 13 shows that the memory block BLK is connected to eight gate lines GTL1, GTL2, ..., GTL8 and three bit lines BL1, BL2, BL3, but is not necessarily limited thereto. no.

14 is a diagram illustrating a system 1000 to which a storage device according to an embodiment of the present invention is applied.

The system 1000 of FIG. 14 is basically a mobile phone such as a mobile phone, a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an internet of things (IOT) device. (mobile) system. However, the system 1000 of FIG. 14 is not necessarily limited to a mobile system, and can be used for vehicles such as a personal computer, a laptop computer, a server, a media player, or a navigation system. It may be an automotive device or the like.

Referring to FIG. 14 , a system 1000 may include a main processor 1100, memories 1200a and 1200b, and storage devices 1300a and 1300b, and additionally includes an image capturing device. 1410, user input device 1420, sensor 1430, communication device 1440, display 1450, speaker 1460, power supplying device 1470 and connections It may include one or more of the connecting interfaces 1480 .

The main processor 1100 may control the overall operation of the system 1000, and more specifically, the operation of other components constituting the system 1000. The main processor 1100 may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

The main processor 1100 may include one or more CPU cores 1110 and may further include a controller 1120 for controlling the memories 1200a and 1200b and/or the storage devices 1300a and 1300b. Depending on embodiments, the main processor 1100 may further include an accelerator 1130 that is a dedicated circuit for high-speed data operations such as artificial intelligence (AI) data operations. Such an accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and/or a data processing unit (DPU), and may be physically independent from other components of the main processor 1100. It may be implemented as a separate chip.

The memories 1200a and 1200b may be used as main memory devices of the system 1000 and may include volatile memories such as SRAM and/or DRAM, but may include non-volatile memories such as flash memory, PRAM, and/or RRAM. may be The memories 1200a and 1200b may also be implemented in the same package as the main processor 1100 .

The storage devices 1300a and 1300b may function as non-volatile storage devices that store data regardless of whether or not power is supplied, and may have a relatively large storage capacity compared to the memories 1200a and 1200b. The storage devices 1300a and 1300b may include storage controllers 1310a and 1310b and non-volatile memories (NVMs) 1320a and 1320b that store data under the control of the storage controllers 1310a and 1310b. can The non-volatile memories 1320a and 1320b may include a 2D (2-dimensional) structure or a 3D (3-dimensional) V-NAND (vertical NAND) structure flash memory, but other types of memory such as PRAM and/or RRAM. It may also include non-volatile memory.

The storage devices 1300a and 1300b may be included in the system 1000 while being physically separated from the main processor 1100 or may be implemented in the same package as the main processor 1100 . In addition, the storage devices 1300a and 1300b have a form such as a solid state device (SSD) or a memory card, so that other components of the system 1000 can be accessed through an interface such as a connection interface 1480 to be described later. It may be coupled to be detachable with the . The storage devices 1300a and 1300b may be devices to which standard rules such as UFS (Universal Flash Storage), eMMC (embedded multi-media card), or NVMe (non-volatile memory express) are applied, but are not necessarily limited thereto. It's not.

According to an embodiment of the present invention, the storage devices 1300a and 1300b may support a parameter change command conforming to a predetermined interface protocol. The main processor 1100 provides a parameter change command including an optimal parameter value for connection characteristics with the storage devices 1300a and 1300b to the storage devices 1300a and 1300b, thereby changing the parameter values stored in the storage devices 1300a and 1300b. can be easily changed. Accordingly, signal transmission quality between the main processor 1100 and the storage devices 1300a and 1300b may be improved.

The photographing device 1410 may capture a still image or a video, and may be a camera, a camcorder, and/or a webcam.

The user input device 1420 may receive various types of data input from a user of the system 1000, and may use a touch pad, a keypad, a keyboard, a mouse, and/or It may be a microphone or the like.

The sensor 1430 can detect various types of physical quantities that can be acquired from the outside of the system 1000 and convert the detected physical quantities into electrical signals. The sensor 1430 may be a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor, and/or a gyroscope sensor.

The communication device 1440 may transmit and receive signals with other devices outside the system 1000 according to various communication protocols. Such a communication device 1440 may be implemented by including an antenna, a transceiver, and/or a modem (MODEM).

The display 1450 and the speaker 1460 may function as output devices that output visual information and auditory information to the user of the system 1000, respectively.

The power supply device 1470 may appropriately convert power supplied from a battery (not shown) and/or an external power source built into the system 1000 and supply the power to each component of the system 1000 .

The connection interface 1480 may provide a connection between the system 1000 and an external device connected to the system 1000 and capable of exchanging data with the system 1000. The connection interface 1480 is an Advanced Technology (ATA) Attachment), Serial ATA (SATA), external SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnection (PCI), PCI express (PCIe), NVMe, IEEE 1394, It can be implemented in various interface methods such as USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC, UFS, eUFS (embedded universal flash storage), CF (compact flash) card interface, etc. there is.

The present invention is not limited by the above-described embodiments and accompanying drawings, but is intended to be limited by the appended claims. Therefore, various forms of substitution, modification, and change will be possible by those skilled in the art within the scope of the technical spirit of the present invention described in the claims, which also falls within the scope of the present invention. something to do.

100, 300: host
200, 400: storage device
210, 410: storage controller
220, 420: sub non-volatile memory
230, 430: buffer memory
240, 440: main non-volatile memory

Claims (20)

In the storage device,
main non-volatile memory; and
A controller communicating with a host according to a predetermined interface protocol and controlling the main non-volatile memory;
The controller
It includes a special function register (SFR) for storing parameters representing connection characteristics with the host, receives a parameter change command according to the interface protocol from the host, and each SFR address and parameter corresponding to a target parameter to be changed. tune an interface by extracting one or more descriptors containing values from the parameter change command and executing the one or more descriptors to write the parameter values to the SFR;
The parameter change command is
Including expiration condition information of the parameter change command
storage device.
delete According to claim 1,
The above expiration condition information
Includes information on the number of power cycling of the storage device;
The controller
Expiring the parameter change command when power cycles are repeated as many times as the number of power cycling after receiving the parameter change command from the host.
storage device.
According to claim 1,
Each of the one or more descriptors is
Further comprising group information indicating a code block to which the target parameter is applied in the firmware source code for controlling the connection with the host
storage device.
According to claim 1,
The one or more descriptors are listed based on group information in the parameter change command,
The controller
Recording the parameter values in the SFR in the order in which the one or more descriptors are listed in the parameter change command
storage device.
According to claim 1,
the storage device
Further comprising a sub non-volatile memory for storing data necessary for the operation of the controller,
The controller
Storing the received parameter change command in the sub non-volatile memory
storage device.
According to claim 6,
The controller
When power supply is detected, the SFR is initialized using a boot loader obtained from the main non-volatile memory, and based on expiration condition information of the parameter change command stored in the sub non-volatile memory, whether the parameter change command expires is determined. and tuning the interface by extracting the one or more descriptors from the parameter change command if the parameter change command has not expired, and overwriting the parameter values in the SFR by executing the one or more descriptors.
storage device.
According to claim 6,
the storage device
Further comprising a buffer memory buffering data read from the main non-volatile memory and providing the data to the controller;
The controller
Acquiring a parameter change command stored in the sub non-volatile memory directly without going through the buffer memory
storage device.
According to claim 1,
The received parameter change command is an encrypted command,
The controller
Decrypting the encrypted command before extracting the one or more descriptors from the parameter change command.
storage device.
According to claim 9,
the storage device
Further comprising a sub non-volatile memory for storing data necessary for the operation of the controller,
The controller
Storing the encrypted command in the sub non-volatile memory
storage device.
According to claim 1,
The interface protocol is
Peripheral Component Interconnect Express (PCIe)
storage device.
According to claim 11,
The parameter change command is
NVMe (Non-Volatile Memory Express) Admin command
storage device.
In the storage device,
main non-volatile memory; and
A controller communicating with a host according to a predetermined interface protocol and controlling the main non-volatile memory;
The controller
a special function register (SFR) for storing parameters representing connection characteristics with the host, and tuning an interface by changing parameter values included in the SFR in response to a parameter change command from the host;
The SFR is an area that does not support access by a host in the interface protocol,
The parameter change command is
Including expiration condition information of the parameter change command
storage device.
According to claim 13,
the storage device
Further comprising a sub non-volatile memory that the controller can directly access using an arbitrary address,
The controller
Storing the parameter change command in the sub non-volatile memory
storage device.
According to claim 14,
The controller
The SFR is initialized using the boot loader obtained from the main non-volatile memory, and the parameter value included in the SFR is changed based on the parameter change command when the parameter change command stored in the sub non-volatile memory has not expired. Tuning the interface by changing
storage device.
In the storage device,
main non-volatile memory;
a controller including a special function register (SFR) that communicates with a host using a predetermined interface protocol, controls the main non-volatile memory, and stores parameters representing connection characteristics with the host;
a buffer memory buffering data read from the main non-volatile memory and providing the data to the controller; and
A sub non-volatile memory for storing data necessary for the operation of the controller and directly accessed by the controller using an address;
The controller
When power supply is sensed, the boot loader stored in the boot area of the main non-volatile memory is loaded into the buffer memory, the SFR is initialized using the boot loader loaded in the buffer memory, and each from the sub non-volatile memory is Tuning an interface by obtaining one or more descriptors including SFR addresses and parameter values, and executing the acquired descriptors to update the SFRs.
storage device.
According to claim 16,
The controller
When receiving a parameter change command including one or more descriptors from the host, storing the parameter change command in the sub non-volatile memory.
storage device.
According to claim 17,
The received parameter change command is an encrypted command,
The controller
Obtaining the one or more descriptors by storing the encrypted command in the sub nonvolatile memory and decrypting the encrypted command stored in the sub nonvolatile memory.
storage device.
According to claim 17,
The parameter change command further includes power cycling number information,
The controller
Expiring the parameter change command when the storage device repeats power cycles as many times as the number of power cycling after receiving the parameter change command.
storage device.
According to claim 16,
The sub non-volatile memory is
At least one of SNOR (Serial NOR) memory and EEPROM (Electrically Erasable Programmable Read-Only Memory),
The main non-volatile memory is
NAND flash memory
storage device.

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