KR102498990B1 - Display device - Google Patents

Abstract

A display device according to the present invention includes a display panel having a plurality of pixels; and a driving circuit for driving the display panel by supplying signals to data lines, scan lines, and emission lines, wherein each pixel is composed of a driving transistor, a light emitting diode, a capacitor, and first to fourth transistors. , The driving circuit divides the display panel into a plurality of blocks in a direction perpendicular to the direction in which the scan line travels, and drives the display panel while sequentially writing data to pixels included in one of the plurality of blocks. The light emitting diodes of the pixels may simultaneously emit light.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to a display device in which a panel is divided into a plurality of blocks and driven.

An active matrix type organic light emitting display device includes an organic light emitting diode (OLED) that emits light by itself, and has advantages of fast response speed, light emitting efficiency, luminance, and viewing angle.

An organic light emitting display device arranges pixels including OLEDs in a matrix form and adjusts luminance by controlling the amount of light emitted from the OLEDs according to the gradation of image data. Each pixel circuit includes an OLED as a light emitting element, a switch transistor or TFT (Thin Film Transistor) for controlling the application of data voltages corresponding to gray levels, and controlling the pixel current flowing through the OLED according to the voltage applied between the gate electrode and the source electrode. and a driving TFT to store the data voltage.

The electrical characteristics of the OLED and the driving TFT deteriorate over time and may differ from pixel to pixel, and the electrical characteristic deviation between these pixels becomes a major factor in deteriorating image quality. In order to compensate for variations in electrical characteristics between pixels, electrical characteristics (threshold voltage of the driving TFT and electron mobility of the driving TFT) of the pixels must be compensated.

Among the pixel circuits that compensate for the change in electrical characteristics of pixels by internal compensation method, the sequential light emission pixel circuit that sequentially emits light while sequentially writing data into the pixels has a complicated configuration and includes an initialization voltage line, two scan signal lines, and light emission. Since it is connected to many wires such as signal lines, it is difficult to secure a pixel design margin, and there is a limit to further increasing the resolution.

In addition, among the pixel circuits of the internal compensation method, the simultaneous light emission pixel circuit that sequentially writes data into pixels and then simultaneously emits light for all pixels has a simple configuration and can reduce the number of connected wires, but reduces the time to write data and OLED the time to emit light is reduced.

The present invention has taken this situation into consideration, and an object of the present invention is to provide a pixel circuit structure that overcomes the limitations of pixel design in response to high resolution.

Another object of the present invention is to provide a pixel circuit structure and a driving method that reduce the size of a bezel and improve response speed.

A display device according to an exemplary embodiment of the present invention includes a display panel having a plurality of pixels; and a driving circuit for driving the display panel by supplying signals to data lines, scan lines, and emission lines, wherein a first electrode and a second electrode of each pixel are connected to a first node and a third node, respectively. a driving transistor having a gate electrode connected to the second node; a light emitting diode having a cathode electrode connected to the second power line; a capacitor having a first electrode and a second electrode connected to a reference power line and a second node, respectively; a first transistor having a first electrode and a second electrode connected to the gate electrode and the second electrode of the driving transistor, respectively, and the gate electrode connected to the scan line; a second transistor having a first electrode and a second electrode connected to the second electrode of the driving transistor and the anode electrode of the light emitting diode, respectively, and having a gate electrode connected to the emission line; a third transistor having a first electrode and a second electrode connected to a first power supply line and a first node, and a gate electrode connected to an emission line; and a fourth transistor having a first electrode and a second electrode connected to the data line and the first node, and a gate electrode connected to the scan line.

In one embodiment, the driving circuit divides and drives the display panel into a plurality of blocks in a direction perpendicular to the direction in which the scan line travels, while sequentially writing data to pixels included in one of the plurality of blocks. Light emitting diodes of pixels included in the remaining blocks may simultaneously emit light.

In one embodiment, the driving circuit may apply the same emission signal to emission lines connected to pixels included in the same block.

In one embodiment, the display device further includes a power generation unit for supplying power to the display panel, and the power generation unit alternately supplies a high potential voltage and a low potential voltage to the first power line and the second power line, but all blocks can be supplied simultaneously.

In one embodiment, the power generator applies a high potential voltage to the first power line and the second power line, and the driving circuit generates a scan signal of a turn-off level and an emitter of a turn-on level to the scan line and the emission line, respectively. Light emission of the light emitting diode may be turned off by applying an operation signal.

In one embodiment, the power generator applies a low potential voltage to the first power line and the second power line, and the driving circuit generates a scan signal of a turn-off level and an emitter of a turn-on level to the scan line and the emission line, respectively. A third node may be initialized by applying an option signal.

In one embodiment, the power generator applies a high potential voltage and a low potential voltage to the first power line and the second power line, respectively, and the driving circuit applies a data voltage to the data line for one block of pixels; , A scan pulse of turn-on level is applied to the scan line, and an emission signal of turn-off level is applied to the emission line to apply a data voltage to the first node, or to pixels of the remaining blocks, the scan line The light emitting diode may emit light by applying a scan signal of a turn-off level to and an emission signal of a turn-on level to an emission line.

A method of driving a display device according to another exemplary embodiment of the present invention includes turning off light emitting diodes included in all pixels of a display panel; Initializing anode electrodes of light emitting diodes included in all pixels; and sequentially writing data to pixels of one block among a plurality of blocks in which the display panel is divided and simultaneously emitting light of pixels of the remaining blocks, which are commonly connected to the pixels of the plurality of blocks to supply power. It is characterized in that a high potential voltage and a low potential voltage are alternately supplied to the first power line and the second power line.

In one embodiment, the step of turning off the light emitting diode supplies a high potential voltage to both the first power line and the second power line so that the high potential voltage is applied to the first electrode of the driving transistor of the pixel and the cathode electrode of the light emitting diode of the pixel. can supply

In an embodiment, the initializing may include supplying a low potential voltage to both the first power line and the second power line to initialize the first electrode and the cathode electrode of the driving transistor of the pixel to the low potential voltage.

In an embodiment, in the step of writing and emitting light, a high potential voltage and a low potential voltage may be supplied to the first power line and the second power line, respectively.

In an embodiment, writing and emitting light may include applying a data voltage to a pixel included in one block through a data line, connecting a second electrode of a driving transistor to a gate electrode, and applying the data voltage to the gate electrode. A voltage in which the threshold voltage of the driving transistor is reflected may be formed.

In one embodiment, the step of writing and emitting light is to turn on the driving transistor by supplying a high potential voltage to the first electrode of the driving transistor for pixels included in the remaining blocks, and to turn on the second electrode of the driving transistor and emit light. The light emitting diode may emit light by connecting an anode electrode of the diode and flowing a current corresponding to a voltage stored in a gate electrode of the driving transistor to the light emitting diode.

In one embodiment, for a pixel of one block, after initializing the anode electrode and before sequentially writing data, the gate electrode of the driving transistor may be initialized by connecting the second electrode and the gate electrode of the driving transistor. .

By reducing the number of transistors and reducing the number of driving signal lines compared to the conventional internal compensation pixel structure that sequentially emits light in units of horizontal lines, the aperture ratio of the pixel is increased to secure the pixel design margin, and accordingly, a higher resolution model can be developed. there will be

In addition, it is possible to increase the luminance by increasing the ratio of the light emission time in the frame compared to the conventional simultaneous driving method in which all pixels simultaneously emit light.

In addition, the response speed is improved according to the effect of inserting a black image according to impulse driving during the initialization period and the sensing period.

In addition, light emitting blocks for sequentially outputting light emitting signals by simultaneously emitting light in block units are removed from the gate driving circuit, thereby reducing the size of the bezel.

1 conceptually illustrates a method of driving while sequentially emitting light in a rolling shutter method;
2 conceptually illustrates a method of simultaneously emitting and driving a panel in a global light emission method;
Figure 3 conceptually shows that data is sequentially written in units of horizontal lines according to the present invention, but light is emitted simultaneously in units of blocks,
4 is a block diagram illustrating an organic light emitting display device according to the present invention;
5 shows an equivalent circuit of a pixel according to an embodiment of the present invention;
6 is a waveform diagram of a driving signal for writing data into the pixel circuit of FIG. 5;
7 is a waveform diagram of a driving signal that causes the pixel circuit of FIG. 5 to emit light;
8A to 8D show connections and operations of pixel circuits for each section of the waveform diagram of FIG. 6;
9A and 9C show connections and operations of pixel circuits for each section of the waveform diagram of FIG. 7;
10A and 10B show configurations for applying high-potential power and low-potential power to a first power line and a second power line and waveform diagrams of switching signals,
11A to 11D show voltages of main nodes when changing the low potential voltage applied to the pixel circuit;
12a to 12d show voltages of main nodes according to combinations of capacitor values of a storage capacitor and an OLED;
13 is a comparison between a plane of a pixel according to the present invention and a plane of a conventional pixel;
14 conceptually illustrates the effect of inserting a black image between light emission periods according to the present invention;
15 is a comparison of the GIP configuration according to the present invention and the conventional GIP configuration,
16 is a table comparing sequential light emission driving methods, simultaneous light emission driving methods, and block unit simultaneous light emission driving methods according to the present invention.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numbers throughout the specification indicate substantially the same elements. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted.

1 conceptually illustrates a method of driving while sequentially emitting light in a rolling shutter method.

As shown in FIG. 1, the method of sequentially emitting light from the panel in units of horizontal lines initializes each pixel for about 2 horizontal periods in 1 frame, detects the electrical characteristics of the pixel (Initial & Sensing), and emits light for the remaining period (Emission). , the light emission period is (1 frame period 2 horizontal periods). Also, since the pixel lines are driven in the form of a rolling shutter, the pixel circuit needs to sequentially apply emission signals in addition to two scan signals for data writing and initialization.

Therefore, when the gate driving circuit is formed on the panel in the form of GIP (Gate Drive IC In Panel), light emitting blocks generating light emitting signals are required as many as the number of horizontal lines in addition to scan blocks generating scan signals, and accordingly, the gate driving circuit There is a problem that the size of the bezel is also increased.

In addition, a pixel to which the method of FIG. 1 is applied requires a large number of switching transistors. For example, it is composed of one driving transistor, six switching transistors, and one capacitor, making the pixel configuration complicated, and the initialization voltage line. , the scan line for the previous pixel line, the scan line for the current pixel line, and the light emitting line for the current pixel line. Since these wires cover a large area of the pixel, it is difficult to reduce the pixel size to increase the resolution It becomes difficult to secure the aperture ratio.

2 conceptually illustrates a method of simultaneously emitting and driving a panel in a global light emission method.

The driving method of FIG. 2 initializes all pixels, detects electrical characteristics, writes data to all pixels (Initial & Sensing), and then emits light at the same time (Emission). The pixel to which the method of FIG. 2 is applied consists of only three transistors and one capacitor, so the pixel configuration is simple, and only one scan line and one light emitting line are connected to each pixel, which is advantageous in securing an aperture ratio, and a single common light emitting signal. Since light emission of pixels is controlled, a light emitting block is not required other than a scan block that generates a scan signal.

On the other hand, in FIG. 2, the scan period and the light emission period are 1:1, and the light emission period is half of one frame. As the panel becomes higher in resolution, there is a limit to reducing the data write period, and the light emission period is shorter than in FIG. It becomes difficult to emit light with high luminance.

FIG. 3 conceptually illustrates that data is sequentially written in units of horizontal lines according to the present invention while simultaneously emitting light in units of blocks.

In the present invention, as conceptually shown in FIG. 3, initialization, sensing, and data writing (Initial & Sensing) are sequentially performed in units of horizontal lines from the top to the bottom of the panel, but the panel is divided into a plurality of blocks and each block For , by simultaneously emitting light at the end of writing data (emission), the disadvantages of the sequential light emission driving method and the simultaneous light emission driving method of FIGS. 1 and 2 are complemented and advantages are utilized.

That is, the present invention secures an aperture ratio in pixel design by reducing the number of switching transistors of the pixel circuit for internal compensation compared to the pixel applying the sequential driving method of FIG. 1 and reducing the number of control signals connected to the pixel, and block unit The simultaneous light-emitting method reduces the size of the bezel by reducing the number of light-emitting blocks, allocates a data write period over one frame (period between vertical blanks), and simultaneously emits light in units of blocks for which data has been written, so that the light-emitting period is the same light-emitting period as shown in FIG. It is possible to make it longer than the method, and it is possible to increase the reaction speed with impulse drive.

4 is a block diagram illustrating an organic light emitting display device according to the present invention. A display device according to the present invention may include a display panel 10 , a timing controller 11 , a data driving circuit 12 , a gate driving circuit 13 , and a power generator 16 .

In the display panel 10, a plurality of data lines 14 arranged in a column direction and a plurality of scan lines 15 arranged in a row direction intersect, and pixels PXL are formed in each intersection area. ) are arranged in a matrix form to form a pixel array. The scan lines 15 include a plurality of scan lines (SL) supplied with scan signals for applying data voltages and a plurality of emission lines or emission lines supplied with light emitting signals for controlling light emission of light emitting elements ( Emission Line: EL).

In the pixel array, the pixels PXL disposed on the same horizontal line are connected to one of the data lines 14, one of the scan lines SL, and one of the emission lines EL to form a pixel line. form The pixel is electrically connected to the data line 14 to receive a data voltage in response to a scan signal input through the scan line SL, and emits light in response to an emission signal input through the emission line EL. Light emission of the device can be controlled. Pixels disposed on the same pixel line simultaneously operate according to a scan signal applied from the same scan line SL and an emission signal applied from the same emission line EL.

The display panel 10 is divided into a plurality of blocks based on a vertical direction (second direction) perpendicular to the horizontal direction (first direction) in which the scan line SL travels, and is driven to simultaneously emit light in block units. For example, in FIG. 3, the display panel is divided into four blocks, and the number of blocks is not limited thereto. The same emission signal is applied to the emission line EL connected to the pixel line belonging to the same block, and the pixels PXL belonging to the same block are driven with one emission signal. All pixel lines included in the corresponding block After the data voltage is applied to , the pixels in the corresponding block emit light at the same time.

The pixel may receive a high-potential driving voltage (V _DD ) and a low-potential driving voltage (V _SS ) from the power generation unit 16 and include a light emitting element, a driving transistor, a storage capacitor, and a plurality of switch transistors. The light emitting device may be an inorganic electroluminescent device or an organic light emitting diode (OLED) device. Hereinafter, for convenience, an OLED will be described as an example.

Transistors (or TFTs) constituting the pixel may be implemented in a P-type or N-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) structure, or a hybrid type in which P-type and N-type transistors are mixed. Although a P-type transistor is exemplified in the following embodiments, the present invention is not limited thereto.

A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within a transistor, carriers start flowing from the source. The drain is an electrode through which carriers exit the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain.

In the case of a P-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a P-type MOSFET, since holes flow from the source to the drain, current flows from the source to the drain. In the case of an N-type MOSFET (NMOS), since carriers are electrons, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. Since electrons flow from the source to the drain in an N-type MOSFET, the direction of current flows from the drain to the source.

It should be noted that the source and drain of a MOSFET are not fixed. For example, the source and drain of a MOSFET can change depending on the applied voltage. In the following embodiments, the invention should not be limited due to the source and drain of the transistor, and the source and drain electrodes are also referred to as first and second electrodes without distinction.

Each pixel PXL includes transistors and capacitors for driving the OLED with a current proportional to pixel data and compensating for a change in the threshold voltage of the driving transistor. A specific pixel circuit structure according to an embodiment of the present invention will be described later. do.

The timing controller 11 supplies image data RGB transmitted from an external host system (not shown) to the data driving circuit 12 . The timing controller 11 receives timing signals such as a vertical sync signal (Vsync), a horizontal sync signal (Hsync), a data enable signal (Data Enable, DE), and a dot clock (CLK) from the host system and receives a data driving circuit ( 12) and control signals for controlling the operation timing of the gate driving circuit 13 are generated. The control signals include a gate timing control signal GCS for controlling the operation timing of the gate driving circuit 13 and a data timing control signal DCS for controlling the operation timing of the data driving circuit 12 .

The timing controller 11 is configured to sequentially apply data to all pixels during a period of initializing all pixels during one frame in which image data constituting one screen is applied to pixels constituting the display panel 10 . It is possible to drive by dividing the section and all pixels into sections that simultaneously emit light.

The data driving circuit 12 converts digital video data RGB input from the timing controller 11 into analog data voltages under the control of the timing controller 11 and outputs them to the data lines 14 . In this case, the data voltage may be a value corresponding to an image signal to be displayed by the organic light emitting device.

The gate driving circuit 13 generates a scan signal and an emission signal based on the gate control signal GDC under the control of the timing controller 11, generates the scan signal in a row-sequential manner, and generates at least one pixel connected to each pixel line. The emission signal may be sequentially provided to one or more scan lines SL, and the emission signal may be simultaneously provided to the emission line EL connected to each pixel line.

The gate driving circuit 13 may be composed of a plurality of gate drive integrated circuits each including a shift register, a level shifter for converting an output signal of the shift register into a swing width suitable for driving a TFT of a pixel, and an output buffer. there is. Alternatively, the gate driving circuit 13 may be directly formed on the lower substrate of the display panel 10 in a GIP (Gate Drive IC in Panel) method. In the case of the GIP method, the level shifter may be mounted on a printed circuit board (PCB), and the shift register may be formed on a lower substrate of the display panel 10 .

The power generation unit 16 generates and supplies voltages necessary for the operation of the data driving circuit 12 and the gate driving circuit 13 using an external power supply, and generates a high potential driving voltage (V _DD ) and a low potential driving voltage. A voltage V _SS may be generated and applied to the display panel 10 .

FIG. 5 shows an equivalent circuit of a pixel according to an embodiment of the present invention, and FIGS. 6 and 7 respectively show waveform diagrams of driving signals that write data into the pixel circuit of FIG. 5 or cause the pixel circuit to emit light. will be.

A circuit for driving the organic light emitting diode (OLED) of FIG. 5 is composed of five transistors and one capacitor.

The OLED emits light by the driving current supplied from the driving transistor DT, and the driving transistor DT controls the driving current applied to the OLED according to its source-gate voltage (V _SG ).

The driving transistor DT includes a first electrode connected to the first node N1, a gate electrode connected to the second node N2, and a second electrode connected to the third node N3. Since the transistor DT is a P type, the first node may be the source electrode and the second node may be the drain electrode.

One electrode of the storage capacitor CST is connected to the reference power supply line REF providing a reference voltage, and the other electrode is connected to the second node N2, that is, to the gate electrode of the driving transistor DT. The reference power line REF serves to keep the voltage of the second node N2 constant through the storage capacitor CST.

In the first transistor T1, the first electrode and the second electrode are connected to the second node N2 and the third node N3, which are the gate electrode and the second electrode of the driving transistor DT, respectively. It is connected to the scan line SCAN(n) and participates in writing data voltages and sensing the threshold voltage V _TH of the driving transistor DT.

The second transistor T2 has a first electrode and a second electrode connected to the third node N3, which is the second electrode of the driving transistor DT, and the fourth node N4, which is the anode electrode of the OLED, respectively. The electrode is connected to the emission line EM(i) to control light emission of the OLED.

In the third transistor T3, a first electrode and a second electrode are respectively connected to a first power line PL1 supplying a first power and a first node N1, and a gate electrode has an emission line EM( It is connected to i)) to control the power supply required for initialization, threshold voltage sensing, data writing, and OLED driving.

In the fourth transistor T4, the first electrode and the second electrode are connected to the data line DATA for applying the data voltage and the first node N1, respectively, and the gate electrode is connected to the scan line SCAN(n). It is connected and participates in the writing of data voltage.

In the OLED, the anode electrode is connected to the second electrode of the second transistor T2 and the cathode electrode is connected to the second power line PL2 supplying the second power. In FIG. 5, the OLED capacitor is connected in parallel to the OLED. (C _OLED ) is a capacitor parasitic to OLED rather than connected as a separate element.

The first power supply and the second power supply supplied through the first power line PL1 and the second power line PL2 are not fixed voltages, but a high potential voltage VDD and a low potential voltage VSS.

The pixel circuit of FIG. 5 is for a pixel included in the n-th pixel line of the i-th block, and the pixel circuit of FIG. The operation signal EM(i) is supplied to control the operation of the first to fourth transistors T1 to T4.

Although the embodiment of the present invention discloses that each transistor is implemented as a P type, the semiconductor type of each transistor is not limited thereto. If the driving transistor DT, the first transistor T1 and the second transistor T2 are implemented as N types, the scan signal SCAN and the emission signal EM shown in FIGS. 6 and 7 are inverted. It should be.

6 and 7 show driving signals applied to the i-th block, the i-th block is composed of the first to M th pixel lines, and the scan signals of SCAN(1) to SCAN(M) are sequentially applied, , the same emission signal EM(i) is applied.

The operation of writing data into the pixel circuit of FIG. 5 is composed of the first to fourth sections t1 to t4 of FIG. 6 , and the operation of making the pixel circuit of FIG. 5 emit light includes the fifth to seventh sections of FIG. 7 ( t5 to t4), the first to fourth sections t1 to t4 of FIG. 6 and the fifth to seventh sections t5 to t4 of FIG. 7 are combined to form one frame.

The first to third sections t1 to t3 of FIG. 6 correspond to a first initialization section in which all pixels included in the corresponding block, i.e., the i-th block, are initialized by turning off light emission, and the fourth section t4 corresponds to the i-th block. Corresponds to a sensing and addressing period in which the threshold voltage (V _TH ) of the driving transistor DT is sequentially sensed and data is written from the first pixel line of the block to the Mth pixel line, which is the last pixel line of the i-th block. 5 and 6th sections (t5, t6) correspond to the second initialization section for initializing all the pixels included in the i-th block, and the 7th section (t7) emits OLEDs of pixels included in the ith block simultaneously. Corresponds to the emission period.

In the first block (or first block) positioned at the top of the display panel 10, all sections from the first section t1 to the seventh section t7 coincide with the frame boundary, but from the second block to the last block. In the blocks up to and including, the entire section does not coincide with the frame boundary, the starting point of the first section (t1) of each block is located in the middle of the frame instead of the starting point of the frame, and the ending point of the seventh section (t7) of each block is the next frame. is located in the middle of

Hereinafter, for convenience of explanation, a frame before the start point of the first section t1 is a previous frame, and the current frame starts at the start point of the first section t1 and ends at the end point of the seventh section t7. It is assumed that after the end point of the seventh section t7 is the next frame, that is, the first section t1 to the seventh section t7 are located in the current frame.

8A to 8D illustrate connections and operations of pixel circuits for each section of the waveform diagram of FIG. 6 .

The period before the first period t1 of the current frame (k-th frame) corresponds to the light emission period of the previous frame ((k-1)-th frame), and the potential of the second node N2 is the previous frame ((k-1) (DATA(k-1))-V TH ) obtained by subtracting the threshold voltage (V _TH ) of the driving transistor (DT) from the data voltage (DATA(k-1)) of the )th _frame ), and the third node (N3) The potential of is the operating voltage of the emitting OLED (V _OLED ), that is, the voltage of the anode electrode of the OLED.

Referring to FIG. 8A , in the first period t1, a high potential voltage instead of the low potential voltage V _SS is applied to the second power line PL2 to which the low potential voltage V _SS has been applied during the light emission period of the previous frame. (V _DD ) is applied so that the third node N3 becomes the high potential voltage V _DD , and the high potential voltage V _DD is applied to the first power line PL1 as it is. This is a state in which a meaningful data voltage is not applied to the data line DATA and the voltage is floating.

In the first period t1, scan signals (SCAN(1) to SCAN(M)) of all pixel lines belonging to the i-th block maintain a high logic level as in the last period of the previous frame, so that the first and fourth transistors (T1, T4) are turned off, and the emission signal (EM(i)) is also maintained at a low logic level like the last section of the previous frame, so that the second and third transistors (T2, T3) are turned on state, and the high potential voltage V _DD is applied to the first power line PL1 as it is.

As the cathode electrode of the OLED changes from the low potential voltage (V _SS ) to the high potential voltage (V _DD ), the potential of the anode electrode of the OLED connected to the OLED capacitor (C _OLED ) increases above the high potential voltage (V _DD ). After that, it settles to a high potential voltage (V _DD ). By the second transistor T2 in the turned-on state, the potential of the second electrode of the driving transistor DT, that is, the third node N3 is also higher than the high potential voltage V _DD , like the potential of the anode electrode of the OLED. After increasing to , it settles to a high potential voltage (V _DD ).

The potential of the first electrode N1 of the driving transistor DT maintains the high potential voltage V _DD , and the potential of the third node N3, which is the second electrode of the driving transistor DT, maintains the potential of the driving transistor DT. Since the potential of the first node N1, which is the first electrode of the first node N1, is maintained, the driving transistor DT is turned on in the reverse direction so that the current flows from the second electrode N3 of the driving transistor DT to the first node N1. flows to the electrode N1. The potential of the second node N2, which is the gate electrode of the driving transistor DT, slightly increases around (DATA(k-1))-V _TH according to the change of the first electrode N1 and the second electrode N3. keep the elevated value. Since the driving transistor DT is turned on in the reverse direction and the OLED also stops emitting light, the first period t1 can be referred to as an off period turning off the OLED.

In the first period t1, the anode electrode of the OLED and the second electrode N3 of the driving transistor DT are set to the high potential voltage V _DD to be initialized.

Referring to FIG. 8B , in the second period t2, the first power line PL1 and the second power line PL2 change from the high potential voltage V _DD to the low potential voltage V _SS , and the scan signal (SCAN(1) to SCAN(M)) and the emission signal EM(i) maintain the logic level in the same low logic state as in the previous section, and the data line DATA is in a floating state as in the previous section. .

The potential of the first electrode N1 of the driving transistor DT is increased by the third transistor T3 which maintains a turn-on state according to the low logic level emission signal EM(i). As the voltage of PL1) changes, it becomes a low potential voltage (V _SS ), and the second power line (PL2) changes to a low potential voltage (V _SS ), so the anode electrode of the OLED also changes to a low potential voltage (V _SS ) and turns- Due to the on-state second transistor T2, the second electrode N3 of the driving transistor DT also becomes the low potential voltage V _SS . When the potential of the first electrode N1 of the driving transistor DT is lower than the potential of the gate electrode N2, the driving transistor DT is turned off.

That is, in the second period t2, the anode electrode of the OLED and the second electrode N3 of the driving transistor DT are initialized to the low potential voltage V _SS .

Referring to FIG. 8C , in the third period t3, the first and second power lines PL1 and PL2 maintain the low potential voltage V _SS , and the data line DATA also maintains a floating state. And, the emission signal EM also maintains the same logic level as the previous section, but the scan signals SCAN(1) to SCAN(M) change from a high logic level to a low logic level.

The driving transistor DT maintains a turned-off state, the second and third transistors T2 and T3 maintain a turned-on state, and the first and fourth transistors T1 and T4 maintain a low logic state. It is turned on by the level scan signal (SCAN).

Even if the fourth transistor T4 is turned on, the first node N1 is connected to the first power line PL1 of the low potential voltage V _SS by the third transistor T3 in the turned-on state. and maintains the low potential voltage (V _SS ) as it is.

When the first transistor T1 is turned on, the second node N2 having a potential of (DATA(k-1))-V _TH ) and the third node N3 having a potential of the low potential voltage V _SS Connected to each other, the potential of the second node N2 and the third node N3 becomes ((DATA(k-1))-V _TH +V _SS )/2, which is the intermediate value, and the turn-on The potential of the anode electrode of the OLED also becomes ((DATA(k-1))-V _TH +V _SS )/2 by the two transistors T2.

That is, in the third period t3, the gate electrode N2 of the driving transistor DT is initialized to a potential of ((DATA(k-1))-V _TH +V _SS )/2, which is By initializing the potential of the gate electrode N2 of the first electrode N1 to a value lower than that of the first electrode N1, the image data DATA(k) is transferred to the first electrode N1 of the driving transistor DT in the next section of the current frame. is applied to turn on the driving transistor DT.

When the operation of the third period t3 is not sufficient for initialization, if the operations of the second period t2 and the third period t3 are repeated, the potential of the gate electrode N2 of the driving transistor DT is lowered to a low potential. It can converge to the voltage (V _SS ).

In order to initialize the potential of the gate electrode N2 of the driving transistor DT to a value lower than the potential of the first electrode N1 in the third period t3, the anode electrode of the OLED is lowered in the second period t2. Since it is necessary to set the potential voltage (V _SS ), and the anode electrode of the OLED cannot be set to the low potential voltage (V _SS ) immediately while the OLED is turned off while emitting light in the previous frame, the anode electrode of the OLED is set to the low potential voltage. Prior to setting the voltage (V _SS ), it is necessary to set it to the high potential voltage (V _DD ) in the first period (t1).

That is, the third period t3 is a step of initializing the gate electrode N2 of the driving transistor DT.

Referring to FIG. 8D , in a fourth period t4, the first power line PL1 changes from a low potential voltage V _SS to a high potential voltage V _DD , and the second power line PL2 has a low potential The voltage V _SS is maintained, the emission signal EM(i) of the i-th block changes from a low logic level to a high logic level, and the first pixel line belonging to the i-th block to the data line DATA Data for M pixel lines is sequentially applied up to the Mth pixel line, and the first scan signal SCAN(1) to the Mth scan signal SCAN(M) are generated in synchronization with the data of the data line DATA. are sequentially applied to corresponding pixel lines.

The scan signal, which was at a low logic level in the third period t3, changes to a high logic level at the beginning of the fourth period t4, and then changes to a low logic level when the scan signal is applied to the corresponding pixel line and scans the next pixel line. When a signal is applied, it changes back to a high logic level. That is, after a high logic level scan signal is applied to all pixel lines in the beginning of the fourth period t4, the first scan signal SCAN(1) becomes a low logic level and returns to a high logic level after a predetermined time has elapsed. and, when the first scan signal SCAN(1) changes to a high logic level, the second scan signal SCAN(2) becomes a low logic level and changes to a high logic level after a predetermined period of time. A low logic level scan pulse is sequentially applied to each pixel line from the signal SCAN(1) to the Mth scan signal SCAN(M).

At the beginning of the fourth period t4, the scan signals SCAN(1) to SCAN(M) of all pixel lines become a high logic level, and in the second half of the fourth period t4, the scan signals SCAN( 1) ~ SCAN(M)) becomes a high logic level.

In the fourth period t4, the data voltage DATA(k) of the n-th pixel line (n-th pixel line of the i-th block) of the k-th frame, which is the current frame, is connected to the data line DATA. and the fourth transistor T4 is turned on according to the low logic level scan signal SCAN(n), and the data line DATA is connected to the first electrode N1 of the driving transistor DT. . In addition, when the emission signal EM(i) becomes a high logic level, the third transistor T3 is turned off and the first electrode N1 of the driving transistor DT is disconnected from the first power line PL1. Separated.

Then, the potential of the first node N1, that is, the first electrode N1 of the driving transistor DT becomes DATA(k) and becomes ((DATA(k-1))-V _TH +V _SS )/2 The potential of the initialized gate electrode N2 and the second electrode N3 is higher than the potential of the driving transistor DT, so that the driving transistor DT is turned on in the forward direction. The second node N2 and the third node N3 are connected by the first transistor T1, which is turned on according to the low logic level scan signal SCAN(n), so that the driving transistor DT is a diode It is connected so that the potential of the gate electrode N2 and the second electrode N3 of the driving transistor DT sets the threshold voltage V _TH of the driving transistor DT at DATA(k), which is the potential of the first electrode N1. The subtracted value is (DATA(k)-V _TH ). A voltage corresponding to a difference between the data voltage and the threshold voltage (DATA(k)-V _TH ) is stored in the storage capacitor CST.

The emission signal EM(i) is changed to a high logic level and the second transistor T2 is turned off to separate the driving transistor DT from the OLED, so that the anode electrode of the OLED is at the third period t3. The potential ((DATA(k-1))-V _TH +V _SS )/2 value is maintained as it is.

Since data is sequentially written to all pixels included in the i-th block from the first pixel line to the M-th pixel line in the fourth period t4 and the threshold voltage is sensed, the fourth period t4 includes data writing and threshold voltage This may be referred to as a sensing section.

Referring to FIG. 9A , in a fifth period t5, the scan signal SCAN maintains a high logic level, the data line DATA is in a floating state, and the emission signal EM(i) is at a logic high level. level to a low logic level, the first power line PL1 maintains the high potential voltage V _DD , and the potential of the second power line PL2 changes from the low potential voltage V _SS to the high potential voltage V _DD ).

The first and fourth transistors T1 and T4 are turned off by the high logic level scan signal SCAN, so that the second node N2 is separated from the third node N3 (DATA(k)- V _TH ) potential is maintained, and the first electrode N1 of the driving transistor DT is disconnected from the data line DATA.

The third transistor T3 is turned on by the low logic level emission signal EM(i) so that the potential of the first electrode N1 of the driving transistor DT becomes the high potential voltage V _DD . .

According to the potential change of the second power line PL2, the anode electrode of the OLED has a lower potential than the cathode electrode, and a reverse voltage is applied to the OLED, so that the current does not flow in the forward direction and does not emit light, and the OLED capacitor (C _OLED ) As a result, the potential of the anode electrode of the OLED becomes higher than the high potential voltage (V _DD ) of the second power line (PL2 ) and then settles to the high potential voltage (V _DD ). The second transistor T2 is turned on according to the low logic level emission signal EM(i), and the third node N3 and the anode electrode of the OLED are connected to the second electrode of the driving transistor DT. The potential of (N3) also increases to a high potential voltage (V _DD ) or higher, like the potential of the anode electrode of the OLED, and then settles to the high potential voltage (V _DD ).

The potential of the first electrode N1 of the driving transistor DT maintains the high potential voltage V _DD , and the potential of the third node N3, which is the second electrode of the driving transistor DT, maintains the potential of the driving transistor DT. After becoming higher than the potential of the first node N1, which is the first electrode of the voltage V _DD , the driving transistor DT is turned on in the reverse direction so that the current flows through the driving transistor DT. ) flows from the second electrode N3 to the first electrode N1.

That is, the fifth period (t5) is a period in which the OLED is turned off and the anode electrode of the OLED is changed to a high potential voltage (V _DD ).

Referring to FIG. 9B , in the sixth period t6, the scan signal SCAN maintains a high logic level, the data line DATA maintains a floating state, and the emission signal EM(i) maintains a low logic level. The logic level is maintained, and the first and second power lines PL1 and PL2 change from the high potential voltage V _DD to the low potential voltage V _SS .

The first and fourth transistors T1 and T4 are kept turned off by the high logic level scan signal SCAN, so that the second node N2 maintains the (DATA(k)-V _TH ) potential. And, the connection between the first electrode N1 of the driving transistor DT and the data line DATA is also maintained in a disconnected state.

The third transistor T3 is maintained in a turned-on state by the low logic level emission signal EM(i), and the first voltage of the driving transistor DT is maintained according to the voltage change of the first power line PL1. The potential of the electrode N1 is changed from the high potential voltage (V _DD ) to the low potential voltage (V _SS ).

The second power line PL2 is changed to a low potential voltage (V _SS ), so the anode electrode of the OLED is also changed to a low potential voltage (V _SS ), and the turn-on second transistor T2 turns on the driving transistor DT. The second electrode N3 also becomes the low potential voltage V _SS .

That is, the sixth period t6 is a period in which the second electrode N3 of the driving transistor and the anode electrode of the OLED are initialized to the low potential voltage V _SS .

In addition, the second electrode N3 of the driving transistor and the anode electrode of the OLED are sequentially initialized to the high potential voltage (V _DD ) and the low potential voltage (V _SS ) in the fifth period (t5) and the sixth period (t6) By doing this, it is possible to prevent a restoration afterimage phenomenon in which the current flowing through the OLED is determined by the value stored in the previous frame.

Referring to FIG. 9C , in the seventh period t7, the scan signal SCAN maintains a high logic level and the data line DATA applies a data voltage, which is necessary to apply the data voltage to the pixel line of the next block. For this, the emission signal EM(i) also maintains a low logic level, the first power line PL1 changes from the low potential voltage V _SS to the high potential voltage V _DD , and the second power line (PL2) maintains the low potential voltage (V _SS ).

The cathode electrode of the OLED is lower than the anode electrode so that the current flows in the forward direction, and the turn-on driving transistor DT passes the turn-on second transistor T2 to flow the current to the OLED. The driving transistor ( DT) causes a current corresponding to DATA(k) offset by the threshold voltage (V _TH ) from (DATA(k)-V _TH ), which is the potential of the gate electrode N2 stored in the storage capacitor CST, to flow through the OLED. .

The potential of the source electrode, that is, the first electrode N1 of the driving transistor DT is the high voltage voltage V _DD , and the potential of the gate electrode N2 of the driving transistor DT is (DATA(k)-V _TH ) Therefore, the relational expression for the drive current (I _OLED ) flowing through the OLED becomes Equation 1 below.

In Equation 1, m/2 represents a proportionality constant determined by electron mobility, parasitic capacitance, channel capacitance, and the like of the driving transistor DT.

As shown in Equation 1, since the threshold voltage (V _TH ) component of the driving transistor DT is canceled in the relational expression of the driving current (I _OLED ), even if the threshold voltage of the driving transistor changes, the data The OLED may emit light with a current corresponding to the data voltage input through the line DATA.

That is, the seventh period t7 corresponds to a period in which OLED emits light.

Meanwhile, the fifth to seventh sections (t5 to t7) in the i-th block are sections corresponding to the first to fourth sections (t1 to t4) of the (i+1)-th block, which is the next block. That is, after data is written to all pixels included in the ith block (t1 to t4), the anode electrode of the OLED of all pixels included in the ith block is initialized and the OLED emits light during the period (t5 to t7) For all pixels included in the (i+1)th block, the OLED is turned off, initialized, and data is written (t1 to t4).

Therefore, the fifth and sixth sections t5 and t6 of the i-th block correspond to the first to third sections t1 to t5 of the (i+1) block, and the seventh section t7 of the i-th block corresponds to the fourth section t4 of the (i+1) block.

Since the scan signal and the emission signal are supplied in units of pixel lines, there is no problem even if they are different for each pixel line or each block. However, since the first and second power lines PL1 and PL2 are commonly connected to all pixels, power must be supplied so that a block in which data is written and a block in which OLED emits light can operate synchronously.

In the present invention, data writing is performed sequentially from the first pixel line to the last pixel line, but since light is sequentially performed in block units, while data is written to pixels in one block, pixels in the other blocks emit light. have to do it

For example, during the seventh period t5 in which OLEDs of the pixels included in the ith block emit light, a high potential voltage V _DD and a low potential voltage V are applied to the first and second power lines PL1 and PL2, respectively. _SS ) must be supplied, and to the first and second power lines PL1 and PL2 even during the fourth period t4 of the (i+1)th block, corresponding to the seventh period t7 of the ith block. A high potential voltage (V _DD ) and a low potential voltage (V _SS ) are respectively applied. During the fourth period t4, a high logic level is applied to the emission line EM(i) and the third transistor T3 is turned off, so that the first node N1 connects to the first power line PL1. , it is possible to connect the first node N1 for writing data to the data line DATA.

In addition, during the first to third intervals t1 to t3 in which the OLED is turned off and each node is initialized for the pixels of the i-th block prepared for writing data, the first and second power lines PL1 and PL2 are also connected. As shown in FIG. 6, a high potential voltage (V _DD ) is applied and then a low potential voltage (V _SS ) is applied. The high potential voltage (V _DD ) and the low potential voltage (V _SS ) are alternated between the first and second power lines (PL1 and PL2), so that the OLED is temporarily turned off.

That is, the 5th and 6th sections t5 and t6 of the light-emitting block are sections for temporarily stopping the light emission of the OLED, for the operation of the 1st to 3rd sections t1 to t3 of the block for writing data Corresponds to the inserted section.

When the display panel is divided into I blocks, data writing is sequentially performed block by block, and the remaining blocks emit light at the same time, the period when one frame period is divided by I, i.e., data writing in one block Among the ongoing periods, the intervals t1 and t2 in which light emission of the OLED is turned off and main nodes of the pixel are initialized are commonly applied to blocks in which data is written and blocks that emit light.

In this way, the present invention does not separately supply power to a block in which data is written and a block which emits light, and the data write operation and the light emission operation can be performed simultaneously for each block while sharing the same power line across all pixels. .

10A and 10B illustrate configurations for applying high-potential power and low-potential power to a first power line and a second power line and waveform diagrams of switching signals.

Since the high potential voltage (V _DD ) and the low potential voltage (V _SS ) should be alternately applied to the first power line (PL1) and the second power line (PL2), the first power line (PL1) is connected to the switches S1 and S2 , the second power line PL2 may be connected to the high potential power supply VDD and the low potential power supply VSS through the switches S3 and S4.

The switch S1 operates on the first power line PL1 in the second, fourth, fifth, and seventh sections t2, t4, t5, and t7 where the high potential voltage V _DD is applied to the first power line PL1. is connected (On) to the high potential power supply (VDD), and the switch S2 is the second, third and sixth sections (t2, t3, t6) in which the low potential voltage (V _SS ) is applied to the first power line (PL1) ), the first power line PL1 is connected (On) to the low-potential power supply VSS.

The switch S3 connects the second power line PL2 to the high potential power supply _VDD in the first and fifth sections t1 and t5 where the high potential voltage V DD is applied to the second power line PL2 ( On), and the switch S4 is applied in the second to fourth sections, the sixth section, and the seventh section (t2 to t4, t6, and t7) in which the low potential voltage (V _SS ) is applied to the second power line (PL2). 2 Connect (On) the power line (PL2) to the low potential power supply (VSS).

The power generator 16 of FIG. 4 controls the operation of the switches S1 to S4 to generate a high potential voltage (V _DD ) and a low potential voltage (V _SS ) in the first power line PL1 and the second power line PL2. ) can be alternately supplied.

11A to 11D show the voltages of main nodes when changing the low potential voltage applied to the pixel circuit, when a data voltage of 4V is applied to the first frame and a data voltage of 3V is applied to the second frame. , shows voltages of main nodes in the first to fifth sections of the second frame.

The storage capacitor (CST) is 50f, the OLED capacitor (COLED) is 20f, the high potential voltage (VDD) is 4.6V, and the scan signal (SCAN) and the emission signal (EM(i)) are -8V to 8V. This is a swinging condition, the low potential voltage V _SS applied to the first power line PL1 is fixed at -3V, and the low potential voltage V _SS applied to the second power line PL2 is -3V, respectively. (FIG. 11a), -5V (FIG. 11b), -7V (FIG. 11c), -8V (FIG. 11d) while changing the voltage of the main node was measured. It can be seen that the variation of the potential of the third node N3 increases as the low potential voltage V _SS applied to the second power line PL2 decreases.

12A to 12D show voltages at major nodes according to combinations of storage capacitor and OLED capacitor values.

The data voltage is 4V, the high potential voltage (VDD) is 4.6V, the low potential voltage (V _SS ) is -3V, and the scan signal (SCAN) and the emission signal (EM(i)) are -8V to 8V. Swing, the storage capacitor CST and the OLED capacitor COLED are respectively 30f and 20f in FIG. 12a, 30f and 30f in FIG. 12b, 50f and 20f in FIG. 12c, and 50f and 30f in FIG. 12d.

As the value of the OLED capacitor COLED increases, the variation of the potential of the third node N3 increases, and as the value of the storage capacitor CST increases, the variation of the potential of the third node N3 decreases.

13 is a comparison between a plane of a pixel according to the present invention and a plane of a conventional pixel.

Compared to a conventional pixel circuit that sequentially emits light in units of horizontal lines, the pixel circuit of the present invention reduces four transistors and eliminates the scan signal line (SCAN(n-1)) of the previous pixel line, resulting in higher resolution. It is possible to secure a margin in pixel design for resolution model development and increase the aperture ratio.

14 conceptually illustrates the effect of inserting a black image between emission periods according to the present invention. One frame in each block is divided into an initialization/sensing period in which nodes are initialized, threshold voltages are sensed, and data is written, and an emission period in which all pixels within the corresponding block simultaneously emit light. During the initialization/sensing period, OLED is turned off and emission period By the impulse driving that turns on the OLED, an effect of inserting a black image between the light emission periods can be obtained, and accordingly, moving picture response time (MPRT) related to response time can be improved.

15 is a comparison between the GIP configuration according to the present invention and the conventional GIP configuration.

In order to sequentially emit light in units of conventional horizontal lines, not only a scan signal (SCAN) but also an emission signal (EM) must be sequentially applied to each pixel line. For this purpose, a scan block for generating scan signals in the GIP and Emission Block must be prepared.

However, in the present invention, since data is sequentially written to all pixels included in the block in units of blocks and then emitted at the same time, a scan block for sequentially supplying a scan signal (SCAN) to each pixel line This GIP should be provided, but since the emission signal (EM) is simultaneously applied to all pixel lines included in the block, an emission block is not required or only a small number of emission blocks are required, reducing the bezel covering the GIP. can

16 is a table comparing sequential light emission driving methods, simultaneous light emission driving methods, and block unit simultaneous light emission driving methods according to the present invention.

The pixel circuit configuration is complicated by using 7 transistors and 1 capacitor in the sequential emission driving method of FIG. 1, but the simultaneous emission driving method of FIG. 2 uses 3 transistors and 1 capacitor, is simpler compared to FIG. 1 using 5 transistors and 1 transistor.

In addition, looking at the number of horizontal wires connected to the pixel line in the horizontal direction, the sequential light emission driving method of FIG. )), the emission line EM(n) of the current pixel line, and the initialization line INITIAL. two, including the emission line (EM) common to the pixel, and the present invention of FIG. There are three including the line (REF).

In addition, looking at the number of emission lines, the sequential emission driving method of FIG. 1 is N, which is the number of horizontal lines of the display panel, and the simultaneous emission driving method of FIG. 2 is one because it is common to all pixels included in the panel. Since the present invention of 3 is common for each block, I is the number of blocks in which the display panel is divided.

In addition, looking at the emission time, the sequential emission driving method of FIG. 1 is the time (1 Frame 2H) excluding 2H of initializing pixels, sensing threshold voltages, and writing data voltages in one frame, and the simultaneous emission driving method of FIG. 2 is 1/2 Frame when the ratio of data writing time and light emission time is 1:1, and the present invention of FIG. 3 subtracts the period of writing data in one block from 1 frame ((I-1) / frame).

In addition, looking at the charging time, which is the time for writing data into the pixels, the sequential emission driving method of FIG. 1 is 1H, the simultaneous emission driving method of FIG. 2 is 1/2H, and the present invention of FIG. 3 is 1H.

That is, the present invention, which simultaneously emits light in block units, compromises the sequential light emission driving method of FIG. 1 and the simultaneous light emission driving method of FIG. 2, and has a relatively simple pixel configuration and horizontal wiring compared to the sequential light emission driving method of FIG. There are advantages in that the number is small, the number of emission wires is small, and compared to the simultaneous emission driving method of FIG. 2 , the emission time and charging time are longer.

Through the above description, those skilled in the art will know that various changes and modifications are possible without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

10: display panel 11: timing controller
12: data driving circuit 13: gate driving circuit
14: data line 15: scan line
16: power generating unit

Claims (13)

a display panel having a plurality of pixels; and
a driving circuit supplying signals to data lines, scan lines, and emission lines to drive the display panel;
each pixel,
a driving transistor having a first electrode and a second electrode connected to a first node and a third node, respectively, and a gate electrode connected to the second node;
a light emitting diode having a cathode electrode connected to the second power line;
a capacitor having a first electrode and a second electrode connected to a reference power line and the second node, respectively;
a first transistor having a first electrode and a second electrode connected to the gate electrode and the second electrode of the driving transistor, respectively, and having a gate electrode connected to the scan line;
a second transistor having a first electrode and a second electrode connected to the second electrode of the driving transistor and the anode electrode of the light emitting diode, respectively, and having a gate electrode connected to the emission line;
a third transistor having a first electrode and a second electrode connected to a first power line and the first node, and a gate electrode connected to the emission line; and
a fourth transistor having a first electrode and a second electrode connected to the data line and the first node, and a gate electrode connected to the scan line;
The driving circuit divides and drives the display panel into a plurality of blocks in a direction perpendicular to the direction in which the scan line travels, and sequentially writes data into pixels included in one of the plurality of blocks while the remaining blocks are sequentially written. A display device that simultaneously emits light from light emitting diodes of pixels included in a block. delete According to claim 1,
The driving circuit applies the same emission signal to emission lines connected to pixels included in the same block. According to claim 1,
Further comprising a power generation unit for supplying power to the display panel;
The display device of claim 1 , wherein the power generation unit alternately supplies a high potential voltage and a low potential voltage to the first power line and the second power line, and simultaneously supplies them to all blocks. According to claim 4,
The power generator applies the high potential voltage to the first power line and the second power line, and the driving circuit generates a scan signal of a turn-off level and an emitter of a turn-on level to the scan line and the emission line, respectively. by applying an option signal to turn off the light emission of the light emitting diode,
The power generator applies the low potential voltage to the first power line and the second power line, and the driving circuit generates a scan signal of a turn-off level and an emitter of a turn-on level to the scan line and the emission line, respectively. and initializing the third node by applying an option signal. According to claim 5,
The power generator applies the high potential voltage and the low potential voltage to the first power line and the second power line, respectively;
The driving circuit applies a data voltage to the data line, a scan pulse of a turn-on level to the scan line, and an emitter of a turn-off level to the emission line for the pixels of the one block. applying a data voltage to the first node by applying a data voltage;
The driving circuit applies a turn-off level scan signal to the scan line and a turn-on level emission signal to the emission line for the pixels of the remaining blocks, so that the light emitting diode emits light A display device characterized in that
a display panel having a plurality of pixels; and
A display device driving method including a driving circuit for driving the display panel by supplying signals to data lines, scan lines, and emission lines,
turning off light emitting diodes included in all pixels provided in the display panel;
initializing anode electrodes of light emitting diodes included in all the pixels; and
The driving circuit divides and drives the display panel into a plurality of blocks in a direction perpendicular to the direction in which the scan line travels, and sequentially writes data into pixels included in one of the plurality of blocks while the remaining blocks are sequentially written. Simultaneously emitting light-emitting diodes of pixels included in the block;
and alternately supplying high potential voltages and low potential voltages to a first power line and a second power line that are commonly connected to the pixels of the plurality of blocks to supply power. According to claim 7,
The step of turning off the light emitting diode may include supplying the high potential voltage to both the first power line and the second power line so that the high potential is applied to the first electrode of the driving transistor of the pixel and the cathode electrode of the light emitting diode of the pixel. A method of driving a display device characterized by supplying a voltage. According to claim 8,
The initializing may include supplying the low potential voltage to both the first power line and the second power line to initialize the first electrode and the cathode electrode of the driving transistor of the pixel with the low potential voltage. How to drive a display device that does. According to claim 9,
In the step of writing and emitting light, the high potential voltage and the low potential voltage are supplied to the first power line and the second power line, respectively. According to claim 10,
In the step of writing and emitting light, a data voltage is applied to the pixels included in the one block through a data line, and a second electrode of the driving transistor is connected to a gate electrode so that the data voltage is applied to the gate electrode. The method of driving the display device comprising forming a voltage reflecting the threshold voltage of the driving transistor. According to claim 10,
The writing and emitting of light may include turning on the driving transistor by supplying the high potential voltage to the first electrode of the driving transistor for the pixels included in the remaining blocks, and The method of driving the display device, characterized in that by connecting the anode electrode of the light emitting diode to flow a current corresponding to the voltage stored in the gate electrode of the driving transistor to the light emitting diode to emit light. According to claim 9,
For the pixels of the one block, after initializing the anode electrode and prior to sequentially writing the data, initializing the gate electrode of the driving transistor by connecting the second electrode and the gate electrode of the driving transistor. A method of driving a display device, characterized in that it further comprises.

Images