KR102490726B1 - Apparatus for generating time synchronization signal linked to master clock, System for monitoring protection control automatically, and Method thereof - Google Patents

Abstract

An apparatus for generating a time synchronization signal linked to a master clock to improve synchronization precision of oscillation pulses in each facility and to secure continuity and stability even if a temporary problem occurs in communication with a master clock. The apparatus for generating a time synchronization signal linked to a master clock includes a master clock generator for generating master clock information, and time synchronization information in conjunction with the master clock information transmitted before the signal cut off state in a signal cut off state with the master clock generator. It is characterized in that it comprises a self-oscillation unit that generates.

Description

Apparatus for generating time synchronization signal linked to master clock, System for monitoring protection control automatically, and Method thereof}

The present invention relates to a time synchronization signal generation technology, and more particularly, to an apparatus and method for generating a time synchronization signal linked to a master clock capable of operating a high-efficiency, high-performance protection control automation system by providing a high-precision time synchronization clock.

As various protection control automation facilities in the field of substation are digitized, facilities are simplified, operational reliability and utilization of various information are further enhanced. In order to efficiently respond to the expanding power supply and demand, an intelligent power grid is gradually being introduced.

To this end, the communication method of the power system constituting the monitoring/protection/control automation substation at home and abroad tends to be established as an international standard based on IEC (International Electrotechnical Commission) 61850.

IEDs (Intelligent Electronic Devices, relays) are installed to enable power monitoring, emergency operation, and relay operation in units of substation facilities such as breakers and transformers. This IED has the ability to monitor current, voltage, phase difference, etc. from each field device at all times and classify accidents immediately. In addition, when an accident occurs in the power supply system, a wide range of lines are protected so that the failure does not spread to other facilities or the entire power supply network to maintain stability and consistency of power supply.

However, if the synchronous error value of current, voltage, phase, etc. received from the IED expands, the substation automation system cannot normally perform protection, control, and monitoring functions, and the frequency of power system failures and blackouts inevitably increases. .

In particular, in future intelligent power grid systems, the level of synchronization of data used in facilities becomes more and more important, and the implementation of high-precision time synchronization devices for intelligent power grid systems is highly functional application systems such as AI (Artificial Intelligence) systems, self-healing systems, and automatic fault recovery systems. It is a key prerequisite for implementation of

In addition, in general, a local oscillator existing in an individual device for time synchronization between devices of an automation system mainly uses quartz crystals. Although a more expensive material may be used for the crystal material for visual synchronization in order to achieve high precision, it is common to use an appropriate material to strike a trade-off between price and performance.

The problem is that a crystal material used as a time-synchronized oscillator causes drift errors on the time axis when generating an oscillation clock due to thermal, mechanical, or aging effects. In particular, the problem of thermal movement (drifts error) is emerging as the most difficult problem in field use of high-precision systems.

In general, IED has a built-in ADC (Analog to Digital Converter) device or a fixed oscillator (oscillator) inside the clock device to generate a sampling clock inside the MU. A synchronization signal from the master clock (main clock source) is received through this oscillator, and the time difference with the internal fixed oscillator is corrected.

In the method of using this time difference signal as a sampling reference point, if the synchronization signal of the master clock is momentarily lost, in a large-scale network system, major signals such as voltage and current are generated by an internal fixed oscillator that is not synchronized with the master clock during that period. As sampling proceeds, a problem occurs in the protection control function.

At this time, the standard related to the accuracy of the internal error of the fixed oscillator is 1 [nsec] in the international standard for the time synchronization accuracy of electronic devices on the transmission path such as SV (Sampled Value) transmitter (MU: Merging unit) and IED in IEC 61850. Although it is specified as inside or outside, it implements its own hardware performance, and precision operation in conjunction with the master clock is impossible, so time synchronization errors may increase.

However, when multiple devices are connected by a bus-type network, protection control requirements for the protection of power facilities such as substations are presented because production guides do not exist in related standards such as IEC for electronic devices on multiple transmission paths. However, it is becoming a constraint for the implementation of an effective network system.

In addition, referring to FIG. 1, referring to the operation algorithm, the reference (Pulse Per Second) signal transmitted every second from the GPS (Global Positioning System) receiver (or IEEE 1588 PTP (Precision Time Protocol) signal and the output clock of the self-fixed oscillator The phase/time information due to the delay between the phases is compared (steps S110 and S120), the difference is corrected (steps S101, S130 and S140), and a sampling clock signal is provided to synchronize with the reference PPS. (Step S150).

The operating characteristics of existing facilities do not cause problems in general operating environments or facility conditions where the facility or system configuration is simple or the master clock providing the reference clock is operated without loss (interruption). However, if the PPS signal, which is the reference clock, is lost, or if the network system constituting the facility has a complex structure, it is difficult to maintain accuracy in synchronizing with other facilities such as IED and MU inside the network system, resulting in accurate protection control monitoring. function cannot be performed.

In addition, referring to FIG. 2, looking at the conceptual diagram of using the self-clock by the self-oscillator when the reference signal is cut off, the master clock provides a PPS signal of 1 clock per second, and the self-clock signal from the self-oscillator of each individual device for 1 second of the interval. will provide In this case, when the master clock signal is lost, it depends on the precision of the oscillator for each device, and it is difficult to perform the normal protection control function as the precision is low or the master clock blocking time is long.

In other words, the core of time synchronization in existing facilities is a structure that provides a sampling clock signal to improve clock precision by compensating for a difference in time delay between devices.

However, it is difficult to maintain time synchronization accuracy when the master clock is lost or when a system having a complex structure is applied. In other words, in the existing international standard (IEC)-based system, as the size of the system expands, the topology (structure) of the network system becomes more complex and the number of component devices increases, ensuring proper time synchronization between IEDs, MUs, and other facilities in the substation. this becomes difficult Therefore, it is impossible to normally perform the protection control and monitoring function of power facilities such as substations, causing malfunction of the system.

In other words, it compares the PPS signal transmitted every second from the GPS receiver with the output clock of the oscillator in the device and synchronizes with the reference PPS by correcting the delay difference. Synchronization accuracy requirements are stipulated at the level of 1 [nsec] in the international standard (IEC), and some global manufacturers are producing products.

The time synchronization level regulated by IEC increases as the loss time of the reference signal increases and the number of devices connected to one network (ring structure; HSR (High-available Seamless Redundancy) method) increases due to the large size of the substation. Inconsistency issues arise.

In addition, in a parallel configuration (PRP (Parallel Redundancy Protocol) method) network configuration, if an individual operating device cannot receive (lose) the reference clock for a long time (more than 1 second), the oscillation clock is implemented in hardware for each individual device. has limitations in maintaining high-precision time synchronization interlocked with the master clock, so it is difficult to satisfy the high-reliability time synchronization accuracy required by network systems.

In addition, when the master clock, which is the reference clock, is lost, the error of the oscillator inside the device increases over time, and the accuracy of signal sampling decreases, causing malfunction of the system.

1. Korea Patent Publication No. 10-2010-0101998

The present invention has been proposed to solve the problems caused by the above background art, and even if a temporary problem occurs in communication with the master clock, the synchronization precision of oscillation pulses in each facility is improved, persistence, and stability are secured. An object of the present invention is to provide an apparatus and method for generating a master clock-linked time synchronization signal.

In addition, the present invention is PID (Proportional Integral Derivative Control) control and Apparatus and method for generating a time synchronization signal linked to a master clock that enables the operation of a highly reliable time synchronization system by maintaining stable high accuracy of the clock for time synchronization using voltage conversion technology of control output value, voltage controlled oscillator, etc. It has a different purpose to provide.

In order to achieve the object presented above, the present invention improves the synchronization precision of oscillation pulses in each facility and secures continuity and stability even if a temporary problem occurs in communication with the master clock. A signal generating device is provided.

The apparatus for generating a time synchronization signal linked to the master clock,

a master clock generator generating master clock information; and

and a self-oscillation unit generating time synchronization information in association with the master clock information transmitted before the signal blocking state in a signal blocking state with the master clock generator.

In addition, the master clock information may be a first PPS (Pulse Per Second) signal based on wireless communication information or a second PPS signal based on wired communication information.

In addition, the master clock generator may include a first receiver for generating the first signal; a second receiver generating the second signal; and a selector for selecting and outputting the first signal or the second signal.

In addition, the self-oscillation unit may include a difference comparator that compares the master clock information and the self-oscillation clock signal to extract a difference value; a PID controller calculating a control value from the difference value using a proportional-integral-differential controller (PID) control scheme; and a synchronization information generator generating the time synchronization information in association with the master clock information according to the control value.

In addition, the synchronization information generator may include a numerical-voltage conversion unit that converts the control value into a control voltage value; and a voltage controlled oscillation unit configured to generate the target time synchronization information through voltage value control according to the control voltage value.

In addition, the time synchronization information is characterized in that it is calculated using an average value of the master clock information for a predetermined time immediately before the signal blocking state in the signal blocking state.

In addition, the synchronization information generator does not adjust the control value when the difference value is within the reference range after comparing the difference value with a preset reference range.

In addition, the synchronization information generator is characterized in that it generates an oscillation frequency using a numerical control method.

In addition, the wireless communication information is GPS (Global Positioning System) information, and the wired communication information is IEEE (Institute of Electrical and Electronics Engineers) 1588 PTP (Precision Time Protocol), which is a packetized time synchronization signal using an Ethernet communication network. to be

In addition, the self-oscillation unit is characterized in that it recognizes the signal cut-off state when the master clock information is not continuously input for a certain period of time preset from the master clock generator.

On the other hand, another embodiment of the present invention is a time server having a master clock generator for generating master clock information; and a plurality of clients having self-oscillating units that generate time synchronization information in association with the master clock information transmitted before the signal cutoff state in a signal cutoff state with the master clock generator.

On the other hand, another embodiment of the present invention, (a) the master clock generator generates the master clock information; (b) checking, by the self-oscillation unit, a signal blocking state with the master clock generator; and (c) as a result of checking, if the signal is cut off, generating time synchronization information by a self-oscillating unit in association with the master clock information transmitted before the signal cut off. A method for generating a time synchronization signal is provided.

Here, the step (a) may include generating the first signal by a first receiver; generating the second signal by a second receiver; and selecting and outputting the first signal or the second signal by a selector.

In addition, the step (c) may include: (c-1) extracting a difference value by comparing the master clock information and a self-oscillating clock signal by a difference comparator; (c-2) calculating, by a PID controller, a control value from the difference value using a proportional-integral-differential controller (PID) control method; and (c-3) generating, by a synchronization information generator, the time synchronization information in association with the master clock information according to the control value.

In addition, the step (c-3) may include converting the control value into a control voltage value by a numerical-voltage conversion unit; and generating, by a voltage controlled oscillation unit, the target time synchronization information through voltage value control according to the control voltage value.

In addition, the step (b) includes recognizing that the self-oscillation unit is in the signal blocking state when the master clock information is not continuously input for a predetermined time set in advance from the master clock generator. do.

According to the present invention, a high-precision time synchronization clock function capable of operating a signal sampling operation by optimizing the level of time synchronization with a master clock using an algorithm and device capable of synchronizing with a master clock can be implemented.

In addition, another effect of the present invention is that it is possible to maintain a high-precision, high-stability time synchronization state linked to the master clock even when the system temporarily loses the synchronization signal from the master clock.

In addition, as another effect of the present invention, a method for implementing high-precision time synchronization uses devices such as a time of flight (TOF) differential comparator and a numerically controlled oscillator (NCO, Numerically Controlled Oscillator), and synchronizes the oscillator in the device with the master clock. For example, it is possible to operate a high-reliability system by applying an algorithm that controls and adjusts signal differentials to provide a high-precision voltage-controlled clock signal.

In addition, as another effect of the present invention, even in terms of time synchronization of a packet transmission method using IEEE (Institute of Electrical and Electronics Engineers) 1588 PTP (Precision Time Protocol), for a system that is limited to a maximum of 15 nodes (750ns) It is possible to configure more than 20 to 30 nodes by applying the master clock-linked time synchronization algorithm.

1 is a flowchart showing a time synchronization operating mechanism and operating principle of a typical existing facility.
2 is a conceptual diagram of using a self-clock by a self-oscillator when a general reference signal is cut off.
3 is a conceptual block diagram of an apparatus for generating a time synchronization signal linked to a master clock for generating a high-precision clock using a master clock prior to loss when a reference signal is cut off according to an embodiment of the present invention.
FIG. 4 is a detailed block diagram of the device for generating a time synchronization signal linked to a master clock shown in FIG. 3 .
5 is a conceptual diagram of time synchronization between facilities in the power system protection control monitoring automation system according to an embodiment of the present invention.
6 is a flowchart showing a process of generating a high-precision time synchronization clock according to an embodiment of the present invention.
7 is a conceptual diagram of an automated power system protection control monitoring system through time synchronization according to an embodiment of the present invention.

Since the present invention can make various changes and have various embodiments, specific embodiments will be illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and scope of the present invention.

In describing each figure, like reference numbers are used for like elements. Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. These terms are only used for the purpose of distinguishing one component from another.

For example, a first element may be termed a second element, and similarly, a second element may be termed a first element, without departing from the scope of the present invention. The term "and/or" includes any combination of a plurality of related listed items or any of a plurality of related listed items.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs.

Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and unless explicitly defined in this application, it should not be interpreted in an ideal or excessively formal meaning. Should not be.

Hereinafter, an apparatus and method for generating a time synchronization signal linked to a master clock according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a conceptual block diagram of an apparatus 300 for generating a time synchronization signal linked to a master clock for high-precision clock generation using a lost master clock when a reference signal is cut off according to an embodiment of the present invention. Referring to FIG. 3, the master clock-linked time synchronization signal generation apparatus 300 synchronizes the time by linking the master clock generator 310 and the master clock generator 310 even when the signal is blocked, in conjunction with the master clock. It is characterized in that it is configured to include a self-oscillation unit 321 that generates information.

The master clock generator 310 generates a master clock and transmits it to individual devices 320 . The master clock is transmitted to the individual devices 320 at regular intervals. The individual device 320 may be an Intelligent Electronic Device (IDE), a Merging Unit (MU), or the like.

An IDE is a digital protection relay or intelligent electronic device, and generally receives analog signals such as transmission and distribution lines, generators, and load voltages and currents, and detects the presence of accidents in the power system through signal processing. In addition, in the event of an accident such as short circuit, ground fault, or open circuit, it is a power system protection device that quickly separates the faulty line from the sound line to limit damage to a minimum range.

In addition, by storing event occurrence information such as relay element operation due to an accident, state change of input/output contact points, and various device setting changes along with the occurrence time information, it provides a function that facilitates failure analysis and inquiry of device operation details. .

MU is an analog-to-digital (Analog to Digital) signal conversion and transmission device that samples analog input signals in the field, converts them to digital values according to the IEC 61850 standard, and transmits them.

The master clock generator 310 and the self-oscillation unit 321 are connected through a signal line (not shown). Analog signals (current, voltage, phase, etc.) are converted into digital signals inside the individual device 320 and output. Acquisition signals (or measurement signals) such as sampled value (SV) and status signal value received by the individual device 320 from the MU share information between IEDs, and the IED is Reports and status values are transmitted through GW (Gate Way), etc.

Referring to FIG. 3, the merging unit (MU) converts the signal source in the field into a digital value and extracts and outputs SV data, and the MUs installed at different points are connected to the master clock (master clock) visual motivation is essential.

If the time synchronization does not satisfy the normal range, when the phases of the voltage data and current data measured on the same line are processed in each MU, an error occurs due to the sampling time mismatch during the digital conversion of the analog signal. It may cause equipment malfunction.

In other words, synchronization 323 between the master clock-linked clock signal generated by the self-oscillation unit 321 and the acquisition signal is performed to prevent such an error. Of course, time synchronization between the master clock generator 310 and the self-oscillation unit 321 to match one reference time is performed for this purpose.

However, signal blocking may occur between the self-oscillating unit 321 and the master clock generator 310 configured in the individual device 320 . In this case, the self-oscillation unit 321 has an algorithm for generating a master clock-linked clock signal using master clock information (ie, a reference signal) received from the master clock generator 310 before the signal is cut off.

In other words, by the algorithm implemented in the self-oscillation unit 321, the long-term signal is acquired and accumulated in advance before the reference signal transmitted from the master clock generator 310 is lost, and the accuracy and precision of the master clock information A visual synchronization signal is generated and implemented by pre-learning, analyzing, and controlling the pattern for the level within the self-oscillator. That is, a high-precision time synchronization clock associated with master clock information is provided.

FIG. 4 is a detailed block diagram of the apparatus 300 for generating a time synchronization signal linked to a master clock shown in FIG. 3 . Referring to FIG. 4, the master clock generator 310 receives GPS information and generates a first signal that is a PPS (Pulse Per Second) signal, the first receiver 411 receives PTP information and generates a second signal that is a 1588 PPS signal. It may be configured to include a second receiver 412 that generates a signal, and a selector 413 that selects and outputs the first signal or the second signal.

The first and second receivers 411 and 412 may include communication modems, electronic circuit elements, and the like. In particular, the second receiver 412 may include a local area network card (LAN card).

The selector 413 may include a multiplexer, a microprocessor, a switching circuit, and a memory. Memory is a flash memory type, a hard disk type, a multimedia card micro type, and a card type memory (e.g., SD (Secure Digital) or XD (eXtreme Digital)). memory, etc.), RAM (Random Access Memory, RAM), SRAM (Static Random Access Memory), ROM (Read Only Memory, ROM), EEPROM (Electrically Erasable Programmable Read Only Memory), PROM (Programmable Read Only Memory), magnetic memory , a magnetic disk, and an optical disk may include at least one type of storage medium.

Sampling values such as voltage and current must exactly match time or phase information to perform accurate protection control and monitoring functions. To this end, all devices required in the system are synchronized and operated through the master clock generator 310 At this time, a generally used clock signal is a PPS (Pulse Per Second) signal.

Meanwhile, in recent years, digital conversion is performed directly at a signal source in the field using a process bus according to the Ethernet-based IEC 61850 standard, and digital data is transmitted. At this time, it is operated by transmitting digital data from the IED based on the IEC61850-9-2 (Sampled Value, SV) standard through an on-site MU or optical CT (Current Transformer)/PT (Potential Transformer). The signal uses a PTP (Precision Time Protocol) signal having a digitized packet form.

In addition, the IEEE 1588 PTP signal, which is widely applied to global digital substations, is emerging as a safe method that can be effectively used in network systems as a time synchronization method for distributing reference time information through Ethernet networks in substations.

Meanwhile, in order to compensate for the lack of time synchronization accuracy, IEC 61588 and IEEE require time synchronization with the master clock to be performed using an IEEE1588-PTP-based time synchronization method to process the time synchronization signal of the MU.

The following table compares the characteristics of time synchronization technology applied with PTP.

PTP network time protocol (NTP) Inter-range instrumentation group (IRIG)-B precision 1microsecond 1 millisecond 1microsecond Visual Synchronous Operating Structure master-slave server-client master-slave Hardware support required need Unnecessary need Time Synchronous Network Configuration LAN Wide Area Network (WAN) dedicated cable

In spite of the guidance of new international standards such as IEEE PTP, when using IEEE PTP and TC (Transparent Clock) in a system connected within a single ring of devices such as MUs, switches, and IEDs, the number of devices is increased to implement an effective protection control automation system. is inevitable As a result, the time synchronization error expands and acts as a limiting factor in the connection of multiple devices or the configuration of a network system. In addition, the configuration of nodes using IEEE 1588 PTP and TC reduces the maximum limit of precision error (1 μs) inside the device. As a measure to satisfy, considering the margin, about 750ns is specified as a limit, and the number of serial configuration nodes (devices) in the network is limited to approximately 15 at most. This soon acts as a constraint for the design and configuration of an effective network system.

The problem of time synchronization accuracy deterioration due to the loss of the reference signal is the same environment for both PPS and PTP signals, but considering some other characteristics such as the signal delay problem of the PPS and PTP signals provided as reference signals, time synchronization is performed in conjunction with the master clock information. generate information

The signal delay characteristics and characteristics of PPS and IEEE 1588 PTP clocks are as follows.

division signal signal delay problem note Cable (wiring or optical) processing unit Calibration Difficulty
PPS Duration consistent (regular) irregular dragon
IEEE1588 PTP Irregular (unstable) time required
- Utilization of Ethernet communication network
- Jitter generation-optical bridge, etc. SV Signal: Data Gathering
-Self-oscillator hold over difficulty
T/C utilization

Referring to FIG. 4 , the self-oscillation unit 321 compares the master clock information, which is a reference synchronization signal, with the self-oscillation clock signal to extract a difference value from the difference comparator 420 and the PID control method. It may include a PID (Proportional-Integral-Differential controller) controller 430 that calculates a control value, a synchronization information generator 440 that generates time synchronization information in conjunction with master clock information according to the control value, and the like. The differential comparator 420 may be a Time Of Flight (TOF) differential comparator. That is, the self-oscillation unit 321 optimizes the master clock information and time synchronization level by comparing Time Of Flight (TOF) differences.

In other words, the self-powered unit 321 oscillates with an internal oscillator at a specific frequency (eg, 1 MHz). Therefore, in order to minimize the error generated by comparing the master clock information with the reference clock, the PID controller 430 and the synchronous information generator 440, which is a numerically controlled oscillator, are used. In addition, by adjusting the oscillation frequency interval by a software method, the oscillation period of the self-oscillating oscillator is adjusted, and the precision between the self-oscillator clock and the reference clock can be adjusted (stabilized) to the level of nsec.

The synchronization information generator 440 includes a numerical-voltage conversion unit 441 that converts the control value generated by the PID controller 430 into a control voltage value, and a voltage control oscillation unit 442 that generates a synchronization clock according to the control voltage value. ).

In other words, the numerical-voltage conversion unit 441 matches the control value and the control voltage value in the form of a lookup table, and converts the control value into a control voltage value. Of course, it is also possible to convert using a mathematical expression. The voltage controlled oscillator 442 generates an oscillation frequency for a control voltage value using a numerical control method. To this end, an oscillator (NCO), electronic circuit elements, and the like are configured. Frequency and clock are inversely proportional. Thus, if the frequency is calculated, the clock can be calculated.

The numerical-voltage conversion unit 441 refers to a unit that processes at least one function or operation, and may be implemented in software and/or hardware. In hardware implementation, ASIC (application specific integrated circuit), DSP (digital signal processing), PLD (programmable logic device), FPGA (field programmable gate array), processor, microprocessor, other It may be implemented as an electronic unit or a combination thereof. In software implementation, software component components (elements), object-oriented software component components, class component components and task component components, processes, functions, properties, procedures, subroutines, segments of program code, drivers, firmware, microcode, data , databases, data structures, tables, arrays, and variables. Software, data, etc. may be stored in memory and executed by a processor. The memory or processor may employ various means well known to those skilled in the art.

5 is a conceptual diagram of time synchronization between facilities in the power system protection control monitoring automation system according to an embodiment of the present invention. Referring to FIG. 5 , a master clock generator 520 is configured in the time server 520 . Therefore, when the master clock generator 520 receives GPS information from the GPS satellite 510 through the GPS receiver 411, the master clock information, which is time information, is transmitted to an individual device 320 installed in another facility by using the GPS information. is transmitted to the first to nth clients 530-1 to 530-n corresponding to . Of course, the self-oscillation unit 321 is installed in the first to nth clients 530-1 to 530-n.

Also, the first to nth clients 530-1 to 530-n may provide reference clocks to each other as well. For example, when a communication connection failure with the time server 520 occurs, the first client 530-1 may provide a reference clock to the second client 530-2.

In addition, in terms of utilizing the packetized time synchronization signal (IEEE 1588 PTP) transmission method using the IEC 61850 Ethernet communication network, 20 to 30 or more nodes (meaning servers, clients, etc.) are applied by applying a master clock-linked clock control and transmission algorithm ), an effective network system is possible even for large-scale power facilities.

6 is a flowchart illustrating a process of generating a high-precision time synchronization clock according to an embodiment of the present invention. Referring to FIG. 6, when the master clock generator 310 generates master clock information (ie, master time synchronization signal) and transmits it periodically, the self-oscillation unit 321 determines whether such an input signal is continuously provided. (Steps S601 and S602). In other words, while the master clock information, which is a reference signal, is transmitted from the master clock generator 310 to the self-oscillation unit 321 through the signal line between the master clock generator 310 and the self-oscillation unit 321, due to a sudden communication failure. determine whether the signal is blocked. Communication failure occurs when a reference signal is lost or when a network system constituting a facility has a complex structure.

In step S602, if it is determined that the input signal is continuously provided, the self-oscillation unit 321 provides a time synchronization signal to the individual device 320 by performing an existing algorithm (steps S603, S641, and S691). That is, the time synchronization signal becomes a sampling clock signal for synchronizing with the master clock information.

On the other hand, in step S602, if it is determined that the input signal is cut off and not sustained, the self-oscillation unit 321 compares the master clock information and the self-oscillation clock signal (step S610).

Then, the self-oscillation unit 321 extracts a difference value between the master clock information and the self-oscillation clock signal according to the comparison result (step S620). When the difference value between the extracted reference signal and the self-oscillating clock signal before synchronization is greater than or less than the preset reference value, the average value and effective value of stable control values for a certain period immediately before the reference signal is lost Calculated to calculate the adjusted control value (steps S630, S640, S650, S651). In other words, if the difference value is smaller than the preset reference value 1, it is determined whether it is smaller than the preset reference value 2.

Calculation of the average value uses the average value of the reference clock coming into the individual device 320 with its own oscillator. It is calculated (calculated) continuously. That is, it is not the frequency of the self-oscillating unit 321. This calculated value is continuously safely held, and therefore, even during a period in which time synchronization is lost, the synchronized signal is continuously transmitted to the sampling unit (not shown) by using the self-oscillation unit 321 interlocked with the calculated average value. ) is forwarded to The average value and the effective value are values calculated at the same time, and the expression for the effective value can be omitted. That is, only the average value may be used. In addition, as the frequency and phase values are also linked values that are calculated simultaneously, it is possible to omit the expression of the phase value.

In step S640, if the difference value is greater than the preset reference value 2, the self-oscillation unit 321 already provides a time synchronization signal according to an existing algorithm to the individual device 320 (steps S603, S641, and S691). That is, the same time synchronization signal as the previous master clock information is provided to the individual device 320 . In other words, if the difference value is in the preset standard range (eg, 10 to 15), the control value is adjusted using the time synchronization signal according to the existing algorithm without the need to adjust the control value. do.

On the other hand, when the adjusted control value is calculated, the self-oscillation unit 321 converts the adjusted control value into a control voltage value and outputs it, and the target time synchronization information through voltage value control according to the control voltage value. is generated (steps S670, S680, S690, S692. S691).

7 is a conceptual diagram of an automated power system protection monitoring system through time synchronization according to an embodiment of the present invention. Referring to FIG. 7 , a first current measuring device 721 and a second current measuring device 722 detecting current flowing in power lines (LineA to LineC) disposed between the first transmission tower 711 and the second transmission tower 712 is connected to the first to nth clients 530-1 to 530-N. The first to nth clients 530-1 to 530-N apply a time synchronization signal linked to the master clock to the measurement data generated from the first current measuring device 721 and the second current measuring device 722 to obtain measurement time information. It is included and transmitted to the management server (not shown).

In other words, the individual devices (130 in FIG. 1) convert the signal source in the field into digital values, extract and output SV data, and the individual devices installed at different points correspond to the master clock (master clock) and visual motivation is essential.

Therefore, when the time synchronization does not satisfy the normal range, when the phases of voltage data and current data, which are measurement data measured on the same line, are processed in each individual device 130, due to sampling time mismatch during digital conversion of analog signals. An error occurs, which causes a malfunction of the substation automation equipment.

Therefore, in the embodiment of the present invention, after the master clock information is cut off to eliminate such time inconsistency, a time synchronization signal is generated in conjunction with the master clock information, thereby enabling continuous time synchronization.

In addition, the steps of a method or algorithm described in connection with the embodiments disclosed herein are implemented in the form of program instructions that can be executed through various computer means such as a microprocessor, processor, CPU (Central Processing Unit), etc. It can be recorded on any available medium. The computer readable medium may include program (instruction) codes, data files, data structures, etc. alone or in combination.

The program (command) code recorded on the medium may be specially designed and configured for the present invention, or may be known and usable to those skilled in computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks and magnetic tapes, optical media such as CD-ROMs, DVDs, and Blu-rays, and ROMs and RAMs ( A semiconductor storage element specially configured to store and execute program (instruction) codes such as RAM), flash memory, or the like may be included.

Here, examples of the program (command) code include high-level language codes that can be executed by a computer using an interpreter, as well as machine language codes such as those produced by a compiler. The hardware devices described above may be configured to act as one or more software modules to perform the operations of the present invention, and vice versa.

*300: Master clock linked time synchronization signal generation device
310: master clock generator 310: individual device
321: self-oscillation unit 322: master clock linked time synchronization generation algorithm
411: first receiver 412: second receiver
413 selector
420: difference comparator
430: PID (Proportional-Integral-Differential controller) controller
440 Synchronous information generator
441: numeric-voltage conversion unit
442: voltage controlled oscillation unit
510: Global Positioning System (GPS) satellites
520: time server
530-1 to 530-n: first to nth clients

Claims (1)

a master clock generator 310 generating master clock information; and
In a signal blocking state with the master clock generator 310, a self oscillation unit 321 generating time synchronization information in conjunction with the master clock information transmitted before the signal blocking state; includes,
The self-oscillation unit 321 recognizes the signal cut-off state when the master clock information is not continuously input for a certain time preset from the master clock generator 310,
The time synchronization information is calculated using an average value of the master clock information for a predetermined time immediately before the signal blocking state in the signal blocking state,
The time synchronization information is generated using a pattern generated through learning and analysis in advance within the self-oscillation unit 321 itself,
Synchronization information generator 440 for generating the time synchronization information in association with the master clock information; time synchronization signal generation device linked to the master clock, characterized in that it comprises

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