KR102472846B1 - Micro-electro mechanical system and manufacturing method thereof - Google Patents

Abstract

A micro electro mechanical system (MEMS) includes a circuit board including an electronic circuit; a supporting substrate having a recess; a bonding layer disposed between the circuit board and the supporting substrate; through holes passing through the circuit board to the opening; a first conductive layer disposed on the front surface of the circuit board; a second conductive layer disposed on an inner wall of the recess; and a third conductive layer disposed on an inner wall of each through hole.

Description

Microelectronic mechanical system and its manufacturing method {MICRO-ELECTRO MECHANICAL SYSTEM AND MANUFACTURING METHOD THEREOF}

related application

This application claims priority to U.S. Provisional Patent Application No. 62/982,712, filed on February 27, 2020, which is incorporated herein by reference in its entirety.

Recently, a micro-electro mechanical system (MEMS) device has been developed. MEMS devices include devices fabricated using semiconductor technology to form mechanical and electrical features. MEMS devices are implemented in pressure sensors, microphones, actuators, mirrors, heaters and/or printer nozzles. Existing devices and methods of forming MEMS devices have generally been suitable for their intended purpose, but have not been entirely satisfactory in all respects.

The present disclosure will be best understood by reading the following detailed description taken in conjunction with the accompanying drawings. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustrative purposes only. Indeed, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.
1A, 1B, 1C and 1D show schematic cross-sectional views of MEMS devices according to embodiments of the present disclosure.
2a, 2b, 2c, 2d, 2e and 2f show schematic cross-sectional views of various stages of a fabrication operation for a MEMS device in accordance with an embodiment of the present disclosure.
3A, 3B, 3C, 3D and 3E show schematic cross-sectional views of various stages of a fabrication operation for a MEMS device according to an embodiment of the present disclosure.
4A, 4B, 4C and 4D show schematic cross-sectional views of various stages of a fabrication operation for a MEMS device in accordance with an embodiment of the present disclosure.
5A, 5B and 5C show schematic cross-sectional views of various stages of a fabrication operation for a MEMS device in accordance with an embodiment of the present disclosure.
6A, 6B and 6C show schematic cross-sectional views of various stages of a fabrication operation for a MEMS device in accordance with an embodiment of the present disclosure.
7A shows a top view of a MEMS device, and FIG. 7B shows a cross-sectional view of a pad structure device according to an embodiment of the present disclosure.
8 illustrates the use of a MEM device according to an embodiment of the present disclosure.
9A, 9B, 9C, and 9D show schematic cross-sectional views of various stages of a fabrication operation for a MEMS device in accordance with an embodiment of the present disclosure.

It should be understood that the following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the dimensions of an element are not limited to the disclosed ranges or values, but may depend on process conditions and/or desired characteristics of the device. Further, in the following description, the formation of the first feature on or over the second feature may include an embodiment in which the first and second features are formed in direct contact, and an additional feature is interposed between the first and second features. Embodiments may also be included that may be interposed, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different sizes for simplicity and clarity.

Also, spatially relative terms such as "below", "below", "below", "above", "upper", etc. refer to the relationship between one element or feature and another element(s) as shown in the figures. or may be used herein for ease of description to describe a relationship between feature(s). Spatially relative terms are intended to encompass different orientations of a device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted correspondingly. Also, the term “made of” can mean “comprising” or “consisting of”. In the present disclosure, at least one of A, B, and C is "A", "B", "C", "A and B", "A and C", "B and C" or "A, B and C" ", and does not mean one from A, one from B, and one from C.

The MEMS device according to the present disclosure may be any one of an electron beam deflector, an electron beam deflector, an accelerometer, a gyroscope, a pressure sensor, a microphone, an RF resonator, an RF switch, or an ultrasonic transducer.

1A and 1B show schematic cross-sectional views of MEMS devices 10A and 10B according to embodiments of the present disclosure.

In some embodiments, MEMS devices 10A and 10B include electronic circuitry 25 (e.g., semiconductor field effect transistors, such as complementary metal-oxide-semiconductor (CMOS) devices). transistors) are formed, and a support substrate 30 having an opening (cavity or recess) 35 for receiving sound, pressure and/or light. In some embodiments, bonding layer 40 is formed between circuit board 20 and support substrate 30 . In some embodiments, bonding layer 40 is a silicon oxide layer. In some embodiments, circuit board 20 includes electronic circuitry 25 such as signal processing circuitry and/or amplifier circuitry formed by electronic circuitry. In some embodiments, recess 35 has a rectangular (eg, square) shape in plan view. In some embodiments, at least one of circuit board 20 and support substrate 30 is made of crystalline silicon. In some embodiments, as shown in FIG. 1A , the bonding layer remains at the bottom of recess 35 , in other embodiments, as shown in FIG. 1B , the bonding layer remains at the bottom of recess 35 . does not exist in

Further, in some embodiments, as shown in FIGS. 1A and 1B , a first conductive layer 50 is formed on the front surface of the circuit board 20 and a second conductive layer is formed on the rear surface of the support substrate 30 . (55) is formed. In some embodiments, as shown in FIG. 1A , bonding layer 40 contacts second conductive layer 55 and does not contact circuit board 20 . In another embodiment, the second conductive layer 55 contacts the circuit board 20 as shown in FIG. 1B. In some embodiments, the first and second conductive layers include one or more layers of Au, Ti, Cu, Ag, and Ni.

In some embodiments, the distance L1 of the size of the recess 35 at the bottom of the circuit board 20 ranges from about 10 mm to about 50 mm, and in other embodiments from about 15 mm to about 20 mm. it's mine In some embodiments, the distance L2 of the size of the cavity 35 at the bottom of the supporting substrate 30 is greater than L1 and is in the range of about 11 mm to about 52 mm, and in other embodiments in the range of about 16 mm to about 22 mm. it's mine In some embodiments, the distance L3 (the width of the frame portion) from the edge of the MEMS device and the edge of the recess 35 at the bottom of the circuit board 20 is in the range of about 2 μm to about 10 μm; In an embodiment, from about 3 μm to about 5 μm. In some embodiments, the thickness T1 of bonding layer 40 is in the range of about 200 nm to about 5 μm, and in other embodiments, in the range of about 500 nm to about 2 μm. In some embodiments, the total thickness T2 of the MEM device is in the range of about 300 μm to about 2 mm, and in other embodiments is in the range of about 600 μm to about 800 μm.

1C and 1D show schematic cross-sectional views of MEMS devices 10C and 10D according to embodiments of the present disclosure. In some embodiments, MEMS devices 10C and 10D are beam deflectors in which one or more electrons or extreme ultraviolet (EUV) rays are deflected by operation of electronic circuitry embedded in the MEMS device.

Similar to MEMS devices 10A and 10B, MEMS devices 10C and 10D have a circuit board 20 on which electronic circuitry 25 is formed, and an opening (common or open) for receiving sound, pressure and/or light. and a support substrate 30 having a recess) 35. In some embodiments, bonding layer 40 is formed between circuit board 20 and supporting substrate 30 . In some embodiments, bonding layer 40 is a silicon oxide layer. In some embodiments, one or more through holes 60 are disposed through the circuit board 20 and the bonding layer 40 so that the beam passes through the through holes 60 . In some embodiments, through holes 60 are arranged in an nxm matrix in plan view, where n and m are integers greater than or equal to 2 and less than or equal to 128, for example.

In some embodiments, as shown in FIGS. 1C and 1D , a first conductive layer 50 is formed on the front side of the circuit board 20 and a second conductive layer 55 is formed on the back side of the supporting substrate 35 . ) is formed. In some embodiments, as shown in FIG. 1C , bonding layer 40 contacts second conductive layer 55 and does not contact circuit board 20 . In another embodiment, the second conductive layer 55 contacts the circuit board 20 as shown in FIG. 1D. In addition, a third conductive layer 57 is disposed on an inner wall of each through hole 60 connecting the first conductive layer 50 and the second conductive layer 55 .

In some embodiments, circuit board 20 includes electronic circuitry 25 such as signal processing circuitry and/or amplifier circuitry formed by electronic circuitry. In some embodiments, electronic circuitry is coupled to the first, second, and/or third conductive layer to control the potential of the third conductive layer in each through hole 60 to pass through the through hole 60. deflect the beam.

In some embodiments, recess 35 has a rectangular (eg, square) shape in plan view. In some embodiments, at least one of circuit board 20 and support substrate 30 is made of crystalline silicon. In some embodiments, as shown in FIG. 1C , the bonding layer remains at the bottom of recess 35 , in other embodiments, as shown in FIG. 1D , the bonding layer remains at the bottom of recess 35 . does not exist in

The dimensions of L1, L2 and L3 of MEMS devices 10C and 10D are the same as or similar to those of MEMS devices 10A and 10B.

2a, 2b, 2c, 2d, 2e and 2f show schematic cross-sectional views of various stages of a fabrication operation for a MEMS device in accordance with an embodiment of the present disclosure. It is understood that additional operations may be provided before, during, and after the process shown in FIGS. 2A-2F, and that some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of actions/processes may be interchanged. Materials, configurations, dimensions, and processes described in relation to FIGS. 1A to 1D may be applied to the following embodiments, and detailed descriptions thereof may be omitted.

As shown in FIG. 2A , a complementary meta-oxide-semiconductor (CMOS) circuit 25 is formed on the front area of the circuit board 20 . One or more passivation films 28 are formed over the front surface of the circuit board. In some embodiments, one or more passivation films 28 include silicon oxide, silicon nitride, or organic films. Then, as shown in Fig. 2B, the back side of the circuit board 20 is thinned by a grinding process or a polishing process. In some embodiments, the remaining thickness of the thinned circuit board 20 is in a range of about 100 μm to about 500 μm.

Next, as shown in FIGS. 2C and 2D , the thinned circuit board 20 is bonded to the support substrate 30 via the bonding layer 40 . In some embodiments, as shown in FIG. 2C , bonding layer 40 is formed on the surface of support substrate 30 by, for example, a thermal oxidation process or a chemical vapor deposition (CVD) process. It is silicon oxide. In another embodiment, bonding layer 40 is formed on the back side of circuit board 20 by, for example, a CVD process.

The back side of the supporting substrate 30 is then recessed using one or more lithography and etching operations. In some embodiments, the etching operation includes a plasma dry etch or wet etch. In some embodiments, wet etching uses a tetramethylammonium hydroxide (TMAH) or KOH solution.

In some embodiments, bonding layer 40 functions as an etch stop layer for forming recesses 35 as shown in FIG. 2E . In some embodiments, one or more conductive layers are formed on the back side of the supporting substrate 30 and on the bonding layer 40 .

In another embodiment, after the recess etch stops at bonding layer 40, bonding layer 40 is further etched by one or more dry etch operations or wet etch operations. In some embodiments, one or more conductive layers are formed on the back side of the supporting substrate 30 . In another embodiment, as shown in FIG. 2F, after bonding layer 40 is removed, a portion of the back side of circuit board 20 is etched and then one or more conductive layers are formed.

3A-7B show schematic cross-sectional views of various stages of a fabrication operation for a MEMS device in accordance with an embodiment of the present disclosure. Additional operations may be provided before, during, and after the process shown in FIGS. 3A-7B , and some of the operations described below are replaced or eliminated for additional embodiments of the method. The order of actions/processes can be interchanged. Materials, configurations, dimensions, and processes described in relation to FIGS. 1A to 1D and 2A to 2F may be applied to the following embodiments, and detailed descriptions thereof may be omitted.

As shown in FIG. 3A, after an electronic circuit is formed on the circuit board 20, one or more planar electrodes 100 are formed and one or more passivation layers 110 are formed. The electrode 100 is electrically connected to an electronic circuit formed on the circuit board 20 . In some embodiments, circuit board 20 includes a crystalline silicon substrate. In some embodiments, one or more openings are formed over electrode 100 in one or more passivation layers. In some embodiments, electrode 100 is made of one or more layers of Cu, Al, Au, Ni, Ag or other suitable conductive material. The passivation layer 110 includes silicon nitride, SiON, silicon oxide, aluminum nitride, or an organic material.

Subsequently, one or more holes 120 for through-silicon-vias (TSVs) are formed in regions other than the electrode 100 . TSV hole 120 is formed by one or more lithography and etching operations. In some embodiments, the TSV holes 120 are arranged in an nxm matrix in plan view (see FIG. 7A), where n and m are integers greater than or equal to 2 and less than or equal to 128, for example. The depth of the TSV is in a range of about 20 μm to about 100 μm from the top of the passivation layer 110 in some embodiments. In some embodiments, the depth is determined such that the bottom of the TSV hole 120 is exposed after a thinning process of the back side of the circuit board is subsequently performed. In some embodiments, the shape of the TSV hole 120 in plan view is round or rectangular (eg, square). In some embodiments, TSV hole 120 is tapered with a larger opening than the bottom. In some embodiments, the diameter (or length of the side) of the TSV hole 120 in the aperture is in a range of about 100 nm to about 12,000 nm.

A first conductive layer 130 is then formed over the electrode 100 , the passivation layer 110 and inside the TSV hole 120 . Then, as shown in FIG. 3B , a filling layer 140 is formed to fill the TSV hole 120 . The first conductive layer 130 has the same or similar function as the first conductive layer 50 shown in FIGS. 1A to 1D. In some embodiments, first conductive layer 130 includes one or more layers of Au, Ti, Cu, Ag, and Ni. In a specific embodiment, a gold layer formed over the Ti layer is used as the first conductive layer 130 . In some embodiments, the thickness of the Ti layer ranges from about 50 nm to about 500 μm, and in other embodiments from about 80 nm to about 300 nm. In some embodiments, the thickness of gold (Au) ranges from about 10 nm to about 10,000 nm, and in other embodiments from about 150 nm to about 250 nm. In some embodiments, fill layer 140 includes silicon oxide or any other suitable insulating material. In some embodiments, a blanket layer of fill material is formed over the first conductive layer 130, followed by a planarization operation, such as a chemical mechanical polishing process or an etch-back process, to charge, as shown in FIG. 3B. The material is left only in the TSV hole 120. In another embodiment, the fill material also remains on the recessed portion above the electrode 100 .

Next, as shown in FIG. 3C , conductive layer 130 is patterned to form one or more openings over passivation layer 110 near TSV hole 120 to partially expose the passivation layer. An insulating layer is then formed and patterned to form island shaped insulating patterns 150 covering the openings. In some embodiments, insulating pattern 150 includes silicon nitride.

In addition, as shown in FIG. 3D, after the first carrier bonding layer 160 is formed on the front surface of the circuit board 20 on which the conductive layer 130 and the pattern 150 are formed, the first carrier substrate 165 is attached The first carrier substrate 165 is a glass substrate, ceramic substrate, semiconductor substrate, or resin substrate in some embodiments. In some embodiments, first carrier bonding layer 160 includes an organic material, silicon oxide, or any other suitable material.

Then, the back side of the circuit board 20 is thinned by a grinding or polishing (eg, CMP) operation. In some embodiments, after thinning, circuit board 20 has a residual thickness in the range of about 20 μm to about 300 μm, and the residual thickness is in the range of about 40 μm to about 180 μm in other embodiments. As shown in FIG. 3D , the lower end of the filling material layer 140 filled in the TSV hole 120 is exposed. In another embodiment, after the thinning operation, the first carrier substrate 165 is attached to the front side of the circuit board 20 .

Also, as shown in FIG. 3E , a bonding layer 170 is formed on the thinned back surface of the circuit board 20 . The bonding layer 170 has the same or similar function as the bonding layer 40 shown in FIGS. 1A to 2F. In some embodiments, bonding layer 170 includes silicon oxide formed by, for example, a CVD process.

Then, as shown in FIG. 4A, the support substrate 30 is prepared and bonded to the circuit board 20 via the bonding layer 170 (oxide fusion bonding). In some embodiments, support substrate 30 is made of crystalline silicon. After oxide fusion bonding, the first carrier substrate 165 and the first carrier bonding layer 160 are removed, as shown in FIG. 4B. As shown in FIG. 4A , the bonding layer 170 is connected to the filling material layer 140 in the TSV hole 120 . In some embodiments, bonding layer 170 and fill material layer 140 are made of the same material.

In another embodiment, bonding layer 170 is formed on support substrate 30 or on both support substrate 30 and circuit board 20 . In some embodiments, the thickness of the support substrate 30 without bonding layer is in the range of about 200 μm to about 1.8 mm, and in other embodiments is in the range of about 500 μm to about 750 μm.

Next, as shown in FIG. 4C , after the first hard mask layer 180 is formed, a second hard mask layer 190 is formed on the entire surface of the circuit board 20 . In some embodiments, the first hard mask layer 180 includes silicon oxide and the second hard mask layer 190 includes polysilicon or amorphous silicon. In some embodiments, the silicon oxide hard mask layer 180 is formed by a CVD process, followed by a planarization process such as a CMP operation. Similarly, in some embodiments, the polysilicon hard mask layer 190 is formed by chemical vapor deposition (CVD) followed by an optional CMP operation. In some embodiments, the thickness of the polysilicon hard mask layer 190 is in a range of about 30 μm to about 70 μm.

Then, by using one or more lithography and etching operations, the second hard mask layer 190 and the first hard mask layer 180 form one or more openings 200 over the electrode 100 as shown in FIG. 4D. patterned to form In some embodiments, the size of the opening 200 is larger than the size of the opening formed in the passivation layer 110 over the electrode 100 . Also, in some embodiments, the insulating pattern 150 is partially exposed at the opening 200 as shown in FIG. 4D.

Next, as shown in FIG. 5A , one or more conductive layers 210 (pillar electrodes) are formed in the openings 200 . In some embodiments, the conductive layer includes gold or a gold alloy (eg, AuCu and AuNi) formed by a plating operation (electroplating or electroless plating). In some embodiments, the thickness of the plated conductive layer 210 is in a range of about 20 μm to about 50 μm. In some embodiments, the thickness (height) of the plated conductive layer 210 is less than the top of the second hard mask layer 190, as shown in FIG. 5A.

Also, as shown in FIG. 5B , a portion of the plating layer 210 on the one or more electrodes 100 is covered by the mask pattern 220 . In some embodiments, mask pattern 220 includes a photoresist pattern. After that, an additional conductive layer 215 (pillar electrode) is formed over the conductive plating layer 210 . In some embodiments, additional conductive layer 215 is formed by a plating operation (electroplating or electroless plating). In some embodiments, additional conductive layer 215 is made of the same material as plated conductive layer 210 and includes gold or a gold alloy (eg, AuCu, AuNi). In another embodiment, additional conductive layer 215 is made of a different material than plated conductive layer 210 . After that, the photoresist pattern 220 is removed as shown in FIG. 5C.

In some embodiments, the thickness of the additional conductive layer 215 is in a range of about 10 μm to about 35 μm. In some embodiments, the total thickness (height) of the plated conductive layer 210 and the additional conductive layer 220 is less than the top of the second hard mask layer 190, as shown in FIG. 5C. In some embodiments, the two different thicknesses (heights) of the plated conductive layers 210/220 control different electrical circuitry. For example, higher ones are used to shelter electrons and lower ones are used to control electric fields.

Subsequently, as shown in FIG. 6A, a second carrier bonding layer 305 is formed on the front surface of the circuit board 20, and the second carrier bonding layer 305 is formed on the front surface of the circuit board 20 through the second carrier bonding layer 305. A carrier substrate 300 is attached. The second carrier substrate 300 is a glass substrate, ceramic substrate, semiconductor substrate, or resin substrate in some embodiments. In some embodiments, the second carrier bonding layer 305 includes an organic material, silicon oxide, or any other suitable material.

The entire substrate is then vertically flipped and then the back side of the supporting substrate 30 is patterned to form recesses 35 . In some embodiments, recess 35 is formed by one or more lithography and etching operations using mask pattern 310 . In some embodiments, mask pattern 35 is made of photoresist.

In some embodiments, the etching operation includes a plasma dry etch or wet etch. In some embodiments, bonding layer 170 functions as an etch stop layer for forming recess 35 . When a plasma dry etching process is used to form the recess 35, the plasma etching can be substantially stopped at the bonding layer 170 to prevent plasma damage on electronic circuitry formed on the circuit board 20.

In some embodiments, after the recess etch stops at bonding layer 170, bonding layer 170 is further etched by one or more dry etching or wet etching operations. In some embodiments, the etching of the bonding layer is highly selective to the circuit board 20 (eg, Si). For example, the etching rate of the bonding layer is 10 times or more than the etching rate of the circuit board 20 . In some embodiments, when bonding layer 170 is made of silicon oxide, a wet etching process using HF or buffered HF is performed to inhibit damage to electronic circuits formed on circuit board 20 . When removing the bonding layer 170, the filling material layer 140 in the TSV hole 120 is also removed if the filling material layer 140 is made of the same material as the bonding layer 170 (e.g., silicon oxide). do. If the filling material layer 140 is made of a material different from that of the bonding layer 170 (eg, silicon nitride), an additional etching operation, such as a wet etching operation, is performed to remove the filling material layer 140.

After the filling material layer 140 is removed from the TSV hole 120, a second conductive layer 320 is formed inside the recess 35 as shown in FIG. 6B.

In some embodiments, as shown in FIG. 6B , the second conductive layer 320 is formed to contact the first conductive layer 130 formed on the inner wall of each TSV hole 120 . In some embodiments, the second conductive layer 320 is also formed on the inner wall of the TSV hole 120 where the first conductive layer 130 has already been formed. In some embodiments, second conductive layer 320 is made of the same or different material as first conductive layer 130 and includes one or more layers of Au, Ti, Cu, Ag, and Ni. In a specific embodiment, a gold layer formed over the Ti layer is used as the second conductive layer 320 . In some embodiments, the thickness of the Ti layer ranges from about 50 nm to about 200 mm, and in other embodiments from about 80 nm to about 120 nm. In some embodiments, the thickness of the gold (Au) layer ranges from about 10 nm to about 400 nm, and in other embodiments from about 150 nm to about 250 nm.

In some embodiments, a plurality of MEMS devices are formed on a Si wafer and the wafer is cut into individual MEMS devices (chips) by sawing (dicing operation) at a scribe line 390 . In some embodiments, the dicing operation does not completely cut the supporting second carrier bonding layer 305 as shown in FIG. 6B. By removing the second carrier bonding layer 305 and thus removing the second carrier substrate 300, the individual MEMS devices are released.

In some embodiments, the dicing operation is performed after second conductive layer 320 is formed. In this case, no conductive layer is formed on the side surface (diced surface) of the MEMS device. In another embodiment, the dicing operation is performed before the second conductive layer 320 is formed. In this case, the second conductive layer 320 is also formed on the side surface of the MEMS device.

In some embodiments, after the second carrier substrate 300 and the second carrier bonding layer 305 are removed, individual MEMS devices are attached onto the frame 400 as shown in FIG. 6C. As shown in FIG. 6C , the TSV hole 120 is exposed by removing the second carrier substrate 300 and the second carrier bonding layer 305 so that electron beams or light rays can pass therethrough.

Figure 7a shows a top view of the MEMS device, and Figure 7b shows a cross-sectional view of the bonding pad structure in the peripheral region (PR). As shown in the plan view of FIG. 7A, the MEMS device has a center region (CR) and a peripheral region surrounding the center region. The TSV hole 120 and the conductive layers 210/220 are disposed in the central region CR. In the peripheral region PR, one or more under bump pad electrodes 250 are formed to connect an electronic circuit formed on the circuit board 20 to one or more circuits outside the MEMS device. In some embodiments, peripheral region PR does not overlap recess 35 in plan view. In another embodiment, the peripheral region PR partially overlaps the recess 35 in plan view.

The under bump pad electrode 250 is formed on the entire surface of the circuit board 20 . In some embodiments, the under bump pad electrodes 250 are arranged in a matrix in the peripheral region PR. In some embodiments, ball bumps 260 are disposed on each of the under bump pad electrodes 250 . In some embodiments, the under bump pad electrode 250 is formed prior to the recess etch, as shown in FIG. 6A. In some embodiments, the under bump pad electrode 250 is formed after the supporting substrate 30 is attached to the circuit board 20 via oxide fusion bonding, as shown in FIGS. 4A and 4B .

In some embodiments, the under bump pad electrode 250 is formed on a metal pad 225 buried in the interlayer dielectric layer 230 and formed as an uppermost metal layer (eg, 8th to 12th metal levels) of an electronic circuit. is formed in In some embodiments, metal pad 225 includes one or more layers of conductive material. In some embodiments, metal pad 225 includes Cu or a Cu alloy.

Also, as shown in FIG. 7B , the under bump pad electrode 250 includes multiple layers of conductive material. In some embodiments, the under bump pad electrode 250 includes a first metallic layer 252 , a second metallic layer 254 , a third metallic layer 256 , and a fourth metallic layer 258 . In some embodiments, the first metallic layer is a TiW layer, the second metallic layer is a Cu layer, the third metallic layer is a Ni layer, and the fourth metallic layer is a Sn layer.

The thickness of TiW layer 252 is in the range of about 50 nm to about 1000 μm in some embodiments, and in the range of about 100 nm to about 500 nm in other embodiments. In some embodiments, the thickness of Cu layer 254 is in the range of about 10 nm to about 2000 μm, and in other embodiments, in the range of about 500 nm to about 1000 nm. In some embodiments, the thickness of the Ni layer 256 is in the range of about 1000 nm to about 5000 μm, and in other embodiments in the range of about 2500 nm to about 3500 nm. In some embodiments, the thickness of Sn layer 258 is in the range of about 500 nm to about 4000 nm, and in other embodiments in the range of about 1500 nm to about 2500 nm. The metallic layer is formed by one or more of CVD, physical vapor deposition (PVD) including sputtering, plating or any other suitable film formation method, and lithography and etching operations.

In some embodiments, the surface of the electronic circuitry is covered with one or more passivation layers. In some embodiments, the passivation layer includes a first passivation layer 242 , a second passivation layer 244 and a third passivation layer 246 . As shown in FIG. 7B , the under bump pad electrode 250 is formed in the opening formed in the passivation layer. In some embodiments, first passivation layer 242 is a SiC layer, second passivation layer 244 is a silicon oxide layer, and third passivation layer 246 is a silicon nitride layer.

8 illustrates the use of a MEM device according to an embodiment of the present disclosure. In some embodiments, MEMS device 10 is used for electronic or electromagnetic wave lithography. In some embodiments, electron beam (or EUV light) 500 is input into MEMS device 10 from the front side of circuit board 20 . The electronic circuit formed on the circuit board 20 independently controls the voltage applied to the conductive layer (eg, the first conductive layer 130 ) formed on the inner wall of each TSV hole 120 . By adjusting the voltage applied to the conductive layer of the TSV hole 120, a portion of the electron beam 500 passes through one or more TSV holes and a portion of the electron beam 500 does not pass through the TSV hole. A portion of the electron beam passing through the TSV hole is directed to a wafer or substrate on which a layer of photoresist is formed. In some embodiments, the wafer is a semiconductor wafer. In some embodiments, the substrate is for a photo mask, such as a transparent substrate or a reflective substrate. By controlling the electronic circuit, the position of the TSV hole 120 passing the electron beam is controlled so that a desired shape can be drawn on the photoresist pattern.

In another embodiment, a silicon-on-insulator (SOI) wafer is used. In this case, the fusion bonding process is omitted, and the oxide layer of the SOI wafer functions as an etch stop layer in the recess etch. 9A, 9B, 9C, and 9D show schematic cross-sectional views of various stages of a fabrication operation for a MEMS device in accordance with an embodiment of the present disclosure. It is understood that additional operations may be provided before, during, and after the processes depicted in FIGS. 9A-9D , and that some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of actions/processes may be interchanged. Materials, configurations, dimensions, and processes described in relation to FIGS. 1A to 7B may be applied to the following embodiments, and detailed descriptions thereof may be omitted.

The SOI substrate includes a device layer (semiconductor layer) 20', an oxide layer 40' and a bulk layer (semiconductor substrate) 30' as shown in Fig. 9A.

As shown in Fig. 9A, a CMOS circuit 25 is formed in the front area of the device layer 20'. One or more passivation films 28 are formed over the entire surface of the device layer 20'. In some embodiments, one or more passivation films 28 include silicon oxide, silicon nitride, or organic films. In some embodiments, TSV holes 120 filled with fill material 140 are formed through device layer 20'. In addition, one or more first conductive layers 50 are formed on the front side of the device layer and in the TSV holes, as shown in FIG. 9A.

Then, as shown in FIG. 9B, the back side of bulk layer 30' is recessed using one or more lithography and etching operations. In some embodiments, the etching operation includes a plasma dry etch or wet etch. In some embodiments, wet etching uses a tetramethylammonium hydroxide (TMAH) or KOH solution.

In some embodiments, oxide layer 40' functions as an etch stop layer for forming recess 35 as shown in FIG. 9B.

After the recess etch stops on the oxide layer 40', the oxide layer 40' is further etched by one or more dry etch or wet etch operations. While etching the oxide layer 40', the fill material layer 140 is also removed from the TSV hole 120, as shown in FIG. 9C.

In some embodiments, one or more second conductive layers 55 are formed on the back side of the bulk layer 30' as shown in FIG. 9D.

In embodiments of the present disclosure, a MEMS device is formed using an SOI substrate or bonding a circuit board and a support substrate through a silicon oxide bonding layer by oxide fusion bonding. The oxide bonding layer (oxide layer) also functions as an etching stop layer for plasma dry etching when the support substrate is etched to form a recess, thereby protecting electronic circuitry formed on the circuit board from damage due to plasma etching. Since the silicon oxide bonding layer can be removed by a wet etching operation, the process of removing the silicon oxide bonding layer does not cause damage to the electronic circuitry formed on the circuit board.

The various embodiments and examples described in this disclosure provide several advantages over existing technologies, as noted above. It will be understood that not all advantages are discussed herein by default and that no particular advantage is required for every embodiment or example, and that other embodiments or examples may provide different advantages.

According to one aspect of the present disclosure, a microelectromechanical system (MEMS) includes a circuit board including electronic circuitry; a supporting substrate having a recess; a bonding layer disposed between the circuit board and the supporting substrate; a through hole passing through the circuit board to the opening; a first conductive layer disposed on the front surface of the circuit board; a second conductive layer disposed on an inner wall of the recess; and a third conductive layer disposed on an inner wall of each through hole. In one or more of the above and below described embodiments, the bonding layer includes silicon oxide. In one or more of the above and below described embodiments, no bonding layer is disposed in the recess, and the bottom of the circuit board is in contact with the second conductive layer. In one or more of the above and below described embodiments, the circuit board includes electrodes having different configurations. In one or more of the above and below described embodiments, the electrode includes a first electrode and a second electrode, a first pillar electrode is disposed on each of the first electrodes, and a second pillar is disposed on each of the second electrodes. The height of the first pillar electrode is different from that of the second pillar electrode. In one or more of the above-mentioned and below-mentioned embodiments, the height difference between the first pillar electrode and the second pillar electrode is 10 μm to 30 μm. is within range In one or more of the foregoing and later-described embodiments, in plan view, the circuit board includes a central region in which a through hole is provided and a peripheral region surrounding the central region, and a plurality of bump electrodes having a configuration different from the electrodes are provided. placed in the surrounding area. and in one or more of the following embodiments, the peripheral region does not overlap the recess in plan view.

According to another aspect of the present disclosure, in a method of manufacturing a microelectromechanical system (MEMS), an electronic circuit is formed over the front surface of a first substrate, one or more holes penetrating into the first substrate are formed, and the holes are filled. filled with a material, the back surface of the first substrate is thinned to expose a portion of the filled hole, and the second substrate is bonded to the back surface of the first substrate while a bonding layer is interposed between the second substrate and the back surface of the first substrate; A set is formed on the second substrate to expose a lower end of the first substrate. In one or more of the above and below described embodiments, the bonding layer is silicon oxide. In one or more of the above and below described embodiments, a bonding layer is formed on the back side of the first substrate. In one or more of the above and below described embodiments, a bonding layer is formed on the second substrate. In one or more of the above and below described embodiments, when the recess is formed, a portion of the second substrate is etched by plasma dry etching to expose the bonding layer but the first substrate is not etched, and the first substrate The bonding layer is etched by an etch that selectively removes the bonding layer from the substrate. In one or more of the above and below described embodiments, when etching the bonding layer, the filling material is also removed from the hole to form a through hole. In one or more of the above and below described embodiments, a first conductive layer is formed over the front surface of the first substrate and on an inner wall of each hole, and a second conductive layer is formed over an inner wall of the recess. In one or more of the embodiments described above and below, at least one of the first conductive layer and the second conductive layer is a stacked layer of an Au layer on a Ti layer. In one or more of the embodiments described above and below, the holes are arranged in a matrix in plan view.

According to another aspect of the present disclosure, in a method of manufacturing a microelectromechanical system (MEMS), an electronic circuit is formed over the front surface of a first substrate, an electrode is formed over the first substrate, and one penetrating into the first substrate The above hole is formed in a region other than the electrode being formed, the hole is filled with a filling material, the rear surface of the first substrate is thinned to expose a part of the filled hole, and a bonding layer made of silicon oxide is bonded to the second substrate. A second substrate is bonded to the rear surface of the first substrate while being interposed between the rear surfaces of the first substrate, pillar electrodes are formed on the electrodes, and recesses are formed in the second substrate to expose a lower end of the first substrate. In one or more of the above and below described embodiments, when the recess is formed, a portion of the second substrate is etched by plasma dry etching to expose the bonding layer, but the first substrate is not etched, and the bonding layer is etched by wet etching. In one or more of the above and below described embodiments, the pillars are formed by one or more plating operations.

The foregoing outlines features of several embodiments or examples so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples presented herein. Should be. In addition, those skilled in the art should appreciate that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present disclosure.

Examples

Example 1. In a micro electro mechanical system (MEMS),

a circuit board including an electronic circuit;

a supporting substrate having a recess;

a bonding layer disposed between the circuit board and the support substrate;

through holes passing through the circuit board to an opening;

a first conductive layer disposed on the front surface of the circuit board;

a second conductive layer disposed on an inner wall of the recess; and

A third conductive layer disposed on the inner wall of each of the through holes

Including, a microelectromechanical system (MEMS).

Example 2. In Example 1,

wherein the bonding layer comprises silicon oxide.

Example 3. In Example 2,

wherein a bonding layer is not disposed in the recess, and a lower end of the circuit board contacts the second conductive layer.

Example 4. In Example 2,

The microelectromechanical system (MEMS), wherein the circuit board includes electrodes having different configurations.

Example 5. In Example 4,

The electrodes include first electrodes and second electrodes, a first pillar electrode is disposed on each of the first electrodes, and a second pillar electrode is disposed on each of the second electrodes, ,

The height of the first pillar electrode is different from the height of the second pillar electrode, the microelectromechanical system (MEMS).

Example 6. In Example 5,

A height difference between the first pillar electrode and the second pillar electrode is in the range of 10 μm to 30 μm.

Example 7. In Example 4,

In plan view, the circuit board includes a central region in which the through hole is provided and a peripheral region surrounding the central region,

wherein a plurality of bump electrodes having a configuration different from those of the electrodes are disposed in the peripheral area.

Example 8. In Example 7,

wherein the peripheral region does not overlap the recess in plan view.

Example 9. A method for manufacturing a microelectromechanical system (MEMS),

forming electronic circuitry over the front surface of the first substrate;

forming one or more holes penetrating into the first substrate;

filling the hole with a filling material;

thinning the back side of the first substrate to expose some of the filled holes;

bonding the second substrate to the rear surface of the first substrate by interposing a bonding layer between the rear surface of the first substrate and the second substrate; and

forming a recess in the second substrate to expose a lower end of the first substrate;

A method of manufacturing a microelectromechanical system (MEMS) comprising a.

Example 10. In Example 9,

wherein the bonding layer is silicon oxide.

Example 11. According to Example 10,

wherein the bonding layer is formed on the back side of the first substrate.

Example 12. According to Example 10,

wherein the bonding layer is formed on the second substrate.

Example 13. According to Example 10,

The recess is:

etching a portion of the second substrate by plasma dry etching to expose the bonding layer without etching the first substrate; and

etching the bonding layer by etching to selectively remove the bonding layer from the first substrate.

A method of manufacturing a microelectromechanical system (MEMS), wherein the method is formed.

Example 14. According to Example 13,

wherein in etching the bonding layer, the fill material is also removed from the hole to form a through hole.

Example 15. According to Example 10,

forming a first conductive layer on the front surface of the first substrate and on inner walls of each of the holes; and

forming a second conductive layer on the inner wall of the recess;

Further comprising, a method of manufacturing a microelectromechanical system (MEMS).

Example 16. According to Example 15,

wherein at least one of the first conductive layer and the second conductive layer is a stacked layer of an Au layer on a Ti layer.

Example 17. According to Example 10,

wherein the holes are arranged in a matrix in plan view.

Example 18. A method of manufacturing a microelectromechanical system (MEMS) comprising:

forming electronic circuitry on the front surface of the first substrate;

forming electrodes on the first substrate;

forming one or more holes penetrating into the first substrate in a region other than the electrode being formed;

filling the hole with a filling material;

thinning the back side of the first substrate to expose some of the filled holes;

bonding the second substrate to the rear surface of the first substrate by interposing a bonding layer made of silicon oxide between the rear surface of the first substrate and the second substrate;

forming pillar electrodes on the electrodes, respectively; and

forming a recess in the second substrate to expose a lower end of the first substrate;

A method of manufacturing a microelectromechanical system (MEMS) comprising a.

Example 19. According to Example 18,

The recess is:

etching a portion of the second substrate by plasma dry etching to expose the bonding layer without etching the first substrate; and

By etching the bonding layer by wet etching

A method of manufacturing a microelectromechanical system (MEMS), wherein the method is formed.

Example 20. According to Example 18,

wherein the pillars are formed by one or more plating operations.

Claims (10)

In a micro electro mechanical system (MEMS),
a circuit board including an electronic circuit;
a supporting substrate having a recess;
a bonding layer disposed between the circuit board and the support substrate to bond the circuit board and the support substrate, the bonding layer being silicon oxide;
through holes passing through the circuit board to an opening;
a first conductive layer disposed on the front surface of the circuit board;
a second conductive layer disposed on an inner wall of the recess; and
A third conductive layer disposed on the inner wall of each of the through holes
wherein the circuit board includes a first pillar electrode and a second pillar electrode, wherein a height of the first pillar electrode is different from a height of the second pillar electrode. ). delete According to claim 1,
wherein a bonding layer is not disposed in the recess, and a lower end of the circuit board contacts the second conductive layer. According to claim 1,
The microelectromechanical system (MEMS), wherein the circuit board further includes planar electrodes having different configurations. According to claim 4,
The planar electrodes include first electrodes and second electrodes, the first pillar electrode is disposed on each of the first electrodes, and the second pillar electrode is disposed on each of the second electrodes. phosphorus, microelectromechanical systems (MEMS). According to claim 1,
A height difference between the first pillar electrode and the second pillar electrode is in the range of 10 μm to 30 μm. According to claim 4,
In plan view, the circuit board includes a central region in which the through hole is provided and a peripheral region surrounding the central region,
A microelectromechanical system (MEMS), wherein a plurality of bump electrodes having a configuration different from that of the planar electrodes are disposed in the peripheral area. According to claim 7,
wherein the peripheral region does not overlap the recess in plan view. A method of manufacturing a microelectromechanical system (MEMS), comprising:
forming electronic circuitry over the front surface of the first substrate;
forming one or more holes penetrating into the first substrate;
filling the hole with a filling material;
thinning the back side of the first substrate to expose some of the filled holes;
bonding the second substrate to the rear surface of the first substrate by interposing a bonding layer between the rear surface of the first substrate and the second substrate; and
forming a recess in the second substrate to expose a lower end of the first substrate;
A method of manufacturing a microelectromechanical system (MEMS) comprising a. A method of manufacturing a microelectromechanical system (MEMS), comprising:
forming electronic circuitry on the front surface of the first substrate;
forming electrodes on the first substrate;
forming one or more holes penetrating into the first substrate in a region other than the electrode being formed;
filling the hole with a filling material;
thinning the back side of the first substrate to expose some of the filled holes;
bonding the second substrate to the rear surface of the first substrate by interposing a bonding layer made of silicon oxide between the rear surface of the first substrate and the second substrate;
forming pillar electrodes on the electrodes, respectively; and
forming a recess in the second substrate to expose a lower end of the first substrate;
A method of manufacturing a microelectromechanical system (MEMS) comprising a.

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