KR102461747B1 - Semiconductor memory device and operating method thereof - Google Patents

Abstract

The present technology relates to an electronic device, and to a semiconductor memory device having improved reliability and an operating method thereof. A semiconductor memory device according to the present technology includes a memory cell array including at least two memory blocks sharing one block word line and a transfer block connected to the at least two memory blocks through bit lines, the at least two When an erase voltage is applied to a peripheral circuit for performing an erase operation on a selected memory block from among the memory blocks and a source line commonly connected to the at least two memory blocks, the one block word line and the transfer block controlling the peripheral circuit to apply a first positive voltage to a corresponding block word line and a second positive voltage having a higher level than the first positive voltage to a global word line of an unselected memory block among the at least two memory blocks wherein the first positive voltage may be a voltage for turning on pass transistors respectively connected to the one block word line and a block word line corresponding to the transfer block.

Description

Semiconductor memory device and operating method thereof

The present invention relates to an electronic device, and more particularly, to a semiconductor memory device and an operating method thereof.

A memory system is widely used as a data storage device of digital devices such as computers, digital cameras, MP3 players, and smart phones. Such a memory system may include a semiconductor memory device in which data is stored and a controller controlling the memory device. Digital devices operate as hosts of a memory system, and the controller transmits commands and data between the host and the semiconductor memory device.

A semiconductor memory device is a memory device implemented using a semiconductor such as silicon (Si, silicon), germanium (Ge, Germanium), gallium arsenide (GaAs, gallium arsenide), or indium phosphide (InP). to be. A semiconductor memory device is largely divided into a volatile memory device and a nonvolatile memory device.

A volatile memory device is a memory device in which stored data is destroyed when power supply is cut off. Volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). The nonvolatile memory device is a memory device that retains stored data even when power supply is cut off. Nonvolatile memory devices include ROM (Read Only Memory), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM), Flash memory, PRAM (Phase-change RAM), MRAM (Magnetic RAM) , RRAM (Resistive RAM), FRAM (Ferroelectric RAM), and the like. Flash memory is largely divided into a NOR type and a NAND type.

SUMMARY Embodiments of the present invention provide a semiconductor memory device having an improved erase operation speed and a method of operating the same.

The method of operating a semiconductor memory device including at least two memory blocks sharing one block word line according to an embodiment of the present invention includes applying an erase voltage to a source line commonly connected to the at least two memory blocks. and applying a first voltage to the one block word line and a third voltage to a global word line of an unselected memory block among the at least two memory blocks when the erase voltage is applied to the source line. wherein the first voltage has a higher level than a turn-on voltage for turning on a pass transistor connected to the block word line, and the third voltage is a local word included in the unselected memory block according to a level of the first voltage. It is characterized in that it is a voltage that floats the line.

A semiconductor memory device according to an embodiment of the present invention includes at least two memory blocks sharing one block word line, a peripheral circuit for performing an erase operation on a selected memory block among the at least two memory blocks, and the When an erase voltage is applied to a source line commonly connected to at least two memory blocks, a first voltage is applied to the one block word line and a third voltage is applied to a global word line of an unselected memory block among the at least two memory blocks. a control circuit for controlling the peripheral circuit to apply a voltage, wherein the first voltage has a level higher than a turn-on voltage for turning on a pass transistor connected to the block word line, and the third voltage is the first voltage. It is characterized in that the voltage floats the local word line included in the unselected memory block according to the magnitude of the voltage.

A semiconductor memory device according to an embodiment of the present invention includes at least two memory blocks corresponding to one block decoder and an address decoder including a plurality of the block decoders, wherein the address decoder includes: When an erase voltage is applied to a source line commonly connected to the memory blocks, a first voltage is applied to a block word line, which is an output line of the one block decoder, and a global word line of an unselected memory block among the at least two memory blocks. a third voltage is applied to the memory block, and the first voltage has a higher level than a turn-on voltage for turning on the pass transistor connected to the block word line, and the third voltage is the unselected memory block according to the level of the first voltage. It is characterized in that it is a voltage that floats the local word line included in the .

A semiconductor memory device according to an embodiment of the present invention includes a memory cell array including at least two memory blocks sharing one block word line and a transfer block connected to the at least two memory blocks through bit lines; When an erase voltage is applied to a peripheral circuit for performing an erase operation on a selected memory block among the at least two memory blocks and a source line commonly connected to the at least two memory blocks, the one block word line and the applying a first positive voltage to a block word line corresponding to the transfer block and a second positive voltage having a higher level than the first positive voltage to a global word line of an unselected memory block among the at least two memory blocks; and a control circuit for controlling a peripheral circuit, wherein the first positive voltage may be a voltage that turns on pass transistors respectively connected to the one block word line and a block word line corresponding to the transfer block.

A semiconductor memory device according to an embodiment of the present invention includes a memory cell array including at least two memory blocks sharing one block word line, a transfer circuit connected to the at least two memory blocks through bit lines, and the When an erase voltage is applied to a peripheral circuit for performing an erase operation on a selected memory block among at least two memory blocks and a source line commonly connected to the at least two memory blocks, the one block word line and the A first positive voltage to a block word line corresponding to the transfer block, a second positive voltage having a higher level than the first positive voltage to a global word line of an unselected memory block among the at least two memory blocks, and a transfer circuit and a control circuit for controlling the peripheral circuit to apply a turn-on voltage for turning on the switch transistors to the gate electrodes of the included switch transistors, wherein the first positive voltage corresponds to the one block word line and the transfer block. It may be a voltage that turns on pass transistors respectively connected to the block word line.

According to an embodiment of the present invention, a semiconductor memory device having an improved erase operation speed and a method of operating the same are provided.

1 is a block diagram showing the configuration of a memory system.
FIG. 2 is a block diagram illustrating the structure of the semiconductor memory device of FIG. 1 .
3 is a block diagram illustrating the structure of the address decoder of FIG. 2 .
4 is a diagram illustrating an embodiment of the memory cell array of FIG. 2 .
5 is a diagram illustrating another embodiment of the memory cell array of FIG. 2 .
6 is a diagram for explaining an erase operation of a semiconductor memory device.
7 is a diagram for explaining voltages applied during an erase operation of a semiconductor memory device.
8 is a diagram for explaining operations of memory blocks during an erase operation of a semiconductor memory device.
9 is a diagram for explaining an erasing method according to an embodiment of the present invention.
10 is a diagram for explaining an erasing method according to another embodiment of the present invention.
11 is a view for explaining an erasing method according to another embodiment of the present invention.
12 is a view for explaining an erasing method according to another embodiment of the present invention.
13 is a view for explaining an erasing method according to another embodiment of the present invention.
14 is a diagram for explaining an erasing method according to another embodiment of the present invention.
15 is a flowchart illustrating an operation of a semiconductor memory device according to an embodiment of the present invention.
16 is a block diagram illustrating an embodiment for implementing the controller of FIG. 1 .
17 is a block diagram illustrating an application example of a memory system including the controller of FIG. 16 .
18 is a block diagram illustrating a computing system including the memory system described with reference to FIG. 17 .

Specific structural or functional descriptions of the embodiments according to the concept of the present invention disclosed in this specification or application are only exemplified for the purpose of explaining the embodiments according to the concept of the present invention, and implementation according to the concept of the present invention Examples may be embodied in various forms and should not be construed as being limited to the embodiments described in the present specification or application.

Since the embodiment according to the concept of the present invention may have various changes and may have various forms, specific embodiments will be illustrated in the drawings and described in detail in the present specification or application. However, this is not intended to limit the embodiment according to the concept of the present invention with respect to a specific disclosed form, and should be understood to include all changes, equivalents or substitutes included in the spirit and scope of the present invention.

Terms such as first and/or second may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one element from another element, for example, without departing from the scope of the present invention, a first element may be called a second element, and similarly The second component may also be referred to as the first component.

When a component is referred to as being “connected” or “connected” to another component, it may be directly connected or connected to the other component, but it is understood that other components may exist in between. it should be On the other hand, when it is said that a certain element is "directly connected" or "directly connected" to another element, it should be understood that the other element does not exist in the middle. Other expressions describing the relationship between elements, such as "between" and "immediately between" or "neighboring to" and "directly adjacent to", etc., should be interpreted similarly.

The terms used herein are used only to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present specification, terms such as "comprise" or "have" are intended to designate that the stated feature, number, step, operation, component, part, or combination thereof exists, and includes one or more other features or numbers. , it is to be understood that it does not preclude the possibility of the presence or addition of steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related art, and should not be interpreted in an ideal or excessively formal meaning unless explicitly defined in the present specification. does not

In describing the embodiments, descriptions of technical contents that are well known in the technical field to which the present invention pertains and are not directly related to the present invention will be omitted. This is to more clearly convey the gist of the present invention by omitting unnecessary description.

Hereinafter, the present invention will be described in detail by describing preferred embodiments of the present invention with reference to the accompanying drawings. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing the configuration of a memory system.

The memory system includes a semiconductor memory device 1000 and a controller 50 .

The semiconductor memory device 1000 includes a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), and a phase change memory ( phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM), etc. can be Also, in the memory system according to the embodiment of the present invention, the semiconductor memory device 1000 may be implemented as a three-dimensional array structure. The present invention can be applied not only to a flash memory device in which the charge storage layer is formed of a conductive floating gate (FG), but also to a charge trap flash (CTF) in which the charge storage layer is formed of an insulating layer.

The semiconductor memory device 1000 includes a memory cell array 100 . The memory cell array 110 includes a plurality of nonvolatile memory cells.

The semiconductor memory device 1000 is configured to receive a command and an address from the controller 50 and access a region selected by the address in the memory cell array. That is, the semiconductor memory device 1000 performs an internal operation corresponding to a command with respect to a region selected by an address.

For example, the semiconductor memory device 1000 may perform a program operation, a read operation, and an erase operation. During a program operation, the semiconductor memory device 1000 may program data in an area selected by an address. During a read operation, the semiconductor memory device 1000 may read data from an area selected by an address. During the erase operation, the semiconductor memory device 1000 may erase data stored in an area selected by an address.

In an embodiment, a read operation and a program operation of the semiconductor memory device 1000 may be performed in units of pages. The erase operation of the semiconductor memory device 1000 may be performed in units of memory blocks.

FIG. 2 is a block diagram illustrating the structure of the semiconductor memory device of FIG. 1 .

The semiconductor memory device 1000 may include a memory cell array 100 , a peripheral circuit 600 , and a control circuit 700 .

The peripheral circuit 600 may include an address decoder 200 , a voltage generator 300 , a read/write circuit 400 , and a data input/output circuit 500 .

The memory cell array 100 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to the address decoder 200 through word lines WL. The plurality of memory blocks BLK1 to BLKz are connected to the read and write circuit 400 through bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In an embodiment, the plurality of memory cells are nonvolatile memory cells. A plurality of memory cells is defined as one page of memory cells connected to the same word line. That is, the memory cell array 100 is composed of a plurality of pages.

Also, each of the plurality of memory blocks BLK1 to BLKz of the memory cell array 100 includes a plurality of cell strings. Each of the plurality of cell strings includes a drain select transistor, a first group of memory cells, a pipe transistor, a second group of memory cells, and a source select transistor coupled in series between a bit line and a source line.

The peripheral circuit 600 drives the memory cell array 100 under the control of the control circuit 700 . For example, the peripheral circuit 600 may drive the memory cell array 100 to perform a program operation, a read operation, and an erase operation under the control of the control circuit 700 .

The address decoder 200 is connected to the memory cell array 110 through word lines WL. The address decoder 200 is configured to operate in response to the control of the control circuit 700 . The address decoder 200 receives the address ADDR from the control circuit 700 through an input/output buffer (not shown) inside the semiconductor memory device 1000 .

The address decoder 200 is configured to decode a block address among the received addresses ADDR. The address decoder 200 selects at least one memory block from among the memory blocks BLK1 to BLKz according to the decoded block address. The address decoder 200 is configured to decode a row address among the received addresses ADDR. The address decoder 200 may select at least one word line of the selected memory block by applying voltages provided from the voltage generator 300 to the at least one word line WL according to the decoded row address.

During a program operation, the address decoder 200 may apply a program voltage to the selected word lines and a pass voltage of a lower level than the program voltage to unselected word lines. During the program verification operation, the address decoder 200 applies a verification voltage to the selected word line and applies a verification pass voltage higher than the verification voltage to the unselected word lines.

During a read operation, the address decoder 200 applies a read voltage to the selected word line and applies a pass voltage higher than the read voltage to the unselected word lines.

In an embodiment, the erase operation of the semiconductor memory device 1000 is performed in units of memory blocks. The address ADDR input to the semiconductor memory device 1000 during an erase operation includes a block address. The address decoder 200 may decode the block address and select one memory block according to the decoded block address. During an erase operation, the address decoder 200 may apply a ground voltage to a word line input to the selected memory block. In an embodiment, the address decoder 200 may include a block decoder, a word line decoder, and an address buffer.

A detailed operation of the address decoder 200 will be described in more detail with reference to FIG. 5 to be described later.

The voltage generator 300 is configured to generate a plurality of voltages using an external power voltage supplied to the semiconductor memory device 1000 . The voltage generator 300 operates in response to the control of the control circuit 700 .

As an embodiment, the internal power supply voltage may be generated by regulating the external power supply voltage. The internal power voltage generated by the voltage generator 300 is used as an operating voltage of the semiconductor memory device 1000 .

As an embodiment, the voltage generator 300 may generate a plurality of voltages using an external power voltage or an internal power voltage. For example, the voltage generator 300 may include a plurality of pumping capacitors for receiving an internal power supply voltage, and selectively activate the plurality of pumping capacitors in response to the control of the control circuit 700 to generate a plurality of voltages. . The generated voltages are applied to the word lines selected by the address decoder 200 .

The read/write circuit 400 includes first to m-th page buffers PB1 to PBm. The first to m-th page buffers PB1 to PBm are respectively connected to the memory cell array 100 through the first to m-th bit lines BL1 to BLm. The first to mth page buffers PB1 to PBm operate in response to the control of the control circuit 700 .

The first to mth page buffers PB1 to PBm communicate data with the data input/output circuit 500 . During programming, the first to mth page buffers PB1 to PBm receive data DATA to be stored through the data input/output circuit 500 and the data lines DL.

During a program operation, the first to mth page buffers PB1 to PBm receive data DATA to be stored through the data input/output circuit 500 when a program pulse is applied to the selected word line. to the selected memory cells through the bit lines BL1 to BLm. Memory cells of a selected page are programmed according to the transferred data DATA. A memory cell connected to a bit line to which a program allowable voltage (eg, a ground voltage) is applied will have a raised threshold voltage. A threshold voltage of a memory cell connected to a bit line to which a program inhibit voltage (eg, a power supply voltage) is applied may be maintained. During the program verify operation, the first to mth page buffers PB1 to PBm read page data from the selected memory cells through the bit lines BL1 to BLm.

During a read operation, the read/write circuit 400 reads data DATA from memory cells of a selected page through bit lines BL, and outputs the read data DATA to the input/output circuit 500 .

During the erase operation, the read and write circuit 400 may float the bit lines BL. In an embodiment, the read and write circuit 123 may include a column selection circuit.

The data input/output circuit 500 is connected to the first to mth page buffers PB1 to PBm through data lines DL. The data input/output circuit 124 operates in response to the control of the control circuit 700 . During programming, the data input/output circuit 124 receives data DATA to be stored from an external controller (not shown). The data input/output circuit 500 outputs data transferred from the first to m-th page buffers PB1 to PBm included in the read and write circuit 400 to an external controller during a read operation.

The control circuit 700 is connected to the address decoder 200 , the voltage generator 300 , the read/write circuit 400 , and the data input/output circuit 500 . The control circuit 700 may control the overall operation of the semiconductor memory device 1000 . The control circuit 700 receives a command CMD and an address ADDR from an external controller. The control circuit 700 may control the peripheral circuit 600 in response to the command CMD. The control circuit 700 may control the address decoder 200 , the voltage generator 300 , the read/write circuit 400 , and the data input/output circuit 500 to perform an operation corresponding to the received command. In an embodiment, the control circuit 700 may apply a high-voltage erase voltage Verase to the source line during an erase operation.

3 is a block diagram illustrating the structure of the address decoder of FIG. 2 .

Referring to FIG. 3 , referring to FIG. 2 , the address decoder 200 includes a block decoder unit 210 and a pass unit 220 .

The block decoder unit 210 includes a plurality of block decoders (X-DECs) 210A to 210C. Each of the plurality of block decoders 210A to 210C corresponds to a plurality of memory blocks BLK1 to BLKz. For example, one block decoder (eg, 210A) may correspond to two memory blocks BLK1 and BLK2. Although the structure in which two memory blocks correspond to one block decoder has been described in the embodiment of the present invention, two or more memory blocks may correspond to one block decoder. That is, a plurality of memory blocks may be commonly connected to one block decoder. Accordingly, a plurality of memory blocks may share one block word line.

Each of the plurality of block decoders 210A to 210C may output any one of the block selection signals BLKWL_A to BLKWL_C to a block word line in response to the address ADDR. Here, the block selection signals may be input to the pass unit 220 through block word lines. For example, the block decoder 210A outputs the block selection signal BLKWL_A in response to the address ADDR, the block decoder 210B outputs the block selection signal BLKWL_B in response to the address ADDR, and the block The decoder 210C outputs the block selection signal BLKWL_C in response to the address ADDR.

The pass unit 122 includes a plurality of pass transistors PTr. Each of the plurality of pass transistors PTr corresponds to the plurality of memory blocks BLK1 to BLKz. In addition, the plurality of pass transistors PTr respond to the plurality of block select signals BLKWL_A to BLKWL_C to the plurality of global word line groups GWL_A to GWL_D and local words of the plurality of memory blocks BLK1 to BLKz. The lines WL are electrically connected. At this time, one of the pass transistors PTr corresponding to the first and second memory blocks (eg, BLK1 and BLK2) among the plurality of pass transistors PTr included in the pass unit 122 is one block decoder 210A. ) is turned on or off in response to the block selection signal BLKWL_A outputted from the . In addition, the pass transistors PTr corresponding to the third and fourth memory blocks BLK3 and BLK4 are turned on or off in response to the block select signal BLKWL_B output from the block decoder 210B, and the z-th - The pass transistors PTr corresponding to the first and z-th memory blocks BLKz-1 and BLKz are turned on or off in response to the block select signal BLKWL_C output from the block decoder 210C.

Accordingly, when the first memory block BLK1 is selected from among the plurality of memory blocks BLK1 to BLKz, corresponding to the first and second memory blocks BLK1 and BLK2 sharing the block decoder 210A, respectively. The pass transistor PTr may be turned on by the block select signal BLKWL_A.

In the present specification, a memory block selected by the address decoder such as the first memory block BLK1 is selected as a selected block, and a second memory block that shares the selected first memory block BLK1 and the block decoder 210A ( A memory block such as BLK2 is referred to as a shared BLK and memory blocks such as the unselected third to zth memory blocks BLK3 to BLKz are referred to as unselected BLK, respectively.

4 is a diagram illustrating an embodiment of the memory cell array of FIG. 2 .

Referring to FIG. 4 , the memory cell array 100_1 includes a plurality of memory blocks BLK1 to BLKz. In FIG. 4 , the internal configuration of the first memory block BLK1 is illustrated for convenience of recognition, and the internal configuration of the remaining memory blocks BLK2 to BLKz is omitted. It will be understood that the second to z-th memory blocks BLK2 to BLKz are configured similarly to the first memory block BLK1.

Referring to FIG. 4 , the first memory block BLK1 includes a plurality of cell strings CS11 to CS1m and CS21 to CS2m. As an embodiment, each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may be formed in a 'U' shape. In the first memory block BLK1 , m cell strings are arranged in the row direction (ie, the +X direction). In FIG. 4 , it is illustrated that two cell strings are arranged in a column direction (ie, a +Y direction). However, this is for convenience of description, and it will be understood that three or more cell strings may be arranged in a column direction.

Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain. and a selection transistor DST.

Each of the selection transistors SST and DST and the memory cells MC1 to MCn may have a similar structure. In an embodiment, each of the selection transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. In an embodiment, a pillar for providing a channel layer may be provided in each cell string. In an embodiment, a pillar for providing at least one of a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer may be provided in each cell string.

The source select transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCp.

In an embodiment, source select transistors of cell strings arranged in the same row are connected to source select lines extending in the row direction, and source select transistors of cell strings arranged in different rows are connected to different source select lines. In FIG. 5 , the source select transistors of the cell strings CS11 to CS1m in the first row are connected to the first source select line SSL1 . The source select transistors of the cell strings CS21 to CS2m of the second row are connected to the second source select line SSL2 .

As another embodiment, the source select transistors of the cell strings CS11 to CS1m and CS21 to CS2m may be commonly connected to one source select line.

The first to nth memory cells MC1 to MCn of each cell string are connected between the source select transistor SST and the drain select transistor DST.

The first to nth memory cells MC1 to MCn may be divided into first to pth memory cells MC1 to MCp and p+1 to nth memory cells MCp+1 to MCn. The first to p-th memory cells MC1 to MCp are sequentially arranged in a direction opposite to the +Z direction, and are connected in series between the source select transistor SST and the pipe transistor PT. The p+1th to nth memory cells MCp+1 to MCn are sequentially arranged in the +Z direction, and are connected in series between the pipe transistor PT and the drain select transistor DST. The first to p-th memory cells MC1 to MCp and the p+1 to n-th memory cells MCp+1 to MCn are connected through the pipe transistor PT. Gates of the first to nth memory cells MC1 to MCn of each cell string are respectively connected to the first to nth word lines WL1 to WLn.

In an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. When the dummy memory cell is provided, the voltage or current of the corresponding cell string may be stably controlled. Accordingly, reliability of data stored in the memory block BLK1 is improved.

A gate of the pipe transistor PT of each cell string is connected to the pipeline PL.

The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MCp+1 to MCn. The cell strings arranged in the row direction are connected to a drain select line extending in the row direction. Drain select transistors of the cell strings CS11 to CS1m of the first row are connected to the first drain select line DSL1. Drain select transistors of the cell strings CS21 to CS2m of the second row are connected to the second drain select line DSL2.

The cell strings arranged in the column direction are connected to bit lines extending in the column direction. In FIG. 4 , the cell strings CS11 and CS21 of the first column are connected to the first bit line BL1 . The cell strings CS1m and CS2m of the m-th column are connected to the m-th bit line BLm.

Memory cells connected to the same word line in the cell strings arranged in the row direction constitute one page. For example, among the cell strings CS11 to CS1m of the first row, memory cells connected to the first word line WL1 constitute one page. Among the cell strings CS21 to CS2m of the second row, memory cells connected to the first word line WL1 constitute another page. When any one of the drain selection lines DSL1 and DSL2 is selected, cell strings arranged in one row direction may be selected. When any one of the word lines WL1 to WLn is selected, one page of the selected cell strings may be selected.

5 is a diagram illustrating another embodiment of the memory cell array of FIG. 2 .

Referring to FIG. 5 , the memory cell array 100_2 includes a plurality of memory blocks BLK1' to BLKz'. In FIG. 5 , the internal configuration of the first memory block BLK1' is illustrated for convenience of recognition, and the internal configuration of the remaining memory blocks BLK2' to BLKz' is omitted. It will be understood that the second to z-th memory blocks BLK2' to BLKz' are configured similarly to the first memory block BLK1'.

The first memory block BLK1' includes a plurality of cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' extends along the +Z direction. In the first memory block BLK1 ′, m cell strings are arranged in the +X direction. In FIG. 7 , it is shown that two cell strings are arranged in the +Y direction. However, this is for convenience of description, and it will be understood that three or more cell strings may be arranged in a column direction.

Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' includes at least one source select transistor SST, the first to n-th memory cells MC1 to MCn, and at least one drain selector. transistor DST.

The source select transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCn. The source select transistors of the cell strings arranged in the same row are connected to the same source select line. Source select transistors of the cell strings CS11' to CS1m' arranged in the first row are connected to the first source select line SSL1. The source select transistors of the cell strings CS21' to CS2m' arranged in the second row are connected to the second source select line SSL2. As another embodiment, the source select transistors of the cell strings CS11' to CS1m' and CS21' to CS2m' may be commonly connected to one source select line.

The first to nth memory cells MC1 to MCn of each cell string are connected in series between the source select transistor SST and the drain select transistor DST. Gates of the first to nth memory cells MC1 to MCn are respectively connected to the first to nth word lines WL1 to WLn.

In an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. When the dummy memory cell is provided, the voltage or current of the corresponding cell string may be stably controlled. Accordingly, reliability of data stored in the memory block BLK1' is improved.

The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MC1 to MCn. Drain select transistors of the cell strings arranged in the row direction are connected to a drain select line extending in the row direction. Drain select transistors of the cell strings CS11' to CS1m' in the first row are connected to the first drain select line DSL1. Drain select transistors of the cell strings CS21' to CS2m' in the second row are connected to the second drain select line DSL2.

As a result, the memory block BLK1 ′ of FIG. 5 has an equivalent circuit similar to that of the memory block BLK1 of FIG. 4 except that the pipe transistor PT is excluded from each cell string.

6 is a diagram for explaining an erase operation of a semiconductor memory device.

Referring to FIG. 6 , the first to fourth memory blocks BLK1 to BLK4 are commonly connected to the 0th to Nth bit lines. The first to fourth memory blocks BLK1 to BLK4 may be included in the memory cell array 100 described with reference to FIG. 5 . Gate electrodes of the memory cells included in the first to fourth memory blocks BLK1 to BLK4 are respectively connected to local word lines, and the local word lines are connected to the global word line A GWL_A through the pass transistor Pass Tr. Alternatively, it may be connected to any one of the global word lines C (GWL_C). 6 illustrates that four memory blocks (first to fourth memory blocks BLK1 to BLK4) are included in the memory cell array for convenience of description, but in an embodiment, five or more memory blocks are included in the memory cell array. can

The local word lines of the first memory block BLK1 may be connected to the global word line A GWL_A through the pass transistor Pass Tr. The local word lines of the second memory block BLK2 may be connected to the global word line C GWL_C through the pass transistor Pass Tr. The local word lines of the third memory block BLK3 may be connected to the global word line C GWL_C through the pass transistor Pass Tr. The local word lines of the fourth memory block BLK4 may be connected to the global word line A GWL_A through the pass transistor Pass Tr.

Pass transistors corresponding to the first memory block BLK1 and the second memory block BLK2 may be commonly connected to one block word line. Accordingly, the first memory block BLK1 and the second memory block BLK2 share one block decoder.

The pass transistors Pass Tr corresponding to the third memory block BLK3 and the fourth memory block BLK4 may be commonly connected to one block word line. Accordingly, the third memory block BLK3 and the fourth memory block BLK4 share one block decoder.

In the embodiment of FIG. 6 , it is assumed that the first memory block BLK1 among the first to fourth memory blocks BLK1 to BLK4 is erased.

The selected first memory block BLK1 is a select block, and the second memory block BLK2 connected to the same block word line BLKWL as the selected first memory block BLK1 is a shared BLK. to be. The unselected third and fourth memory blocks BLK3 and BLK4 are unselected blocks.

Since the block word line BLKWL connected to the pass transistor Pass Tr of the first memory block BLK1 must be turned on to apply the word line voltage 0V, the block selection voltage Vselect is applied to the selected block word line. can be Since the pass transistor Pass Tr of the second memory block BLK2 shares the block word line BLKWL with the pass transistor Pass Tr of the first memory block BLK1, the pass transistor of the second memory block BLK2 The same block selection voltage Vselect is also applied to (Pass Tr).

Since the first memory block BLK1 is a memory block to be erased, the global word line A GWL_A is selected and the global word line C GWL_C is unselected.

A block word line connected to the pass transistors Pass Tr of the third and fourth memory blocks BLK3 and BLK4 that is an unselected BLK is an unselected block word line Unselected BLKWL, and has a ground voltage of 0V. This may be authorized.

7 is a diagram for explaining voltages applied during an erase operation of a semiconductor memory device.

8 is a diagram for explaining operations of memory blocks during an erase operation of a semiconductor memory device.

While an erase operation is being performed, the semiconductor memory device generates an erase voltage Verase and applies the generated erase voltage Verase to the common source line CSL (Source Bias). At this time, the source select transistor SST and the drain select transistor DST are controlled to be in a floating state.

A ground voltage may be applied to local word lines of the selected memory block. Thereafter, the potential level of the channel increases according to the potential level of the common source line CSL, and is connected to a plurality of source select transistors and drain select transistors in a floating state according to the potential level of the channel. A potential level of the source select lines and the drain select lines may increase due to a coupling phenomenon.

Data stored in the memory cells are erased by the increased potential level of the channel. That is, electrons stored in the charge storage layer of the memory cells are detrapped by the potential of the channel due to the FN tunneling phenomenon. To explain this in more detail, depending on the difference between the potential level of the raised channel and the potential level of the local word lines having the ground level, electrons stored in the charge storage layer of the memory cells are discharged to the channel and detrapped or , a hot hole generated in the channel flows into the charge storage layer of the memory cells, and electrons stored in the charge storage layer are detrapped. In this case, the local word lines may maintain a ground level or may be changed to a ground level in a floating state.

After the data of the memory cells is erased by the erase operation, the erase voltage Verase applied to the common source line CSL is cut off, and the potential of the common source line CSL is discharged.

In an erase operation, when an erase voltage Verase having a high voltage level is applied to the common source line CSL, the source select transistor is in a floating state, and thus a gate induced current (GIDL) is leakage) occurs, a hot hole is generated and flows in the channel direction, and the potential of the channel rises. At this time, the bit line maintains a floating state. The erase voltage Verase may be transferred to the bit line in which the erase voltage Verase is in a floating state through a coupling capacitance between the common source line CSL and the bit lines and the channel of the erase block.

Since word line voltages are 0V in the selected memory block, data in the memory cells is erased as the hot hole tunnels to the memory cell.

However, the voltage of the bit line may be lower than the erase voltage of the common source line CSL due to a built-in potential or a coupling ratio. Accordingly, due to the potential difference between the common source line CSL and the bit lines, the channel potential and the hole are introduced in the bit line direction, and thus the erase characteristic may be deteriorated.

In particular, in the address decoder structure sharing the block word line described with reference to FIG. 6 , the selected block and the shared block may exist simultaneously when the pass transistor connecting the global word line and the local word line is turned on.

7 and 8, at time t0, a block word line (shared BLKWL) that commonly connects the selected block (select BLK) and the shared block (shared BLK) is grounded to the local word line for erasing the selected memory block. Since a voltage must be applied, a first positive voltage Vpositive1=Vselect for turning on the pass transistor Pass Tr may be applied.

A ground voltage 0V is applied to the block word line Unsel. BLKWL connected to the unselected memory block Unselect BLK.

Local word lines of a shared BLK are formed as floating nodes to avoid an erase phenomenon. To this end, the shared BLK global word line (Shared BLK Global WL), the source select line (SSL), the drain select line (DSL) and the pipe cell gate (PCG) of the shared block (shared BLK) have blocks connected to the shared BLK A second positive voltage (Vpositive2=Vglobal) having a higher voltage than the word line (shared BLKWL) may be applied. Accordingly, a floating state may be formed (Vlocal) in a state in which the local wordlines are charged with a potential lower than that of the shared block wordline (shared BLKWL).

The global source select line, drain select line, and pipe cell gate of the memory block selected at time t1 may have voltages corresponding to the source select line voltage VSSL, the drain select line voltage VDSL, and the pipe cell voltage VPCG, respectively. have.

Accordingly, when the threshold voltages of the memory cells included in the shared block are low, the memory cells are turned on, and the erase voltage Verase is transferred from the source SO to the bit line BL so that the bit line can be precharged (shared). BLK(Low Vt)). However, when the threshold voltages of the memory cells are high, they are turned off, so that the erase voltage Verase is not transferred from the source SO to the bit line BL, and precharge of the bit line is impossible (shared BLK (High Vt). )).

According to an embodiment of the present invention, even when the threshold voltages of the memory cells included in the shared block are high, by turning on the memory cells, the erase voltage Verase is smoothly transferred to the bit line to enable the bit line precharge.

9 is a diagram for explaining an erasing method according to an embodiment of the present invention.

Referring to FIG. 9 , an erase voltage Verase is applied to the source line Source Bias at time t2.

A first voltage V1 may be applied to the block word line Share BLKWL of the selected block and the shared block. The first voltage V1 may be a voltage that turns on the pass transistors of the selection block and the shared block. In an embodiment, the first voltage V1 may be a voltage having a level higher than a voltage for turning on the pass transistors of the selection block and the shared block by a preset value.

A ground voltage (0V) is applied to the block word line Unsel.BLKWL of the unselected block.

A third voltage V3 may be applied to the global word line Global WL, the source select line SSL, the drain select line DSL, and the pipe cell gate PCG of the shared block BLK. The third voltage V3 may be a voltage that forms local word lines of the shared block as floating nodes in order to avoid an erase phenomenon of the shared block. In an embodiment, the third voltage V3 may be a voltage that forms the local word lines of the shared block as floating nodes in response to the level of the first voltage.

A second voltage V2 having a lower voltage level than the first voltage V1 may be applied to the block word line Share BLKWL of the selected block and the shared block at time t3. In an embodiment, the second voltage V2 may be a voltage that turns on the pass transistors of the selection block and the shared block.

A fourth voltage level lower than the third voltage V3 is applied to the global word line Global WL, the source select line SSL, the drain select line DSL, and the pipe cell gate PCG of the shared block BLK. A voltage V4 may be applied. In an embodiment, the fourth voltage V4 may be a voltage that forms the local word lines of the shared block as floating nodes according to the magnitude of the second voltage.

At time t4, the global source selection line Global SSL, the drain selection line DSL, and the pipe cell gate PCG of the selected block Sel. BLK have a source selection line voltage VSSL and a drain selection line voltage VDSL, respectively. and a voltage corresponding to the pipe cell voltage VPCG.

According to the embodiment of FIG. 9 , a block word line (Share BLKWL) of a selection block and a shared block, a global word line (Global WL) of a shared block (Shared BLK), a source selection line (SSL), and a drain selection line (DSL) , the first voltage V1 and the third voltage V3 increased by preset values from the first positive voltage Vpositive1 and the second positive voltage Vpositive2 applied to the pipe cell gate PCG in the embodiment of FIG. 7 . ) is applied for a predetermined reference time to turn on the memory cells included in the shared block for a short time at the beginning of the erase operation, the potential of the floating local word line may be increased. Accordingly, even if the memory cell included in the shared block has a high threshold voltage, the erase voltage Verase is smoothly transferred to the bit line to enable the bit line precharge, so that the erase operation can be performed more quickly.

10 is a diagram for explaining an erasing method according to another embodiment of the present invention.

Referring to FIG. 10 , an erase voltage Verase is applied to the source line Source Bias at time t5.

A first voltage V1 may be applied to the block word line Share BLKWL of the selected block and the shared block. The first voltage V1 may be a voltage that turns on the pass transistors of the selection block and the shared block. In an embodiment, the first voltage V1 may be a voltage having a level higher than a voltage for turning on the pass transistors of the selection block and the shared block by a preset value.

A ground voltage (0V) is applied to the block word line Unsel.BLKWL of the unselected block.

A third voltage V3 may be applied to the global word line Global WL, the source select line SSL, the drain select line DSL, and the pipe cell gate PCG of the shared block BLK. The third voltage V3 may be a voltage that forms local word lines of the shared block as floating nodes in order to avoid an erase phenomenon of the shared block. In an embodiment, the third voltage V3 may be a voltage that forms the local word lines of the shared block as floating nodes in response to the level of the first voltage.

In the embodiment of FIG. 10, unlike the embodiment of FIG. 9, the block word line (Share BLKWL) of the selection block and the shared block, the global word line (Global WL) of the shared block (Shared BLK), the source selection line (SSL), the drain The memory cell included in the shared block is continuously turned on without changing the voltage applied to the selection line DSL and the pipe cell gate PCG.

At time t6, the global source select line Global SSL, drain select line DSL, and pipe cell gate PCG of the selected block Sel. BLK have a source select line voltage VSSL and a drain select line voltage VDSL, respectively. and a voltage corresponding to the pipe cell voltage VPCG.

According to the embodiment of FIG. 10 , a block word line (Share BLKWL) of a selection block and a shared block, a global word line (Global WL) of a shared block (Shared BLK), a source selection line (SSL), and a drain selection line (DSL) , the first voltage V1 and the third voltage V3 increased by preset values from the first positive voltage Vpositive1 and the second positive voltage Vpositive2 applied to the pipe cell gate PCG in the embodiment of FIG. 7 . ) is continuously applied to turn on the memory cell included in the shared block (Full Range), the potential of the floating local word line can be increased. Accordingly, even if the memory cell included in the shared block has a high threshold voltage, the erase voltage Verase is smoothly transferred to the bit line to enable the bit line precharge, so that the erase operation can be performed more quickly.

11 is a view for explaining an erasing method according to another embodiment of the present invention.

Referring to FIG. 11 , an erase voltage Verase is applied to the source line Source Bias at time t7.

A first positive voltage Vpositive1 may be applied to the block word line Share BLKWL of the selected block and the shared block. The first positive voltage Vpositive1 may be a voltage that turns on the pass transistors of the selection block and the shared block.

A fifth voltage V5 is applied to the block word line Unsel.BLKWL of the unselected block. In an embodiment, the fifth voltage V5 may be a voltage that turns on the pass transistor of the unselected block. In an embodiment, the global word line voltage of the unselected block may be maintained equal to the fifth voltage V5.

A second positive voltage Vpositive2 may be applied to the global word line Global WL, the source select line SSL, the drain select line DSL, and the pipe cell gate PCG of the shared block BLK. The second positive voltage Vpositive2 may be a voltage that forms local word lines of the shared block as floating nodes in order to avoid an erase phenomenon of the shared block. In an embodiment, the second positive voltage Vpositive2 may be a voltage that forms the local word lines of the shared block as floating nodes corresponding to the level of the first positive voltage Vpositive1 .

At time t8, the fifth voltage V5 that was applied to the block word line Unsel.BLKWL of the unselected block may be discharged. That is, the ground voltage may be applied to the block word line Unsel.BLKWL of the unselected block. In the embodiment of FIG. 11 , the potential of the floating local word line may be increased by turning on the memory cells included in the unselected block for a short time. Accordingly, the erase operation can be performed more quickly by allowing the erase voltage Verase to be smoothly transferred to the bit line to enable the bit line precharge.

At time t8, the global source selection line Global SSL, the drain selection line DSL, and the pipe cell gate PCG of the selected block Sel. BLK have a source selection line voltage VSSL and a drain selection line voltage VDSL, respectively. and a voltage corresponding to the pipe cell voltage VPCG.

12 is a view for explaining an erasing method according to another embodiment of the present invention.

12 , an embodiment in which a memory block other than a main block among a plurality of memory blocks included in a semiconductor memory device is used as a transfer block will be described.

Referring to FIG. 12 , the first to fourth memory blocks BLK1 to BLK4 and the transfer block BLKx are commonly connected to the 0 to Nth bit lines. The first to fourth memory blocks BLK1 to BLK4 and the transfer block BLKx may be included in the memory cell array 100 described with reference to FIG. 5 . Gate electrodes of the memory cells included in the first to fourth memory blocks BLK1 to BLK4 and the transfer block BLKx are respectively connected to local word lines, and the local word lines are connected to a global word through a pass transistor Pass Tr. It may be connected to either the line A (GWL_A) or the global word line C (GWL_C). In FIG. 12 , it is illustrated that five memory blocks (first to fourth memory blocks BLK1 to BLK4 and transfer block BLKx) are included in the memory cell array for convenience of explanation, but in the embodiment, 5 memory blocks are included in the memory cell array More than one memory block may be included.

In an embodiment, the transfer block BLKx other than the main block among the plurality of memory blocks included in the semiconductor memory device may be a memory block other than the main block used to store data. For example, the transfer block may correspond to any one of a system block for storing system operation information of the semiconductor memory device and a repair block including redundancy strings required for a repair operation.

The local word lines of the first memory block BLK1 may be connected to the global word line A GWL_A through the pass transistor Pass Tr. The local word lines of the second memory block BLK2 may be connected to the global word line C GWL_C through the pass transistor Pass Tr. The local word lines of the third memory block BLK3 may be connected to the global word line C GWL_C through the pass transistor Pass Tr. The local word lines of the fourth memory block BLK4 may be connected to the global word line A GWL_A through the pass transistor Pass Tr. The local word lines of the transfer block BLKx may be connected to the global word line C GWL_C through the pass transistor Pass Tr.

Pass transistors corresponding to the first memory block BLK1 and the second memory block BLK2 may be commonly connected to one block word line. Accordingly, the first memory block BLK1 and the second memory block BLK2 share one block decoder.

The pass transistors Pass Tr corresponding to the third memory block BLK3 and the fourth memory block BLK4 may be commonly connected to one block word line. Accordingly, the third memory block BLK3 and the fourth memory block BLK4 share one block decoder.

In the embodiment of FIG. 6 , it is assumed that the first memory block BLK1 among the first to fourth memory blocks BLK1 to BLK4 is erased.

The selected first memory block BLK1 is a select block, and the second memory block BLK2 connected to the same block word line BLKWL as the selected first memory block BLK1 is a shared BLK. to be. The unselected third and fourth memory blocks BLK3 and BLK4 are unselected blocks.

Since the block word line BLKWL connected to the pass transistor Pass Tr of the first memory block BLK1 must be turned on to apply the word line voltage 0V, the block selection voltage Vselect is applied to the selected block word line. can be Since the pass transistor Pass Tr of the second memory block BLK2 shares the block word line BLKWL with the pass transistor Pass Tr of the first memory block BLK1, the pass transistor of the second memory block BLK2 The same block selection voltage Vselect is also applied to (Pass Tr).

Since the first memory block BLK1 is a memory block to be erased, the global word line A GWL_A is selected and the global word line C GWL_C is unselected.

A block word line connected to the pass transistors Pass Tr of the third and fourth memory blocks BLK3 and BLK4 that is an unselected BLK is an unselected block word line Unselected BLKWL, and has a ground voltage of 0V. This may be authorized.

According to the erase method of the present invention, the block word line (Share BLKWL) of the selected block and the shared block, the global word line (Global WL) of the shared block (Shared BLK), the source select line (SSL), and the drain select line (DSL) , the first voltage V1 and the third voltage V3 increased by preset values from the first positive voltage Vpositive1 and the second positive voltage Vpositive2 applied to the pipe cell gate PCG in the embodiment of FIG. 7 . ) is applied for a predetermined reference time and the memory cells included in the shared block are turned on for a short time (short tun-on) at the beginning of the erase operation, the potential of the floating local word line may be increased. Accordingly, even if the memory cell included in the shared block has a high threshold voltage, the erase voltage Verase is smoothly transferred to the bit line to enable the bit line precharge, so that the erase operation can be performed more quickly.

12 , the first transfer block word line voltage 3 ^rd BLKWL may be applied to the gate electrode of the pass transistor of the transfer block BLKx. In an embodiment, the first transfer block word line voltage may be a turn-on voltage of the pass transistor Pass Tr of the transfer block (Vselect). Accordingly, the pass transistor Pass Tr of the transfer block BLKx is turned on and the voltage of the global word line C GWL_C is transferred to the local word line of the transfer block. Thereafter, the semiconductor memory device may discharge the transfer block word line voltage and apply a second transfer block word line voltage (0V). In an embodiment, the second transfer block word line voltage may be a ground voltage. Accordingly, the local word line of the transfer block BLKx will be set from a positive voltage state to a floating state. The time for applying the first transfer block word line voltage Vselect may be a time for floating the local word line of the transfer block when the second transfer block word line voltage 0V is applied thereafter.

When the local word line of the transfer block BLKx is formed in the floating state, the erase voltage Verase applied to the common source line is transferred to the bit line in the floating state so that the bit line potential is equal to or equal to that of the common source line during the erase operation. more can be formed. Accordingly, the erase operation may be smoothly performed regardless of the threshold voltage of the memory cell in the shared block.

In an embodiment, the embodiment of FIG. 12 may be applied to the erase operation to which a voltage is applied according to the embodiment of FIG. 7 in addition to the erase operation to which a voltage is applied according to the embodiment of FIGS. 9 to 11 .

13 is a view for explaining an erasing method according to another embodiment of the present invention.

Referring to FIG. 13 , the memory cell array of the semiconductor memory device according to an embodiment of the present invention may further include a transfer block (TB). The transfer circuit TB may include switch transistors Tr connecting the common source line CSL and the bit line therein. In an embodiment, a turn-on bias may be applied to the gate electrodes of the switch transistors Tr in an initial stage of an erase operation. The transfer circuit TB may precharge the bit line with the erase voltage Verase from the voltage of the common source line in the bit line direction. The embodiment of FIG. 13 is an embodiment implemented as a transfer circuit including a plurality of switches Tr instead of the transfer block BLKx in the embodiment of FIG. 12 .

According to the embodiment of FIG. 13 , a separate transfer circuit is provided so that data of a system block or a repair block other than the main block among the memory blocks is not damaged, thereby achieving the same effect as the operation of FIG. 12 .

A first electrode of the switch transistors included in the transfer circuit TB may be connected to the bit lines, respectively, and a second electrode may be connected to a common source line. Accordingly, the source bias may be transferred in the bit line direction regardless of the threshold voltages of the memory cells in the shared block. In an embodiment, the first electrode may be a drain electrode, and the second electrode may be a source electrode. Alternatively, the first electrode may be a source electrode and the second electrode may be a drain electrode.

14 is a diagram for explaining an erasing method according to another embodiment of the present invention.

Referring to FIG. 14 , the memory cell array of the semiconductor memory device according to an exemplary embodiment may further include a transfer block (TB). The transfer circuit TB may include a plurality of switch transistors Tr connected to the bit line therein.

A first electrode of the switch transistors included in the transfer circuit TB may be connected to the bit lines, respectively, and a second electrode may be connected to a precharge electrode. In the embodiment of FIG. 14 , a random precharge voltage Vx is applied without connecting the switches Tr included in the transfer block to the common source line, unlike in FIG. 13 .

Accordingly, during an erase operation of the semiconductor memory device, a constant precharge voltage Vx may be precharged in the bit line direction regardless of the erase voltage applied to the common source line.

In an embodiment, the first electrode may be a drain electrode, and the second electrode may be a source electrode. Alternatively, the first electrode may be a source electrode and the second electrode may be a drain electrode.

12 to 14 may be applied to the erase operation to which a voltage is applied according to the embodiment of FIG. 7 in addition to the erase operation to which a voltage is applied according to the embodiment of FIGS. 9 to 11 .

15 is a flowchart illustrating an operation of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 15 , in operation 1401 , the semiconductor memory device may apply an erase voltage to the source line.

In operation 1403, the semiconductor memory device may apply a first voltage to the block word line of the shared block and a third voltage to the global word line of the shared block. Here, the first voltage may be a voltage that turns on the pass transistors of the selection block and the shared block. In an embodiment, the first voltage may be a voltage having a level higher than a voltage for turning on the pass transistors of the selection block and the shared block by a preset value. The third voltage may be a voltage that forms local word lines of the shared block as floating nodes in order to avoid an erase phenomenon of the shared block. In an embodiment, the third voltage may be a voltage that forms the local word lines of the shared block as floating nodes in correspondence to the level of the first voltage.

In operation 1405 , the semiconductor memory device determines whether a reference time has been exceeded. If it is determined that the reference time is exceeded, the process proceeds to step 1407 .

In operation 1407 , the semiconductor memory device may change the first voltage applied to the block word line of the shared block to a second voltage and change the third voltage applied to the global word line of the shared block to a fourth voltage and apply it. Here, the second voltage has a lower level than the first voltage. The fourth voltage has a lower level than the third voltage. The fourth voltage may be a voltage that forms local word lines of the shared block as floating nodes according to the second voltage.

16 is a block diagram illustrating an embodiment for implementing the controller of FIG. 1 .

Referring to FIG. 16 , the controller 1200 includes a random access memory (RAM) 1210, a processing unit 1220, a host interface 1230, a memory interface 1240, and an error correction block. (1250).

The processing unit 1220 controls overall operations of the controller 1200 . The RAM 1210 may be used as at least one of an operation memory of the processing unit 1220 , a cache memory between the semiconductor memory device and the host, and a buffer memory between the semiconductor device and the host.

The host interface 1230 includes a protocol for performing data exchange between the host and the controller 1200 . In an embodiment, the controller 1200 may include a Universal Serial Bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, At least among various interface protocols such as Serial-ATA protocol, Parallel-ATA protocol, SCSI (small computer small interface) protocol, ESDI (enhanced small disk interface) protocol, and IDE (Integrated Drive Electronics) protocol, private protocol, etc. It is configured to communicate with the host through one.

The memory interface 1240 interfaces with the semiconductor memory device.

The error correction block 1250 decodes data received from the semiconductor memory device 1300 using an error correction code.

In FIG. 16 , the semiconductor memory device 1300 may have the same configuration as the semiconductor memory device 1000 described with reference to FIG. 2 .

17 is a block diagram illustrating an application example of a memory system including the controller of FIG. 16 .

Referring to FIG. 17 , a memory system 2000 includes a semiconductor memory device 2100 and a controller 2200 . The semiconductor memory device 2100 includes a plurality of semiconductor memory chips. The plurality of semiconductor memory chips are divided into a plurality of groups.

In FIG. 17 , the plurality of groups are illustrated to communicate with the controller 2200 through first to kth channels CH1 to CHk, respectively. Each semiconductor memory chip is configured and operated similarly to the semiconductor memory device 1000 described with reference to FIG. 2 .

Each group is configured to communicate with the controller 2200 through one common channel. The controller 2200 may be configured similarly to the controller 1200 described with reference to FIG. 16 , and may be configured to control a plurality of memory chips of the semiconductor memory device 2100 through a plurality of channels CH1 to CHk. . In FIG. 17 , it has been described that a plurality of semiconductor memory chips are connected to one channel. However, it will be understood that the memory system 2000 may be modified such that one semiconductor memory chip is connected to one channel.

The controller 2200 and the semiconductor memory device 2100 may be integrated into one semiconductor device. In an embodiment, the controller 2200 and the semiconductor memory device 2100 may be integrated into one semiconductor device to constitute a memory card. For example, the controller 2200 and the semiconductor memory device 2100 are integrated into one semiconductor device, such as a personal computer memory card international association (PCMCIA), a compact flash card (CF), and a smart media card (SM, SMC). ), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), universal flash storage (UFS), etc.

The controller 2200 and the semiconductor memory device 2100 may be integrated into one semiconductor device to constitute a solid state drive (SSD). When the memory system is used as a semiconductor drive (SSD), the operating speed of the host connected to the memory system 2000 is remarkably improved.

As another example, the memory system 2000 may be a computer, an Ultra Mobile PC (UMPC), a workstation, a net-book, a Personal Digital Assistants (PDA), a portable computer, a web tablet, a wireless A wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box ), digital camera, 3-dimensional television, digital audio recorder, digital audio player, digital picture recorder, digital image player ( digital picture player, digital video recorder, digital video player, device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, composing a computer network It is provided as one of various components of the electronic device, such as one of various electronic devices constituting a telematics network, one of various electronic devices constituting a telematics network, an RFID device, or one of various components constituting a computing system.

As an exemplary embodiment, the semiconductor memory device 2100 or the memory system 2000 may be mounted in various types of packages. For example, the semiconductor memory device 2100 or the memory system 2000 may include Package on Package (PoP), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), and Plastic Dual In Line. Package(PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board(COB), Ceramic Dual In Line Package(CERDIP), Plastic Metric Quad Flat Pack(MQFP), Thin Quad Flatpack(TQFP), Small Outline integrated circuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP) , Wafer-Level Processed Stack Package (WSP), etc. may be packaged and mounted.

18 is a block diagram illustrating a computing system including the memory system described with reference to FIG. 17 .

Referring to FIG. 18 , the computing system 3000 includes a central processing unit 3100 , a RAM 3200 , a random access memory, a user interface 3300 , a power supply 3400 , a system bus 3500 , and a memory system. (2000).

The memory system 2000 is electrically connected to the central processing unit 3100 , the RAM 3200 , the user interface 3300 , and the power supply 3400 through the system bus 3500 . Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000 .

In FIG. 18 , the semiconductor memory device 2100 is illustrated as being connected to the system bus 3500 through the controller 2200 . However, the semiconductor memory device 2100 may be configured to be directly connected to the system bus 3500 . In this case, the functions of the controller 2200 may be performed by the central processing unit 3100 and the RAM 3200 .

In FIG. 18 , the memory system 2000 described with reference to FIG. 17 is shown to be provided. However, the memory system 2000 may be replaced with the memory system described with reference to FIG. 16 . As an embodiment, the computing system 3000 may be configured to include all of the memory systems described with reference to FIGS. 16 and 17 .

As described above, although the present invention has been described with reference to limited embodiments and drawings, the present invention is not limited to the above embodiments, and various modifications and variations from these descriptions can be made by those skilled in the art to which the present invention pertains. This is possible.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined by the following claims as well as the claims and equivalents.

In the above-described embodiments, all steps may be selectively performed or omitted. In addition, the steps in each embodiment do not necessarily occur in order, and may be reversed. On the other hand, the embodiments of the present specification disclosed in the present specification and drawings are merely presented as specific examples to easily explain the technical contents of the present specification and help the understanding of the present specification, and are not intended to limit the scope of the present specification. That is, it will be apparent to those of ordinary skill in the art to which this specification belongs that other modified examples may be implemented based on the technical spirit of the present specification.

On the other hand, in the present specification and drawings, preferred embodiments of the present invention have been disclosed, and although specific terms are used, these are only used in a general sense to easily explain the technical content of the present invention and help the understanding of the present invention, It is not intended to limit the scope of the invention. It will be apparent to those of ordinary skill in the art to which the present invention pertains that other modifications based on the technical spirit of the present invention can be implemented in addition to the embodiments disclosed herein.

50: controller
100: memory cell array
1000: semiconductor memory device

Claims (29)

A method of operating a semiconductor memory device including at least two memory blocks sharing one block word line, the method comprising:
applying an erase voltage to a source line commonly connected to the at least two memory blocks; and
applying a first voltage to the one block word line and a third voltage to a global word line of an unselected memory block among the at least two memory blocks when the erase voltage is applied to the source line; but,
The first voltage has a higher level than a turn-on voltage for turning on the pass transistor connected to the block word line;
The third voltage is a voltage for floating a local word line included in the unselected memory block according to a level of the first voltage. The method of claim 1,
When the reference time elapses, a second voltage of a level lower than the first voltage is applied to the block word line, and a local word line included in the unselected memory block is floated on the global word line according to the second voltage. The method of operating a semiconductor memory device further comprising a; The method of claim 2, wherein the second voltage is
A method of operating a semiconductor memory device that is a voltage that turns on a pass transistor connected to the block word line. The method of claim 2, wherein the first voltage is
A method of operating a semiconductor memory device having a level higher than the second voltage by a preset value. The method of claim 2, wherein the fourth voltage is
A method of operating a semiconductor memory device having a level lower than the third voltage. The method of claim 4, wherein the fourth voltage is
The method of operating a semiconductor memory device having a level lower than the third voltage by the preset value. The method of claim 1,
and applying the third voltage to the source select line and the drain select line of the unselected memory block while the third voltage is applied to the global word line of the unselected memory block. Way. at least two memory blocks sharing one block word line; and
a peripheral circuit for performing an erase operation on a selected one of the at least two memory blocks; and
When an erase voltage is applied to a source line commonly connected to the at least two memory blocks, a first voltage is applied to the one block word line and a first voltage is applied to a global word line of an unselected memory block among the at least two memory blocks. 3 A control circuit for controlling the peripheral circuit to apply a voltage; including,
The first voltage has a higher level than a turn-on voltage for turning on the pass transistor connected to the block word line;
The third voltage is a voltage for floating a local word line included in the unselected memory block according to a level of the first voltage. The method of claim 8, wherein the control circuit comprises:
When the reference time elapses, a second voltage of a level lower than the first voltage is applied to the block word line, and a local word line included in the unselected memory block is floated on the global word line according to the second voltage. A semiconductor memory device for controlling the peripheral circuit to apply a fourth voltage to The method of claim 9, wherein the second voltage is
A semiconductor memory device that is a voltage that turns on a pass transistor connected to the block word line. The method of claim 9, wherein the first voltage is
A semiconductor memory device having a level higher than the second voltage by a preset value. The method of claim 9, wherein the fourth voltage is
A semiconductor memory device having a level lower than the third voltage. The method of claim 11, wherein the fourth voltage is
A semiconductor memory device having a level lower than the third voltage by the preset value. The method of claim 8, wherein the control circuit comprises:
and controlling the peripheral circuit to apply the third voltage to the source select line and the drain select line of the unselected memory block while the third voltage is applied to the global word line of the unselected memory block. at least two memory blocks corresponding to one block decoder; and
an address decoder including a plurality of the block decoders;
The address decoder is
When an erase voltage is applied to a source line commonly connected to the at least two memory blocks, a first voltage is applied to a block word line, which is an output line of the one block decoder, and an unselected memory block from among the at least two memory blocks. applying a third voltage to the global word line of
The first voltage has a higher level than a turn-on voltage for turning on the pass transistor connected to the block word line;
The third voltage is a voltage for floating a local word line included in the unselected memory block according to a level of the first voltage. The method of claim 15, wherein the address decoder comprises:
a block decoder for outputting block selection signals according to an input address;
A semiconductor memory device comprising: a pass unit connecting global word lines and local word lines of the at least two memory blocks, respectively. The method of claim 15, wherein the address decoder comprises:
When the reference time elapses, a second voltage of a level lower than the first voltage is applied to the block word line, and a local word line included in the unselected memory block is floated on the global word line according to the second voltage. A semiconductor memory device to which a fourth voltage is applied. The method of claim 17, wherein the second voltage is
A semiconductor memory device that is a voltage that turns on a pass transistor connected to the block word line. The method of claim 17, wherein the first voltage is
A semiconductor memory device having a level higher than the second voltage by a preset value. The method of claim 19, wherein the fourth voltage is
A semiconductor memory device having a level lower than the third voltage by the preset value. a memory cell array comprising at least two memory blocks sharing one block word line and a transfer block connected to the at least two memory blocks through bit lines;
a peripheral circuit for performing an erase operation on a selected one of the at least two memory blocks; and
When an erase voltage is applied to a source line commonly connected to the at least two memory blocks, a first positive voltage is applied to the one block word line and a block word line corresponding to the transfer block, and the at least two memory blocks a control circuit for controlling the peripheral circuit to apply a second positive voltage having a higher level than the first positive voltage to the global word line of the non-selected memory block;
The first positive voltage is a voltage that turns on pass transistors respectively connected to the one block word line and a block word line corresponding to the transfer block. The method of claim 21, wherein the control circuit comprises:
A semiconductor memory device for applying a ground voltage to a block word line corresponding to the transfer block when a reference time elapses. The method of claim 21, wherein the forwarding block comprises:
A semiconductor memory device that is a memory block other than main blocks among a plurality of memory blocks included in the memory cell array. The method of claim 21, wherein the forwarding block comprises:
A semiconductor memory device which is a memory block for storing system information among a plurality of memory blocks included in the memory cell array. The method of claim 21, wherein the forwarding block comprises:
A semiconductor memory device which is a repair block among a plurality of memory blocks included in the memory cell array. a memory cell array including at least two memory blocks sharing one block word line;
a transfer circuit connected to the at least two memory blocks through bit lines;
a peripheral circuit for performing an erase operation on a selected one of the at least two memory blocks; and
When an erase voltage is applied to a source line commonly connected to the at least two memory blocks, a first positive voltage is applied to the one block word line and a block word line corresponding to the transfer circuit, and a first positive voltage is applied to the at least two memory blocks. to apply a second positive voltage having a higher level than the first positive voltage to the global word line of the non-selected memory block and a turn-on voltage for turning on the switch transistors to gate electrodes of the switch transistors included in the transfer circuit A control circuit for controlling the circuit; including,
The first positive voltage is a voltage that turns on pass transistors respectively connected to the one block word line and a block word line corresponding to the transfer circuit. 27. The method of claim 26, wherein the switch transistors,
A semiconductor memory device in which first electrodes are respectively connected to the bit lines, and second electrodes are connected to the source line. 27. The method of claim 26, wherein the switch transistors,
A semiconductor memory device in which first electrodes are respectively connected to the bit lines, and a precharge voltage is applied to the second electrodes. 29. The method of claim 28, wherein the pre-charge voltage is
A semiconductor memory device having a level equal to or higher than the erase voltage.

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