KR102461460B1 - Nonvolatile memory module, computing system having the same, and pvt compensation method thereof - Google Patents

Abstract

A non-volatile memory module according to the present invention includes a plurality of non-volatile memories and a non-volatile memory module controller for controlling the plurality of non-volatile memories, wherein the non-volatile memory module controller includes a RAM for inputting and outputting data, a command and a command parser for inputting and recognizing , and a PVT compensation unit for performing a process, voltage, temperature (PVT) compensation operation in response to a refresh command or a precharge command recognized by the command parser.

Description

NONVOLATILE MEMORY MODULE, COMPUTING SYSTEM HAVING THE SAME, AND PVT COMPENSATION METHOD THEREOF

The present invention relates to a non-volatile memory module, a computing system including the same, and a PVT (process, voltage, temperature) compensation method thereof.

Research on nonvolatile memory compatible with various interfaces of currently used computing systems is being conducted. That is, attempts have been made to use a flash memory as a data storage device or a working memory by mounting the flash memory in the same slot or channel as the main memory (or working memory). In this case, compatibility with a conventionally used volatile RAM (eg, DRAM) should be considered. There is a need for a technology capable of providing the best data integrity and low power characteristics while maintaining compatibility with volatile RAM.

An object of the present invention is to provide a non-volatile memory module with improved performance, a computing system including the same, and a PVT compensation method thereof.

A non-volatile memory module according to an embodiment of the present invention includes a plurality of non-volatile memories and a non-volatile memory module controller for controlling the plurality of non-volatile memories, wherein the non-volatile memory module controller is configured to input/output data and a RAM, a command parser for inputting and recognizing a command, and a PVT compensation unit for performing a PVT (process, voltage, temperature) compensation operation in response to a refresh command or a precharge command recognized by the command parser.

In an embodiment, the RAM includes: a write data area for storing data to be written to the plurality of non-volatile memories; a command area for receiving a non-volatile memory command for controlling the plurality of non-volatile memories; a state area for storing information indicating the state of the RAM; and a read data area storing data read from the plurality of non-volatile memories.

In an embodiment, the RAM is a dualport static random access memory (SRAM).

In an embodiment, the device further comprises a buffer memory temporarily storing input/output data of the plurality of non-volatile memories, wherein the non-volatile memory module controller further includes a memory controller for controlling the buffer memory and the plurality of non-volatile memories and, data input/output between the RAM and the memory controller is in the form of a packet.

In an embodiment, the non-volatile memory module communicates with the outside through a double data rate (DDR) interface, and the RAM and the memory controller communicate with the outside through an advance extensible interface (AXI) interface.

In an embodiment, the PVT compensation unit includes: a host interface layer firmware that outputs at least one control signal for performing a PVT compensation operation in response to the refresh command or the precharge command; and a core for driving the host interface layer firmware.

In an embodiment, the display device further includes a buffer driver connected to at least one of a data pad, a data strobe signal pad, and a ZQ pad, wherein the PVT compensation unit is configured to change the slope of the buffer driver in response to the refresh command or the precharge command. Adjust the intensity.

In an embodiment, a clock buffer for receiving a clock input and generating an internal clock; and a duty cycle correction unit for controlling a duty cycle of the clock buffer, wherein the PVT compensation unit adjusts the duty cycle correction unit in response to the refresh command or the precharge command.

In an embodiment, the PVT compensation unit determines the delay of the data signal or the data strobe signal by adjusting delay tap delay cells in response to the refresh command or the precharge command.

In an embodiment, data buffers for buffering the data of the RAM and inputting and outputting the data to the outside are further included.

In an embodiment, the PVT compensation unit performs a PVT compensation operation on each of the data buffers in response to the refresh command or the precharge command.

In an embodiment, the data buffers include first data buffers connected to the non-volatile memory module controller by at least one first control line and the non-volatile memory module controller by at least one second control line. and second data buffers coupled to

A computing system according to an embodiment of the present invention includes a processor, at least one dual in-line memory module connected to the processor through a first double date rate (DDR) slot, and connected to the processor through a second DDR slot and at least one nonvolatile memory module configured to be used, wherein the at least one nonvolatile memory module performs a process, voltage, temperature (PVT) compensation operation in response to a refresh command or a precharge command input from the processor.

In an embodiment, the at least one non-volatile memory module includes: at least one buffer memory; a plurality of non-volatile memories; and a non-volatile memory module controller for controlling the at least one buffer memory and the plurality of non-volatile memories, wherein the non-volatile memory module controller inputs/outputs data through the processor and a DDR interface, and performs the PVT compensation operation the physical layer to perform; and a memory controller for inputting and outputting data of the physical layer through a memory interface.

In an embodiment, the at least one non-volatile memory module includes: at least one buffer memory; a plurality of non-volatile memories; and a non-volatile memory module controller for controlling the at least one buffer memory and the plurality of non-volatile memories, wherein the non-volatile memory module controller inputs/outputs data through the processor and a DDR interface, and performs the PVT compensation operation the physical layer to perform; data buffers for buffering data input from the processor, transmitting the buffered data to the physical layer, buffering data read from the physical layer, and outputting the buffered read data to the processor; and a memory controller for inputting and outputting data of the physical layer through a memory interface.

In an embodiment, the at least one non-volatile memory module includes: at least one buffer memory; a plurality of volatile memories for inputting and outputting data through the processor and the DDR interface; a plurality of non-volatile memories; and a non-volatile memory module controller for controlling the at least one buffer memory and the plurality of non-volatile memories, wherein the non-volatile memory module controller inputs/outputs data through the processor and the DDR interface, and compensates the PVT a physical layer that performs operations; and a memory controller for inputting and outputting data of the physical layer through a memory interface.

In an embodiment, the processor and the at least one dual in-line memory module communicate via a double data rate 4 (DDR4) interface, and the processor and the at least one non-volatile memory module communicate via the DDR4 interface. do.

A process, voltage, temperature (PVT) compensation method of a nonvolatile memory module according to an embodiment of the present invention includes receiving a refresh command or a precharge command and performing a PVT compensation operation in response to the refresh command or the prague command. comprising the steps of performing

In an embodiment, the PVT compensation operation is performed by internally adjusting input/output control signals.

The non-volatile memory module according to an embodiment of the present invention may improve overall performance by performing an effective PVT compensation operation when a refresh/precharge command required only for a DRAM-based memory module is input.

1 is a block diagram illustrating a computing system according to an embodiment of the present invention.
2 is a diagram exemplarily illustrating a data communication method between a host and an NMM according to the present invention.
3 is a diagram exemplarily showing pointers of a RAM according to an embodiment of the present invention.
4 is a diagram exemplarily showing a firmware structure of an NMM according to an embodiment of the present invention.
5 is a diagram illustrating a firmware operation of an NMM for conceptually explaining the present invention.
6 is a view showing a PVT compensation method according to the first embodiment of the present invention.
7 is a diagram illustrating a PVT compensation method according to a second embodiment of the present invention.
8 is a diagram illustrating a PVT compensation method according to a third embodiment of the present invention.
9 is a block diagram illustrating a computing system according to another embodiment of the present invention.
10 is a diagram illustrating a PVT compensation method according to a fourth embodiment of the present invention.
11 is a flowchart exemplarily illustrating a PVT compensation method of an NMM according to an embodiment of the present invention.
12 is a block diagram exemplarily showing a computing system to which a non-volatile memory module according to the present invention is applied.
13 is a block diagram exemplarily showing any one of the nonvolatile memory modules of FIG. 12 .
14 is a block diagram exemplarily showing any one of the nonvolatile memory modules of FIG. 12 .
15 is a block diagram illustrating another example of a computing system to which a non-volatile memory module according to the present invention is applied.
16 is a block diagram exemplarily illustrating a first embodiment of the nonvolatile memory module of FIG. 15 .
17 is a block diagram exemplarily illustrating a second embodiment of the nonvolatile memory module of FIG. 15 .
18 is a block diagram exemplarily illustrating a third embodiment of the nonvolatile memory module of FIG. 15 .
19 is a diagram exemplarily illustrating a server system to which a nonvolatile memory system according to an embodiment of the present invention is applied.
20 is a view exemplarily showing a FlashDIMM according to an embodiment of the present invention.

Hereinafter, the content of the present invention will be described clearly and in detail to the extent that a person skilled in the art can easily implement it using the drawings.

Since the present invention can have various changes and can have various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention. Terms such as first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms.

The above terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. When an element is referred to as being “connected” or “connected” to another element, it is understood that it may be directly connected or connected to the other element, but other elements may exist in between. it should be On the other hand, when it is said that a certain element is "directly connected" or "directly connected" to another element, it should be understood that the other element does not exist in the middle.

Other expressions describing the relationship between elements, such as "between" and "immediately between" or "neighboring to" and "directly adjacent to", should be interpreted similarly. The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise.

In the present application, terms such as "comprise" or "have" are intended to designate the existence of an embodied feature, number, step, operation, component, part, or combination thereof, but one or more other features or numbers , it should be understood that it does not preclude the possibility of the existence or addition of steps, operations, components, parts, or combinations thereof. Unless defined otherwise, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with the context of the related art, and unless explicitly defined in the present application, they are not to be interpreted in an ideal or excessively formal meaning. .

1 is a block diagram illustrating a computing system according to an embodiment of the present invention. Referring to FIG. 1 , a computing system 10 according to an embodiment of the present invention includes a host 100 and a nonvolatile memory module (NMM) 200 .

In an embodiment, the computing system 10 is a computer, a portable computer, an ultra mobile PC (UMPC), a workstation, a data server, a netbook, a PDA, a web tablet, a wireless phone, a mobile phone, and a smart phone. Receiving and transmitting information from phones, e-books, portable multimedia players (PMPs), digital cameras, digital audio recorders/players, digital cameras/video recorders/players, portable game machines, navigation systems, block boxes, 3D televisions, and wireless environments device, any one of various electronic devices constituting a home network, any one of various electronic devices constituting a computer network, any one of various electronic devices constituting a telematics network, RFID, or a computing system. Any one of various electronic devices may be used.

The host 100 may perform an access operation such as a write request or a read request to the nonvolatile memory module 200 based on the NMM driver 110 . In an embodiment, the NMM driver 110 may be implemented to access the NMM 220 through a DRAM-based double data rate (DDR) interface. The NMM driver 110 may be implemented in hardware/software/firmware. The host 100 may access the physical layer NMMPHY 212 provided in the non-volatile memory module controller NMM CNTL 210 to write data to or read data from the NMM 200 .

For example, the host 100 may be at least one processor, a central processing unit (CPU), a graphic processing unit (GPU), or the like.

The nonvolatile memory module 200 may include a nonvolatile memory module controller NMM CNTL 210 , at least one buffer memory 220 , and a plurality of nonvolatile memories NVM 230 .

The NNM CNTL 210 is a physical layer 212 for lower-level interfacing with the host 100 , and a memory controller that performs data communication between the physical layer 212 and the buffer memory 220 or the non-volatile memory 230 . (MEM CNTL, 214).

The physical layer 212 may include a RAM (RAM) 212-1, a RAM controller (RAM CNTL, 212-2), and a process, voltage, temperature (PVT) compensation unit 212-4. In an embodiment, the physical layer 212 may include all or part of a dual in-line memory module (DIMM) physical layer.

The RAM 212-1 exchanges data with the host 100 using the data DQ and the data strobe signal DQS according to the DDR interface, or the buffer memory 220 and/or the nonvolatile memory 220 according to the memory interface. It may be implemented to exchange data in the form of packets with the memories NVM 230 . In an embodiment, the RAM 212-1 may be implemented as a volatile/nonvolatile memory device capable of high-speed random access. For example, the RAM 212-1 may be a dual port static random access memory (SRAM). In an embodiment, the memory interface (MEM interface) is implemented by a system on chip (SoC) dedicated interface such as AXI (Advanced eXtensible Interface, AXI3, AXI4, etc.), AMBA (Advanced Microcontroller Bus Architecture), OCP (open core protocol), etc. can be

In an embodiment, specific areas of the RAM 212-1 may be accessed from/to the host and the nonvolatile memory 230 or the buffer memory 220 in order to write or read data to or from the NNM 200 .

According to the interfacing protocol defined in the physical layer 212 of the host 100 and the NMM 200 , the host 100 transmits data in a basic transmission unit when writing data to the RAM 212-1. That is, during one write operation, the host 100 writes data of a basic transmission unit (eg, 512 bytes) to the RAM 212-1 of the NMM 200 . In this case, even when data of a relatively small size (eg, 16 bytes) is written, 16 bytes of substantially meaningful data and 496 bytes of invalid dummy data may be written into the RAM 212-1. .

The RAM controller 212-2 may receive a RAM command CMD, a RAM address ADDR, a clock CLK, etc. from the host 100 and control the RAM 212-1 based on these inputs. . The RAM controller 212-2 includes a command parser 212-3 that receives and interprets the RAM command CMD. In an embodiment, the RAM command CMD may include a command for a normal DIMM.

The PVT compensation unit 212-4 performs a PVT compensation operation in the physical layer 212 in response to the refresh command REF/precharge command PRE interpreted from the command parser 212-3. can be done The present invention will not necessarily be limited thereto. The PVT compensation unit 212 - 4 may perform a PVT compensation operation for any device in the NMM 200 .

In an embodiment, the PVT compensation operation may include a PVT change detection operation. A PVT compensation operation may be performed in response to the detected PVT change information. In another embodiment, the PVT compensation operation may be performed based on previously stored PVT change information. In an embodiment, the PVT compensation unit 212-4 may be implemented in hardware/software/firmware. The PVT compensation unit 212 - 4 may include a separate core for performing a PVT compensation operation.

The at least one buffer memory 220 may store data for managing/controlling the non-volatile memories 230 or temporarily store data related to data input/output to/from the non-volatile memories 230 . In an embodiment, the buffer memory 220 may include a random access memory such as DRAM, SRAM, PRAM, MRAM, RRAM, FeRAM, or the like.

The plurality of non-volatile memories NVM 230 may store data requested from the host 100 . Non-volatile memory (NVM) includes NAND Flash Memory, Vertical NAND (VNAND), NOR Flash Memory, Resistive Random Access Memory (RRAM), and Phase Change. Memory (Phase-Change Memory: PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin Transfer Torque Random Access Memory (STT-RAM) etc. can be Also, the nonvolatile memory device may be implemented as a three-dimensional array structure. In an embodiment of the present invention, a three-dimensional memory array is monolithically at one or more physical levels of an array of memory cells having an active area disposed over a silicon substrate and circuitry associated with the operation of the memory cells. ) can be formed. The circuitry involved in the operation of the memory cells may be located in or on the substrate. The term monolithic means that the layers of each level of the three-dimensional array are deposited directly over the layers of the lower level of the three-dimensional array.

As an embodiment according to the concept of the present invention, the 3D memory array has vertical directionality and includes vertical NAND strings in which at least one memory cell is positioned on another memory cell. At least one memory cell includes a charge trap layer. Each vertical NAND string may include at least one select transistor positioned over memory cells. The at least one selection transistor may have the same structure as the memory cells, and may be monolithically formed together with the memory cells.

A three-dimensional memory array is composed of a plurality of levels, with word lines or bit lines shared between the levels. A suitable configuration for a three-dimensional memory array, filed by Samsung Electronics, will be described in US 6,791,33, US 8,553,466, US 8,654,587, US 8,559,235, and US 2011/0233648, which are incorporated by reference in this application. The nonvolatile memory device (NVM) of the present invention is applicable not only to a flash memory device in which the charge storage layer includes a conductive floating gate, but also to a charge trap flash (CTF) in which the charge storage layer includes an insulating layer.

The NMM 200 of the present invention performs an effective PVT compensation operation when a command (eg, refresh/precharge command) required only for a DRAM-based memory module or unnecessary for an NVM-based memory module is input, thereby improving overall performance. can devise

2 is a diagram exemplarily illustrating a data communication method between the host 100 and the NMM 200 according to the present invention. Referring to FIG. 2 , the host 100 and the NMM 200 may transmit/receive data through a queuing method.

The NMM driver 110 of the host 100 may include a submission queuing handler 112 and a completion queuing handler 114 . In response to an access request from the NMM 200 of the host 100 , the submission queuing handler 112 sends a necessary non-volatile command (CMD_NVM) related to the operation of the non-volatile memory (NVM) in the NMM 200 to the RAM 212- 1) to the command area CR. When the access request is a write operation, the submission queuing handler 112 transmits data to be written to the write data area WR of the RAM 212-1 and transmits a command for the write request to the command area CR. . When the access request is a read operation, the submission queuing handler 112 transmits a command for the read request to the command area CR of the RAM 212-1. In an embodiment, the submission queuing handler 112 may preferentially check whether there is an empty space in the write data area WR from the state area SR of the RAM 212-1.

The completion queuing handler 114 reads status information indicating whether to process a command from the status area SR of the RAM 212-1, and reads from the read data area RR of the RAM 212-1. Read data according to the request. The completion queuing handler 114 transmits the read state information and/or read data to the upper layer as a result value.

3 is a diagram exemplarily showing pointers of the RAM 212-1 according to an embodiment of the present invention. Referring to FIG. 3 , the pointers of the RAM 212-1 include a head pointer and a tail pointer in each of areas CR, WR, RR, and SR.

The size of each of the regions CR, WR, RR, and SR may be fixed/variable according to the number of configured registers. For example, the size of the command area CR may be 32 bytes, the sizes of the write data area WR and the read data area RR may each be 64 bytes, and the size of the status area SR may be 16 bytes. have.

In an embodiment, when the location indicated by the head pointer and the tail pointer of the area CR/WR/RR/SR are the same, the area CR/WR/RR/SR is empty. may mean In the embodiment, when the value obtained by subtracting 1 from the location indicated by the head pointer of the area CR/WR/RR/SR is the location indicated by the tail pointer, the area CR/WR/RR/SR is full ( full) may mean

The head pointer of the command area CR indicates an area in which a next command to be processed by the NMM controller 210 is stored. The NMM controller 210 may track the head pointer of the command area CR. The head pointer of this command area CR is usable by one register. The tail pointer of the command area CR indicates an area in which a next command submission has been received from the NMM driver 110 . The NMM driver 110 may track the tail pointer of the command area CR.

The head pointer of the write data area WR indicates an area in which next write data to be processed by the NMM controller 210 is stored. The NMM controller 210 may track the head pointer of the write data area WR. The head pointer of the write data area WR can be used as a register. The tail pointer of the write data area WR indicates an area in which a next command submission has been received from the NMM driver 110 . The NMM driver 110 may track the tail pointer of the write data area WR. The tail pointer may be written to the write commit pointer register by the NMM driver 110 .

The head pointer of the read data area RR indicates an area in which the next read data read by the NMM driver 110 is stored. The NMM driver 110 may track the head pointer of the read data area RR. The head pointer of the read data area RR will be written to the register of the NMM controller 210 by the NMM driver 110 . The tail pointer of the read data area RR indicates an area in which next read data to be written by the NMM controller 210 is stored. The NMM controller 210 may internally track the tail pointer of the read data area RR.

The head pointer of the state area SR indicates an area in which the next completion read by the NMM driver 110 is stored. The NMM driver 110 may track the head pointer of the state area SR. The head pointer of the status area SR will be written to the register of the NMM controller 210 by the NMM driver 110 . The tail pointer of the state area SR indicates an area in which the next completion to be written by the NMM controller 210 is stored. The NMM controller 210 may internally track the tail pointer of the state area SR.

4 is a diagram exemplarily showing a firmware architecture of the NMM 200 according to an embodiment of the present invention. Referring to FIG. 4 , in the firmware structure of the NMM 200 , a read path and a write path may be separated.

First, the read path is composed as follows. Hardware corresponding to a host interface layer (HIL), for example, the command parser 212-3 of FIG. 1 , analyzes an input command (write command/read command). When the input command is a read command, information (IPC) corresponding to the read operation is transmitted to a meta-only flash translation layer (FTL). The core B converts a logical address into a physical address according to the information IPC, and transmits it to a flash interface layer (FIL). The core D will access the nonvolatile memory device NVM corresponding to the converted physical address for a read operation.

On the other hand, the write path is configured as follows. Hardware corresponding to the host interface layer (HIL), for example, the command parser 212-3 of FIG. 1 , analyzes an input command (write command/read command). When the input command is a write command, a stream packet corresponding to the write operation is formed, and this stream pattern is transmitted to the stream buffer. In an embodiment, the stream buffer may exchange data with the RAM ( FIGS. 1 and 212-1 ). In an embodiment, the size of the stream packet may be 512 Kbytes.

The core C converts a logical address into a physical address according to the input/output dedicated file translation layer (FTL), and transmits it to the flash interface layer (FIL). The core D may access the nonvolatile memory device NVM corresponding to the converted physical address for a write operation.

Meanwhile, the host interface layer firmware (HIL FW) may decode a transmitted packet (command packet) and perform a corresponding command operation. The host interface layer firmware may be performed on the core (Core A).

5 is a diagram showing the firmware operation of the NMM 200 for conceptually explaining the present invention. Referring to FIG. 5 , the host interface layer hardware, that is, the command parser 213-3 receives a refresh command or a precharge command (REF/PRE) from the host 100 (refer to FIG. 1 ), recognizes it, and the core ( The host interface layer firmware (HIL FW) running in Core A) generates at least one control signal (PVT CMPS) for PVT operation in response to a refresh command or a precharge command (REF/PRE).

6 is a view showing a PVT compensation method according to the first embodiment of the present invention. 1 to 6 , the PVT compensation unit 212-4 responds to the refresh/precharge command REF/PRE to the data pad/data strobe signal pad/ZQ pad (DQ/DQS/ZQ, 201). It is possible to adjust the slew and/or strength of the buffer driver 202 connected to the .

7 is a diagram illustrating a PVT compensation method according to a second embodiment of the present invention. 1 to 5 and 7 , the PVT compensation unit 212-4 controls the duty cycle correction unit 204 coupled to the clock buffer 203 in response to the refresh/precharge command REF/PRE. can do. As a result, the duty of the clock CLK is adjusted, so that an optimal internal clock ICLK may be generated.

8 is a diagram illustrating a PVT compensation method according to a third embodiment of the present invention. 1 to 5 and 8 , the PVT compensation unit 212-4 may adjust the delay of the input/output data/data strobe signal DQ/DQS in response to the refresh/precharge command REF/PRE. have. Here the delay is formed by the direl tap control.

Meanwhile, the NMM 200 illustrated in FIG. 1 directly stores input/output data (DQ/DQS) in the RAM 212-1. However, the present invention will not necessarily be limited thereto. The NMM of the present invention may store input/output data (DQ/DQS) in the RAM via a data buffer buffering it.

9 is a block diagram illustrating a computing system according to another embodiment of the present invention. Referring to FIG. 9 , the computing system 20 according to an embodiment of the present invention includes a host 100 and a non-volatile memory module (NMM, 200a). The nonvolatile memory module 200a further includes data buffers 205 for inputting and outputting input/output data (DQ/DQS) compared to the nonvolatile memory module 200 illustrated in FIG. 1 . The operation of the NMM controller 210a including the NMM physical layer 212a to control the data buffers 205 may be different from that of the NMM controller 210 of FIG. 1 .

10 is a diagram illustrating a PVT compensation method according to a fourth embodiment of the present invention. 1 to 10 , the PVT compensation unit 212 - 4a may perform a PVT compensation operation of each of the data buffers DB1 to DB9 in response to the refresh/precharge command REF/PRE. In an embodiment, the PVT compensation operation includes the first data buffers DB1 to DB5 connected to the first control signal lines CS1 and the second data buffers DB6 connected to the second control signal lines CS2. ~ DB9) can be performed individually.

11 is a flowchart exemplarily illustrating a PVT compensation method of an NMM according to an embodiment of the present invention. 1 to 11 , the PVT compensation method of the NMM 200/200a is as follows. A refresh command or a precharge command is input from the host 100 ( S110 ). When the command parser 212-3 of the NMMs 200 and 200a recognizes the refresh command/precharge command, the host interface layer firmware (HIL FW) of the NMM controller 210/210a performs a PVT compensation operation. do (S120).

The PVT compensation method of the NMM according to an embodiment of the present invention may perform a PVT compensation operation in response to a refresh command or a prage command.

12 is a block diagram exemplarily showing a computing system to which a non-volatile memory module according to the present invention is applied. Referring to FIG. 12 , the computing system 1000 includes a processor 1100 , RAM modules 1200 and 1250 , non-volatile memory modules 1300 and 1305 , a chipset 1400 , a GPU 1500 , and an input/output device ( 1600 ), and a storage device 1700 .

The processor 1100 may control overall operations of the computing system 1000 . The processor 1100 may perform various operations performed by the computing system 1000 .

The RAM modules 1200 and 1250 and the nonvolatile memory modules 1300 and 1305 may be directly connected to the processor 1100 . For example, each of the RAM modules 1200 and 1250 and the nonvolatile memory modules 1300 and 1305 may have the form of a dual in-line memory module (DIMM). Alternatively, each of the RAM modules 1200 and 1250 and the nonvolatile memory modules 1300 and 1305 may be mounted in a DIMM socket directly connected to the processor 1100 to communicate with the processor 1100 . For example, the nonvolatile memory modules 1300 and 1305 may be the nonvolatile memory modules 200 and 200a described with reference to FIGS. 1 to 11 .

The RAM modules 1200 and 1250 and the nonvolatile memory modules 1300 and 1305 may communicate with the processor 1100 through the same interface 1150 . For example, the nonvolatile memory modules 1300 and 1305 and the RAM modules 1200 and 1250 may communicate through the double data rate (DDR) interface 1150 . For example, the processor 1100 may use the RAM modules 1200 and 1250 as an operating memory, a buffer memory, or a cache memory of the computing system 1000 .

The chipset 1400 is electrically connected to the processor 1100 , and may control hardware of the computing system 1000 according to the control of the processor 1100 . For example, the chipset 1400 may be connected to each of the GPU 1500 , the input/output device 1600 , and the storage device 1700 through major buses, and may serve as a bridge for the major buses.

The GPU 1500 may perform a series of arithmetic operations for outputting image data of the computing system 1000 . For example, the GPU 1500 may be mounted in the processor 1100 in the form of a system-on-chip.

The input/output device 1600 includes various devices that input data or commands to the computing system 1000 or output data to the outside. For example, the input/output device 1600 includes user input devices such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, a piezoelectric element, and an LCD ( Liquid Crystal Display), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, and user output devices such as an LED, a speaker, and a motor may be included.

The storage device 1700 may be used as a storage medium of the computing system 1000 . The storage device 1600 may include mass storage media such as a hard disk drive, an SSD, a memory card, and a memory stick.

For example, the non-volatile memory modules 1300 and 1305 may be used by the processor 1100 as a storage medium of the computing system 1000 . The interface 1150 between the nonvolatile memory modules 1300 and 1305 and the processor 1100 may be a higher-speed interface than the interface between the storage device 1700 and the processor 1100 . That is, since the processor 1100 uses the non-volatile memory modules 1300 and 1305 as a storage medium, the performance of the computing system is improved.

13 is a block diagram exemplarily showing any one of the nonvolatile memory modules of FIG. 12 . For example, FIG. 13 shows a nonvolatile memory module 1300 having a load reduced DIMM (LRDIMM) form. Illustratively, the nonvolatile memory module 1300 shown in FIG. 13 has the form of a dual in-line memory module (DIMM) and is mounted in a DIMM socket to communicate with the processor 1100 . can

Referring to FIG. 13 , the nonvolatile memory module 1300 includes a nonvolatile memory module controller 1310 , a buffer memory 1320 , a nonvolatile memory device 1330 , and a serial presence detection chip 1340 (SPD; Serial Presence). detect chip). The nonvolatile memory module controller 1310 may include a RAM 1311 . For example, the non-volatile memory device 1330 may include a plurality of non-volatile memories (NVM). Each of the plurality of nonvolatile memories included in the nonvolatile memory device 1330 may be implemented as a separate chip, a separate package, a separate device, or a separate module. Alternatively, the nonvolatile memory device 1330 may be implemented as one chip or one package.

For example, the nonvolatile memory module controller 1310 , the RAM 1311 , the buffer memory 1320 , and the nonvolatile memory device 1330 include the nonvolatile memory module controller 210 described with reference to FIGS. 1 to 11 . ), the RAM 213 , the buffer memory 220 , and the plurality of nonvolatile memories 230 may operate the same or similarly.

For example, the nonvolatile memory module controller 1310 may transmit/receive a plurality of data signals DQ and a plurality of data strobe signals DQS to and from the processor 1100 , and may receive a RAM command through separate signal lines. (CMD_R), a RAM address (ADDR_R), and a clock (CK) may be received.

The SPD 1340 may be a programmable read-only memory (EEPROM). The SPD 1340 may include initial information or device information of the nonvolatile memory module 1300 . For example, the SPD 1340 may include initial information or device information such as a module type, a module configuration, a storage capacity, a module type, and an execution environment of the nonvolatile memory module 1300 . When the computing system including the non-volatile memory module 1300 is booted, the processor 1100 of the computing system may read the SPD 1340 and recognize the non-volatile memory module 1300 based thereon. The processor 1100 may use the nonvolatile memory module 1300 as a storage medium based on the SPD 1340 .

For example, the SPD 1340 may communicate with the processor 1100 through a side-band communication channel. The processor 1100 may send and receive an additional signal (SBS) with the SPD 1340 through an additional communication channel. Illustratively, the SPD 1340 may communicate with the non-volatile memory module controller 1310 through an additional communication channel. Exemplarily, the additional communication channel may be a channel based on I2C communication. For example, the SPD 1340 , the nonvolatile memory module controller 1310 , and the processor 1100 may communicate with each other or exchange information based on I2C communication.

14 is a block diagram exemplarily showing any one of the nonvolatile memory modules of FIG. 12 . For example, FIG. 14 is a block diagram of a nonvolatile memory module 2300 having a registered DIMM (RDIMM) form. Illustratively, the nonvolatile memory module 2300 shown in FIG. 14 has the form of a dual in-line memory module (DIMM) and is mounted in a DIMM socket to communicate with the processor 1100 . can

Referring to FIG. 14 , the nonvolatile memory module 2300 includes a nonvolatile memory module controller 2310 , a buffer memory 2320 , a nonvolatile memory device 2330 , and a serial presence detection chip 2340 (SPD; Serial Presence Detect). chip), and a data buffer circuit 2350 . The non-volatile memory module controller 2310 includes a RAM 2311 . Since the nonvolatile memory module controller 2310 , the RAM 2311 , the nonvolatile memory device 2330 , and the SPD 2340 have been described with reference to FIGS. 1 and 22 , a detailed description thereof will be omitted.

The data buffer circuit 2350 receives information or data from the processor 1100 (refer to FIG. 12 ) through the data signal DQ and the data strobe signal DQS, and converts the received information or data to the nonvolatile memory module controller 2350 ) can be passed as Alternatively, the data buffer circuit 2350 receives information or data from the nonvolatile memory module controller 2310 and transmits the received information or data to the processor 1100 through the data signal DQ and the data strobe signal DQS. can

For example, the data buffer circuit 2350 may include a plurality of data buffers. Each of the plurality of data buffers may transmit and receive a data signal DQ and a data strobe signal DQS to and from the processor 1100 . Alternatively, each of the plurality of data buffers may transmit and receive signals to and from the nonvolatile memory module controller 2310 . For example, each of the plurality of data buffers may operate under the control of the nonvolatile memory module controller 2310 .

For example, the nonvolatile memory module controller 2310 may perform a PVT compensation operation according to the operation method described with reference to FIGS. 1 to 11 .

15 is a block diagram illustrating another example of a computing system to which a non-volatile memory module according to the present invention is applied. For concise description, detailed descriptions of the above-described components are omitted. Referring to FIG. 15 , a computing system 3000 includes a processor 3100 , a non-volatile memory module 3200 , a chipset 3400 , a GPU 3500 , an input/output device 3600 , and a storage device 3700 . . Since the processor 3100 , the chipset 3400 , the GPU 3500 , the input/output device 3600 , and the storage device 3700 are substantially the same as those of FIG. 12 , a detailed description thereof will be omitted.

The nonvolatile memory module 3200 may be directly connected to the processor 3100 . For example, the non-volatile memory module 3200 may have the form of a dual in-line memory module (DIMM) and may be mounted in a DIMM socket to communicate with the processor 3100 .

The nonvolatile memory module 3200 may include a control circuit 3210 , a nonvolatile memory device 3220 , and a RAM device 3230 . Unlike the non-volatile memory modules 1300 and 2300 of FIGS. 12 to 14 , the processor 3100 may access the non-volatile memory device 3220 and the RAM device 3230 of the non-volatile memory module 3200, respectively. have. As a more detailed example, the control circuit 3210 may store the received data in the nonvolatile memory device 3220 or the RAM device 3230 according to the control of the processor 3100 . Alternatively, the control circuit 3210 may transmit data stored in the nonvolatile memory device 3220 to the processor 3100 or data stored in the RAM device 3230 to the processor 3100 under the control of the processor 3100 . have. That is, the processor 3100 may recognize the nonvolatile memory device 3220 and the RAM device 3230 included in the nonvolatile memory module 3200 , respectively. The processor 3100 may store data or read stored data in the nonvolatile memory device 3220 of the nonvolatile memory module 3200 . Alternatively, the processor 3100 may store data in the RAM device 3230 or read the stored data.

For example, the processor 3100 may use the nonvolatile memory device 3220 of the nonvolatile memory module 3200 as a storage medium of the computing system 3000 , and the processor 3100 may include the nonvolatile memory module 3200 . of the RAM device 3230 may be used as the main memory of the computing system 3000 . That is, the processor 3100 may selectively access a nonvolatile memory device or a RAM device included in one memory module mounted in one DIMM socket, respectively.

For example, the processor 3100 may communicate with the nonvolatile memory module 3200 through a double data rate (DDR) interface 3300 .

16 is a block diagram exemplarily illustrating the nonvolatile memory module of FIG. 15 . Referring to FIG. 16 , the nonvolatile memory module 3200 includes a control circuit 3210 , a nonvolatile memory device 3220 , and a RAM device 3220 . For example, the nonvolatile memory device 3220 may include a plurality of nonvolatile memories, and the RAM device 3230 may include a plurality of DRAMs. For example, the plurality of non-volatile memories may be used as storage of the computing system 3000 by the processor 3100 . Exemplarily, each of the plurality of non-volatile memories (NVM) may include an electrically erasable and programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a phase-change RAM (PRAM), a resistive RAM (ReRAM), and a ferroelectric RAM (FRAM). ) and non-volatile memory devices such as STT-MRAM (Spin-Torque Magnetic RAM).

The plurality of DRAMs may be used by the processor 3100 as main memory of the computing system 3000 . For example, the RAM device 3230 may include random access memory devices such as DRAM, SRAM, SDRAM, PRAM, ReRAM, FRAM, and MRAM.

The control circuit 3210 includes a non-volatile memory module controller 3211 and an SPD 3212 . The nonvolatile memory module controller 3211 may receive a command CMD, an address ADDR, and a clock CK from the processor 3100 . In response to signals received from the processor 3100 , the nonvolatile memory module controller 3211 converts the data received through the data signal DQ and the data strobe signal DQS to the nonvolatile memory device 3220 or the RAM device. 3230 may optionally be stored. Alternatively, in response to signals received from the processor 3100 , the nonvolatile memory module controller 3211 converts data stored in the nonvolatile memory device 3220 or the RAM device 3230 into a data signal DQ and a data strobe signal ( DQS) may be selectively transmitted to the processor 3100 .

For example, the processor 3100 may selectively access the nonvolatile memory device 3220 or the RAM device 3230 through a command CMD, an address ADDR, or a separate signal or separate information. That is, the processor 3100 may selectively access the nonvolatile memory device 3220 or the RAM device 3230 included in the nonvolatile memory module 3200 .

17 is a block diagram exemplarily illustrating the nonvolatile memory module of FIG. 15 . For example, the nonvolatile memory module 4200 of FIG. 17 may have a dual in-line memory module (DIMM) form, and may be mounted in a DIMM socket to communicate with the processor 3100 .

15 and 17 , the nonvolatile memory module 4200 includes a control circuit 4100 , a nonvolatile memory device 4220 , and a RAM device 4230 . The control circuit 4210 includes a non-volatile memory module controller 4211 , an SPD 4212 , and a data buffer circuit 4213 .

The nonvolatile memory module controller 4211 receives a command CMD, an address ADDR, and a clock CK from the processor 3100 . The nonvolatile memory module controller 4211 may control the nonvolatile memory device 4220 or the RAM device 4230 in response to the received signals. For example, the processor 3100 may selectively access each of the nonvolatile memory device 4220 or the RAM device 4230 . The nonvolatile memory module controller 4231 may control the nonvolatile memory device 4220 or the RAM device 4230 under the control of the processor 4100 .

The data buffer circuit 4213 may receive the data signal DQ and the data strobe signal DQS from the processor 3100 , and provide the received signals to the nonvolatile memory module controller 4211 and the RAM device 4230 . have. Alternatively, the data buffer circuit 4213 may provide the data received from the nonvolatile memory module controller 4211 or the RAM device 4230 to the processor 3100 through the data signal DQ and the data strobe signal DQS. can

For example, when the processor 3100 stores data in the nonvolatile memory device 4220 , data received through the data signal DQ and the data strobe signal DQS is transmitted to the nonvolatile memory module controller 4211 . provided, the nonvolatile memory module controller 4211 may process the received data and provide it to the nonvolatile memory device 4220 . Alternatively, when the processor 3100 reads data stored in the nonvolatile memory device 4220 , the data buffer circuit 4213 converts the data provided from the nonvolatile memory module controller 4211 into a data signal DQ and a data strobe signal. (DQS) may be provided to the processor 3100 . Alternatively, when the processor 3100 stores data in the RAM device 4230 , the data received by the data buffer circuit 4213 is provided to the RAM device 4230 , and the nonvolatile memory module controller 4231 receives the received command. The CMD, the address ADDR, and the clock CK may be transmitted to the RAM device 4230 . Alternatively, when the processor 3100 reads data stored in the RAM device 4230 , the nonvolatile memory module controller 4231 transmits the received command CMD, the address ADDR, and the clock CK to the RAM device 4230 . , the RAM device 4230 provides data to the data buffer circuit 4213 in response to the transmitted signals, and the data buffer circuit 4213 provides a data signal DQ and a data strobe signal DQS. Through this, data may be provided to the processor 3100 . For example, the nonvolatile memory module controller 3211 may improve performance according to the operating method described with reference to FIGS. 1 to 11 .

18 is a block diagram exemplarily illustrating the nonvolatile memory module of FIG. 15 . Referring to FIG. 18 , the nonvolatile memory module 5200 includes a control circuit 5210 , a nonvolatile memory device 5220 , and a RAM device 5230 . The control circuit 5210 includes a non-volatile memory module controller 5211 and an SPD 5212 . The nonvolatile memory module 5200 may operate similarly to the nonvolatile memory module 4200 of FIG. 17 . However, the nonvolatile memory module 5200 does not include the data buffer circuit 4213 unlike the nonvolatile memory module 4200 of FIG. 17 . That is, the nonvolatile memory module 5200 of FIG. 18 transmits data received from the processor 3100 through the data signal DQ and the data strobe signal DQS to the nonvolatile memory module controller 5211 or the RAM device 5230 . can be provided directly. Alternatively, data from the non-volatile memory module controller 5211 of the non-volatile memory module 5200 of FIG. 18 or data from the RAM device 5230 is transmitted through a data signal DQ and a data strobe signal DQS, It may be provided directly to the processor 3100 .

For example, the nonvolatile memory module 4200 of FIG. 17 may be a load redued DIMM (LRDIMM) type memory module, and the nonvolatile memory module 5200 of FIG. 18 may be a registered DIMM (RDIMM) type memory module. .

Exemplarily, the nonvolatile memory module controller 5211 accumulates sub data in a RAM (not shown) according to the operation method described with reference to FIGS. 1 to 18 , and according to a command from the processor 3100 , the nonvolatile memory device ( 5220) can be programmed.

19 is a diagram exemplarily illustrating a server system to which a nonvolatile memory system according to an embodiment of the present invention is applied. Referring to FIG. 19 , the server system 6000 may include a plurality of server racks 6100 . Each of the plurality of server racks 6100 may include a plurality of non-volatile memory modules 6200 . The plurality of non-volatile memory modules 6200 may be directly connected to the processors included in each of the plurality of server racks 6100 . For example, the plurality of non-volatile memory modules 6200 may have the form of a dual in-line memory module and may be mounted in a DIMM socket electrically connected to the processor to communicate with the processor. For example, the plurality of non-volatile memory modules 6200 may be used as storage of the server system 6000 . For example, the plurality of non-volatile memory modules 6200 may perform a PVT compensation operation according to the method described with reference to FIGS. 1 to 11 .

20 is a diagram exemplarily showing a FlashDIMM 6200 according to an embodiment of the present invention. Referring to FIG. 20 , the FlashDIMM 6200 may be externally inserted into a DIMM slot, and may include a plurality of flash memory devices 6211 to 6219 and a FlashDIMM controller 6220 for controlling each of the flash memory devices. . The FlashDIMM controller 6220 may include a command parser 6222 for command parsing and a PVT compensation unit 6224 . When a refresh/precharge command input is instructed by the command parser 6222 , the PVT compensation unit 6224 may perform at least one PVT compensation operation in the FlashDIMM 6200 .

The nonvolatile memory and/or the nonvolatile memory module controller according to the present invention may be mounted using various types of packages. For example, the non-volatile memory and/or the non-volatile memory module controller according to the present invention is a PoP (Package on Package), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package(PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board(COB), Ceramic Dual In-Line Package(CERDIP), Plastic Metric Quad Flat Pack(MQFP), Thin Quad Flatpack(TQFP) ), Small Outline(SOIC), Shrink Small Outline Package(SSOP), Thin Small Outline(TSOP), System In Package(SIP), Multi Chip Package(MCP), Wafer-level Fabricated Package(WFP), Wafer-Level Processed It can be mounted using packages such as Stack Package (WSP).

Meanwhile, it has been described that the nonvolatile memory module of the present invention performs the PVT compensation operation in response to the refresh command/precharge command. However, the present invention will not necessarily be limited thereto. It is understood that the nonvolatile memory module of the present invention may perform various operations (ZQ calibration, leveling, skew adjustment, etc.) for improving the reliability of data/clock in addition to the PVT compensation operation in response to the refresh command/precharge command it should be

On the other hand, the contents of the present invention described above are only specific examples for carrying out the invention. The present invention will include not only concrete and practically usable means, but also technical ideas, which are abstract and conceptual ideas that can be utilized as future technologies.

10: Computing system
100: host
200: non-volatile memory module
210: non-volatile memory module controller
220: buffer memory
230: non-volatile memory
212: physical layer
214: memory controller
212-1: RAM
212-2: RAM controller
212-3: Command Parser
212-4: PVT compensation unit
110: non-volatile memory module driver

Claims (10)

a plurality of non-volatile memories;
a buffer driver coupled to at least one of a data pad, a data strobe signal pad, and a ZQ pad; and
a non-volatile memory module controller for controlling the plurality of non-volatile memories;
The non-volatile memory module controller comprises:
RAM for inputting and outputting data;
a command parser for inputting and recognizing commands; and
a PVT compensation unit configured to perform a process, voltage, temperature (PVT) compensation operation in response to a refresh command or a precharge command recognized by the command parser;
and the PVT compensation unit adjusts the strength of the buffer driver in response to the refresh command or the precharge command. The method of claim 1,
The ram is
a write data area for storing data to be written to the plurality of non-volatile memories;
a command area for receiving a non-volatile memory command for controlling the plurality of non-volatile memories;
a state area for storing information indicating the state of the RAM; and
a read data area for storing data read from the plurality of non-volatile memories;
The RAM is a dual-port (dualport) SRAM (static random access memory) non-volatile memory module. 3. The method of claim 2,
Further comprising a buffer memory for temporarily storing the input/output data of the plurality of non-volatile memories,
The non-volatile memory module controller further comprises a memory controller for controlling the buffer memory and the plurality of non-volatile memories,
Data input/output between the RAM and the memory controller is in the form of a packet,
The non-volatile memory module communicates with the outside through a double data rate (DDR) interface,
The RAM and the memory controller communicate with an advance extensible interface (AXI) interface. The method of claim 1,
The PVT compensation unit may include: a host interface layer firmware that outputs at least one control signal for performing a PVT compensation operation in response to the refresh command or the precharge command; and
and a core for driving the host interface layer firmware. delete The method of claim 1,
a clock buffer that receives a clock and generates an internal clock; and
A duty cycle correction unit for controlling a duty cycle of the clock buffer,
and the PVT compensation unit adjusts the duty cycle correction unit in response to the refresh command or the precharge command. The method of claim 1,
The nonvolatile memory module further comprising data buffers for buffering the data of the RAM and for inputting and outputting the data to the outside. 8. The method of claim 7,
The PVT compensation unit is configured to perform a PVT compensation operation for each of the data buffers in response to the refresh command or the precharge command. processor;
at least one dual in-line memory module coupled to the processor through a first double date rate (DDR) slot; and
at least one non-volatile memory module connected to the processor through a second DDR slot;
The at least one non-volatile memory module comprises:
a buffer driver coupled to at least one of a data pad, a data strobe signal pad, and a ZQ pad, and
A process, voltage, temperature (PVT) compensation operation is performed in response to a refresh command or a precharge command input from the processor,
The performing of the PVT compensation operation includes adjusting the strength of the buffer driver in response to the refresh command or the precharge command. 10. The method of claim 9,
The at least one non-volatile memory module comprises:
at least one buffer memory;
a plurality of non-volatile memories; and
a non-volatile memory module controller controlling the at least one buffer memory and the plurality of non-volatile memories;
The non-volatile memory module controller comprises:
a physical layer for inputting and outputting data through the processor and the DDR interface and performing the PVT compensation operation;
data buffers for buffering data input from the processor, transmitting the buffered data to the physical layer, buffering data read from the physical layer, and outputting the buffered read data to the processor; and
and a memory controller for inputting and outputting data of the physical layer through a memory interface.

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