KR102431688B1 - Array substrate with enhanced thermal resistance and display device having thereof - Google Patents

Abstract

The present invention relates to an array substrate and a display device having a planarization layer in which porous copper particles are dispersed in a binder resin having excellent heat resistance between a touch panel and a display panel. By applying a planarization layer in which porous copper particles having excellent heat resistance are dispersed between the touch panel and the display panel, the planarization layer is not deteriorated even by a high-temperature thin film transistor manufacturing process. In addition, when the planarization layer of the present invention is applied, adhesive properties, crack resistance, and static resistance properties are excellent, so that stable bonding between the display panel and the touch panel is possible, and the driving voltage can be lowered by having a low dielectric constant In addition, it is possible to prevent device failure by rapidly discharging static electricity.

Description

Array substrate with improved heat resistance and display device including same

The present invention relates to an array substrate, and more particularly, to an array substrate for a display device having improved heat resistance by being applied to an in-cell type display device, and a display device including the same.

As smart devices become widespread, touch screen panels are being applied to flat panel displays such as Liquid Crystal Display Device (LCD) or Organic Light Emitting Diode Display Device (OLED display device). A touch screen panel refers to an input device that recognizes a location and transmits it to a system when a user presses or touches the screen with a finger or pen, etc. on the screen.

A touch screen panel consists of a touch panel, a controller IC, and driver software. The touch panel is composed of a substrate on which a transparent electrode is deposited, and the position of signal generation due to contact or electrical capacitance change is identified and transmitted to the controller IC. It converts the coordinates into coordinates that can be expressed in

According to the application method of the touch panel, two substrates coated with a transparent electrode layer such as indium-tin-oxide (ITO) are bonded so that the transparent electrode layer faces each other with a dot space between them. In the resistive touch type, which recognizes the pressure applied to the upper substrate, a transparent electrode is formed by coating conductive metal on both sides of the substrate constituting the touch screen sensor, and a certain amount of current flows to the surface of the substrate. A capacitive touch type that recognizes a part in which the amount of current is changed by understanding the capacitance in the human body through the potential difference between two conductors is typically used. In addition, there are the Surface Acoustic Wave Touch Type, which recognizes the area touched by the user or the pen using sound propagation characteristics, and the Infrared Touch Type, which utilizes the property of blocking infrared rays when they collide with obstacles. has been proposed

On the other hand, according to the stacked-up structure of the touch panel and the display panel, the touch panel is interposed between the outside of the substrate constituting the display panel and the cover glass, and the touch panel is interposed between the display panel and the display panel. It can be divided into an embedded type. The built-in touch panel also includes an on-cell type in which the touch panel is built-in on top of the display panel, and an in-cell type in which the touch panel is mounted inside the display panel (eg, a lower substrate). can be divided into Compared to the external touch panel, the built-in touch panel does not require a separate substrate for the touch sensor, so it is possible to reduce the thickness and weight. In addition, since the built-in type reduces light-reflection on the surface of the touch panel, power consumption required for the display device is also reduced.

1 is a cross-sectional view schematically illustrating a display device to which an in-cell type touch panel is applied. As shown in FIG. 1 , the display device 1 to which the conventional in-cell type touch panel is applied includes a lower substrate 11 , an upper substrate 12 facing the lower substrate 11 , and a lower substrate ( 11 ) and the display panel 20 positioned between the upper substrate 12 and the touch panel 30 positioned between the lower substrate 11 and the display panel 20 .

The display panel 20 includes a thin film transistor (TFT) 22 for driving the display panel 20 . The thin film transistor 22 includes an inorganic insulating film laminated by a silicon material, and the inorganic insulating film is deposited at a high temperature, for example, at a process condition of 350° C. or higher. The touch panel 30 positioned directly on the upper surface of the lower substrate 11 includes a first touch electrode 32 and a second touch electrode 34 made of, for example, a transparent metal such as ITO. Since the touch panel 30 and the display panel 20 cannot be directly attached to each other due to the touch electrodes 32 and 34 , the thin film transistor 22 positioned below the touch panel 30 and the display panel 20 is disposed. A planarization film 36 made of an insulating material is interposed therebetween.

Conventionally, an acrylate-based resin is generally adopted as an insulating material for forming the planarization film 36 positioned between the display panel 20 and the touch panel 30 . However, the acrylate-based resin has good processability, but has poor heat resistance. Accordingly, the planarization film 36 made of the acrylate-based resin is easily deteriorated under high-temperature process conditions for forming the thin film transistor 22 constituting the display panel 20 positioned thereon. As the planarization layer 36 deteriorates, a lifting phenomenon occurs at the interface between the display panel 20 and the touch panel 30 , cracks occur in the planarization layer 36 , and a finally manufactured display device In (1), the problem of yellow mura occurs.

Therefore, there is a need to develop a planarization film that has sufficient heat resistance, so that it does not deteriorate even under high-temperature process conditions, and that suppresses lifting or cracking at the interface between the touch panel and the display panel and has excellent adhesion to the display panel.

The present invention has been proposed to solve the problems of the prior art, and an object of the present invention is to have excellent heat resistance and thus not deteriorate even by a high temperature process for manufacturing a thin film transistor, and a display device including the same is intended to provide

Another object of the present invention is to provide an array substrate for a display device having adhesive properties to a substrate, crack-resistance properties, and scratch-resistance properties, and a display device including the same.

Another object of the present invention is to provide an array substrate for a display device having light transmission characteristics and excellent static discharge characteristics, and a display device including the same.

According to one aspect of the present invention having the above object, the present invention provides an array substrate for a display device having a planarization film in which porous copper particles are dispersed in a binder resin having excellent heat resistance between a touch panel and a thin film transistor constituting the display panel, and A display device including the same is provided.

In an exemplary embodiment, a buffer layer may be further interposed between the planarization layer, the touch panel, and the thin film transistor, respectively.

The porous copper particles may be mesoporous copper particles, for example, mesoporous copper particles impregnated in the inner wall of the porous silicate particles.

According to the present invention, an array substrate for a display device in which a planarization film in which porous copper particles are dispersed in a heat-resistant binder resin is positioned between a touch panel and a thin film transistor or a display panel positioned on an upper portion of the substrate, and a display device including the same .

The planarization film of the present invention has excellent heat resistance and is not deteriorated by a high-temperature process for manufacturing a thin film transistor applied to a display panel.

In particular, by adopting the pore structure, a passage for dispersing heat generated in the array panel to the touch panel is formed. Accordingly, the coefficient of thermal expansion (CTE) of these panels can be lowered, so that the thermal stress applied to these panels can be made similar. Therefore, the planarization film of the present invention has excellent adhesion properties to the substrate even by high-temperature treatment, and has excellent crack resistance and scratch resistance, so that the touch panel and the display panel do not peel off even under external impact or severe process conditions. It can bond well.

Since the light-transmitting characteristic of the planarization film of the present invention is not deteriorated even by the curing process, good luminance can be obtained even in a display device to which the planarization film is applied. In addition, since the planarization film of the present invention can reduce parasitic capacitance by adopting a low-k material, it is possible to reduce power consumption.

In addition, since the planarization layer of the present invention can rapidly attenuate static electricity, deterioration of drivability of the display panel or touch panel due to generation of static electricity can be prevented.

1 is a cross-sectional view schematically illustrating a display device including a touch panel according to the related art.
2 is a schematic cross-sectional view of a planarization film applied between a touch panel and a display panel according to an exemplary embodiment of the present invention.
3A is a diagram schematically illustrating a process for manufacturing MCM-41 used as a template for manufacturing mesoporous copper particles according to an exemplary embodiment of the present invention.
FIG. 3b is a diagram schematically illustrating a process for preparing mesoporous copper particles from MCM-41 used as a template.
4 is a cross-sectional view schematically illustrating a display device to which a high heat-resistant planarization film is applied between a touch panel and a liquid crystal display panel according to an exemplary embodiment of the present invention.
5 is a cross-sectional view schematically illustrating a display device to which a high heat resistance planarization film is applied between a touch panel and a light emitting diode display panel according to an exemplary embodiment of the present invention.
6A to 6F show analysis results of mesoporous copper particles synthesized according to an exemplary embodiment of the present invention, respectively.
Figure 6a is a graph showing the XRD (X-ray diffraction) analysis results for the mesoporous copper particles, Figure 6b is FTIR spectroscopy (Fourier transform ultraviolet spectroscopy, Fourier transform Infrared spectroscopy) for the mesoporous copper particles showing the analysis results It is one graph.
FIG. 6c is a graph showing the results of Brunauer-Emmett-Teller (BET) analysis for mesoporous copper particles, and FIG. 6d is a graph showing the results of NMR spectrum analysis for mesoporous copper particles. In FIG. 6c, A shows the analysis result of copper-impregnated mesoporous particles, and B shows the analysis result of the porous silicate before copper impregnation.
6e and 6f are SEM images and TEM images of mesoporous copper particles, respectively.
7A is a pattern photograph according to an adhesion test of a planarization film in which mesoporous copper particles are dispersed in a polysiloxane resin according to an exemplary embodiment of the present invention.
7B and 7C are pictures of patterns according to an adhesion test of a planarization film composed of only a polyacrylate binder resin in which mesoporous particles are not dispersed and a polysiloxane resin, respectively, as comparative examples.
7D and 7E are pattern photographs according to an adhesion test of a planarization film in which mesoporous aluminum particles and mesoporous chromium particles are dispersed in a polysiloxane resin as a comparative example, respectively.
8A is a photograph analyzing crack characteristics of a planarization film in which mesoporous copper particles are dispersed in a polysiloxane resin according to an exemplary embodiment of the present invention.
8B and 8C are photographs of analyzing crack characteristics of a planarization insulating film composed of only a polyacrylate binder resin in which mesoporous particles are not dispersed and a polysiloxane resin as comparative examples, respectively.
8D and 8E are photographs of analyzing crack characteristics of a planarization insulating film in which mesoporous aluminum particles and mesoporous chromium particles are dispersed in polysiloxane resin as comparative examples, respectively.
9A is a photograph analyzing the peel strength of a planarization insulating film in which mesoporous copper particles are dispersed in a polysiloxane resin according to an exemplary embodiment of the present invention.
9b and 9c are photographs of analysis of peel strength of a planarization insulating film composed of only a polyacrylate binder resin in which mesoporous particles are not dispersed and a polysiloxane resin as comparative examples, respectively.
9D and 9E are photographs of analyzing crack characteristics of a planarization insulating film in which mesoporous aluminum particles and mesoporous chromium particles are dispersed in a polysiloxane resin as a comparative example, respectively.
10A is a photograph analyzing crack characteristics according to stress application of a planarization insulating film in which mesoporous copper particles are dispersed in a polysiloxane resin according to an exemplary embodiment of the present invention.
10b and 10c are photographs of analysis of crack characteristics according to stress application of a planarization insulating film composed of only a polyacrylate binder resin in which mesoporous particles are not dispersed and a polysiloxane resin as a comparative example, respectively.
10D and 10E are photographs analyzing crack characteristics according to stress application of a planarization insulating film in which mesoporous aluminum particles and mesoporous chromium particles are dispersed in a polysiloxane resin as a comparative example, respectively.

According to one aspect of the present invention, the present invention provides a touch panel positioned on a substrate; a thin film transistor spaced apart from the touch panel; and a planarization layer interposed between the touch panel and the thin film transistor, wherein the planarization layer includes porous copper particles dispersed in a binder resin.

It may further include a first buffer layer positioned between the touch panel and the planarization layer, and a second buffer layer positioned between the planarization layer and the thin film transistor.

The porous copper particles may include mesoporous copper particles, and the binder resin may be selected from the group consisting of polysiloxane-based resins, polyimide-based resins, and combinations thereof.

For example, the porous copper particles may be dispersed in the binder resin in an amount of 0.5 to 10 parts by weight to the binder resin, and the porous copper particles are impregnated in the porous silicate particles.

According to another aspect of the present invention, there is provided a first substrate; a touch panel positioned on the first substrate; a display panel spaced apart from the touch panel; and a planarization layer interposed between the touch panel and the display panel, wherein the planarization layer includes porous copper particles dispersed in a binder resin.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings, if necessary.

2 is a planarization film applied between a touch panel (TP, see FIG. 4) and a display panel (DP, see FIG. 4), for example, an array panel (AP, see FIG. 4) according to an exemplary embodiment of the present invention; It is a schematic cross-sectional view. The planarization film 300 includes a planarization layer 310 in which porous copper particles 320 are dispersed in a binder resin 312 , and a first buffer layer 332 positioned below and above the planarization layer 310 , respectively. ) and a second buffer layer 334 .

In one exemplary embodiment, the binder resin 312 constituting the planarization layer 310 may use a binder resin having excellent heat resistance properties. For example, the binder resin 312 may be a polysiloxane-based resin and/or a polyimide-based (PI) resin. Since the polysiloxane-based resin and the polyimide-based resin have basically good heat resistance, they have an advantage that they do not deteriorate even under high-temperature conditions. The planarization layer 310 may be coated and laminated on the touch panel TP (refer to FIG. 4 ) through the first buffer layer 332 .

In order to form the planarization layer 310 composed of the binder resin 312 in which the porous copper particles 320 are dispersed on the first buffer layer 332, a reactive component that can be cured with a binder resin, an organic solvent, and a crosslinking accelerator And after coating the binder composition blended with other additives on the upper portion of the first buffer layer 332, it is cured.

In one exemplary embodiment, in order to obtain a polysiloxane-based resin as the binder resin 312 , a silane monomer or a siloxane monomer having at least one silanol group and/or siloxane group may be used as the thermally reactive component. Heat treatment of these appropriate silane monomers and/or siloxane monomers can form crosslinks between these monomers to obtain a polysiloxane-based resin. Examples of the monomer compound having a silanol group according to the present invention include silanol group-containing monomers obtained by hydrolyzing a silyl group-containing unsaturated monomer such as ethylenically unsaturated alkoxy silanes and ethylenically unsaturated acyloxy silanes. .

Examples of the ethylenically unsaturated alkoxy silane compound include acrylate-based alkoxy silanes such as γ-acryloxypropyl-trimethoxysilane and γ-acryloxypropyl-triethoxysilane, 2) γ-methacryloxypropyl-trime and methacrylate-based alkoxy silanes such as oxysilane, γ-methacryloxypropyl-triethoxysilane, and γ-methacryloxypropyl-tris(2-methoxyethoxy)silane. On the other hand, examples of the ethylenically unsaturated acyloxysilane compound include acrylate-based acetoxysilane, methacrylate-based acetoxysilane, and ethylenically-unsaturated acetoxysilane (eg, acrylatetopropyltriacetoxysilane, methacrylateto propyltriacetoxysilane) and the like.

In addition, examples of the silyl group-containing unsaturated compound that can obtain a monomer having a silanol group through hydrolysis etc. include chlorodimethylvinylsilane, 5-trimethylsilyl-1,3-cyclopentadiene, 3-trimethylsilylallyl alcohol, Trimethylsilyl methacrylate, 1-trimethylsilyloxy-1,3-butadiene, 1-trimethylsilyloxy cyclopentene, 2-trimethylsilyloxyethyl methacrylate, 2-trimethylsilyloxyfuran, 2-trimethylsilyloxypropene , allyloxy-t-butyldimethylsilane and trisalkoxy vinylsilanes such as allyloxytrimethylsilane, trimethoxyvinylsilane, triethoxyvinylsilane, tris(methoxyethoxy)vinylsilane. The above-mentioned monomers having a silanol group may be used alone or in mixture of two or more.

On the other hand, a monomer having a siloxane group can also be used as a reactive component for obtaining a polysiloxane-based resin. As the monomer having a siloxane group, a compound having a linear siloxane group, a compound having a cyclic siloxane group, a compound having a tetrahedral siloxane group, silsesquioxane, and the like can be used.

_{Examples of} the monomer compound having _a linear siloxane group include alkylsiloxane, alkoxysiloxane, alkoxyalkylsiloxane, _{vinylalkoxysiloxane} , N-( 2-Aminoethyl)-3-aminopropylmethyldimethoxysilane, N-(2-aminoethyl)-3-aminopropylmethyltrimethoxysilane, 3-aminopropyltriethoxysilane, 3-glycidoxypropyltri Ethoxysilane, 3-glycidoxypropylmethyldimethoxysilane, 2-(3,4-ethoxy cyclohexyl)ethyltrimethoxysilane, 3-chloropropyl methyldimethoxysilane, 3-chloropropyl trimethoxysilane , 3-methacryloxypropyltrimethoxysilane, 3-mercaptopropyltrimethoxysilane, etc. may be included, and one or a mixture of two or more selected from these may be used, but the present invention is not limited thereto. . For example, having a linear siloxane group containing an alkoxy group, such as TMOS, TEOS, MTMS, vinyltris(2-methoxyethoxy)-silane, N-(2-aminoethyl)-3-aminopropylmethyldimethoxysilane, etc. Monomers can be used individually or in mixture of 2 or more types.

Meanwhile, non-limiting examples of the cyclic siloxane include methylhydro-cyclosiloxane, hexamethyl-cyclotrisiloxane, cyclotrisiloxane such as hexaethyl-cyclotrisiloxane; cyclotetrasiloxanes such as tetraoctyl-cyclotetrasiloxane, hexamethyl-cyclotetrasiloxane, octamethyl-cyclotetrasiloxane; tetra- and penta-methylcyclotetrasiloxanes; tetra-, penta-, hexa- and hepta-methylcyclopentasiloxanes; tetra-, penta- and hexamethyl-cyclohexasiloxane, tetraethyl-cyclotetrasiloxane, and tetraphenyl cyclotetrasiloxane; Decamethyl-cyclopentasiloxane, dodecamethyl cyclosiloxane, 1,3,5,7-tetramethyl-cyclotetrasiloxane, 1,3,5,7,9-pentamethyl-cyclopentasiloxane, and 1,3, One or a mixture of two or more selected from 5,7,9,11-hexamethylcyclohexasiloxane may be particularly used, but the present invention is not limited thereto.

Further, non-limiting examples of the monomer having a tetrahedral siloxane group include tetrakisdimethylsiloxysilane, tetrakisdiphenylsiloxysilane and tetrakisdiethylsiloxysilane, and mixtures thereof.

In addition, in addition to linear, cyclic and tetrahedral siloxanes, for example, silsesquioxane (SSQ), which can be synthesized by the reaction of methyltrichlorosiloxane and dimethylchlorosiloxane, can also be used as a reactive material for synthesizing polysiloxane. can Silsesquioxane can be synthesized as polysilsesquioxane having a ladder structure or a cage structure by crosslinking. For example, by hydrolysis of organotrichlorosilane, a partially cage-structured heptamer-type siloxane and a cage-structured heptamer-type and octamer-type siloxane are obtained. A silsesquioxane monomer can be obtained by isolating the siloxane in the form, and by condensing it with an organotrialkoxysilane or organotrichlorosilane. Silsesquioxane may have a chemical structure of approximately RSiO _3/2 (R is hydrogen, an alkyl group having 1-10 carbon atoms; alkenyl having 2-10 carbon atoms; an aryl group such as phenyl; an arylene group), but in the present invention The silsesquioxane that can be used is not limited thereto.

Meanwhile, as a reactive material for synthesizing polyimide that can be used as the binder resin 312 , an amine compound and an anhydride may be included. The polyimide may include, for example, aromatic polyimide (PI) and colorless polyimide (CPI). For example, CPI introduces relatively strong electronegative elements such as trifluoromethyl (-CF ₃ ), sulfone (-SO ₂ ), and ether (-O-) into the main chain of PI to prevent the movement of π electrons. A method of reducing the density of π electrons present in the main chain by limiting or introducing a cyclo-olefin structure other than benzene may be used. Polyimide is obtained by adding diamine and dianhydride to an appropriate solvent to synthesize polyamic acid, and reacting the obtained polyamic acid through an appropriate imidization process, for example, thermal imidization process or catalytic/chemical imidization process. can be obtained

As the transparent dianhydride and transparent diamine for preparing the transparent polyimide (CPI), the following transparent dianhydride and transparent diamine may be used.

Transparent dianhydride is 4,4'-(hexafluoroisopropylidene)diphthalic anhydride (6FDA), 1,2,4,5-cyclobutanetetracarboxylic dianhydride ( 1,2,4,5-cyclobutane tetracarboxylic dianhydride, CBDA), 1,2,4,5-cyclohexane tetracarboxylic dianhydride (CHDA), 4,4'- Oxydiphthalic anhydride (4,4'-oxydiphthalic anhydride, ODPA), 3,3',4,4'-diphenylsulfone tetracarboxylic dianhydride (3,3',4,4'-diphenylsulfone tetracarboxylic dianhydride, DSDA) , 3,3',4,4'-benzophenonetetracarboxylic dianhydride (3,3',4,4'-benzophenone tetracarboxylic dianhydride, BPDA or BTDA), 2,2-Bis[4-(3,4- dicarboxyphenoxy)phenol]]propane dianhydride (2,2-Bis[4-(3,4-dicarboxyphenoxy)phenyl]propane dianhydride, BPADA) and combinations thereof, but in the present invention This is not limited thereto.

On the other hand, transparent diamine is 4,4'-oxydianiline (4,4'-oxydianiline, ODA), 2,2-Bis[4-(4-aminophenoxy)phenyl]propane (2,2-Bis[4) -(4-aminophenoxy)phenyl]propane, BAPP), 2,2'-bis(trifluoromethyl)-4,4'-biphenyldiamine (2,2'-Bis(trifluoromethyl)-4,4'- biphenyldiamine, TFMB or TFB), 4,4'-Bis(4-aminophenoxy)biphenyl (4,4'-Bis(4-aminophenoxy)biphenyl, BAPB), cyclohexyl diamine (CHDAM), Aminobenzene cyanide (DABN), 2,2-Bis [4- (4-aminophenoxy) phenyl] hexafluoropropane (2,2-bis [4- (4-aminophenoxy) phenyl] hexafluoropropane, 6FBAPP), bis[4-(4-aminophenoxy)phenyl]sulfone (Bis[4-(4-aminophenoxy)phenyl]sulfone, BAPS), and combinations thereof, However, the present invention is not limited thereto.

The reactive component of the binder resin 312, silanol/siloxane-based monomer, or dianhydride/diamine, is approximately 5 to 40 parts by weight, preferably 10 to 30 parts by weight, in the binder composition for synthesizing the binder resin 312 . can be combined with Unless otherwise stated herein, parts by weight mean a weight ratio between components to be blended.

As the porous copper particles 320 dispersed in the binder resin 312 , any porous particles having a pore structure may be used. For example, the porous copper particles 320 include microporous copper particles, mesoporous copper particles, and macroporous copper particles. As used herein, microporous particles mean porous particles having an average pore diameter of less than 2 nm, mesoporous particles mean porous particles having an average pore diameter of 2 nm or more and less than 50 nm, and macroporous particles are pore average diameter This refers to porous particles of 50 nm or more. In one exemplary embodiment, the porous copper particles are mesoporous particles. The mesoporous copper particles have a pore size sufficient to dissipate heat generated from the array panel (AP, see FIG. 4 ) positioned on the planarization layer 310 of the present invention to the outside, and have a uniform pore size and pore dispersion. Mesoporous particles having the advantage of easy preparation.

To obtain mesoporous copper particles, mesoporous silicate can be used as a template, and mesoporous silicate can be synthesized by various methods. In one exemplary embodiment, the mesoporous copper particles 320 may be synthesized using mesoporous silicate, which is a porous molecular sieve material, as a template. Since the mesoporous silicate of the porous molecular sieve material has a uniform pore size and excellent specific surface area, it may be suitable for use as a template for the porous copper particles 320 of the present invention.

The mesoporous silicate, which can be used as a template for synthesizing the porous copper particles 320, uses a surfactant such as cetyltrimethyl ammonium bromide (CTAB) as a structure directing material (structure directing material) and , including the Mobile Composition of Matter (MCM) series using tetramethyl orthosilicate (TMOS), tetraethyl orthosilicate (TEOS) or sodium methasilicate as a silica-introducing material. . Optionally, a surfactant or a terpolymer in the form of pluronic, for example a non-P123 (poly(ethylene oxide)-poly(propylene oxide)-poly(ethylene) oxide; PEO-PPO-PEO) SBA (Santa Barbara Amorphous) series using a non-ionic triblock copolymer as a structure inducing material and using TMOS, TEOS, etc. as a silica introduction material may be applied as a mesoporous silicate. These mesoporous silicates have various types of structures depending on the silica-introducing component, the type of surfactant, their content, and the charge density at the interface between the surfactant and the silica-introducing component.

For example, in MCM-41, SBA-3, and SBA-15, one-dimensional nanopores are in a regular hexagonal arrangement, and in MCM-48, two types of nanopores are independently three-dimensionally connected to each other. It has a structure (cubic Ia3d). MCM-50 is a layered material, SBA-1 and SBA-6 are a three-dimensionally connected structure with spherical mesopores having a cubic Pm3n lattice structure, and SBA-16 is a three-dimensional pore material having a cubic Im3m lattice structure. . In addition to these, SBA-based materials having a structure in which mesopores are regularly arranged and KIT-1 (Korea Advanced Institute of Science and Technology-1) and MSU-X (Michigan State University-) having a structure in which mesopores are irregularly connected X), HMS (hexagonal mesoporous silica), etc. are known.

For the process of synthesizing the porous copper particles 320 dispersed in the binder resin 312 constituting the planarization layer 310 according to the present invention, a case in which MCM-41 is used as a template will be described as an example. 3A is a diagram schematically illustrating a process for manufacturing MCM-41 used as a template for manufacturing mesoporous copper particles according to an exemplary embodiment of the present invention.

As shown in FIG. 3A , a surfactant 322 such as CTAB is used as a structure inducing material, and a silica-introduced material such as TEOS, TMOS, sodium metasilicate, fumed silica, Ludox (eg Ludox HS40) is acidified. Alternatively, the hydrothermal reaction is carried out in the presence of a catalyst such as a base. In this process, the surfactant 322 is arranged in a micellar structure, and the silicate formed by hydrolysis and condensation of the silica-introduced component around the surfactant 322 arranged in the micellar structure is self-contained. - self-assembly to form supra-molecules. Specifically, an organic-inorganic complex in the form of a solid powder or a film is formed by the interaction between a hydrophilic moiety located on the surface of the surfactant self-arranged in a micellar structure and an inorganic material such as silicate. Subsequently, when the organic-inorganic complex is calcined at a high temperature of 500° C. or higher to remove organic molecules such as the surfactant 322, the mesoporous silicate 324 having the mesopores 326 is hexagonally arranged and MCM-41 have a structure.

Continuing, FIG. 3b is a diagram schematically illustrating a process for preparing mesoporous copper particles from MCM-41 used as a template. A copper precursor, for example, a copper oxide precursor, (CuNO ₃ ) hydrate, CuCOOH hydrate, CuCl hydrate, Cu(II) acetylacetonate, etc. reacting in an appropriate solvent (eg, chloroform, etc.), the copper particles 328 from the copper precursor material are impregnated into the inner wall of the pores 326 of the mesoporous silicate 324, and mesoporous copper particles can be obtained. have. Therefore, according to an exemplary embodiment of the present invention, the porous copper particles 320 (refer to FIG. 2 ) may be impregnated with the porous silicate particles, but the present invention is not limited thereto.

For example, the porous copper particles 320 may be dispersed in the binder resin 312 in an amount of about 0.5 to 10 parts by weight. If the content of the porous copper particles 320 is less than this, it is difficult to expect improvement in physical properties such as improvement in heat resistance. On the other hand, even if the content of the porous copper particles 320 is greater than this, the physical properties do not increase in proportion to the amount added, and light-transmittance may be reduced.

On the other hand, the solvent used in the binder composition is not particularly limited, alcohol solvents such as methanol and ethanol; Tetrahydrofuran, ethylene glycol monomethyl ether, ethylene glycol monoethyl ether, diethylene glycol monomethyl ether, diethylene glycol monoethyl ether, diethylene glycol dimethyl ether, diethylene glycol diethyl ether, diethylene glycol methyl ethyl ether, Ether solvent selected from ethylene glycol dimethyl ether, ethylene glycol diethyl ether, ethylene glycol methyl ethyl ether, propylene glycol monomethyl ether, propylene glycol monoethyl ether, propylene glycol propyl ether, propylene glycol butyl ether, etc.; Ethylene glycol monoethyl ester, methyl lactate, ethyl lactate, methyl acetate, ethyl acetate, propyl acetate, ethyl 2-hydroxypropionate, methyl 2-hydroxy-2-methylpropionate, 2-hydroxy-2-methylpropionate ethyl, an ester solvent selected from at least one selected from methyl hydroxyacetate, ethyl hydroxyacetate, propylene glycol methyl ethyl propionate, and propylene glycol ethyl ether propionate; an acetate-based solvent selected from ethylene glycol monomethyl ether acetate, ethylene glycol monoethyl ether acetate, propylene glycol monomethyl ether acetate, and propylene glycol monoethyl ether acetate; an aromatic hydrocarbon-based solvent selected from toluene, xylene, cresol, and the like; a ketone solvent selected from acetone, methyl ethyl ketone, cyclopentanone, cyclohexanone, 2-heptanone, and 4-hydroxy-4-methyl-2-pentanone; One or more amides selected from N-methylpyrrolidone (NMP), N-methylacetamide, N,N-dimethylacetamide (DMAc), N-methylformamide, and N,N-dimethylformamide (DMF) system solvent; A lactone-based solvent that may be γ-butyrolactone and a combination thereof may be used. These solvents may be blended in the binder composition in an amount of 40 to 100 parts by weight, preferably 50 to 90 parts by weight, and more preferably 60 to 80 parts by weight.

If necessary, the binder composition may further include a functional additive. The functional additive may include a coupling agent, a surfactant, a crosslinking accelerator, and the like. The coupling agent is for improving bonding properties between the binder resin 312 and the substrate, and may be at least one selected from a silane-based coupling agent, an aluminum-based coupling agent, a titanium-based coupling agent, and a zirconium-based coupling agent, and is particularly preferably is a silane coupling agent. These coupling agents are not particularly limited as long as adhesion to the substrate can be improved by surface treatment of the binder resin 312, but may be preferably blended in a ratio of 1 to 10 parts by weight in the binder composition.

In addition, as the surfactant for inducing dispersion of the thermally reactive component, an anionic surfactant, a cationic surfactant, an amphoteric surfactant, and a nonionic surfactant may be used. As anionic surfactants, alkyl sulfonic acids (sulfonates), alkyl sulfuric acids (sulfates), aralkyl and alkaryl anionic surfactants, alkyl succinic acids (succinates), and alkyl sulfosuccinates (sulfosuccinates) can be used. have. In particular, preference is given to sodium, magnesium, ammonium and monoethanolamine, diethanolamine and triethanolamine salts of alkaryl sulfonic acids, alkyl sulfuric acids and alkaryl sulfuric acids. The content of the surfactant may vary depending on the type of solvent used, the content of the reactive component, etc., but the content may be approximately 0.01 to 1.0 parts by weight in the binder composition.

In addition, a crosslinking accelerator for accelerating crosslinking such as silanol/siloxane monomer used as a reactive component may be used in the binder composition. Crosslinking accelerators that can be used include dimethylaniline, 1,1'-methylenebis(3-methylpiperidine) (MBMP), dimethylbenzylamine (DMBA), tris(dimethylaminomethyl)phenol (TDMAMP), hexamethylenetetramine and tertiary amines such as monoethylamine such as 1,6-bis-(dimethylamino)hexane, trimethylamine and octyldimethylamine; N-4-chlorophenyl-N',N'-dimethylurea, N-3-chloro-4-methylphenyl-N',N'-dimethylurea, N-(2-hydroxyphenyl)-N',N' - urea derivatives such as dimethylurea; For example, imidazole, benzimidazole, 1-methylimidazole, 3-methylimidazole, 1,2-dimethylimidazole, 2-ethyl-4-methylimidazole, 1-vinylimidazole , 2-vinylimidazole, 2-phenylimidazole, 2-phenyl-4-methylimidazole, 1-(2,6-dichlorobenzoyl)-2-phenylimidazole and 1-(2,4 substituted or unsubstituted unsubstituted imidazoles such as ,6-trimethylbenzoyl)-2-phenylimidazole; organic phosphines such as triphenylphosphine; One type or a mixture of two or more types selected from silsesquioxanes and the like can be used.

In particular, the siloxane-based reactive component has a risk of lowering heat resistance as a crosslinking accelerator is added. Therefore, it may be preferable to use a crosslinking accelerator that does not affect the heat resistance of the planarization layer 310 composed of the finally prepared binder resin 312 . An example of such a crosslinking accelerator is polyhedral oligomeric silsesquioxane (POSS), which is a silsesquioxane having a cage structure among polysilsesquioxanes. The content of the crosslinking accelerator may vary depending on the type and content of the solvent and used in the binder composition, but the content may be approximately 0.01 to 0.1 parts by weight in the binder composition.

A planarization layer ( 320) can be obtained. The coating method is not limited, and methods such as spin coating, roll coating, spray coating, bar coating, slit coating using a slit nozzle such as ejection nozzle coating can be used, and two or more coating methods can be combined to coat. have. At this time, the thickness of the coated film may vary depending on the coating method, the concentration of solids in the binder composition, the viscosity, etc., but after drying, the thickness of the planarization layer 310 may be 0.1 to 2.0 μm.

Specifically, the solvent is evaporated by performing the curing process for the above-described binder composition, and finally, the binder resin 312 in which the porous copper particles 320 are dispersed on the substrate may be formed. This process can be used as a method of volatilizing the solvent by applying appropriate heat. For example, in the case of using a polysiloxane-based resin as the binder resin 312 , preheating (pre-baking) is performed at a temperature of 80 to 120° C. for 0.1 to 5 minutes, and then 5 to 200 at a temperature of 150 to 400° C. The main heating (post-baking) may be carried out for a minute, preferably 10 to 100 minutes.

On the other hand, in order to prepare the binder resin 312 in which the porous copper particles 320 are dispersed in polyimide, the binder composition including the above-described amine compound, anhydride and porous copper particles 320 is coated on a substrate, and the amine Thermal imidization process in which polyamic acid obtained by the reaction of a compound and anhydride is heated at 140 to 300 ° C., and chemical imidization in which imidization is chemically performed using a dehydration catalyst such as acetic anhydride/pyridine. The methods may be used alone or in combination.

Returning to FIG. 2 , the first buffer layer 332 and the second buffer layer 334 respectively positioned below and above the planarization layer 310 constituting the planarization layer 300 are positioned. As described above, in the planarization layer 310 , the porous copper particles 320 as a metal component are dispersed in the binder resin 312 . When the planarization layer 310 is directly interposed between the touch panel (TP, see FIG. 4) and the array panel (AP), a plurality of metallic electrodes or wires constituting the touch panel and the array panel, and the porous copper particles 320 ) may cause an electrical short. To prevent this, a first buffer layer 332 and a second buffer layer 334 made of an insulating material are respectively disposed below and above the planarization layer 310 .

In one exemplary embodiment, the first buffer layer 332 and the second buffer layer 334 may be laminated using an inorganic material. For example, the first buffer layer 332 and the second buffer layer 334 may be fabricated using silicon oxide (SiO ₂ ) and/or silicon nitride (SiNx), such as plasma enhanced chemical vapor deposition (PECVD) or the like. method can be used. In this case, the first buffer layer 332 and the second buffer layer 334 may each be stacked to a thickness of 500 to 2000, but the present invention is not limited thereto.

According to the present invention, the planarization layer 310 as an insulating film in which the porous copper particles 320 are dispersed in the binder resin 312 has excellent heat resistance. When the planarization layer 310 is used as a planarization layer 300 between the touch panel (TP, see FIG. 4) and the array panel (AP, see FIG. 4) constituting the display panel (DP, see FIG. 4), the array Deterioration such as destruction of the structure of the planarization layer 310 does not occur even by a high temperature process of 350° C. or higher for manufacturing the thin film transistor (Tr, see FIG. 4 ) constituting the panel.

That is, the planarization film 300 including the planarization layer 310 manufactured according to the present invention adopts the binder resin 310 having excellent heat resistance properties, while heat is easily discharged using the porous copper particles 320 . Since the passage is formed, the heat dissipation property is good. Accordingly, the thermal stress is similar between the array panel AP (refer to FIG. 4 ) positioned above the planarization layer 300 and the touch panel TP (refer to FIG. 4 ) positioned below the planarization layer 300 .

Therefore, excellent adhesion to the touch panel or substrate respectively positioned above and below the array panel can be maintained even under high temperature conditions (refer to FIG. 7A ). In addition, since no lifting occurs at the interface with the substrate, cracks do not occur (see FIGS. 8A and 10A ), and peel strength is excellent (see FIG. 9A ). Furthermore, since the light-transmitting characteristic is not deteriorated even by high-temperature treatment, it can be applied to a display device to obtain good luminance, and since it contains the particles 320 having a porous structure, a low-dielectric constant can be achieved. There is an advantage in that the driving voltage can be lowered. In addition, since the porous copper particles 320 having a low dielectric constant structure are dispersed to lower the resistance of the planarization layer 310 used as an insulating film, static electricity that may be caused in the driving process can be quickly attenuated, thereby improving product yield. can do it

Subsequently, an array substrate for a display device and a display device to which the planarization layer 310 composed of the binder resin 312 in which the porous copper particles 320 are dispersed according to the present invention can be applied will be described. 4 is a cross-sectional view schematically illustrating a display device to which a high heat-resistant planarization film is applied between a touch panel and a liquid crystal display panel according to an exemplary embodiment of the present invention. The in-cell touch type liquid crystal display 100 according to the second embodiment of the present invention includes a touch panel TP positioned on a first substrate 101 and an array panel ( and a display panel DP including an AP). The second substrate 102 facing the first substrate 101 is positioned on the upper end of the display panel DP, and the liquid crystal layer 180 is interposed between the first substrate 101 and the second substrate 102 . have. The first substrate 101 and the second substrate 102 may be made of not only glass, but also a plastic material such as polyimide (PI).

The touch panel TP senses a user's touch, and the touch panel TP includes a plurality of first touch electrodes 112 arranged in a first direction and a second direction different from the first direction. and a plurality of second electrodes 114 that become For example, the first direction may be parallel to a data line (not shown) and the second direction may be parallel to a gate line (not shown), but is not limited thereto.

The first touch electrode 112 and the second touch electrode 114 are spaced apart from each other. For example, the plurality of first touch electrodes 112 may be integrally formed on the first substrate 101 in a first direction and connected to each other in an island shape spaced apart from each other in the second direction. A plurality of second touch electrodes 114 may be formed. In one exemplary embodiment, the first touch electrode 112 may be a transmit (Tx) electrode, and the second touch electrode 114 may be a receive (Rx) electrode.

Although not shown in the drawings, the touch panel TP includes, in addition to the first and second touch electrodes 112 and 114 , a driving line connected to the first touch electrode 112 , and a second touch electrode 114 . A sensing line connected to the , a touch pad (not shown) is formed. The touch pad (not shown) is electrically connected to a plurality of transmission wirings (not shown) or receiving wirings (not shown), and for example, the display pad through a connection means (not shown) that is an anisotropic conductive film. (not shown) may be electrically connected to.

A first buffer layer 332 covering the first and second touch electrodes 112 and 124 is formed on the touch panel TP. The first buffer layer 332 may be formed of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx). The first buffer layer 332 is interposed between the touch panel TP and the planarization layer 310 , and is disposed between the first and second touch electrodes 112 and 114 and the porous copper particles dispersed in the planarization layer 310 . Prevent electrical short.

A planarization layer 310 in which porous copper particles are dispersed in a binder resin is positioned on the upper surface of the first buffer layer 332 . For example, the porous copper particles are mesoporous porous copper particles. A second buffer layer 334 made of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is positioned on the planarization layer 310 , and the porous copper particles dispersed in the planarization layer 330 and , to prevent an electrical short between a plurality of electrodes and wires constituting the array panel AP, such as the gate electrode 132 and/or the data wire 170 .

The array panel AP constituting the display panel DP is formed on the second buffer layer 334 . The array panel AP includes a plurality of electrodes and wires to control the operation of the backlight unit (not shown).

An electrode and wiring constituting the array panel AP will be described in detail. A plurality of gate wires (not shown) extend in one direction on the second buffer layer 334 , and intersect the plurality of gate wires (not shown) to define a plurality of pixel areas P and move in the second direction. A plurality of data lines 170 are formed. A gate pad (not shown) is formed in the non-display area by being connected to one end of the gate line (not shown), and a data pad (not shown) is formed in the non-display area by being connected to one end of the data line 170 . .

In each of the plurality of pixel regions P, a semiconductor layer 140 including a gate electrode 132 , a gate insulating layer 136 , an active layer 142a and an ohmic contact layer 142b , and source and drain electrodes 152 . , 154) is formed with a thin film transistor Tr. The gate electrode 132 is connected to a gate line (not shown) and is formed on the second buffer layer 334 . A gate insulating layer 136 made of an inorganic insulating material, for example, an inorganic insulating material that may be silicon oxide or silicon nitride, is formed on the gate wiring (not shown) and the gate electrode 132 .

An active layer 142a made of pure amorphous silicon is formed on the gate insulating layer 136 , and an ohmic contact layer 142b formed on the active layer 142a to expose the center of the active layer 142a and made of impurity amorphous silicon is formed. has been The active layer 142a and the ohmic contact layer 142b form the semiconductor layer 140 .

A source electrode 152 and a drain electrode 154 that are spaced apart from each other to expose the center of the active layer 142a are formed on the semiconductor layer 140 . The source electrode 152 is positioned on the semiconductor layer 140 and extends from the data line 170 , and the drain electrode 154 is positioned on the semiconductor layer 140 to be spaced apart from the source electrode 152 . The thin film transistor Tr is positioned in the switching region TrA.

In addition, a data line 170 extending in the second direction is formed on the gate insulating layer 136 to cross the gate line (not shown). The data line 170 extends from the source electrode 152 of the thin film transistor Tr positioned in the pixel region P. Meanwhile, although not shown in the drawings, in one exemplary embodiment, a common wiring (not shown) is formed along the second direction parallel to the data line 170 on the gate insulating layer 136 , and the gate wiring (not shown) ) intersect with In an alternative embodiment, the common wiring (not shown) may be formed on the same layer as the gate wiring (not shown) in parallel to the gate wiring (not shown).

Meanwhile, the first passivation layer 160 covering the data line 170 , the source electrode 152 , the drain electrode 154 , and the common line (not shown) is formed as a first interlayer insulating layer. A drain contact hole 164 exposing the drain electrode 154 of the thin film transistor Tr is formed in the first passivation layer 160 . The first protective layer 160 may be formed of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx), or an organic insulating material such as benzocyclobutene or photo acryl. . The first protective layer 160 prevents the ohmic contact layer 142b from being damaged in the process of forming the pixel electrode 176 .

In addition, in each pixel region P, a pixel electrode 176 as a first electrode electrically connected to the drain electrode 174 of the thin film transistor Tr through a drain contact hole 164 and is electrically connected is a first protective layer. It is formed on (160). The pixel electrode 176 is made of a transparent conductive material, and may have a plate shape in each pixel region P. For example, the transparent conductive material may be indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). Although not shown in the drawings, a gate pad electrode and a data pad electrode made of the same transparent conductive material as the pixel electrode 176 are formed in the non-display area on the upper portion of the first passivation layer 160 . It is electrically connected to the gate pad through a pad contact hole (not shown), and the data pad electrode is electrically connected to the data pad through a data pad contact hole (not shown).

A second passivation layer 178 serving as a second interlayer insulating layer is formed on the pixel electrode 176 . The second protective layer 178 may be formed of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx), or an organic insulating material such as benzocyclobutene or photo acryl. .

Meanwhile, a common electrode 190 overlapping the plate-shaped pixel electrode 176 and having a plurality of slit-shaped holes (openings) 192 is formed on the second passivation layer 178 . Like the pixel electrode 176 , the common electrode 190 serving as the second electrode may be made of a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). The common electrode 190 is formed on the entire surface of the display area in which the plurality of pixel areas P are formed. When a voltage is applied between the pixel electrode 176 , which may be a plate-shaped first electrode, and the common electrode 190 , which may be a second electrode having an opening 192 , a fringe field is formed to form a liquid crystal. By driving, the transmission efficiency is improved and a high-quality image is displayed.

Although not shown in the drawings, a black matrix, which is a light blocking member having an opening corresponding to each pixel region P, is formed on the lower portion of the second substrate 102, and the second substrate exposed through the lower portion of the black matrix and the opening of the black matrix is formed. 2 A color filter layer is formed under the substrate 102 . The color filter layer (not shown) includes red, green, and blue color filters corresponding to the pixel area P. In addition, an overcoat layer (not shown) made of a material such as polyimide, polyacrylate, polyurethane, etc. is provided between the color filter layer (not shown) and the liquid crystal layer 180 to protect the color filter layer (not shown) and planarize the surface. more can be formed. In addition, although not shown, a polarizing plate may be positioned on the second substrate 102 , and a cover window may be disposed on the polarizing plate (not shown) through an optically clear adhesive (OCA).

The display device 100 according to the first embodiment of the present invention includes a planarization layer having porous copper particles dispersed in a high heat-resistant binder resin between the array panel AP and the touch panel TP constituting the display panel DP. 310 is located. Accordingly, the planarization layer 310 is not deteriorated even by a high temperature process of 350° C. or higher for manufacturing the thin film transistor Tr constituting the array panel AP. Due to these characteristics, even after the array panel AP is finally manufactured, the planarization layer 310 is firmly adhered to the touch panel TP and the array panel AP, and thus the touch panel TP and the array panel AP AP) can be firmly maintained.

In addition, since the planarization layer 310 according to the present invention can maintain its properties even by a high-temperature process, cracks and/or peeling by the high-temperature process do not occur. Since the light transmittance is not lowered even by the high-temperature process, good luminance can be obtained, and since the porous copper particles having a pore structure are dispersed, a low dielectric constant can be secured and the driving voltage can be lowered. In addition, due to the pore structure, static electricity that may be caused during the operation of the device can be quickly attenuated and removed, so that it is possible to prevent malfunction of the device or a decrease in yield due to static electricity.

4 illustrates an in-cell type display device using the liquid crystal display 100 as a display device as a display device, but the planarization film of the present invention is an in-cell type display device using an organic light emitting diode as a display device. can also be applied to 5 is a cross-sectional view schematically illustrating a display device to which a high heat-resistant planarization film is applied between a touch panel and a light emitting diode display panel according to a second exemplary embodiment of the present invention. The in-cell touch type organic light emitting diode display 200 according to the second embodiment of the present invention includes a touch panel TP positioned on a substrate 201 and an array panel ( AP) and a light emitting diode E on the array panel AP. The touch panel TP senses a user's touch, the light emitting diode E serves as a light source, and the array panel AP serves to control the operation of the light emitting diode E. The substrate 201 is made of a glass or plastic material.

The touch panel TP includes a plurality of first touch electrodes 212 arranged in a first direction and a plurality of second electrodes 214 arranged in a second direction different from the first direction. For example, the first direction may be parallel to a data line (not shown) and the second direction may be parallel to a gate line (not shown), but is not limited thereto.

The first touch electrode 212 and the second touch electrode 214 are spaced apart from each other. For example, the plurality of first touch electrodes 212 may be integrally formed on the substrate 201 in a first direction to be connected to each other, and a plurality of islands in the shape of an island spaced apart from each other along the second direction may be formed. of the second touch electrode 214 may be formed. In one exemplary embodiment, the first touch electrode 212 may be a transmit (Tx) electrode, and the second touch electrode 214 may be a receive (Rx) electrode.

Although not shown in the drawings, the touch panel TP includes, in addition to the first and second touch electrodes 212 and 214 , a driving line connected to the first touch electrode 212 , and a second touch electrode 214 . A sensing line connected to the , a touch pad (not shown) is formed. The touch pad (not shown) is electrically connected to a plurality of transmission wirings (not shown) or receiving wirings (not shown), and for example, the display pad through a connection means (not shown) that is an anisotropic conductive film. (not shown) may be electrically connected to.

A first buffer layer 332 covering the first and second touch electrodes 112 and 124 is formed on the touch panel TP. The first buffer layer 332 may be formed of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx). The first buffer layer 332 is interposed between the touch panel TP and the planarization layer 310 , and is disposed between the first and second touch electrodes 112 and 114 and the porous copper particles dispersed in the planarization layer 310 . Prevent electrical short.

A planarization layer 310 in which porous copper particles are dispersed in a binder resin is positioned on the upper surface of the first buffer layer 332 . For example, the porous copper particles are mesoporous porous copper particles. A second buffer layer 334 made of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is positioned on the planarization layer 310 , and the porous copper particles dispersed in the planarization layer 330 and , to prevent an electrical short between a plurality of electrodes constituting the array panel AP such as the gate electrode 232 and wiring.

The array panel AP is located on the touch panel TP and includes a driving thin film transistor Tr for controlling the operation of the light emitting diode E, a switching thin film transistor (not shown), a gate wiring (not shown), and data Includes wiring (not shown) and power wiring (not shown).

Although not shown, the data line extends along the second direction and intersects the gate line to define the pixel region P, and the power line for supplying a high potential voltage is located apart from the data line. The switching thin film transistor is connected to the gate line and the data line. The driving thin film transistor Tr is connected to the switching thin film transistor and the power supply wiring, and applies the voltage of the power supply wiring to the light emitting diode E by the operation of the switching thin film transistor.

Each of the switching thin film transistor and the driving thin film transistor Tr may include a gate electrode 232 , a gate insulating layer 236 , a semiconductor layer 240 , a source electrode 252 , and a drain electrode 254 . For example, the gate electrode 232 is formed on the second buffer layer 334 formed on the planarization layer 310 . A gate insulating layer 236 may cover the gate electrode 232 , and the semiconductor layer 240 may overlap the gate electrode 232 on the gate insulating layer 236 . In addition, the source electrode 252 and the drain electrode 254 are spaced apart from each other on the semiconductor layer 240 .

For example, the gate wiring, the gate electrode 232 , the data wiring, the source electrode 252 , and the drain electrode 254 may be formed of a low-resistance metal material such as aluminum, aluminum alloy, copper, copper alloy, molybdenum. , may be made of any one of chromium.

In FIG. 2 , the semiconductor layer 240 of the driving thin film transistor Tr is described as being made of an oxide semiconductor layer, and an etch-stopper 242 is formed to protect the semiconductor layer 240 made of an oxide semiconductor material. was shown However, it is obvious that the etch-stopper 242 may be omitted. Also, the structure of the driving thin film transistor Tr shown in FIG. 2 is not limited. For example, instead of the semiconductor layer 240 made of an oxide semiconductor material, the semiconductor layer may include an active layer of pure amorphous silicon and an ohmic contact layer of impurity amorphous silicon. In addition, a top gate type thin film transistor using a semiconductor layer made of polysilicon may be included.

In addition, a first passivation layer 260 covering the driving thin film transistor Tr is formed, and a second passivation layer 262 covering the first passivation layer 260 and providing a flat top surface is formed. The passivation layers 260 and 262 include a drain contact hole 264 exposing the drain electrode 254 of the driving thin film transistor Tr.

The first protective layer 260 is made of an inorganic insulating material such as silicon oxide or silicon nitride to improve contact characteristics with the semiconductor layer 240, and the first protective layer 260 made of an inorganic insulating material. may have a concave-convex shape due to the step difference between the lower components of the . When the light emitting diode E is formed on the first passivation layer 260 , the characteristics of the organic light emitting layer 274 may be deteriorated. Accordingly, the second passivation layer 262 made of an organic insulating material such as photo-acryl and having a flat top surface is formed on the first passivation layer 260 . However, it goes without saying that any one of the first passivation layer 260 and the second passivation layer 262 may be omitted.

A light emitting diode E is formed on the second passivation layer 262 to correspond to the pixel region P. The light emitting diode E includes a first electrode 272 electrically connected to the drain electrode 254 of the driving thin film transistor Tr, a second electrode 276 facing the first electrode 272, and a second electrode 276 and an organic light emitting layer 274 positioned between the first and second electrodes 272 and 276 . Although the drawing shows that the first electrode 272 is in contact with the drain electrode 254 of the driving thin film transistor Tr through the drain contact hole 264, it can be connected through a separate connection electrode. .

In the organic light emitting layer 274 , light is generated by a combination of electrons and holes injected by the first electrode 272 and the second electrode 276 . In addition, at the edge of the first electrode 272 , a bank 277 is positioned along the boundary of the pixel region P, and the first electrode 272 and the organic light emitting layer 274 are connected to the bank 277 . It is formed by being separated for each pixel area P based on . Meanwhile, the second electrode 276 is formed to correspond to the entire substrate 201 .

In this case, the first electrode 272 as an anode is made of a material having a relatively high work function value, and may be made of, for example, a transparent conductive material such as ITO or IZO. The second electrode 276 is a negative electrode and may be made of a material having a relatively small work function value. In one exemplary embodiment, the light emitted from the organic light emitting layer 274 may be a bottom light emission method that is externally displayed through the first electrode 272 and the substrate 201 . In this case, for light efficiency, the second electrode 276 may be made of a reflective metal material such as silver (Ag), aluminum (Al), or an aluminum-magnesium alloy (AlMg).

In addition, although not shown, a polarizing plate may be positioned on the second substrate facing the substrate 201, and a cover window may be disposed on the polarizing plate (not shown) through an optically clear adhesive (OCA). have.

In the display device 200 according to the second embodiment of the present invention, a planarization layer 310 having porous copper particles dispersed in a high heat-resistant binder resin is positioned between the array panel AP and the touch panel TP. Accordingly, the planarization layer 310 is not deteriorated even by a high temperature process of 350° C. or higher for manufacturing the thin film transistor Tr constituting the array panel AP. Due to these characteristics, even after the array panel AP is finally manufactured, the planarization layer 310 is firmly adhered to the touch panel TP and the array panel AP, and thus the touch panel TP and the array panel AP AP) can be firmly maintained.

In addition, since the planarization layer 310 according to the present invention can maintain its properties even by a high-temperature process, cracks and/or peeling by the high-temperature process do not occur. Since the light transmittance is not lowered even by the high-temperature process, good luminance can be obtained, and since the porous copper particles having a pore structure are dispersed, a low dielectric constant can be secured and the driving voltage can be lowered. In addition, due to the pore structure, static electricity that may be caused during the operation of the device can be quickly attenuated and removed, so that it is possible to prevent malfunction of the device or a decrease in yield due to static electricity.

Hereinafter, the present invention will be described in more detail through exemplary embodiments. However, the present invention is not limited to the technical spirit described in the following examples.

Synthesis Example: Synthesis of mesoporous copper particles

In this example, mesoporous copper particles adopting the MCM-41 structure were synthesized. First, to synthesize mesoporous silicate (Si-MCM-41), sodium metasilicate was used as a silica introduction material, and cetyltrimethylammonium bromide (CTAB) was used as a surfactant to synthesize under hydrothermal conditions. The pore size was controlled by treating the synthesized MCM-41 with tetraethyl orthosilicate, and structural properties and physical properties can be controlled by treating with Si-MCM-41, which is not calcined as a copper oxide precursor. . By calcining at a temperature of 500 ° C. or higher to remove organic materials including surfactants, mesoporous silicate was synthesized. A copper oxide precursor was added to the prepared Si-MCM-41 to synthesize mesoporous copper particles in which the copper oxide precursor was impregnated at the pore inlets.

Analysis was performed on the synthesized mesoporous copper particles. In the XRD analysis result of FIG. 6a, the mesoporous crystallinity was measured in the range of 2 to 3θ to confirm the hexagonal structure. From the FTIR spectroscopic analysis result of FIG. 6b , it can be seen that IR peaks exist at a wavelength of 1093 cm ^-1 and 988 cm ^-1 depending on the type of copper ions. Meanwhile, it can be seen from the BET analysis result of FIG. 6c that the synthesized material is a mesoporous material. The results of analysis of porous particles using N ₂ adsorption and desorption in relation to BET analysis and Barrett-Joyner-Halenda (BJH) analysis are also shown in Table 1 below.

Table 1: BET analysis results for mesoporous copper particles

In the NMR analysis result of FIG. 6d, the peaks of copper atoms were 53 ppm and 0 ppm. As can be seen from the micrographs of FIGS. 6E and 6F , it was confirmed that a hexagonal mesoporous material was synthesized.

Example 1: Preparation of a planarization insulating film

A planarization insulating film in which the porous copper particles obtained in Synthesis Example were dispersed was prepared, and this was applied to bare glass. To prepare a polysiloxane-based binder resin, 5 to 40 parts by weight of a reactive component in which TEOS and silsesquioxane are blended, and 40 to 100 parts by weight of a solvent in which PGME (propylene glycol methyl ether) and NMP (N-methylpyrrolidone) are blended. Part, 0.5 to 10 parts by weight of the mesoporous copper particles obtained in Synthesis Example, 0.5 to 5 parts by weight of POSS as a crosslinking accelerator, and 0.5 to 5 parts by weight of surfactant as an additive were coated on bare glass. Pre-baking at 110° C. for 120 seconds, and post-baking at 350° C. for 30 minutes again, a planarization insulating film composed of a polysiloxane binder in which mesoporous copper particles are dispersed was formed on the bare glass to a thickness of 2.0 nm.

Comparative Example 1: Preparation of planarization insulating film of acrylate-based resin (over-coat)

An over-coat layer obtained by UV curing using an acrylate-based monomer was formed on bare glass to prepare a planarization insulating film.

Comparative Example 2: Preparation of a planarization insulating film of polysiloxane-based binder resin without porous particles

The procedure of Example 1 was repeated except that the porous particles synthesized in the synthesis example were not used to form a planarization insulating film on the bare glass.

Comparative Example 3: Preparation of a planarization insulating film of polysiloxane-based binder resin in which porous aluminum (Al) particles are dispersed

The procedure of Example 1 was repeated except that mesoporous aluminum particles were used instead of the mesoporous copper particles synthesized in Synthesis Example to form a planarization insulating film on bare glass.

Comparative Example 4: Preparation of a planarization insulating film of polysiloxane-based binder resin in which porous chromium (Cr) particles are dispersed

The procedure of Example 1 was repeated except that mesoporous chromium particles were used instead of the mesoporous porous copper particles synthesized in Synthesis Example to form a planarization insulating film on bare glass.

Example 2: Evaluation of the adhesion of the planarization insulating film

Adhesion to each of the planarization insulating films prepared in Example 1 and Comparative Examples 1-4 was analyzed. The planarization insulating film using mesoporous copper particles had no problem in adhesion to the substrate (Fig. 7a), but all of the planarization insulating films prepared in Comparative Example had problems in adhesion (Figs. 7b to 7e). Therefore, it was evaluated that the planarization insulating film of the present invention has excellent material processability to improve production yield and reduce production time and product cost.

Example 3: Evaluation of crack characteristics of planarization insulating film

The crack characteristics of the planarized insulating films in the form of insulating films prepared in Example 1 and Comparative Examples 1-4, respectively, were analyzed. The planarization insulating film using mesoporous copper particles did not crack ( FIG. 8A ), whereas the planarization insulating film prepared in Comparative Example all had cracks ( FIGS. 8B to 8E ). As in Example 2, the planarization insulating film of the present invention was evaluated to have good material processability and excellent production yield and the like.

Example 4: Measurement of peel strength of a planarization insulating film

Peel strength of each of the planarization insulating films prepared in Example 1 and Comparative Examples 1-4 was measured. Measurement mode was constant-load mode, horizontal speed was 1,000 nm/sec, vertical speed was 5 nm/sec, vertical load was 0.2N, and blade was diamond cutter 0.3 mm. The measurement results are shown in FIGS. 9A to 9E, and are also shown in Table 2 below. It can be seen that the planarization insulating film prepared according to the present invention has very good peel strength because the sensitivity to stress to heat is small.

Table 2: Peel strength of planarized insulating film

Example 5: Measurement of transmittance of planarized insulating film

After leaving the planarized insulating films prepared in Example 1 and Comparative Examples 1-4 respectively at a high temperature for a long period of time, transmittance was measured. The measurement results are shown in Tables 3 to 7 below.

As can be seen from these results, the planarization insulating film in which the mesoporous copper particles are dispersed according to the present invention can minimize the reaction by heat with non-reactants remaining in the thin film while easily discharging heat without being trapped in the thin film. It was superior to the comparative example with a transmittance change rate of 1.3% according to the (350° C.) process. In terms of staining, if the change in transmittance rate according to the high temperature (350°C) process changes by about 3.0%, there is a problem of yellowing and yellowish stains in the transmittance characteristics, which means that the heat resistance is insufficient. It shows the lack of heat resistance.

Table 3: Transmittance of planarized insulating film in which mesoporous copper particles are dispersed

Table 4: Transmittance of acrylate binder planarization insulating film

Table 5: Transmittance of planarized insulating film without mesoporous particles

Table 6: Transmittance of planarization film in which mesoporous aluminum particles are dispersed

Table 7: Transmittance of planarized insulating film in which mesoporous chromium particles are dispersed

Example 6: Measurement of dielectric constant

The dielectric constant of each of the planarization insulating films prepared in Example 1 and Comparative Examples 1-4 was measured. On the lower electrode of the dot pattern, the insulating films prepared in Example 1 and Comparative Examples 1-4 were coated on the entire surface, and an upper electrode (Al square pattern) was deposited on the dot pattern. The tip contact part insulator for measuring the lower electrode was removed, and the dielectric constant between the upper and lower electrodes was measured (based on 100 kHz). After each dielectric film sample was prepared, it was measured for each time difference, and at least 5 points were measured each time it was measured. Table 8 shows the average of the measured values and the standard deviation of the permittivity by thickness.

In the case of the planarization insulating film made of the binder resin in which the mesoporous copper particles are dispersed according to the present invention, bulky characteristics were secured due to the influence of the pore size in the particles, and the packing density was lowered, so the dielectric constant was relatively low at 3.02 level. Therefore, it is estimated that the driving voltage can be lowered because no parasitic current is generated.

Table 8: Permittivity of planarization insulating film

Example 7: Measurement of the static damping effect of the planarization insulating film

The degree of static attenuation of each of the planarization insulating films prepared in Example 1 and Comparative Examples 1-4 was measured. When static electricity is generated in the conductive layer after voltage is applied, the voltage rises to generate a saturation voltage, and the time it takes for the saturated voltage to decay to 1/2 level was measured. Decay time measurement after constant voltage charging by corona discharge method (friction electric type, superior reproducibility and precision compared to direct voltage application), attenuation time (50%) measurement range is 70 ms to 23 hrs (displayable in increments of 0.001 seconds) (STATIC HONESTMETER, model name: H-0110). The measurement results are shown in Table 9.

According to the present invention, the static decay time of the insulating film in which the mesoporous copper particles are dispersed is within 1 sec, and the static electricity is rapidly discharged. However, the static decay time of the insulating film prepared in Comparative Example was 5 sec or more, so static discharge was slow. That is, it was evaluated that the planarization insulating film of the comparative example was vulnerable to static electricity, and when static electricity was generated, a problem occurred in driving the panel, which could affect the yield.

Table 9: Static decay time of planarized insulating film

Example 8: Evaluation of Crack Characteristics for Manufacturing a Lower Metal-Based Planarization Film

Cu was laminated to a thickness of 5000 as a metal electrode on a glass substrate, and silicon nitride was laminated to a thickness of 1000 as a first buffer layer thereon. After coating and forming the planarization insulating film prepared in Example 1 and Comparative Examples 1-4 to a thickness of 2-4 μm on the first buffer layer, silicon nitride is again 1,000 thick as a second buffer layer on the planarization insulating film was laminated with The upper portion of the second buffer layer was left at a high temperature of 350° C. or higher, and the degree of cracking or lifting between the planarization insulating film and the buffer layer was evaluated according to whether the coefficient of thermal expansion was adjusted. According to the present invention, there was no crack or lifting phenomenon in the planarization insulating film sprayed with mesoporous copper particles (Fig. 10a), but it can be seen that cracks occurred in the planarization insulating film prepared in Comparative Example (Figs. 10b to 10e). That is, the insulating film manufactured according to the present invention has an excellent thermal expansion coefficient with good thermal stress matching that alleviates the lifting or cracking between the upper and lower layers in a high-temperature process.

In the above, the present invention has been described based on exemplary embodiments and examples of the present invention, but the present invention is not limited to the technical ideas described in the above embodiments and examples. Rather, those skilled in the art to which the present invention pertains can easily propose various modifications and changes based on the above-described embodiments and examples. However, it will become clearer through the appended claims that all such modifications and changes fall within the scope of the present invention.

100, 200: display device 101, 201: first substrate
102, 202: second substrate 300: planarization film
310: planarization layer 312: binder resin
320: porous copper particles 332, 334: buffer layer
AP: Array panel DP: Display panel
TP: Touch panel Tr: Thin film transistor
E: organic light emitting diode P: display area

Claims (14)

a touch panel positioned on the substrate;
a thin film transistor spaced apart from the touch panel;
a planarization layer interposed between the touch panel and the thin film transistor;
The planarization layer includes porous copper particles dispersed in a binder resin, wherein the porous copper particles are impregnated with porous silicate particles.
The method of claim 1,
The array substrate for a display device further comprising: a first buffer layer positioned between the touch panel and the planarization layer; and a second buffer layer positioned between the planarization layer and the thin film transistor.
The method of claim 1,
The porous copper particles include an array substrate for a display device including mesoporous copper particles.
The method of claim 1,
The binder resin is an array substrate for a display device selected from the group consisting of polysiloxane-based resins, polyimide-based resins, and combinations thereof.
The method of claim 1,
The porous copper particles are dispersed in the binder resin in a ratio of 0.5 to 10 parts by weight to the binder resin array substrate for a display device.
delete a first substrate;
a touch panel positioned on the first substrate;
a display panel spaced apart from the touch panel;
a planarization layer interposed between the touch panel and the display panel;
wherein the planarization layer includes porous copper particles dispersed in a binder resin, and wherein the porous copper particles are impregnated with porous silicate particles.
8. The method of claim 7,
The display device further comprising: a first buffer layer positioned between the touch panel and the planarization layer; and a second buffer layer positioned between the planarization layer and the display panel.
8. The method of claim 7,
The porous copper particles include mesoporous copper particles.
8. The method of claim 7,
The binder resin is a display device selected from the group consisting of polysiloxane-based resins, polyimide-based resins, and combinations thereof.
8. The method of claim 7,
The porous copper particles are dispersed in the binder resin in an amount of 0.5 to 10 parts by weight to the binder resin.
delete The method of claim 1,
The porous silicate includes tetramethyl orthosilicate, tetraethyl orthosilicate or sodium metasilicate.
8. The method of claim 7,
The porous silicate includes tetramethyl orthosilicate, tetraethyl orthosilicate or sodium metasilicate.

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