KR102425869B1 - CMOS-based crossbar deep learning accelerator - Google Patents

Abstract

A crossbar array deep learning accelerator based on CMOS according to the present invention includes: a crossbar array including a plurality of conductors crossing each other in horizontal and vertical directions; a resistance element that crosses and connects the horizontal conductors (rows) and longitudinal conductors (columns); an update engine for updating and training the neural network provided by the crossbar array; and a processing engine for performing input/output operations of the neural network provided by the crossbar array, thereby providing a hardware artificial intelligence device.

Description

CMOS-based crossbar deep learning accelerator

The present invention relates to a crossbar array deep learning accelerator based on CMOS.

Artificial intelligence based on software has reached a significant level and can be easily applied anywhere. However, since computer resources are utilized, power efficiency is reduced, calculation time is long, and high-level utilization is impossible unless a server is connected to a network and used.

As an improvement on this disadvantage, by making the hardware itself suitable for the computation of the artificial neural network, faster recognition speed and higher power efficiency can be realized compared to software. As the hardware artificial neural network, a method of applying a device to a crossbar array may be exemplified. In this method, since the memory device itself can be a crossbar array, it is possible to improve the arithmetic efficiency.

Examples of the device include a memristor or a resistive RAM (RRAM). However, the device has problems in that it is difficult to design the device together with a circuit based on CMOS, and the reliability of conductance response is low.

Accordingly, if a resistance element can be manufactured using a CMOS element, it is expected to be easy to integrate and to have a wider operating range than a memristor.

In 'Capacitor-based Cross-point Array for Analog Neural Network with Record Symmetry and Linearity', unveiled at the 2018 Symposium on VLSI Technology Digest of Technical Papers, a cross-array based on capacitors manufactured with microprocessing for the realization of artificial intelligence is introduced. In this document, an accelerator using a transistor-based crossbar array in a DRAM process is presented.

There is a problem in that the above literature does not specifically present the configuration of the resistance element.

'Capacitor-based Cross-point Array for Analog Neural Network with Record Symmetry and Linearity' unveiled at the 2018 Symposium on VLSI Technology Digest of Technical Papers

The present invention is proposed under the background described above, and proposes a CMOS-based crossbar array deep learning accelerator capable of adjusting a resistance element with a controlled conductance value.

A crossbar array deep learning accelerator based on CMOS according to the present invention includes: a crossbar array including a plurality of conductors crossing each other in horizontal and vertical directions; a resistance element that crosses and connects the horizontal conductors (rows) and longitudinal conductors (columns); an update engine for updating and training the neural network provided by the crossbar array; and a processing engine for performing input/output operations of the neural network provided by the crossbar array, thereby providing a hardware artificial intelligence device.

The resistance element includes: first PMOS and second PMOS connected in series to control a flowing current; a second NMOS having a drain connected to a driving voltage, an input voltage connected to a gate, and a source connected to the gate of the second PMOS; and a first NMOS constituting the second NMOS and a first source follower circuit. Accordingly, by preventing the second PMOS from entering the saturation region, pre-programmed learning can be faithfully performed. Of course, according to this, the range in which learning is performed can be made larger.

According to the present invention, it is possible to implement a wide control range.

According to the present invention, the conductance of the resistance element can be adjusted according to the control state.

More specifically, in the case of memristors, the problem of currently stuck-at-fault, that is, a problem in which a value does not exist within the desired conductance range and stays at both extremes (for example, a conductance value that becomes open or short in the circuit) have. This is a problem of the memristor element itself, and when too large a voltage is applied between the memristor elements, the insulator in the memristor element does not maintain its characteristics and enters a different state (completely disconnected or connected). However, since the present invention is implemented based on CMOS, stable performance can be guaranteed.

In addition, since a memristor cannot be manufactured together with the CMOS process, a memristor-based crossbar array and a signal transmission/reception peripheral circuit must be separately manufactured. However, since the present invention uses a general CMOS process rather than a memristor, peripheral circuits can be integrated together in one chip, thereby simplifying manufacturing. In other words, a deep learning accelerator with a crossbar array structure can be easily implemented with a single chip.

In addition, since the present invention is CMOS-based, compared with other CMOS-based accelerators, since it is an in-memory device in the form of a crossbar array, the degree of integration is higher than that of an off-chip memory SRAM-based accelerator. That is, it can have more memory capacity than a typical CMOS-based accelerator.

1 is a configuration diagram of a crossbar array deep learning accelerator based on CMOS according to an embodiment;
2 is a view showing the configuration of a bias generator and a charge pump.
3 is a diagram showing the configuration of an amplifier and a dynamic comparator;
4 is a view showing the configuration of a resistance element.
5 and 6 are views for explaining the operation of the source follower provided to the resistance element.

Hereinafter, specific embodiments of the present invention will be described in detail with reference to the drawings. However, the spirit of the present invention is not limited to the embodiments presented below, and those skilled in the art who understand the spirit of the present invention may add, change, delete, and add components to other embodiments included within the scope of the same spirit. It will be easily proposed by the , but this will also be included within the scope of the present invention.

1 is a configuration diagram of a crossbar array deep learning accelerator based on CMOS according to an embodiment.

Referring to FIG. 1 , a crossbar array 2 including a plurality of conducting wires crossing each other in the horizontal and vertical directions is included.

The crossbar array 2 further includes a resistance element 20 that crosses and connects horizontal conductors (rows) and longitudinal conductors (columns). The resistance element 20 may be provided by connecting each column and each row to each other. The resistance element 20 may be operated by a reference signal supplied by each scanning signal of the row to which the control signal of the column is supplied.

The resistance element may not be a resistor in a general sense, but may be an abbreviation for a resistance arithmetic element which consequently operates as a resistance element. The resistance operation element may be implemented by a transistor and a MOS.

The resistance element will be described in detail later.

An update engine 11 for updating and training a neural network provided by a crossbar array 2 comprising the resistive element 12, and a crossbar array 2 comprising the resistive element 12 A processing engine 12 for performing input/output operations of the neural network is further included.

The approximate operation of the deep learning accelerator 1 according to the embodiment is as follows.

First, the input of the low pulse driver 3 of the processing engine 12 is transformed into a current to fit the crossbar array 2 and is applied thereto.

Thereafter, the values calculated while passing through each resistance element 20 of the crossbar array 2 are integrated by the amplifier 4 . A capacitive trans-impedance amplifier may be applied to the amplifier 4 . The output value of the amplifier 4 may be calculated as a result value by the dynamic comparator 5 .

Thereafter, after neural network learning is performed using the result value, the resistance value of the resistance element 20 of the crossbar array 2 is changed using the update engine 11 .

The change in the resistance value is controlled by outputting a reference current Im from the master bias 7 , and controlling the reference current according to a value programmed by a programmable bias generator 8 . outputting the current Ib, and adjusting the charge value according to the control current in a column parallel charge pump 9 .

The charge value CPout may be input as a reference voltage Vcon of the resistance element 20 .

As a result, the reference voltage Vcon for controlling the resistance element may be adjusted according to a value previously programmed in the bias generator 8 .

Hereinafter, the structure and operation of each component of the deep learning accelerator 1 according to the embodiment will be described.

2 is a diagram showing the configuration of the bias generator and the charge pump.

Referring to FIG. 2 , the bias generator 8 includes an R-2R resistor ladder to binarize the reference current Im.

Each flip-flam FF is connected to each other, and currents such as 1/2Im, 1/4Im, and 1/8Im sequentially flow from the left toward the output side. By programming 1 or 0 in the flip-flop, the circuit can be switched to flow to the control current Ib for the charge pump 9 or to the ground. For example, all currents on the output side, in which a value of 1 is programmed, may flow by being summed as the control current Ib.

Accordingly, the control current Ib acting as the bias value of the charge pump 9 may be changed according to the value previously programmed in the bias generator 8 .

The charge pump 9 may increase or decrease the charge of the output node by applying a voltage up or down at every operation clock. At this time, the value that can change the charge per one clock is changed according to the control current Ib. Through the above process, it is possible to change the reference voltage Vcon a lot or a little at a time according to a pre-programmed value, so that various values can be adjusted.

Meanwhile, when the charge pump 9 of any one column operates, the row scanner 10 sequentially operates to adjust a position to which the reference voltage is applied.

3 is a diagram showing the configuration of the amplifier and the dynamic comparator.

Referring to FIG. 3 , two rows of resistance element columns may be connected to the crossbar array 2 to implement positive weights and negative weights for the neural network.

The total amount of current passing through the two columns is integrated by the amplifier (4). The integrated output value may provide an output of the neural network by the dynamic comparator 5 .

The dynamic comparator 5 may determine an output value of 0 or 1 by comparing a random signal with the integrated output value for every clock. The output of the neural network can be determined according to how many of the output values occur in an arbitrary period.

The description of the dynamic comparator and the operation associated with the dynamic comparator is in Registration No. 10-1965850, 'a method for probabilistic implementation of an activation function used in an artificial neural network and a system including the same', which the present inventor has already applied for. As it is described, it can be referred to. Within the necessary range, the description of the above registered patent of the inventor shall be included in the description of the present invention within the range necessary for the implementation of the present invention.

4 is a diagram showing the configuration of the resistance element, and FIGS. 5 and 6 are diagrams for explaining the operation of the source follower provided to the resistance element.

Referring to FIG. 4 , in the resistance element 20 according to the embodiment, a first PMOS (P1) 25 and a second PMOS (P2) 26 connected in series to control a flowing current are provided. Included. The sources of the first and second PMOS 25 and 26 are connected to each other, the input side is connected to the drain of the first PMOS 25, and the output side is connected to the drain of the second PMOS.

On the other hand, a device referred to as MOS in the embodiment should be interpreted as referring to all devices capable of driving as a transistor.

In the resistance element 20 according to the embodiment, the driving voltage Vdd is connected to the drain, the input voltage Va is connected to the gate, and the source is connected to the gate of the second PMOS 26 . (22), and the second NMOS 22 and the first NMOS 21 constituting the first source follower circuit are included.

The gate voltage of the second NMOS 22 that is the input of the first source follower may be directly reflected to the source voltage of the second NMOS 22 and the drain voltage of the first NMOS 21 that are the output of the source follower. have. Ideally, you could have a one-to-one variation.

In the resistance element 20 according to the embodiment, the driving voltage Vdd is connected to the drain, the output voltage Vb is connected to the gate, and the source is connected to the gate of the first PMOS 25 . (24), and a fourth NMOS 24 and a third NMOS 21 constituting a second source follower circuit are included.

The gate voltage of the fourth NMOS 24 that is the input of the second source follower may be directly reflected to the source voltage of the third NMOS 23 and the drain voltage of the fourth NMOS 24 that are the output of the source follower. have. Ideally, you could have a one-to-one variation.

The reference voltage Vcon is connected to gates of the first NMOS 21 and the second NMOS 22 . The drain of the first NMOS 21 is connected to the source of the second NMOS 22 , and the source of the third NMOS 23 is connected to the source of the fourth NMOS 24 .

The main operation of the resistance element 20 according to the embodiment will be described.

When the input voltage Va changes, the first source follower senses it (see FIG. 5). The output voltage of the first source follower is applied to the gate of the second PMOS 26 and is reflected in the output voltage Vb (refer to FIG. 6).

Accordingly, it is possible to prevent the second PMOS 26 from entering the saturation region.

As a result, the amount of current programmed to be implemented by the first and second PMOS 25 and 26 can be implemented. Accordingly, the programmed conductance value can be maintained. Furthermore, the range of the programmable current may be enlarged.

The response to the change in the input voltage Va is the same as the response to the change in the output voltage Vb. For example, it is possible to prevent the first PMOS 25 from entering the saturation region by the operation of the second source follower.

The concept of a resistance element constituting one main idea of the present invention will be more easily understood by presenting a comparative example.

In the comparative example, the first, second, third, and fourth NMOS (21, 22, 23, 24) are not used, and the gates of the first, second PMOS (25, 26) are not used. It is a configuration in which the reference voltage Vcon is directly connected.

The examples are compared with the comparative examples.

Even in the case of the comparative example, the current flowing according to the reference voltage may be adjusted. However, when the reference voltage is fixed, the operating regions of the first and second PMOS 25 and 26 may reach a saturation region depending on source and drain voltages. For example, since the reference voltage Vcon does not change despite the increase of the input voltage Va and the source voltage, the voltage difference between the source and the drain in the second PMOS 26 increases. In this case, the second PMOS 26 may enter the saturation region.

As a result, the programmed current cannot flow. According to this, the current area that can be programmed is reduced.

In contrast, in the resistance element 20 of the embodiment, when the input voltage Va increases, the gate voltage of the second PMOS 26 increases accordingly. Accordingly, the second PMOS 26 may maintain a triods region without reaching the saturation region.

Accordingly, it is possible to control the resistance element in response to the current in all regions previously programmed in the bias generator 8 .

According to the present invention, a CMOS-based crossbar array deep learning accelerator can be used stably in a wider range.

20: resistance element

Claims (5)

a crossbar array including a plurality of conductive wires crossing each other in horizontal and vertical directions;
a resistance element that crosses and connects horizontal conductors (rows) and longitudinal conductors (columns) in the plurality of conductors;
an update engine used for updating and training a neural network provided to the resistance element and the crossbar array; and
a processing engine for performing input/output operations of the neural network provided to the resistive element and the crossbar array;
In the resistance element,
a first PMOS and a second PMOS connected in series with sources connected to each other to control a flowing current;
a second NMOS having a drain connected to a driving voltage, a gate connected to an input voltage, and a source connected to the gate of the second PMOS; and
a first NMOS constituting the second NMOS and a first source follower circuit;
The gate voltage of the second NMOS, which is the input of the first source follower circuit, is applied to the CMOS that is reflected to the source and drain voltages of the second NMOS, which is the output of the first source follower circuit, and the first NMOS. Based on a crossbar array deep learning accelerator. The method of claim 1,
The source connected to the first PMOS and the second PMOS includes a CMOS-based crossbar array deep learning in which an input side is connected to a drain of the first PMOS and an output side is connected to a drain of the second PMOS. accelerator. The method of claim 1,
The gate of the first NMOS is a CMOS-based crossbar array deep learning accelerator to which a reference voltage including information programmed in the update engine is applied. The method of claim 1,
a fourth NMOS having a drain connected to a driving voltage, a gate connected to an output voltage, and a source connected to the gate of the first PMOS; and
a third NMOS constituting the fourth NMOS and the second source follower circuit is included;
The gate voltage of the fourth NMOS that is the input of the second source follower circuit is applied to the CMOS that is reflected to the source and drain voltages of the fourth NMOS and the third NMOS that are the output of the second source follower circuit. Based on a crossbar array deep learning accelerator. 5. The method of claim 4,
The gate of the third NMOS is a CMOS-based crossbar array deep learning accelerator to which a reference voltage including information programmed in the update engine is applied.

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