KR102420606B1 - Method for packet data processing using cache path and electronic device for supporting the same - Google Patents

Abstract

In a method of an electronic device according to various embodiments, the method of the electronic device comprises: an operation of performing a control plane role for network functions including a virtualization function in an edge node CPU including at least one core; and an operation of offloading at least some operations for the network functions including the virtualization function on the at least one core by performing a data plane role for the network functions including the virtualization function in an intelligent network interface card (NIC), wherein the operation of performing the data plane role for the network functions including the virtualization may include: an operation of receiving a packet through a first interface of a data plane; an operation of parsing the packet through a parser table; an operation of checking a meta-cache table based on the parsed packet; and an operation of modifying a header and meta data of the packet and transmitting the modified header and meta data to a second interface when the parsed packet is checked in the meta-cache table. Other embodiments are also possible. A purpose of the present invention is to resolve a problem that may be raised in connection with a legacy system required for constructing a 5G-based edge computing in a 5G technology environment.

Description

A method for processing packet data using a cache path and an electronic device using the same

Various embodiments of the present invention relate to a packet data processing method and an electronic device using the same, and more particularly, to an edge platform network acceleration solution.

In the 4th industry, which is a hot topic today, vast amounts of data can be hyper-connected through various devices. In such an environment, the market for innovative convergence new products and service solutions reflecting user needs may expand, and for this, it may be necessary to secure an infrastructure for product development, testing, and demonstration.

Internet of Things (IoT) traffic continues to grow and this trend may continue. The growth of this trend can be attributed to the increasing number of devices in the Internet of Things. For example, various types of Internet of Things devices such as conventional phones, PCs, smart phones, set-top boxes, home appliances, wearable devices, connected cars, and augmented/virtual reality devices (AR/VR) are emerging.

5G provides a variety of services in the environment of eMBB (enhanced mobile broadband), mMTC (massive machine-type communication), and uRLLC (ultra-reliable and low latency communications) technology. As an enabler that makes it possible, it can provide an opportunity for the entire industry and various dedicated networks related to the explosive increase of data to be integrated into one network. However, problems with existing legacy systems that are necessary when building 5G-based edge computing may arise. For example, in terms of performance, ultra-low latency/ultra-high speed traffic transmission may not be possible in existing CPU-based networking. For example, in terms of cost, CPU load due to networking may reduce service directivity and thus require multiple CPU servers. For example, in terms of flexibility, fixed networking that cannot provide new functions and services on-demand may be a problem. In terms of security, CPU-based processing may be vulnerable to performance degradation due to multiple security policies and arbitrary attacks by unspecified numbers such as DDoS attacks.

A method of an electronic device according to various embodiments of the present disclosure includes: performing, in an edge node CPU including at least one core, a control plane for a network function including a virtualization function; and in an intelligent network interface card (NIC), at least a portion of a network function including the virtualization function in the at least one core by performing a data plane role for the network function including the virtualization function. An operation of offloading an operation, and the operation of performing a data plane role for a network function including the virtualization function includes receiving a packet through a first interface of the data plane movement; parsing the packet through a parser table; checking a meta-cache table based on the parsed packet; and when the parsed packet is checked in the meta cache table, modifying the header and meta data of the packet and transmitting the modified packet to the second interface.

In an electronic device according to various embodiments, there is provided an electronic device comprising: a software stack serving as a control plane for a network function including a virtualization function in an edge node CPU including at least one core; an intelligent NIC including a switch data plane unit serving as a data plane for network functions including the virtualization function; and an edge node CPU offloading at least some operations related to network functions including the virtualization function in the at least one core, wherein the intelligent NIC includes: packet), parses the packet through a parser table, checks a meta-cache table based on the parsed packet, and When it is confirmed in the meta cache table, it may be configured to modify the header and metadata of the packet and transmit it to the second interface to serve as a data plane for network functions including the virtualization function.

1A is a diagram schematically illustrating an architecture of a software stack according to various embodiments of the present disclosure;
1B is a diagram schematically illustrating an architecture of a software stack according to various embodiments of the present invention.
1C is a diagram schematically illustrating a port mapping relationship between an architecture of a software stack and an intelligent NIC according to various embodiments of the present disclosure.
2A and 2B are diagrams illustrating differences between an intelligent NIC-based networking solution and other networking solutions according to various embodiments of the present disclosure.
3A is a diagram schematically illustrating a packet flow of an intelligent NIC-based networking solution according to various embodiments of the present disclosure.
3B is a diagram illustrating a difference between packet flows between an intelligent NIC-based networking solution and other networking solutions according to various embodiments of the present disclosure.
4A and 4B are diagrams illustrating differences between an intelligent NIC-based networking solution and other networking solutions according to various embodiments of the present disclosure.
5 is a flowchart of an algorithm of an intelligent NIC-based networking solution according to various embodiments of the present disclosure.
6 is a diagram schematically illustrating a method of processing a packet through an intelligent NIC-based networking solution according to various embodiments of the present disclosure.
7 is a diagram illustrating a first method of processing a packet through an intelligent NIC-based networking solution according to various embodiments of the present disclosure.
8 is a diagram illustrating a second method of processing a packet through an intelligent NIC-based networking solution according to various embodiments of the present disclosure.
9 is a diagram illustrating a third method of processing a packet through an intelligent NIC-based networking solution according to various embodiments of the present disclosure.

The various embodiments of this document and the terms used therein are not intended to limit the technical features described in this document to specific embodiments, and should be understood to include various modifications, equivalents, or substitutions of the embodiments. In connection with the description of the drawings, like reference numerals may be used for similar or related components. The singular form of the noun corresponding to the item may include one or more of the item, unless the relevant context clearly dictates otherwise. As used herein, "A or B", "at least one of A and B", "at least one of A or B," "A, B or C," "at least one of A, B and C," and "A , B, or C" each may include all possible combinations of items listed together in the corresponding one of the phrases. Terms such as "first", "second", or "first" or "second" may simply be used to distinguish an element from other elements in question, and may refer elements to other aspects (e.g., importance or order) is not limited. It is said that one (eg, first) component is “coupled” or “connected” to another (eg, second) component, with or without the terms “functionally” or “communicatively”. When referenced, it means that one component can be connected to the other component directly (eg by wire), wirelessly, or through a third component.

As used herein, the term “module” may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as, for example, logic, logic block, component, or circuit. A module may be an integrally formed part or a minimum unit or a part of the part that performs one or more functions. For example, according to an embodiment, the module may be implemented in the form of an application-specific integrated circuit (ASIC).

According to various embodiments of the present document, one or more instructions stored in a storage medium (eg, internal memory 136 or external memory 138) readable by a machine (eg, electronic device 101) may be implemented as software (eg, the program 140) including For example, the processor (eg, the processor 120 ) of the device (eg, the electronic device 101 ) may call at least one of the one or more instructions stored from the storage medium and execute it. This makes it possible for the device to be operated to perform at least one function according to the called at least one command. The one or more instructions may include code generated by a compiler or code executable by an interpreter. The device-readable storage medium may be provided in the form of a non-transitory storage medium. Here, 'non-transitory' only means that the storage medium is a tangible device and does not contain a signal (eg, electromagnetic wave), and this term refers to the case where data is semi-permanently stored in the storage medium and It does not distinguish between temporary storage cases.

According to an embodiment, the method according to various embodiments disclosed in this document may be provided by being included in a computer program product. Computer program products may be traded between sellers and buyers as commodities. The computer program product is distributed in the form of a machine-readable storage medium (eg compact disc read only memory (CD-ROM)), or through an application store (eg Play Store™) or on two user devices (eg, It can be distributed (eg downloaded or uploaded) directly, online between smartphones (eg: smartphones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily created in a machine-readable storage medium such as a memory of a server of a manufacturer, a server of an application store, or a relay server.

According to various embodiments, each component (eg, a module or a program) of the above-described components may include a singular or a plurality of entities. According to various embodiments, one or more components or operations among the above-described corresponding components may be omitted, or one or more other components or operations may be added. Alternatively or additionally, a plurality of components (eg, a module or a program) may be integrated into one component. In this case, the integrated component may perform one or more functions of each component of the plurality of components identically or similarly to those performed by the corresponding component among the plurality of components prior to the integration. . According to various embodiments, operations performed by a module, program, or other component are executed sequentially, in parallel, repeatedly, or heuristically, or one or more of the operations are executed in a different order, omitted, or , or one or more other operations may be added.

1A is a diagram schematically illustrating an architecture of an electronic device according to various embodiments of the present disclosure;

a software stack 14000 serving as a control plane for network functions including virtualization functions in the edge node CPU including the at least one core;

an intelligent NIC 20000 including a switch data plane 21000 serving as a data plane for network functions including the virtualization function; and

The edge node CPU 11000 offloads at least some operations related to the network function including the virtualization function in the at least one core.

The virtualization function offloaded from the switch data plane unit 21000 to the edge node CPU 11000 may further include a compiler 15000 for generating binary codes performed by the switch data plane unit.

An embodiment of the present invention may further include a data plane unit management module 13000 that transmits the binary code to the switch data plane unit 21000 and requests execution.

The electronic device may further include an operating system kernel 12000 .

The data plane management module 13000 may be included in the operating system kernel 12000 .

The data plane part management module 13000 may include a library that processes the data plane part and/or a control driver that controls the intelligent NIC 20000 or the general NIC 30000 . In addition, the data plane management module 13000 may include an interface capable of controlling the intelligent NIC 20000 or the general NIC 30000, for example, an application programming interface (API) or an application. . The data plane management module 13000 may be, for example, a data plane development kit (DPDK).

An embodiment of the present invention further includes the general NIC 30000, and the data plane management module 13000 may request the general NIC to perform a non-virtualized network function.

An embodiment of the present invention may further include a high-speed data path framework 12100 that offloads the virtualization function from the switch data plane unit 21000 to the edge node CPU 11000. .

The high-speed data path framework 12100 may add an initial hook to the RX path, and the virtualization function may control packet processing. The hook may be disposed in the NIC driver included in the data plane management module immediately after interrupt processing and before memory allocation required for the network stack itself.

The high-speed data path framework 12100 may be included in the operating system kernel 12000 .

The intelligent NIC may further include a Field Programmable Gate Array (FPGA) 22400.

The intelligent NIC may further include an application specific integrated circuit (ASIC, 22200).

According to various embodiments, a virtual router serves as a control plane of network function virtualization (NFV), and open-platform forwarding entities (OFE) It may serve as a data plane.

1B is a diagram schematically illustrating an architecture of a software stack according to various embodiments of the present disclosure;

The software stack 14000 may further include a management/setting module 14100 configured to manage and/or configure network services. The management/configuration module 14100 is a container automatic deployment operation, for example, Puppet, Ansible, etc., remote procedure call operation, for example, gRPC, HTTP API, etc., Openflow operation, user plane (user plane)-data plane (data plane) bridge interface (bridge interface), for example, 3GPP N4, command line interface (command line interface), may be to perform tasks such as SMTP (Simple Mail Transfer Protocol).

The software stack 14000 may further include a service module 14200 that provides and/or controls a network service. The service module 14200 is a state service (state service), MEC (Multi-Access Edge Computing)-DP (Data Plane) service, routing service, for example, Quagga / FRR, 5G UPF (User Plane Function), It may be to provide a platform service, link aggregation (LAG), connection tracking, monitoring service, and the like.

The software stack 14000 may further include an interface module 14300 that performs input/output operations of the intelligent NIC 20000 or the general NIC 30000 and the network function performed by the edge node CPU. The interface module 14300 may include the data plane part management module 13000 or perform all or part of tasks required for input/output. The service module 14200 may include a switch abstract interface 21100 that simulates direct access to the intelligent NIC 20000 or the general NIC 30000 and performs input/output, or may perform this by calling from the outside. The interface module 14300 may include a compiler 15000 that performs all or part of the operation of generating the binary, or may perform this by calling it from the outside.

The interface module 14300 includes a compiler-based hardware abstraction layer 13100, and the service operation performed by the service module 14200 is performed by the binary built in the compiler 15000 of the intelligent NIC 20000. By executing in hardware, the service module accesses and controls the intelligent NIC 20000 through the switch abstract interface 21100 that simulates direct access to the intelligent NIC 20000 or the general NIC 30000 and performs input/output. can make it possible The interface module 14300 may include one or more channels 14310 that are mapped to a physical port or a virtual port of the intelligent NIC 20000 or the general NIC 30000 and can be manipulated.

The interface module 14300 may be all included in the software stack 14000 or may be included as an interface capable of calling an external module.

1C is a diagram schematically illustrating a port mapping relationship between an architecture of a software stack and an intelligent NIC according to various embodiments of the present disclosure.

The electronic device may further include a memory, and an operating system for allocating and/or controlling the resources of the electronic device may be allocated to the memory, and the memory may be where the operating system directly controls the electronic device It may include an operating system kernel 12000 that performs a task for performing a task, and an operating system user area 15000 that performs a task for a user who uses the electronic device to control the electronic device.

The operating system kernel 12000 may directly access the resources of the intelligent NIC 20000 or the general NIC 30000, and may directly access the CPU 11000. .

The high-speed data path framework 12100 can access and/or control the port 22000 of the intelligent NIC 20000 or the general NIC 30000 through the operating system kernel 12000, and does not exist, but a virtual function port 22300 capable of inputting and outputting packets in the same way as an actual physical port may be created and/or removed.

The operating system user area 15000 receives some resources of the electronic device from the operating system kernel 12000 and executes a single virtual operating system or a part of the operating system in the operating system user area 15000. One or more app containers 15100 ) may be executed and include it, and the app container 15100 may include a network service app 15120 . Also, among the app containers 15100 , the software stack 14000 may be the software stack container 15200 in which the software stack 14000 is executed. The network service app 15120 for Multi-Access Edge Computing (MEC), artificial intelligence (Artificial Intelligence) service, content delivery network (Contents Delivery Network), AR (augmented reality) service, VR (virtual reality) service, etc. It may be an application that provides

The app container 15100 or the software stack container 15200 processes a packet required for a service through the high-speed data path framework 12100 between a Single Root I/O Virtualization (SRIOV) and the virtualization function port 22300 can do.

A channel 14310 connected to the software stack 14000 may be mapped to the physical port 22000 or the virtualization function port 22300 in software.

According to various embodiments, a network, particularly, an intelligent connected vehicle (ICV) coupled with a cloud may provide a safer and more environmentally friendly transportation system. However, for existing networks, they are limited to providing low latency response times and may be limited due to inherent delays, disruptions, and inflexibility to dynamic changes.

According to various embodiments, the intelligent NIC-based networking solution may provide a platform for ICV communication based on a 5G system architecture. An intelligent NIC-based networking solution can solve the forwarding performance problem of existing CPU-based network functions. An intelligent NIC-based networking solution can perform network function virtualization (NFV) by introducing the concept of a software defined network (SDN) compiler.

According to various embodiments, the intelligent NIC-based networking solution provides a service providing system requiring ultra-delay switching, for example, a financial trading system, a large-capacity content transmission system, for example, an AR/VR content transmission system, and a streaming game system. can be done

According to various embodiments, an intelligent NIC-based networking solution may offload ICV traffic transmission to hardware through a software-defined network method. In addition, intelligent NIC-based networking solutions can ensure service level agreements (SLAs) of heterogeneous network slices and provide interoperable systems.

According to various embodiments, it is possible to minimize the CPU load due to the DDoS attack through hardware offloading and solve the problem of service stability and security through this. The intelligent NIC-based networking solution can provide a system with improved service stability and security by blocking the CPU from external hacking and attacks based on networking through strict separation between networking and CPU-based applications.

2A and 2B are diagrams illustrating differences between an intelligent NIC-based networking solution and other networking solutions according to various embodiments of the present disclosure.

According to various embodiments, referring to FIG. 2A , in the conventional case, a virtual network function (VNF) 313 may be entirely performed by an edge node CPU. Thereafter, it can communicate with a traditional NIC (eg, a hardware-based NIC, 311) and pass data via PCIE (PCI express). For example, in the conventional case, since 16 cores of the edge node CPU are used to perform a virtual network function (VNF), an overload of the edge node CPU may occur. For example, in the case of the conventional Single Root I/O Virtualization (SRIOV), there may be a restriction that only 16 virtual functions can be created.

According to various embodiments, referring to FIG. 2B , in the case of an intelligent NIC-based networking solution, a virtual network function (VNF) is divided into a VNF CP (control plane, 323) and a VNF DP (data plane, 325). VNF CP can be performed on an edge node CPU (edge node CPU), and VNF DP can be performed on an intelligent NIC (eg, software-based NIC, 321). For example, in the case of an intelligent NIC-based networking solution, since 4 cores of the edge node CPU are used to perform a virtual network function (VNF), the load on the edge node CPU can be relatively reduced. For example, by using an intelligent NIC, a virtual function for processing packets in a conventional CPU may be substituted by compiling a function with a compiler at the NIC stage. That is, an intelligent NIC can be defined as a software compiler and offloading of virtualization functions can be performed.

3A is a diagram schematically illustrating a packet flow of an intelligent NIC-based networking solution according to various embodiments of the present disclosure. The NFVs 11100 loaded on the CPU 11000 are offloaded to the ASIC 22200, NPU 22300, and FPGA 22400 of the intelligent NIC 20000, respectively, so that the load of the CPU 11000 is distributed, intelligent It can be seen that various hardware functions of the NIC can be utilized.

3B is a diagram schematically illustrating a packet flow of an intelligent NIC-based networking solution according to various embodiments of the present disclosure. In the case of the electronic device 100000 using a typical virtual switch function, packet processing may be delayed due to a high delay rate, a low bandwidth, and a concentrated load on the CPU, but the electronic device 200000 according to an embodiment of the present invention Packets are offloaded to the intelligent NIC, resulting in low latency, high bandwidth, and distributed load on the CPU, enabling acceleration of packet processing.

4A and 4B are diagrams illustrating differences between an intelligent NIC-based networking solution and other networking solutions according to various embodiments of the present disclosure.

According to various embodiments, the intelligent NIC-based networking solution 430 may be different in architecture from the software networking-based solution 410 and the SRIOV-based networking solution 420 . For example, the intelligent NIC-based networking solution 430 may perform forwarding by separating the control plane (CP, 431) and the data plane (DP, 433). For example, the data plane 433 may consist of a hardware-level forwarding table and an agent for the control plane 431 . For example, the control plane 431 may include an NFV-based user application, an agent, and a compiler application. For example, the intelligent NIC-based networking solution 430 may offload the NFV of the data plane 433 to a hardware switch and guarantee hardware-level quality of service (QoS) in performing network slicing. In other words, it is possible to perform communication with very low cost and near-real-time response by accelerating virtualized networks (eg, switches, routers, etc.).

According to various embodiments, in the software networking-based solution 410 and the SRIOV-based networking solution 420, the control planes 411 and 421 and the data planes 413 and 423 perform all operations from the guest user to the host kernel. can However, in the intelligent NIC-based networking solution 430 , the operation from the guest user to the host kernel may be performed in the control plane 431 , and virtualization functions thereafter may be performed in the data plane 433 .

According to various embodiments, the intelligent NIC-based networking solution 430 may include a software stack, for example, a Loxilight software stack from NetLOX. The software stack may include all or part of a P4 core compiler, an offload conflict resolver, and a function loader.

The P4 core compiler can understand the high-level P4 intermediate representation, and can output various types of logic such as Verilog, Micro-Code, eBPF, or vendor SDK C code. .

The offload conflict resolver may change the output form of the P4 core compiler to logic in a form in which no conflict occurs when the intermediate representation of the P4 language conflicts with the hardware of the intelligent NIC or the hardware resource of the general NIC.

The function loader may compile logic data output from the compiler, for example, an extended Berkeley Packet Filter (eBPF) user program into eBPF byte code and load it into the data plane. The function load is the operating system kernel of the electronic device by using, for example, a low level virtual machine (LLVM) and/or a Clang compiler in a hardware block of an intelligent NIC or a hardware block of a general NIC by using the logic data output from the compiler. It can be loaded into a realm as XDP, as a proprietary interface to the intelligent NIC's FPGA, or as a proprietary interface to the intelligent NIC's network processor.

5 is a flowchart of an algorithm of an intelligent NIC-based networking solution according to various embodiments of the present disclosure.

According to various embodiments, the intelligent NIC-based networking solution 500 may check network functions in the form of a match-action (MA) pair in operation 510 .

According to various embodiments, the intelligent NIC-based networking solution 500 may determine whether more network functions exist in operation 520 .

According to various embodiments, the intelligent NIC-based networking solution 500 branches to operation 525 when more network functions do not exist in operation 520 , and converts the generated logic in the form of various offload blocks. can be loaded

According to various embodiments, the intelligent NIC-based networking solution 500 branches to operation 530 when there are more network functions in operation 520, eBPF (BPF virtual machine) and XDP (eXpress Data Path) ) can create a baseline fallback for

According to various embodiments, the intelligent NIC-based networking solution 500 may determine whether it is sufficiently offloaded in operation 540 .

According to various embodiments, the intelligent NIC-based networking solution 500 branches to operation 545 when it is not sufficiently offloaded in operation 540, generates offload logic for the most optimized block, and branches to operation 560. , XDP & intelligent NIC can insert metadata to embed offload logic in hybrid mode.

According to various embodiments, the intelligent NIC-based networking solution 500 branches to operation 540, when sufficiently offloaded, to operation 550 to generate offload logic for the most sufficient network function, and branch to operation 560, In XDP & intelligent NIC hybrid mode, you can insert metadata to embed offload logic.

Table 1 below shows the GTP tunnel management heuristic algorithm of the intelligent NIC-based networking solution according to various embodiments of the present invention.

Algorithm 1 GTP Tunnel Management Heuristic Procedure : gtp_tunnel_add():
in-args : tunnel_name, tunnel src-ip, tunnel dst-ip, ingress tunnel-id, egress tunnel-id, vrf-id
out-args : Error Code or 0 for success.
Description : Create a new GTP tunnel interface with a terminating end-point.
1. Prepare tunnel hash key with ingress tunnel-id, egress tunnel-id, vrf-id.
2. Lookup the Tunnel hash table for existing tunnel element
3. If present then return with error ALREADY_EXIST else continue.
4. Allocate tunnel element and copy tunnel key, tunnel src-ip, tunnel dst-ip, ingress tunnel-id and egress tunnel-id.
5. Store tunnel element in tunnel hash table.
6. Install incoming GTP tunnel flow with Match dst ip as tunnel src-ip, src ip as tunnel dst-ip, ingress tunnel-id, gtp udp dst port with actions DECAP_GTP_TUNNEL.
7. Return 0

Procedure : gtp_tunnel_del():
in-args : tunnel_name, ingress tunnel-id, egress tunnel-id, vrf-id
out-args : Error Code or 0 for success.
Description : Delete a existing GTP tunnel interface.
1. Prepare tunnel hash key with ingress tunnel-id, egress tunnel-id, vrf-id.
2. Lookup the Tunnel hash table for existing tunnel element.
3. If not present then return with error NOT_EXIST else continue.
4. Uninstall Incoming GTP tunnel flows with match tunnel src-ip, tunnel dst-ip, ingress tunnel-id, gtp udp dst port.
5. Remove tunnel element from tunnel hash table.
6. Return 0

According to various embodiments, the GTP tunnel management heuristic algorithm may include generating a new GTP tunnel interface using a terminal point (S100), and creating the GTP tunnel interface (S100) may include the following steps. There is: preparing a tunnel hash using an ingress tunnel ID, an outgoing tunnel ID, and a VRF (Virtual Routing and Forwarding) ID (S110);

Inquiring an existing tunnel element in the tunnel hash table (S120);

terminating generation of the GTP tunnel interface when the existing tunnel element exists in the tunnel hash table (S130);

copying the assignment and tunnel key of the tunnel element, the tunnel departure IP, the tunnel arrival IP, the in-tunnel ID, and the outgoing tunnel ID to the assigned tunnel element (S140);

storing the tunnel element in the tunnel hash table (S150); and

installing an incoming GTP tunnel flow using the tunnel departure IP as the arrival IP, the tunnel arrival IP as the departure IP, the incoming tunnel ID, and the GTP UDP arrival port and the DECAP_GTP_TUNNEL operation (S160);

According to various embodiments, the GTP tunnel management heuristic algorithm may include removing the GTP tunnel interface using a terminal point (S200), and removing the GTP tunnel interface (S200) may include the following steps. :

preparing a tunnel hash using an ingress tunnel ID, an outgoing tunnel ID, and a virtual routing and forwarding (VRF) ID (S210);

Inquiring an existing tunnel element in the tunnel hash table (S220);

terminating the removal of the GTP tunnel interface when the existing tunnel element exists in the tunnel hash table (S230);

removing the incoming GTP tunnel flow by using the tunnel departure IP as the arrival IP, the tunnel arrival IP as the departure IP, the incoming tunnel ID, and the GTP UDP arrival port and the DECAP_GTP_TUNNEL operation (S240); and

removing the tunnel element from the tunnel hash table (S250);

Table 2 below is an example of a GTP user flow management heuristic algorithm of an intelligent NIC-based networking solution according to various embodiments of the present invention.

Algorithm 2 GTP User Flow Management Heuristic Procedure : gtp_user_flow_add():
in-args : src-ip, dst-ip, ip-proto, l4 src port, l4 dst port, in-port, tunnel-name
out-args : Error Code or 0 for success
Description : Create a new GTP User flow
1. Prepare user flow hash key with src-ip, dst-ip, ip-proto, l4 src port, l4 dst port, in-port.
2. Lookup the user flow hash table for existing user flow element.
3. If present then return with error ALREADY_EXIST else continue.
4. Lookup the tunnel element with tunnel name as auxiliary key.
5. Allocate user flow element and copy user flow key and tunnel elem.
6. Store user flow element in user flow hash table.
7. Install ingress user flow with match tunnel attributes for outer header and user flow attributes for inner header with actions DECAP_GTP_TUNNEL.
8. Install egress user flow with match user flow attributes and action as ENCAP_GTP_TUNNEL with gtp tunnel attributes.
9. Return 0

Procedure : gtp_user_flow_del():
in-args : tunnel_name, ingress tunnel-id, egress tunnel-id, vrf-id
out-args : Error Code or 0 for success
Description : Delete a existing GTP User flow
1. Prepare user flow hash key with src-ip, dst-ip, ip-proto, l4 src port, l4 dst port, in-port.
2. Lookup the user flow hash table for existing user flow element.
3. If not present then return with error NOT_EXIST else continue.
4. Uninstall egress user flow with match user flow attributes.
5. Uninstall ingress user flow with match tunnel attributes for outer header and user flow attributes for inner header.
6. Remove user flow element from user flow hash table.
7. Return 0

According to various embodiments, the GTP tunnel management heuristic algorithm includes generating a new GTP user flow (S300), and generating the new GTP user flow (S300) may include the following steps: Departure IP , preparing a user flow hash using the arrival IP, IP protocol, I4 departure port, I4 arrival port and in-port (S310);

Inquiring an existing user flow element in the user flow hash table (S320);

If the existing user flow element exists in the user flow hash table, terminating the creation of a new GTP user flow (S330);

inquiring a tunnel element using the tunnel name as a secondary key (S340);

Allocating a user flow element and copying the assigned user flow element with the user flow key and the tunnel element (S350);

Storing the user flow element in the user flow hash table (S360);

installing a receiving user flow in which the tunnel attribute of the outer header and the user flow attribute of the inner header match (S370); and

Installing a sending user flow with matching user flow attributes and actions as ENCAP_GTP_TUNNEL with GTP tunnel attributes (S380).

According to various embodiments, the GTP tunnel management heuristic algorithm includes the step of removing the GTP user flow (S400), and the step of removing the GTP user flow (S400) may include the following steps:

Preparing a user flow hash using the departure IP, arrival IP, IP protocol, I4 departure port, I4 arrival port and in-port (S410);

Inquiring an existing user flow element in the user flow hash table (S420);

If the existing user flow element exists in the user flow hash table, terminating the removal of the GTP user flow (S430);

removing the sending user flow by using the matching user flow attribute (S440);

Replacing the receiving user flow in which the tunnel attribute of the outer header and the user flow attribute of the inner header match (S450); and

Step of removing the user flow element in the user flow hash table (S460)

According to various embodiments, the GTP tunnel management heuristic algorithm may include the step of removing the GTP user flow (S400), and the step of removing the new GTP user flow (S400) may include the following steps:

preparing a user flow hash by using a departure IP, an arrival IP, an IP protocol, an I4 departure port, an I4 arrival port, and an in-port (S410);

Inquiring an existing user flow element in the user flow hash table (S420);

If the existing user flow element exists in the user flow hash table, terminating the removal of the new GTP user flow (S430);

removing the transmission flow element by using the matching user flow attribute (S440);

removing the received user flow user flow in which the tunnel attribute of the outer header and the user flow user flow attribute of the inner header match (S450); and

Inquiring the existing user flow elements in the user flow hash table (S460).

Table 3 below is an example of a packet input/output event handler heuristic algorithm of an intelligent NIC-based networking solution according to various embodiments of the present disclosure.

Algorithm 3 Packet I/O event handler Heuristic Procedure : cp-lox-vif-init():
in-args : SmartNIC Control Plane device name
out-args : Error Code or 0 for success
Description : Creating a RAW Socket for poll event and listening to all the packets sent on the SmartNIC's control plane device ("vf0_0").
1. Create a RAW socket, sock with ETH_TYPE_LOX family.(All the packets sent from the SmartNIC will be having a SHIM Header comprising of the metadata like incoming port, outgoing port, table missed)
2. Get the SmartNIC control plane device index
ifidx = if_nametoindex("vf0_0")
3. Bind sock to ifidx using bind()
4. Add a poll event to read all the packets on this socket using vif-rx().
Procedure : cp-lox-rx():
in-args : Packet buffer
out-args : Error Code or 0 for success
Description : cp-lox-rx () will called by a poll event whenever a packet from SmartNIC is ready to be received by Loxilight application.
1. Read the SHIM hdr (LOX header) from the packet.
2. Derive the front port (incoming port) information from the LOX header.
3. If no present then return with error NOT_EXIST else continue.
4. Derive a flow from packet's original headers.
5. Send the packet and flow information to all the registered applications.
6. Return 0
Procedure : cp-lox-tx():
in-args : Packet buffer
out-args : Error Code or 0 for success
Description : cp-lox-tx () will called by a poll event whenever a packet is to be sent to SmartNIC is by Loxilight application.
1. Derive the data path port, dp_port from front port (outgoing vif).
2. Prepare the SHIM hdr (LOX header) with outport as dp_port.
3. Concatenate the SHIM header and packet into a local buffer, buff.
4. Get the cp_fd for the control plane device ("vf0_0")
5. Issue write(cp_fd, buff, MAX_BUF_LEN)
6. Return 0

According to various embodiments, the packet input/output event handler heuristic algorithm includes a step (S500) of creating a RAW socket for receiving a poll event and all packets transmitted to the control plane device (“vf0_0”) of the smart NIC (S500), The step of creating the RAW socket ( S500 ) may include the following steps:

Creating a RAW socket using the ETH_TYPE_LOX family (S510);

Receiving the index of the SmartNIC control plane device (S520);

binding a socket to the received index (S530); and

Adding a poll event for reading all packets to the socket (S540).

According to various embodiments, the packet input/output event handler heuristic algorithm includes a step (S500) of creating a RAW socket for receiving a poll event and all packets transmitted to the control plane device (“vf0_0”) of the smart NIC (S500), The step of creating the RAW socket ( S500 ) may include the following steps:

A packet reception step (S600) of the smart NIC that is called by a poll event whenever it is ready to be received by the Roxylite application, and the step (S600) of the packet reception of the smart NIC may include the following steps:

Reading the SHIM header (LOX header) from the packet (S610);

Getting front port (receiving port) information from the LOX header (S620);

If the front port (receiving port) information does not exist, terminating the packet reception of the smart NIC (S630);

reading the flow from the original header of the packet (S640); and

Sending packet and flow information to all registered applications (S650).

Each time the Roxylite application transmits a packet to the smart NIC, the smart NIC transmits a packet (S700), which is called by a poll event, and the smart NIC transmits a packet (S700) may include the following steps :

obtaining the data path port dp_port from the front port (outgoing vif) (S710);

preparing a SHIM header (LOX header) using an outport as dp_port (S720);

merging the SHIM header and the packet into a local buffer (S730);

obtaining cp_fd from the control plane device (“vf0_0”) (S740); and

A delivery step of writing the contents of the merged local buffer to cp_fd as much as MAX_BUF_LEN (S750).

6 is a diagram schematically illustrating a method of processing a packet through an intelligent NIC-based networking solution according to various embodiments of the present disclosure.

According to various embodiments, the intelligent NIC-based networking solution 430 may include a software stack 14000, for example, a Loxilight software stack 14000 from NetLOX. have. The software stack 14000 may include all or a part of a P4 core compiler, an offload conflict resolver, and a function loader.

According to various embodiments, the function loader may compile logic data output from the compiler, for example, an extended Berkeley Packet Filter (eBPF) user program into eBPF bytecodes and load it into the data plane. The function load is the operating system kernel of the electronic device by using, for example, a low level virtual machine (LLVM) and/or a Clang compiler in a hardware block of an intelligent NIC or a hardware block of a general NIC by using the logic data output from the compiler. It can be loaded into a realm with XDP, loaded into the intelligent NIC's FPGA with a proprietary interface, or loaded into the intelligent NIC's network processor with a proprietary interface.

According to various embodiments, the intelligent NIC-based networking solution 430 may add a hook in the TC or XDP layer and control packet processing. For example, the hook may be placed in the NIC driver included in the data plane management module immediately after interrupt handling and before allocating memory required for the network stack itself.

According to various embodiments, when the intelligent NIC-based networking solution 430 executes a hook-up through the XDP layer for POD to POD or POD to outside traffic, it may not provide a performance gain. can

According to various embodiments, the intelligent NIC-based networking solution 430 may smoothly perform load balancing of phy-port to phy-port through the XDP layer.

According to various embodiments, the intelligent NIC-based networking solution 430 may boost packet processing performance by adding an eBPF hook in the TC layer.

7 is a diagram illustrating a first method of processing a packet through an intelligent NIC-based networking solution according to various embodiments of the present disclosure.

According to various embodiments, the intelligent NIC-based networking solution may use a slow-path for processing a packet. For example, a slow path may mean going through a multi-stage pipeline of the eBPF data plane. For example, a slow path is very flexible, but can require multiple memory lookups and can lead to performance degradation.

According to various embodiments, the slow path of the intelligent NIC-based networking solution may be as the following flow. For example, referring to FIG. 7 , in a slow path, a packet may arrive at an interface. Parsing can be performed through the Parser table. If a miss occurs in the meta-cache table, the SMAC, TMAC, and RTV tables may be progressed. Thereafter, when a miss occurs in the CT/FW4 table, the packet may be transferred to ConnTrack Mgr in user space. Through ConnTrack Mgr, the life cycle can be updated for each protocol and transmitted to the CT/FW4 table. For example, ConnTrack Mgr can maintain a 10-tuple based on a link table. ConnTrack Mgr may fill the CT/FW4 table with bidirectional traffic when a connection is established. Thereafter, the packet may be processed by proceeding to the NH, DMAC, and INTERFACE tables.

8 is a diagram illustrating a second method of processing a packet through an intelligent NIC-based networking solution according to various embodiments of the present disclosure.

According to various embodiments, the intelligent NIC-based networking solution may use a fast-path for processing a packet. For example, the fast path may mean processing a packet through only a multi-edge pipeline of the data plane without forwarding the packet to the user space.

According to various embodiments, a fast path of an intelligent NIC-based networking solution may be as follows. For example, referring to FIG. 8 , in a fast path, a packet may arrive at an interface. Parsing can be performed through the Parser table. If a miss occurs in the meta-cache table, the SMAC, TMAC, and RTV tables may be progressed. Thereafter, when a hit occurs in the CT/FW4 table, the packet may be processed by proceeding to the NH, DMAC, and INTERFACE tables without forwarding the packet to the ConnTrack Mgr of the user space.

9 is a diagram illustrating a third method of processing a packet through an intelligent NIC-based networking solution according to various embodiments of the present disclosure.

According to various embodiments, the intelligent NIC-based networking solution may use a cache-path for processing a packet. For example, the cache path may mean processing a packet by proceeding directly to the INTERFACE table without passing through the SMAC, TMAC, RTV, NH, and DMAC tables.

According to various embodiments, the cache path of the intelligent NIC-based networking solution may be as follows. For example, referring to FIG. 9 , in a cache path, a packet may arrive at an interface. Parsing can be performed through the Parser table. When a hit occurs in the meta-cache table, the packet header and metadata can be modified, and then, the packet can be processed by proceeding to the INTERFACE table.

A method of an electronic device according to various embodiments of the present disclosure includes: performing, in an edge node CPU including at least one core, a control plane for a network function including a virtualization function; and in an intelligent network interface card (NIC), at least a portion of a network function including the virtualization function in the at least one core by performing a data plane role for the network function including the virtualization function. An operation of offloading an operation, and the operation of performing a data plane role for a network function including the virtualization function includes receiving a packet through a first interface of the data plane movement; parsing the packet through a parser table; checking a meta-cache table based on the parsed packet; and when the parsed packet is checked in the meta cache table, modifying the header and meta data of the packet and transmitting the modified packet to the second interface.

When the parsed packet is not checked in the meta cache table, the operation of performing the role of a data plane for a network function including the virtualization function may include: SMAC protocol, TMAC protocol, RTV table, and transmitting via the CT/FW table; and transmitting the packet to a user area when the packet is not identified in the CT/FW table.

When the packet is checked in the CT/FW table, the method may include transmitting the packet through NH, DMAC, and the second interface without transmitting the packet to the user area.

The edge node CPU includes 24 cores, and the operation of performing the control plane role includes an operation of activating at least some of the cores of the edge node CPU, and the network function including the virtualization function. The operation of offloading at least a part of the operation may include an operation of inactivating the at least part of the core.

The intelligent NIC may be a software-based NIC.

The intelligent NIC may be a NIC implemented as a software defined network (SDN).

The intelligent NIC may be configured to operate as a compiler.

The operation of serving as a control plane for a network function including the virtualization function may include an operation of using a compiler in a software stack.

The operation of performing the role of a control plane for the network function including the virtualization function and the operation of performing the role of the data plane regarding the network function including the virtualization function are performed together in the edge node CPU It can be set not to run.

An electronic device according to various embodiments of the present disclosure includes: a software stack serving as a control plane for a network function including a virtualization function in an edge node CPU including at least one core; an intelligent NIC including a switch data plane unit serving as a data plane for network functions including the virtualization function; and an edge node CPU that offloads at least some operations related to network functions including the virtualization function in the at least one core, wherein the intelligent NIC includes: packet), parses the packet through a parser table, checks a meta-cache table based on the parsed packet, and When it is confirmed in the meta cache table, it may be configured to modify the header and metadata of the packet and transmit it to the second interface to serve as a data plane for network functions including the virtualization function.

The virtualization function offloaded from the switch data plane unit to the edge node CPU may further include a compiler for generating a binary code performed by the switch data plane unit.

The method may further include a data plane unit management module that transmits the binary code to the switch data plane unit to request execution.

The apparatus further includes the general NIC, wherein the data plane management module may request the general NIC to perform a non-virtualized network function.

A high-speed data path framework for offloading the virtualization function from the switch data plane unit to the edge node CPU may be further included.

The intelligent NIC may further include a field programmable gate array.

Claims (15)

A method for an electronic device, comprising:
In the edge node CPU including at least one core, the operation of performing a control plane (control plane) role with respect to a network function including a virtualization function; and
In an intelligent network interface card (NIC), at least some operations related to the network function including the virtualization function in the at least one core by serving as a data plane for the network function including the virtualization function Including;
The operation to serve as a data plane for a network function including the virtualization function is,
receiving a packet through a first interface of the data plane;
parsing the packet through a parser table;
checking a meta-cache table based on the parsed packet;
when the parsed packet is checked in the meta cache table, modifying a header and meta data of the packet and transmitting it to a second interface;
if the parsed packet is not checked in the meta cache table, transmitting the packet through a SMAC protocol, a TMAC protocol, an RTV table, and a CT/FW table;
transmitting the packet to a user area when the packet is not identified in the CT/FW table; and
and transmitting the packet through NH, DMAC, and the second interface without transmitting the packet to a user area when the packet is checked in the CT/FW table. delete delete The method of claim 1,
The edge node CPU includes 24 cores,
The operation of performing the control plane role is,
activating at least some of the cores of the edge node CPU,
The operation of offloading at least a part of an operation related to a network function including the virtualization function includes an operation of inactivating the at least part of the core. The method of claim 1,
wherein the intelligent NIC is a software-based NIC. 6. The method of claim 5,
The method of the electronic device, wherein the intelligent NIC is a NIC implemented with a software defined network (SDN). 7. The method of claim 6,
The intelligent NIC is a method of an electronic device configured to operate as a compiler. The method of claim 1,
The operation of performing the role of a control plane for a network function including the virtualization function includes using a compiler in a software stack. The method of claim 1,
The operation of performing the role of a control plane for the network function including the virtualization function and the operation of performing the role of the data plane regarding the network function including the virtualization function are performed together in the edge node CPU A method for an electronic device that is set to not run. a software stack serving as a control plane for network functions including virtualization functions in an edge node CPU including at least one core;
an intelligent NIC including a switch data plane unit serving as a data plane for network functions including the virtualization function; and
An edge node CPU for offloading at least some operations related to a network function including the virtualization function in the at least one core;
The intelligent NIC,
Receives a packet through the first interface of the data plane, parses the packet through a parser table, and a meta-cache table based on the parsed packet , and when the parsed packet is checked in the meta cache table, the header and meta data of the packet are modified and transmitted to the second interface, and when the parsed packet is not checked in the meta cache table , the packet is transmitted through the SMAC protocol, the TMAC protocol, the RTV table, and the CT/FW table,
If the packet is not identified in the CT/FW table, the packet is transmitted to the user area;
When the packet is checked in the CT/FW table, the packet is transmitted through NH, DMAC, and the second interface without transmitting the packet to the user area, so that the network function including the virtualization function An electronic device configured to act as a data plane for 11. The method of claim 10,
The electronic device further comprising a compiler that generates a binary code performed by the virtualization function offloaded to the edge node CPU from the switch data plane part in the switch data plane part. 12. The method of claim 11,
The electronic device further comprising: a data plane part management module that transmits the binary code to the switch data plane part and requests execution. 13. The method of claim 12,
It includes more general NICs,
The data plane management module will request the general NIC to perform a non-virtualized network function. 11. The method of claim 10,
The electronic device further comprising a high-speed data path framework for offloading the virtualization function from the switch data plane unit to the edge node CPU. 11. The method of claim 10,
wherein the intelligent NIC further comprises a field programmable gate array.

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