KR102408698B1 - Voltage Controller, Display Device and Method for driving thereof - Google Patents

Abstract

The voltage adjusting device of the present invention has an effect of preventing a decrease in luminance of a low grayscale image frame while improving luminance characteristics in a high grayscale image frame by changing a scan signal according to a high grayscale image frame or a low grayscale image frame.
In addition, the display device of the present invention includes a display panel, first and second gate drivers, a timing controller, and a voltage divider, and is a high grayscale image frame or a low grayscale image based on grayscale voltages corresponding to luminance control information for each image frame. By determining whether it is a frame and changing the scan signal, there is an effect of preventing a decrease in luminance of the low grayscale image frame.
In addition, the method for driving a display device of the present invention improves luminance characteristics in a high grayscale image frame by changing the scan signal supplied to the display panel according to the case where it is determined as the high grayscale image frame and when the low grayscale image frame is determined. There is an effect of preventing the decrease in luminance of the low grayscale image frame.

Description

Voltage controller, display device, and driving method thereof

The present invention relates to a voltage regulator, a display device, and a driving method thereof.

Recently, an organic light emitting display device, which has been in the spotlight as a display device, has advantages such as fast response speed, luminous efficiency, luminance, and viewing angle by using an organic light emitting diode (OLED) that emits light by itself.

In such an organic light emitting display device, pixels (subpixels) including organic light emitting diodes are arranged in a matrix form, and the brightness of the subpixels selected by a scan signal is controlled according to a gray level of data.

Each sub-pixel disposed on the display panel of the organic light emitting diode display basically includes a driving transistor for driving an organic light emitting diode, a switching transistor for transferring a data voltage to a gate node of the driving transistor, and maintaining a constant voltage for one frame time. It may be configured to include a storage capacitor or the like that serves to provide a function.

Recently, in order to reduce power consumption of an organic light emitting display device, a driving method using a Peak Luminance Control (PLC) algorithm that controls the maximum luminance of each image frame according to the input image signals (R, G, B) has been proposed. .

The method of driving an organic light emitting display device using a PLC algorithm is a technology of calculating an average picture level (APL) from an input image frame and determining a maximum luminance value according to the calculated APL value. Here, the PLC driving method reduces the power consumption of the organic light emitting display device by setting the luminance value to be lower as the APL value increases.

However, in the driving method to which the conventional PLC algorithm is applied, there is a problem in that when a low grayscale image frame is displayed, the screen quality is deteriorated due to a drop in the data voltage due to the kickback voltage ΔVp. In particular, when the PLC algorithm is applied, the difference between the gate high voltage and the gate low voltage is greatly changed to improve the high luminance and black display characteristics when displaying high and low grayscale image frames. ) increases, resulting in darkening defects in low-grayscale images.

The present invention provides a voltage adjusting device, a display device and a display device that improve luminance characteristics in a high-gradation image frame and prevent luminance deterioration of a low-gray image frame by changing gate voltages differently when driving a high-gradation image frame and a low-gradation image frame; An object of the present invention is to provide a driving method thereof.

In addition, the present invention improves turn-on and turn-off characteristics of a switching transistor by differently changing gate voltages corresponding to a high gray image frame having a high ratio of high gray voltages and a low gray image frame having a small ratio of low gray voltages. Another object is to provide a voltage regulator, a display device, and a driving method thereof.

In order to solve the problems of the prior art as described above, the voltage adjusting device of the present invention includes a storage unit for receiving brightness control information for a display panel and storing grayscale voltages corresponding to the brightness control information for each image frame, and the storage unit An arithmetic unit that calculates gradation voltages of the high gradation region and the gradation voltages of the low gradation region based on the stored gradation voltages for each image frame, and compares the calculated value of the operation unit with a preset reference value to determine whether the image frame is a high gradation image frame or a low gradation image and a determining unit that determines whether the frame is a frame, and a control unit that changes the scan signal supplied to the display panel according to the determination unit as a high grayscale image frame or a low grayscale image frame. This has the effect of preventing the decrease in luminance of the low grayscale image frame while improving the image quality.

Also, in the display device of the present invention, a display panel in which a plurality of data lines and a plurality of gate lines are disposed, a plurality of subpixels are disposed in a matrix type, and first and second gate drivers for driving the plurality of gate lines , a timing controller for controlling the first and second gate drivers, and a voltage divider for supplying scan signals to the first and second gate drivers; Voltage control for storing grayscale voltages corresponding to control information, determining whether an image frame is a high grayscale image frame or a low grayscale image frame based on the stored grayscale voltages, and changing a scan signal supplied from the voltage divider to the display panel By further including the part, there is an effect of preventing a decrease in luminance of a low grayscale image frame while improving the luminance characteristic of the high grayscale image frame.

In addition, the display device driving method of the present invention includes a display panel in which a plurality of data lines and a plurality of gate lines are disposed and a plurality of sub-pixels are disposed in a matrix type, and first and second driving the plurality of gate lines A method of driving a display device comprising: a second gate driver; a timing controller for controlling the first and second gate drivers; and a voltage divider for supplying a scan signal to the first and second gate drivers, wherein the display panel obtaining luminance control information for , receiving the obtained luminance control information and determining whether the image frame is a high grayscale image frame or a low grayscale image frame based on grayscale voltages corresponding to the brightness control information for each image frame; By changing the scan signal supplied to the display panel according to the case where it is determined as the high-grayscale image frame and the case where it is determined as the low-grayscale image frame, the luminance characteristic of the high-gradation image frame is improved and the luminance of the low-grayscale image frame is reduced. has a preventive effect.

A voltage adjusting device, a display device, and a driving method thereof according to the present invention change the gate voltage to be different from each other when driving a high grayscale image frame and a low grayscale image frame, thereby improving luminance characteristics in a high grayscale image frame and lowering the low grayscale image frame It has the effect of preventing the decrease in luminance.

In addition, the voltage adjusting device, the display device, and the driving method thereof according to the present invention change gate voltages corresponding to a high grayscale image frame having a high ratio of high gray voltages and a low grayscale image frame having a low ratio of low gray voltages differently from each other. By doing so, there is an effect of improving the turn-on and turn-off characteristics of the switching transistor.

1 is a schematic system configuration diagram of an organic light emitting diode display according to the present invention.
2 and 3 are exemplary views of a sub-pixel circuit of an organic light emitting diode display according to the present invention.
4 is a reference diagram for explaining a PLC algorithm.
5A and 5B are diagrams for explaining a dark defect occurring at an edge of a display panel when a low grayscale image frame is driven.
6 is a block diagram illustrating a voltage control system for changing a scan signal in an organic light emitting diode display according to the present invention.
7 is a diagram illustrating a state in which a scan signal for each image frame is changed by the voltage adjuster of FIG. 6 .
8A and 8B are diagrams for explaining improvement of a dark defect at an edge of a display panel when a low grayscale image frame is driven in the organic light emitting diode display according to the present invention.
9 is a diagram illustrating a relationship between luminance and grayscale voltage of sub-pixels of an organic light emitting diode display according to the present invention.
10 is a diagram illustrating a negative shift degree of a transistor according to a data voltage in an organic light emitting diode display according to the present invention.
11 is a diagram illustrating a method of driving an organic light emitting display device according to the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms. When it is described that a component is “connected”, “coupled” or “connected” to another component, the component may be directly connected or connected to the other component, but other components may be interposed between each component. It should be understood that each component may be “interposed” or “connected”, “coupled” or “connected” through another component.

1 is a schematic system configuration diagram of an organic light emitting diode display 100 according to the present invention.

Referring to FIG. 1 , the organic light emitting display device 100 according to the present exemplary embodiments includes a display panel 110 , a data driver 120 , a scan driver, a timing controller 140 , and each driver and a timing controller 140 . and a power distribution unit 150 for supplying a voltage to the . The scan driver includes a first gate driver 130a and a second gate driver 130b.

In the display panel 110 , a plurality of data lines DL and a plurality of gate lines GL are disposed in a direction crossing each other. Also, in the display panel 110 , a plurality of sub-pixels (SP) are arranged in a matrix type.

The data driver 120 drives the plurality of data lines by supplying data voltages to the plurality of data lines.

Each of the first and second gate drivers 130a and 130b sequentially drives the plurality of gate lines by sequentially supplying a scan signal to the plurality of gate lines. Here, the scan signal includes a gate high voltage VGH and a gate low voltage VGL.

The timing controller 140 supplies a control signal to the data driver 120 and the first and second gate drivers 130a and 130b to provide the data driver 120 and the first and second gate drivers 130a, 130b) is controlled.

The timing controller 140 starts scanning according to the timing implemented in each image frame, converts externally input image data to match the data signal format used by the data driver 120 , and outputs the converted image data. and control the data drive at an appropriate time according to the scan signal.

The first and second gate drivers 130a and 130b constituting the scan driver receive a plurality of scan signals (gate high voltage VGH) or gate low voltage VGL under the control of the timing controller 140 . A plurality of gate lines are sequentially driven by sequentially supplying them to the gate lines of

According to the driving method, as shown in FIG. 1 , the first and second gate drivers 130a and 130b may be positioned on both sides of the display panel 110 , or only one gate driver may be positioned on one side of the display panel 110 .

Also, each of the first and second gate drivers 130a and 130b may include one or more gate driver integrated circuits (GDICs), and the gate driver integrated circuits (GDICs) include shift registers, level shifters, and the like. may include

When a specific gate line is opened, the data driver 120 converts the image data received from the timing controller 140 into analog data voltage and supplies it to the data lines, thereby driving a plurality of data lines.

The data driver 120 may include one or more source driver integrated circuits (SDICs), also referred to as data driver integrated circuits (SDICs), and each of the source driver integrated circuits (SDICs) includes a shift register. , latches, digital-to-analog converters (DACs), output butters, and the like.

Also, in some cases, an analog-to-digital converter (ADC) for sensing an analog voltage value for sub-pixel compensation, converting it into a digital value, and generating and outputting sensed data may be further included.

Meanwhile, the timing controller 140 includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable (DE: Data Enable) signal, and a clock signal (CLK) together with image data of an input image from the outside. and receive various timing signals, including

The timing controller 140 converts the image data input from the outside to match the data signal format used by the data driver 120 to output the converted image data, and the data driver 120 , the first and second In order to control the gate drivers 130a and 130b, the data driver 120 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input DE signal, and a clock signal, and generates various control signals. ), and output to the first and second gate drivers 130a and 130b.

In particular, the timing controller 140 controls the scan signals (gate high voltage VGH and gate low voltage VGL) supplied from the voltage divider 150 to the first and second gate drivers 130a and 130b. . The voltage divider 150 may be implemented by a Power Management IC (PMIC).

Circuit elements, such as transistors and capacitors, are formed in each sub-pixel SP disposed on the display panel 110 schematically illustrated in FIG. 1 . For example, a circuit including an organic light emitting diode (OLED), two or more transistors, and one or more capacitors is formed in each subpixel on the display panel 110 .

Hereinafter, a sub-pixel circuit will be exemplarily described with reference to FIGS. 2 and 3 .

Referring to FIG. 2 , in the organic light emitting diode display 100 according to the present invention, each sub-pixel includes an organic light emitting diode (OLED) and a driving circuit.

The driving circuit may be basically composed of two transistors (a driving transistor (DRT), a switching transistor (SWT)) and one capacitor (a storage capacitor (Cstg)).

Referring to FIG. 2 , an organic light emitting diode (OLED) includes a first electrode (eg, an anode electrode or a cathode electrode), an organic layer, and a second electrode (eg, a cathode electrode or an anode electrode).

For example, in the organic light emitting diode OLED, a source node or a drain node of the driving transistor DRT may be electrically connected to a first electrode, and a ground voltage EVSS may be applied to a second electrode.

Referring to FIG. 2 , the driving transistor DRT is a transistor that supplies a driving current to the organic light emitting diode OLED to drive the organic light emitting diode OLED.

The driving transistor DRT includes a first node (N1 node) corresponding to a source node or drain node, a second node (N2 node) corresponding to a gate node, and a third node (N1 node) corresponding to a drain node or a source node. N3 node).

For example, in this driving transistor DRT, the N1 node may be electrically connected to the first electrode or the second electrode of the organic light emitting diode (OLED), and the N2 node is the source node or the drain node of the switching transistor SWT. It may be electrically connected, and the N3 node may be electrically connected to the driving voltage line DVL supplying the driving voltage EVDD.

Referring to FIG. 2 , the switching transistor SWT is a transistor that transfers the data voltage Vdata to the N2 node corresponding to the gate node of the driving transistor DRT.

The switching transistor SWT is controlled by a scan signal SCAN (gate high voltage VGH and gate low voltage VGL) applied to the gate node, and the N2 node of the driving transistor DRT and the data line DL ) are electrically connected between

Referring to FIG. 2 , the storage capacitor Cstg may be electrically connected between the N1 node and the N2 node of the driving transistor DRT.

The storage capacitor Cstg serves to maintain a constant voltage for one frame time.

Referring to FIG. 3 , a driving circuit in a subpixel having a compensation structure includes, for example, three transistors (a driving transistor (DRT), a switching transistor (SWT), a sensing transistor (SENT)) and one capacitor (storage). capacitor (Cstg)).

As described above, a sub-pixel including three transistors DRT, SWT, and SENT and one capacitor Cstg is said to have a “3T1C structure”.

Referring to FIG. 3 , the driving transistor DRT is a transistor that supplies a driving current to the organic light emitting diode OLED to drive the organic light emitting diode OLED.

In the driving transistor DRT, the N1 node may be electrically connected to the first electrode or the second electrode of the organic light emitting diode (OLED), and the N2 node may be electrically connected to the source node or the drain node of the switching transistor SWT. and the N3 node may be electrically connected to the driving voltage line DVL supplying the driving voltage EVDD.

Referring to FIG. 3 , the switching transistor SWT is a transistor that transfers the data voltage Vdata to the N2 node corresponding to the gate node of the driving transistor DRT.

The switching transistor SWT is controlled by a scan signal SCAN (gate high voltage VGH and gate low voltage VGL) applied to the gate node, and the N2 node of the driving transistor DRT and the data line DL ) are electrically connected between

Meanwhile, referring to FIG. 3 , the sensing transistor SENT newly added compared to the basic subpixel structure of FIG. 2 is controlled by a sense signal SENSE, which is a type of scan signal applied to the gate node, and a reference voltage line It may be electrically connected between a reference voltage line (RVL) and the N1 node of the driving transistor DRT.

The sensing transistor SENT is turned on to apply the reference voltage Vref supplied through the reference voltage line RVL to the N1 node (eg, a source node or a drain node) of the driving transistor DRT. .

In addition, the sensing transistor SENT serves to sense the voltage of the N1 node of the driving transistor DRT by the analog-to-digital converter ADC electrically connected to the reference voltage line RVL.

The role of the sensing transistor SETN is related to a compensation function for the intrinsic characteristic value of the driving transistor DRT. Here, the intrinsic characteristic value of the driving transistor DRT may include, for example, a threshold voltage (Vth), mobility, and the like.

4 is a reference diagram for explaining a PLC algorithm.

Referring to FIG. 4 , the organic light emitting display device 100 of the present invention has a lowest luminance (Lmin: for example, 150 nit) and a highest luminance (Lmax: for example, 500 nit) according to a driving method using a PLC algorithm. It is possible to implement an image with

PLC (Peak Luminance Control) algorithm calculates APL (Average Picture Level) and uses PLC to reduce power consumption and minimize the lifetime limit of organic light emitting diodes.

Here, the average picture level (APL) means an average image gradation voltage of an input image, and is a value obtained by dividing a difference between a reference white gradation voltage and a black gradation voltage of an input image of one image frame.

For example, a value obtained by normalizing each subpixel of the input image as a maximum value may be obtained by taking gamma and multiplying the luminance ratio of each subpixel as an average value. However, all known PLC algorithms are applicable to the organic light emitting display device of the present invention. As an example, the present invention can be applied to the PLC algorithm disclosed in Korean Patent Application Laid-Open No. 10-2006-0053903 (May 22, 2006).

PLC (Peak Luminance Control) algorithm calculates the APL (Average Picture Level) of each image frame, and applies the maximum luminance (PL: Peak Luminance) set according to the calculated APL (Average Picture Level) value to implement the input image. Algorithm that controls

For example, in FIG. 4 , when the APL (Average Picture Level) value of the input image frame is 35%, the maximum luminance PL is between Lmax and Lmin. When Lmax is 500 nits, the maximum luminance (PL) of 35% APL is about 450 nits.

Accordingly, an image can be realized by adjusting each grayscale (gray voltages) in the image frame by setting the maximum luminance of 450 nit for the input image frame, and as a result, power consumption of the organic light emitting diode display can be reduced.

The organic light emitting display device of the present invention determines whether an image frame is a high grayscale image frame or a low grayscale image frame based on luminance control information obtained by a PLC algorithm, and transmits scan signals to each other according to the high grayscale image frame and the low grayscale image frame. By making a different change, the luminance was improved in the high-grayscale image frame, while the deterioration of the image quality in the low-grayscale image frame was prevented.

5A and 5B are diagrams for explaining a dark defect occurring at an edge of a display panel when a low grayscale image frame is driven.

Referring to FIGS. 5A and 5B together with FIG. 3 , when the organic light emitting diode display device is driven using the PLC algorithm, it is supplied to the switching transistor SWT in order to improve the luminance characteristics of the image frame and the data voltage transfer characteristics. The deviation of the scan signal SCAN is increased.

For example, the gate high voltage VGH of the scan signal SCAN is higher and the gate low voltage VGL is lowered to improve the on/off characteristics of the switching transistor.

However, the data voltage (N2 node voltage) supplied through the data line DL is transferred to the N2 node by the operation of the switching transistor SWT, and the difference between the gate high voltage VGH and the gate low voltage VGL is If it is large, the kickback voltage ΔVp increases according to Equation 1, so that the N2 node voltage (data voltage) drops significantly in the emission period Te. Accordingly, the voltage difference between the N2 node and the N1 node is reduced in the light emission period Te, so that the luminance is reduced.

………….(수학식 1)

… … … … .(Equation 1)

(Cgs represents the parasitic capacitor formed between the gate electrode and the source electrode of the switching transistor)

That is, referring to FIG. 5A , the organic light emitting display device generates compensation data based on the sensing step of sensing the characteristic value of the driving transistor DRT for each sub-pixel, and the information obtained in the sensing step, and uses the data voltage (Vdata) can be divided into a writing step of supplying to the second node N2 and an emission step of emitting light from the organic light emitting diode (OLED).

That is, after the data voltage (N2 node voltage) in the writing period Tw is sharply decreased by the kickback voltage ΔVp at the data voltage to which the compensation value is applied or the gate low voltage, in the light emitting period Te, the required data voltage (dashed line) ), the luminance decreases because it emits light with a lower data voltage (solid line). In particular, in the case of a low grayscale image frame, since the overall data voltage is small, when such a large kickback voltage ΔVp is generated, a dark defect appears as shown in FIG. 5B .

Also, referring to FIG. 5B , as shown in FIG. 1 , when the organic light emitting diode display 100 has a structure in which the first and second gate drivers 130a and 130b are positioned on the left and right sides of the display panel 110 , the gate line It can be seen that, when output from the first and second gate drivers 130a and 130b, the difference between the gate high voltage and the gate low voltage is greatest due to the line resistance and line capacitance of GL. On the other hand, as the scan signal is transmitted to the central region of the display panel 110 , the gate high voltage becomes gentle.

Accordingly, when the low grayscale image frame is displayed on the display panel 110 , the dark defect due to the kickback voltage ΔVp is the greatest in the edge regions of both sides of the display panel 110 .

In the present invention, it is determined whether an image frame is a high grayscale image frame or a low grayscale image frame based on the luminance control information obtained by the PLC algorithm, and the gate high voltage and gate low voltage are different for each image frame, so that the high grayscale image frame When displaying , luminance is improved, and when displaying a low grayscale image frame, a dark defect as shown in FIG. 5B is prevented.

6 is a block diagram illustrating a voltage control system for changing a scan signal in an organic light emitting display device according to the present invention, and FIG. 7 is a diagram illustrating a state in which a scan signal for each image frame is changed by the voltage adjuster of FIG. 6 . it is one drawing

Referring to FIGS. 6 and 7 together with FIG. 1 , the organic light emitting diode display 100 of the present invention includes a display panel 110 , first and second gate drivers 130a and 130b , a data driver 120 , It includes a timing controller 140 and a voltage divider 150 .

In addition, the organic light emitting display device 100 of the present invention receives the luminance control information from the PLC algorithm (PLC) and the PLC algorithm (PLC) for obtaining the luminance control information for the display panel 110 described in FIG. The grayscale voltages corresponding to the luminance control information are stored for each frame, and it is determined whether the image frame is a high grayscale image frame or a low grayscale image frame based on the stored grayscale voltages, and is supplied from the voltage divider 150 to the display panel 110 . It further includes a voltage adjuster 600 for changing the scan signal.

The voltage adjuster 600 includes a storage unit 601 that stores grayscale voltages corresponding to luminance control information of a PLC algorithm (PLC) for each image frame, and a storage unit 601 based on the grayscale voltages for each image frame stored in the storage unit 601 . The operation unit 602 that calculates grayscale voltages in the high grayscale region and the grayscale voltages in the low grayscale region compares the calculated value of the operation unit 602 with a preset reference value to determine whether the image frame is a high grayscale image frame or a low grayscale image frame generating a control signal for changing the scan signal supplied to the display panel 110 according to the determination unit 603 for determining, and when it is determined as a high grayscale image frame or a low grayscale image frame by the determination unit 603 a control unit 604 .

More specifically, as described in FIG. 4 , the luminance control information supplied by the PLC algorithm (PLC) includes the information in which the gradation voltages are changed so that the luminance control information is applied to the maximum luminance (PL) set according to the calculated APL and APL values for each image frame. include Accordingly, the luminance control information includes each subpixel (red (R), green (G) and blue (B) subpixels or red (R), white (W), green (G) and blue (B) subpixels of the image frame. sub-pixels) and luminance information and grayscale voltage information.

The storage unit 601 of the voltage adjuster 600 stores grayscale voltages set in subpixels in each image frame based on the luminance control information. The calculator 602 calculates grayscale voltages according to grayscales for each image frame from the storage unit 601 , for example, red (R), white (W), green (G), and blue (B) included in the image frame. grayscale voltages for each grayscale (0 to 255 gray) may be calculated.

When the grayscale voltages are calculated by the operation unit 602, it is determined whether the image frame is a high grayscale image frame or a low grayscale image frame by comparing it with a preset reference value. For example, if the ratio of 4 grays to 32 grays among the grayscales of the image frame is equal to or greater than the reference value, it is determined as a low grayscale image frame, and the ratio of 200 to 255 grays among the grayscales of the image frame is higher than the reference value. If it is equal to or greater than the reference value, it may be determined as a high grayscale image frame. That is, the high grayscale image frame is a high luminance image frame that needs to increase the luminance, which is an image frame with many high grayscale voltages, and the low grayscale image frame is an image frame that needs to decrease the luminance, and it can be viewed as an image frame with many low grayscale voltages.

The reference value may be set to various reference values according to a structure of a display device, image data, a place of use, and the like. In addition, if the ratio of 4 grays to 32 grays among the gray levels of the image frame is equal to or greater than the reference value, the image frame is determined as a low gray level image frame, and other image frames are determined as high gray level image frames or the gray level range is divided into a plurality of gray levels. A plurality of low-grayscale image frames and high grayscale image frames may be set separately. When a plurality of image frames for each gray level are set, the scan signal may be driven with a different rate of change for each.

As described above, when the determination unit 603 determines whether the frame is a high grayscale image frame or a low grayscale image frame, the control unit 604 supplies a control signal to the voltage divider 150 based on this, and provides a scan signal (gate high voltage and gate low voltage).

Referring to FIG. 7 , when the image frame is determined to be a high grayscale image frame by the voltage adjuster 600 , the voltage divider 150 generates a gate high voltage VGH in response to a control signal from the controller 604 . The previous gate high voltage (dotted line) is higher (solid line), and the gate low voltage (VGL) is lower than the previous gate low voltage (dotted line). That is, for the high grayscale image frame, the luminance characteristic was improved by increasing the difference between the gate high voltage VGH and the gate low voltage VGL.

In addition, when it is determined as a high grayscale image frame to increase the deviation of the scan signal, the luminance characteristic may be improved by increasing only the gate high voltage VGH or decreasing only the gate low voltage VGL.

In addition, when the image frame is determined to be a low grayscale image frame by the voltage adjuster 600 , the voltage divider 150 transmits the gate high voltage VGH to the previous gate high voltage in response to the control signal of the controller 604 . (dotted line) is lower than (solid line), and the gate low voltage VGL is higher than the previous gate low voltage (dotted line). That is, for the low-gray image frame, the kickback voltage ΔVp is reduced by reducing the difference between the gate high voltage VGH and the gate low voltage VGL, thereby improving the dark defect occurring in the low gray image frame.

In addition, when it is determined that the scan signal is a low grayscale image frame in order to reduce the deviation of the scan signal, only the gate high voltage VGH or only the gate low voltage VGL is increased to improve the darkening defect in the low grayscale region. .

Accordingly, in the present invention, the difference between the gate high voltage VGH and the gate low voltage VGL is large when implementing the high grayscale image frame, but when implementing the low grayscale image frame, the gate high voltage VGH and the gate low voltage VGL ) is reduced, thereby improving the dark defect at both edges of the display panel 110 that occurs when displaying a low-grayscale image frame.

8A and 8B are diagrams for explaining improvement of a dark defect at an edge of a display panel when a low grayscale image frame is driven in the organic light emitting diode display according to the present invention.

Referring to FIGS. 8A and 8B together with FIG. 3 , when the organic light emitting diode display is driven using the PLC algorithm, as in FIG. 7 , different scan signals (SCAN) in the high grayscale image frame and the low grayscale image frame ), the difference between the gate high voltage VGH and the gate low voltage VGL is reduced in the low grayscale image frame.

Accordingly, the kickback voltage ΔVp is reduced in the low grayscale image frame, and accordingly, the data voltage drop degree of the N2 node also decreases.

As shown in FIG. 8A , the data voltage to which the compensation value is applied in the writing period Tw is decreased by the kickback voltage ΔVp of Equation 1, but does not decrease as rapidly as in FIG. 5A . Accordingly, since the organic light emitting diode emits light in a state in which the data voltage drop does not occur significantly in the light emission period Te, the dark defect in the low grayscale image frame is improved.

Also, referring to FIG. 8B , unlike in FIG. 5B , the scan signal supplied from both sides of the display panel 110 , that is, the gate high voltage VGH is decreased and the gate low voltage VGL is increased, so that the deviation is reduced. can see. In addition, even when only the gate high voltage VGH is lowered or only the gate low voltage VGL is increased, the deviation of the scan signal is reduced.

Accordingly, in the organic light emitting display device of the present invention, when the display panel 110 displays a low-grayscale image frame, the kickback voltage ΔVp in both edge regions of the display panel 110 is reduced to a small extent, and thus the data voltage N2 node) has the advantage of minimizing descent. As described above, when the drop of the data voltage (node N2) is reduced, since the organic light emitting diode can emit light with a data voltage almost close to the required data voltage (dotted line), darkening defects can be improved.

9 is a diagram illustrating the relationship between luminance and grayscale voltage of sub-pixels of an organic light emitting diode display according to the present invention, and FIG. 10 is a diagram illustrating a negative shift degree of a transistor according to a data voltage in an organic light emitting diode display according to the present invention. .

As shown in FIG. 9 , the organic light emitting diode display has pixels composed of red (R), green (G), and blue (B) subpixels or includes red (R), white (W), green (G) and In the case of having a pixel composed of blue (B) sub-pixels, the grayscale curve (gamma curve) in the luminance control information by applying the PLC algorithm for each color has a curve as shown in FIG. 9 .

That is, the grayscale curve has a shape in which the luminance increases as the grayscale voltages increase in red (R), white (W), green (G), and blue (B).

Accordingly, in the case of a high grayscale image frame having high luminance, since grayscale voltages have large values, it is desirable to increase the turn-on characteristic of the switching transistor in order to increase the luminance characteristic in the high grayscale image frame.

In the present invention, as described with reference to FIGS. 6 and 7 , an image frame having a high ratio of high gray voltages is determined as a high gray image frame, and when the high gray image frame is displayed, the gate high voltage VGH is increased or the gate When the low voltage VGL is lowered or the gate high voltage VGH is increased and the gate low voltage VGL is lowered, the luminance characteristic of the high grayscale image frame can be improved.

In addition, each sub-pixel of the organic light emitting diode display includes a switching transistor, a driving transistor, and a sensing transistor as shown in FIGS. 2 and 3 .

Although not shown in the drawings, a light shield (LS) is disposed in each transistor to prevent deterioration of the transistor performance due to light incident on the transistor.

However, there is a problem in that the threshold voltage Vth of each transistor is shifted due to the body effect of the light blocking layer LS, and thus the driving characteristics of the transistor are deteriorated.

FIG. 10 shows that as the voltage V connected to the source node of the switching transistor, that is, the data line DL, increases, the negative shift of the switching transistor SWT due to the body effect of the light blocking layer LS increases. .

When the threshold voltage Vth of the switching transistor SWT is negatively shifted, a problem occurs that the switching transistor is turned on even when the turn-off voltage is applied.

In the present invention, as described with reference to FIGS. 6 and 7 , when a high grayscale image frame with a high data voltage (grayscale voltage) is displayed, the gate low voltage VGL applied to the switching transistor SWT is lowered or the gate high voltage ( VGH) is increased and the gate low voltage (VGL) is lowered, so that the malfunction of the switching transistor due to the body effect can be improved as described above.

That is, although the threshold voltage Vth of the switching transistor SWT is lowered due to the high data voltage, the driving characteristics of the switching transistor SWT are not deteriorated even if a negative shift occurs because the gate low voltage VGL is lowered.

Similarly, in the low grayscale image frame, since the degree of negative shift of the switching transistor SWT is small, even if the gate low voltage VGL is increased, the driving characteristics of the switching transistor SWT due to the negative shift are not deteriorated.

As described above, in the present invention, by changing the scan signal differently according to the high grayscale image frame and the low grayscale image frame, it is possible to improve the performance degradation caused by the negative shift of the switching transistor SWT that may be additionally generated. .

11 is a diagram illustrating a method of driving an organic light emitting display device according to the present invention. As shown in FIG. 11, the organic light emitting display device driving method of the present invention uses the luminance control information obtained by the PLC algorithm with a voltage adjuster ( 600) is provided (S801), and based on this, grayscale voltages corresponding to luminance control information for each image frame are stored (S802).

Then, grayscale voltages for each grayscale (0 to 255 gray) included in the image frame are calculated, and based on this, it is determined whether the image frame is a high grayscale image frame or a low grayscale image frame (S803).

When it is determined that the image frame is a low grayscale image frame, the scan signals (gate high voltage and gate low voltage) are changed so that the gate high voltage supplied to the display panel 110 is decreased and the gate low voltage is increased ( S804 ). In addition, the deviation of the scan signal may be small by lowering only the gate high voltage VGH or increasing only the gate low voltage VGL.

By driving the organic light emitting diode display according to the changed scan signal, a dark defect caused by a large kickback voltage ΔVp when realizing a low grayscale image frame was improved.

On the other hand, when it is determined that the image frame is a high grayscale image frame, the deviation of the scan signal is greatly changed to increase the gate high voltage supplied to the display panel 110 and decrease the gate low voltage (S805). In addition, the deviation of the scan signal may be significantly changed by increasing only the gate high voltage VGH or decreasing only the gate low voltage VGL.

By driving the organic light emitting display device based on the changed scan signal corresponding to the high grayscale image frame, the high luminance image quality of the high grayscale image frame is improved.

As described above, in the voltage adjusting device, display device, and driving method thereof according to the present invention, the gate voltage is changed differently when driving a high grayscale image frame and a low grayscale image frame, thereby improving luminance characteristics in a high grayscale image frame while improving the low grayscale image frame. There is an effect of preventing a decrease in the luminance of the image frame.

In addition, the voltage adjusting device, the display device, and the driving method thereof according to the present invention change gate voltages corresponding to a high grayscale image frame having a high ratio of high gray voltages and a low grayscale image frame having a low ratio of low gray voltages differently from each other. By doing so, there is an effect of improving the turn-on and turn-off characteristics of the switching transistor.

The above description and the accompanying drawings are merely illustrative of the technical idea of the present invention, and those of ordinary skill in the art to which the present invention pertains can combine configurations within a range that does not depart from the essential characteristics of the present invention. , various modifications and variations such as separation, substitution and alteration will be possible. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: organic light emitting display device
120: data driving unit
130a: first gate driver
130b: second gate driver
140: timing controller
150: voltage divider
600: voltage regulator

Claims (23)

a storage unit receiving luminance control information for the display panel and storing grayscale voltages corresponding to luminance control information for each image frame;
an operation unit for calculating gray voltages in a high gray scale region and gray scale voltages in a low gray scale region based on gray voltages for each image frame stored in the storage unit;
a determination unit that compares the calculated value of the operation unit with a preset reference value to determine whether the image frame is a high grayscale image frame or a low grayscale image frame; and
and a control unit configured to change the scan signal supplied to the display panel according to a case in which the determination unit determines that the image frame is a high grayscale image frame or a low grayscale image frame. According to claim 1,
A voltage adjusting device for increasing a gate high voltage of the scan signal when the determination unit determines that the image frame is a high grayscale image frame. According to claim 1,
A voltage adjusting device for lowering a gate low voltage of the scan signal when the determination unit determines that the image frame is a high grayscale image frame. According to claim 1,
A voltage adjusting device for increasing a gate high voltage of the scan signal and decreasing a gate low voltage of the scan signal when the determining unit determines that the image frame is a high grayscale image frame. According to claim 1,
A voltage adjusting device for lowering a gate high voltage of the scan signal when the determination unit determines that the image frame is a low grayscale image frame. According to claim 1,
A voltage adjusting device for increasing a gate low voltage of the scan signal when the determination unit determines that the image frame is a low grayscale image frame. According to claim 1,
When the determination unit determines that the image frame is a low grayscale image frame, a voltage adjusting device for lowering a gate high voltage of the scan signal and increasing a gate low voltage of the scan signal. a display panel in which a plurality of data lines and a plurality of gate lines are disposed, and a plurality of subpixels are disposed in a matrix type;
first and second gate drivers for driving the plurality of gate lines;
a timing controller controlling the first and second gate drivers; and
and a voltage divider supplying a scan signal to the first and second gate drivers;
Receives luminance control information for the display panel, stores gradation voltages corresponding to luminance control information for each image frame, determines whether an image frame is a high gradation image frame or low gradation image frame based on the stored gradation voltages, and divides the voltage The display device further comprising a voltage adjusting unit for changing the scan signal supplied to the display panel from the distribution unit. 9. The method of claim 8,
The voltage regulator,
a storage unit for receiving the brightness control information and storing grayscale voltages corresponding to the brightness control information for each image frame;
an operation unit for calculating gray voltages in a high gray scale region and gray scale voltages in a low gray scale region based on gray voltages for each image frame stored in the storage unit;
a determination unit which compares the calculated value of the operation unit with a preset reference value to determine whether the image frame is a high grayscale image frame or a low grayscale image frame;
and a control unit configured to change the scan signal supplied to the display panel according to a case in which the determination unit determines that the image frame is a high grayscale image frame or a low grayscale image frame. 10. The method of claim 9,
When the determination unit determines that the image frame is a high grayscale image frame, the gate high voltage of the scan signal is increased. 10. The method of claim 9,
The display device lowers the gate low voltage of the scan signal when the determination unit determines that the image frame is a high grayscale image frame. 10. The method of claim 9,
A display device configured to increase a gate high voltage of the scan signal and decrease a gate low voltage of the scan signal when the determining unit determines that the image frame is a high grayscale image frame. 10. The method of claim 9,
The display device lowers the gate high voltage of the scan signal when the determination unit determines that the image frame is a low grayscale image frame. 10. The method of claim 9,
When the determination unit determines that the image frame is a low grayscale image frame, the gate low voltage of the scan signal is increased. 10. The method of claim 9,
When the determination unit determines that the image frame is a low grayscale image frame, the gate high voltage of the scan signal is lowered and the gate low voltage of the scan signal is increased. A display panel in which a plurality of data lines and a plurality of gate lines are disposed and a plurality of subpixels are disposed in a matrix type, first and second gate drivers driving the plurality of gate lines, and the first and second A method of driving a display device comprising: a timing controller for controlling a gate driver; and a voltage divider for supplying scan signals to the first and second gate drivers;
obtaining luminance control information for the display panel;
receiving the obtained luminance control information and determining whether the image frame is a high gradation image frame or a low gradation image frame based on gradation voltages corresponding to the luminance control information for each image frame; and
A display device driving method for changing a scan signal supplied to the display panel according to a case in which it is determined as the high grayscale image frame and a case in which the low grayscale image frame is determined. 17. The method of claim 16,
The step of determining whether the image frame is a high grayscale image frame or a low grayscale image frame includes:
storing the gradation voltages corresponding to the luminance control information for each image frame;
calculating gradation voltages in a high gradation region and gradation voltages in a low gradation region based on the stored gradation voltages for each image frame;
determining whether the image frame is a high grayscale image frame or a low grayscale image frame by comparing the calculated value calculated in the step of calculating the grayscale voltages of the high grayscale region and the grayscale voltages of the low grayscale region with a preset reference value Display device driving method. 17. The method of claim 16,
In the step of determining whether the image frame is a high grayscale image frame or a low grayscale image frame, when it is determined that the image frame is a high grayscale image frame, the gate high voltage of the scan signal is increased. 17. The method of claim 16,
In the step of determining whether the image frame is a high grayscale image frame or a low grayscale image frame, when it is determined that the image frame is a high grayscale image frame, a gate low voltage of the scan signal is lowered. 17. The method of claim 16,
In the step of determining whether the image frame is a high grayscale image frame or a low grayscale image frame, when it is determined that the image frame is a high grayscale image frame, the display device increases the gate high voltage of the scan signal and decreases the gate low voltage of the scan signal driving method. 17. The method of claim 16,
In the step of determining whether the image frame is a high grayscale image frame or a low grayscale image frame, when it is determined that the image frame is a low grayscale image frame, a gate high voltage of the scan signal is lowered. 17. The method of claim 16,
In the step of determining whether the image frame is a high grayscale image frame or a low grayscale image frame, when it is determined that the image frame is a low grayscale image frame, the gate low voltage of the scan signal is increased. 17. The method of claim 16,
In the step of determining whether the image frame is a high grayscale image frame or a low grayscale image frame, when it is determined that the image frame is a low grayscale image frame, the gate high voltage of the scan signal is lowered and the gate low voltage of the scan signal is increased. driving method.

Images