KR102391916B1 - Method for manufacturing semiconductor device - Google Patents

Abstract

The present invention relates to a method of manufacturing a 3D semiconductor memory device, and more particularly, to a method of manufacturing a 3D semiconductor memory device, comprising: forming a stacked structure including insulating layers and sacrificial layers alternately and repeatedly stacked on a substrate; forming a first lower layer and a first photoresist pattern on the laminate structure; etching the first lower layer using the first photoresist pattern as a mask to form a first lower pattern; and etching one end of the stacked structure using the first lower pattern as a mask to form the one end in a step shape. The first lower layer includes a novolac-based organic polymer, and the first photoresist pattern includes a polymer containing silicon.

Description

Method for manufacturing semiconductor device

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a three-dimensional semiconductor memory device.

In order to meet the excellent performance and low price demanded by consumers, it is required to increase the degree of integration of semiconductor devices. In the case of a semiconductor memory device, since the degree of integration is an important factor determining the price of a product, an increased degree of integration is particularly required. In the case of a conventional two-dimensional or planar semiconductor memory device, since the degree of integration is mainly determined by an area occupied by a unit memory cell, it is greatly affected by the level of a fine pattern forming technique. However, since ultra-expensive equipment is required for pattern miniaturization, the degree of integration of the 2D semiconductor memory device is increasing, but is still limited.

To overcome this limitation, three-dimensional semiconductor memory devices including memory cells arranged three-dimensionally have been proposed. However, for mass production of a 3D semiconductor memory device, a process technology capable of realizing reliable product characteristics while reducing a manufacturing cost per bit compared to that of a 2D semiconductor memory device is required.

An object of the present invention is to provide a method of manufacturing a semiconductor device using a bi-layer process of a photoresist pattern and an underlying layer.

According to a concept of the present invention, a method of manufacturing a semiconductor device includes: forming a stacked structure including insulating layers and sacrificial layers that are alternately and repeatedly stacked on a substrate; forming a first lower layer and a first photoresist pattern on the laminate structure; etching the first lower layer using the first photoresist pattern as a mask to form a first lower pattern; and etching one end of the stacked structure using the first lower pattern as a mask to form the one end in a step shape. The first lower layer may include a novolac-based organic polymer, and the first photoresist pattern may include a polymer containing silicon.

The silicone-containing polymer may include a unit represented by the following Chemical Formula 5.

[Formula 5]

In Formula 5, R ₁₀ is hydrogen, C1-C10 alkyl, C1-C10 alkenyl, C1-C10 alkynyl, C6-C10 aryl, adamantyl, C1-C5 alkyl-adamantyl, or C2-C6 lactone, t is an integer of 1 to 10, and the silicone-containing polymer may have a weight average molecular weight of 1,000 to 100,000.

The amount of silicon in the first photoresist pattern may be 10 wt% to 40 wt%.

The first lower layer may further include a crosslinking agent containing a compound of Formula 1 below.

[Formula 1]

In Formula 1, at least two of R ₄ OOC(CX ₂ ) _n -, R ₅ - and R ₆ OOC(CX ₂ ) _m - are different acid or ester groups, and R ₄ , R ₅ , R ₆ and X are each independently hydrogen or a non-hydrogen substituent, wherein the non-hydrogen substituent is a substituted or unsubstituted C1-10 alkyl, substituted or unsubstituted C2-10 alkenyl or C2-10 alkynyl, substituted or unsubstituted C1-10 alkanoyl, substituted or unsubstituted C1-10 alkoxy, epoxy, substituted or unsubstituted C1-10 alkylthio, substituted or unsubstituted C1-10 alkylsulfinyl, substituted or unsubstituted C1-10 alkyl sulfonyl, substituted or unsubstituted carboxy, substituted or unsubstituted -COO-C1-8 alkyl, substituted or unsubstituted C6-12 aryl, or substituted or unsubstituted 5-10 membered heteroalicyclic or It is a heteroaryl group, and n and m are the same as or different from each other, and each may be an integer greater than 0.

Forming the one end in the step shape may include repeating the cycle by using the following steps as one cycle. etching the at least one insulating layer exposed by the first lower pattern using the first lower pattern as a mask; etching at least one of the sacrificial layers under the at least one insulating layer; and trimming the first lower pattern to reduce its width and height.

Trimming the first photoresist pattern may include: reducing the width by a first length; and reducing the height by a second length, wherein the second length may be greater than the first length and less than 1.5 times the first length.

The cycle may be repeated until the lowermost insulating layer and the sacrificial layer of the stacked structure are etched.

One end of the stacked structure includes a first contact area adjacent to the cell array area, and a second contact area spaced apart from the cell array area with the first contact area interposed therebetween, wherein the first contact area includes the It is formed in the step shape by the first lower pattern, and the manufacturing method includes: forming a second lower pattern including a novolak-based organic polymer on the laminate structure; and etching the second contact region using the second lower pattern as a mask to form the second contact region in a step shape.

One end of the stacked structure includes a first contact region adjacent to the cell array region, and a second contact region spaced apart from the cell array region with the first contact region interposed therebetween, wherein the second contact region includes the It is formed in the step shape by the first lower pattern, and the manufacturing method includes: forming a second photoresist pattern on the laminate structure; and etching the first contact region using the second photoresist pattern as a mask to form the first contact region in a step shape, wherein the second photoresist pattern is represented by Chemical Formulas 2 and 3 below. It may contain units and optionally a copolymer including units of the following formula (4).

[Formula 2]

[Formula 3]

[Formula 4]

In Formulas 2 to 4, R ₇ to R ₉ are each independently hydrogen, a hydrocarbon having 1 to 20 carbon atoms, or a hydrocarbon having 1 to 20 carbon atoms substituted with -OR ₁₁ , wherein R ₁₁ is C1-C10 alkyl , C2-C10 alkenyl, C2-C10 alkynyl, C6-C10 aryl or C3-C10 cycloalkyl, wherein p is an integer from 1 to 10, q is an integer from 1 to 10, and r is from 1 to 10 is an integer, and the copolymer may have a weight average molecular weight of 1,000 to 100,000.

The manufacturing method may include forming channel holes exposing the substrate through a cell array region of the stacked structure; and sequentially forming a gate insulating film and a channel film covering an inner wall thereof in each of the channel holes.

The manufacturing method may include forming recess regions between the insulating layers by selectively removing the sacrificial layers; and forming gate electrodes filling the recess regions.

The shape of one end of the gate electrodes corresponds to the step shape that is the shape of one end of the sacrificial layers, and the manufacturing method includes passing through one end of at least one of the insulating layers, the end of at least one of the gate electrodes and the The method may further include forming electrically connected contacts.

According to another concept of the present invention, a method of manufacturing a semiconductor device includes: forming a stacked structure including insulating layers and sacrificial layers that are alternately and repeatedly stacked on a substrate; forming an organic polymer film and a photoresist film containing silicon on the organic polymer film on the laminate structure; exposing and developing the photoresist film to form a photoresist pattern; etching the organic polymer layer using the photoresist pattern as a mask to form an organic polymer pattern; and etching one end of the stacked structure using the organic polymer pattern as a mask to form the one end in a step shape. The thickness of the organic polymer layer may be 10 to 30 times the thickness of the photoresist layer.

The photoresist layer may include a polymer having a unit represented by the following Chemical Formula 5.

[Formula 5]

In Formula 5, R ₁₀ is hydrogen, C1-C10 alkyl, C1-C10 alkenyl, C1-C10 alkynyl, C6-C10 aryl, adamantyl, C1-C5 alkyl-adamantyl, or C2-C6 lactone, t is an integer of 1 to 10, and the polymer may have a weight average molecular weight of 1,000 to 100,000.

The organic polymer film may include a novolak-based polymer.

In the method of manufacturing a semiconductor device according to the present invention, dispersion of the lower pattern can be improved by using a double layer process of the photoresist pattern and the lower layer. Furthermore, a thick lower pattern may be formed using an organic polymer film having a high etch selectivity with respect to the photoresist pattern. Accordingly, a large number of step structures can be formed through a single photoresist process, so that an efficient process can be achieved.

1 is a simplified circuit diagram illustrating a cell array of a 3D semiconductor memory device according to embodiments of the present invention.
2 is a plan view of a 3D semiconductor memory device according to embodiments of the present invention.
3 is a cross-sectional view of a semiconductor memory device according to an exemplary embodiment of the present invention, and is a cross-sectional view taken along line I-I' of FIG. 2 .
4 to 23 are cross-sectional views for explaining a method of manufacturing a 3D semiconductor memory device according to embodiments of the present invention, and are cross-sectional views taken along line I-I' of FIG. 2 .
24 to 26 are cross-sectional views illustrating a method of manufacturing a 3D semiconductor memory device according to embodiments of the present invention, and are cross-sectional views taken along line II′ of FIG. 2 .

In order to fully understand the configuration and effect of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various forms and various modifications may be made. However, it is provided so that the disclosure of the present invention is complete through the description of the present embodiments, and to fully inform those of ordinary skill in the art to which the present invention belongs, the scope of the invention.

In this specification, when a component is referred to as being on another component, it may be directly formed on the other component or a third component may be interposed therebetween. In addition, in the drawings, the thickness of the components is exaggerated for effective description of the technical content. Parts indicated with like reference numerals throughout the specification indicate like elements.

Embodiments described herein will be described with reference to cross-sectional and/or plan views, which are ideal illustrative views of the present invention. In the drawings, thicknesses of films and regions are exaggerated for effective description of technical content. Accordingly, the regions illustrated in the drawings have a schematic nature, and the shapes of the illustrated regions in the drawings are intended to illustrate specific shapes of regions of the device and not to limit the scope of the invention. In various embodiments of the present specification, terms such as first, second, third, etc. are used to describe various components, but these components should not be limited by these terms. These terms are only used to distinguish one component from another. Embodiments described and illustrated herein also include complementary embodiments thereof.

The terminology used herein is for the purpose of describing the embodiments and is not intended to limit the present invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, the terms 'comprises' and/or 'comprising' do not exclude the presence or addition of one or more other components.

1 is a simplified circuit diagram illustrating a cell array of a 3D semiconductor memory device according to embodiments of the present invention.

Referring to FIG. 1 , a cell array of a 3D semiconductor memory device according to embodiments of the present invention includes a common source line CS, a plurality of bit lines BL, and the common source line CS and the bit line. It may include a plurality of cell strings CSTR disposed between the cells BL.

The common source line CS may be a conductive thin film disposed on a substrate or an impurity region formed in the substrate. In some embodiments, the common source line CS may be spaced apart from the substrate and may be conductive patterns (eg, a metal line) disposed on the substrate. The bit lines BL may be conductive patterns (eg, metal lines) spaced apart from the substrate and disposed on the substrate. In some example embodiments, the bit lines BL may be vertically spaced apart from each other while crossing the common source line CS. The bit lines BL are two-dimensionally arranged, and a plurality of cell strings CSTR may be connected in parallel to each of the bit lines BL. The cell strings CSTR may be commonly connected to the common source line CS. That is, a plurality of the cell strings CSTR may be disposed between the plurality of bit lines BL and the common source line CS. According to an embodiment, the common source line CS may be provided in plurality and may be two-dimensionally arranged. Here, the same voltage may be applied to the common source lines CS, or each of the common source lines CS may be electrically controlled.

Each of the cell strings CSTR includes a ground select transistor GST connected to the common source line CS, a string select transistor SST connected to the bit line BL, and the ground and string select transistors. It may include a plurality of memory cell transistors MCT disposed between the GST and SST. In addition, the ground select transistor GST, the string select transistor SST, and the memory cell transistors MCT may be connected in series.

The common source line CS may be commonly connected to sources of the ground select transistors GST. In addition, a lower select line LSL, a plurality of word lines WL0 - WL5 and an upper select line USL disposed between the common source line CS and the bit lines BL are connected to the ground It may be used as gate electrodes of the select transistor GST, the memory cell transistors MCT, and the string select transistor SST, respectively. In addition, each of the memory cell transistors MCT may include a data storage element.

2 is a plan view of a 3D semiconductor memory device according to embodiments of the present invention. 3 is a cross-sectional view of a semiconductor memory device according to an exemplary embodiment of the present invention, and is a cross-sectional view taken along line I-I' of FIG. 2 .

A substrate 100 may be provided. The substrate 100 may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate 100 may include common source regions CSL doped with impurities. The common source regions CSL may have a line shape extending in a second direction D2 parallel to the top surface of the substrate 100 . The common source regions CSL may be arranged along a first direction D1 crossing the second direction D2 .

First stacked structures ST1 and second stacked structures ST2 in which insulating layers 110 and gate electrodes LSL, WL1, WL2, and USL are alternately and repeatedly stacked on the substrate 100 This can be arranged. The second stacked structures ST2 may be respectively disposed on the first stacked structures ST1 . Each of the stack structures ST1 and ST2 may have a line shape extending in the second direction D2 in a plan view. Each of the stack structures ST1 and ST2 may be arranged in the first direction D1 .

The common source regions CSL may be disposed on the substrate 100 between the stacked structures ST1 and ST2 . A lower insulating layer 105 may be disposed between the substrate 100 and the first stacked structures ST1 . The lower insulating layer 105 may include, for example, a high dielectric layer such as a silicon nitride layer, an aluminum oxide layer, or a hafnium oxide layer. The lower insulating layer 105 may have a thickness smaller than that of the insulating layers 110 .

The gate electrodes LSL, WL1, WL2, and USL may be stacked in a third direction D3 perpendicular to both the first direction D1 and the second direction D2. The gate electrodes LSL, WL1, WL2, and USL may be vertically separated from each other by the insulating layers 110 disposed between the gate electrodes LSL, WL1, WL2, and USL. For example, the gate electrodes LSL and WL1 of each of the first stacked structures ST1 may include a lower selection line LSL and first word lines WL1 . The gate electrodes WL2 and USL of each of the second stacked structures ST2 may include an upper selection line USL and second word lines WL2 . For example, the gate electrodes LSL, WL1, WL2, and USL may include doped silicon, metal (eg, tungsten), metal nitride, metal silicides, or a combination thereof. The insulating layers 110 may include a silicon oxide layer.

The lower selection line LSL may be a gate electrode of a lowermost layer among the gate electrodes LSL and WL1 of each of the first stacked structures ST1 . The lower select line LSL may be used as a gate electrode of the ground select transistor GST described above with reference to FIG. 1 . The upper selection line USL may be a gate electrode of an uppermost layer among the gate electrodes WL2 and USL of each of the second stacked structures ST2 . The upper select line USL may be used as a gate electrode of the string select transistor SST described above with reference to FIG. 1 . The first and second word lines WL1 and WL2 may be used as gate electrodes of the memory cell transistors MCT described with reference to FIG. 1 .

Each of the stack structures ST1 and ST2 may include a cell array region CAR, a first contact region CTR1 and a second contact region CTR2. The first and second contact regions CTR1 and CTR2 may be disposed on at least one end of the stack structure ST1 and ST2. Here, the first contact region CTR1 may be a region of one end of the first stacked structure ST1 , and the second contact region CTR2 may be a region of one end of the second stacked structure ST2 . there is. For example, the second contact region CTR2 may be adjacent to the cell array region CAR. The first contact region CTR1 may be spaced apart from the cell array region CAR with the second contact region CTR2 interposed therebetween.

Each of the stacked structures ST1 and ST2 includes the first and second contact regions CTR1 for electrical connection between the gate electrodes LSL, WL1, WL2, USL and a peripheral logic structure thereof. CTR2) may have a stepwise structure. That is, vertical heights of the first and second contact regions CTR1 and CTR2 may gradually increase as they are adjacent to the cell array region CAR. In other words, the stack structures ST1 and ST2 may have a sloped profile in the first and second contact regions CTR1 and CTR2 .

The planar areas of the gate electrodes LSL and WL1 of the first contact region CTR1 may decrease as they move away from the top surface of the substrate 100 in the third direction D3 . Accordingly, the area of the lower selection line LSL of the lowermost layer among the gate electrodes LSL and WL1 may be the largest. A planar area of the gate electrodes WL2 and USL of the second contact region CTR2 may decrease as the distance from the top surface of the substrate 100 in the third direction D3 increases. Accordingly, the area of the upper selection line USL of the uppermost layer among the gate electrodes WL2 and USL may be the smallest.

A first interlayer insulating layer 180 covering the stacked structures ST1 and ST2 may be disposed on the entire surface of the substrate 100 . The first interlayer insulating layer 180 may have a planarized top surface and may cover the first and second contact regions CTR1 and CTR2 . A second interlayer insulating layer 190 may be disposed on the first interlayer insulating layer 180 .

A plurality of channel holes CH passing through the cell array region CAR of the stack structures ST1 and ST2 may be disposed. A plurality of channel layers 135 may extend toward the substrate 100 along inner walls of the channel holes CH, respectively. The channel layers 135 may be electrically connected to the substrate 100 . That is, the channel layers 135 may directly contact the top surface of the substrate 100 . The channel layers 135 may be arranged along the second direction D2 in a plan view. For example, the channel layers 135 may be arranged in one direction along the second direction D2 . As another example, the channel layers 135 may be arranged in a zigzag shape along the second direction D2 .

For example, the channel membranes 135 may have an open top and a bottom pipe shape or a macaroni shape. As another example, the channel membranes 135 may have a closed pipe shape or a macaroni shape.

The channel layers 135 may be in an undoped state or may be doped with an impurity having the same conductivity type as that of the substrate 100 . The channel layers 135 may include a semiconductor material having a polycrystalline structure or a single crystal structure. For example, the channel layers 135 may include silicon. An interior of the channel layers 135 may be filled with a buried insulating pattern 150 . For example, the buried insulating pattern 150 may include a silicon oxide layer.

Gate insulating layers 145 may be interposed between the stack structures ST1 and ST2 and the channel layers 135 . That is, each of the gate insulating layers 145 may directly cover the inner wall of the channel hole CH. The gate insulating layers 145 may extend in the third direction D3 . The gate insulating layers 145 may be in the form of a pipe having open top and bottom ends or a macaroni shape.

Each of the gate insulating layers 145 may include one thin film or a plurality of thin films. In an embodiment, the gate insulating layer 145 may include a tunnel insulating layer and a charge storage layer of a charge trap type flash memory transistor. The tunnel insulating layer may be one of materials having a band gap larger than that of the charge storage layer. For example, the tunnel insulating layer may be one of high-k layers such as an aluminum oxide layer and a hafnium oxide layer. The charge storage layer may be one of an insulating layer rich in trap sites such as a silicon nitride layer, a floating gate electrode, or an insulating layer including conductive nano dots. The tunnel insulating layer may directly contact the channel layer 135 . Meanwhile, although not shown, a blocking insulating layer may be interposed between each of the gate electrodes LSL, WL1, WL2, and USL and the charge storage layer. The blocking insulating layer may extend between each of the gate electrodes LSL, WL1, WL2, and USL and the insulating layer 110 . The blocking insulating layer may be one of materials having a band gap smaller than that of the tunnel insulating layer and larger than that of the charge storage layer. For example, the blocking insulating layer may be one of high-k layers such as an aluminum oxide layer and a hafnium oxide layer.

In another embodiment, the gate insulating layer 145 may include the tunnel insulating layer, the charge storage layer, and the blocking insulating layer. The tunnel insulating layer may directly contact the channel layer 135 , and the blocking insulating layer may directly contact the gate electrodes LSL, WL1, WL2, and USL. The charge storage layer may be interposed between the tunnel insulating layer and the blocking insulating layer. In this case, the gate electrodes LSL, WL1, WL2, and USL may directly contact the insulating layers 110 .

The buried insulating layer 170 may fill the trenches TR between the stacked structures ST1 and ST2 adjacent to each other. The buried insulating layer 170 may include a silicon oxide layer.

An upper portion of each of the channel layers 135 may include a drain region DR. Conductive pads 160 respectively contacting the drain regions DR of the channel layers 135 may be disposed. The second interlayer insulating layer 190 may cover the conductive pads 160 . Bit line plugs BPLG may be disposed through the second interlayer insulating layer 190 to be electrically connected to the conductive pads 160 . Bit lines BL may be disposed on the bit line plugs BPLG. Each of the bit lines BL may be electrically connected to the plurality of conductive pads 160 through the plurality of bit line plugs BPLG. The bit lines BL may have a line shape extending in the first direction D1 .

A wiring structure for electrically connecting the gate electrodes LSL, WL1, WL2, and USL and a peripheral logic structure may be disposed on the first and second contact regions CTR1 and CTR2.

Specifically, on the first contact region CTR1 , first contact plugs pass through the first and second interlayer insulating layers 180 and 190 and are respectively connected to ends of the gate electrodes LSL and WL1 . (PLG1) may be disposed. In addition, on the second contact region CTR2 , second contact plugs pass through the first and second interlayer insulating layers 180 and 190 and are respectively connected to ends of the gate electrodes WL2 and USL. (PLG2) may be placed. A vertical length of the first and second contact plugs PLG1 and PLG2 may be decreased as they are adjacent to the cell array region CAR. Top surfaces of the first and second contact plugs PLG1 and PLG2 may be coplanar.

In addition, first connection lines CL1 electrically connected to the first contact plugs PLG1 may be disposed on the second interlayer insulating layer 190 of the first contact region CTR1 . Second connection lines CL2 electrically connected to second contact plugs PLG2 may be disposed on the second interlayer insulating layer 190 of the second contact region CTR2 .

4 to 23 are cross-sectional views for explaining a method of manufacturing a 3D semiconductor memory device according to embodiments of the present invention, and are cross-sectional views taken along line I-I' of FIG. 2 .

2 and 4 , stacked structures ST1 and ST2 may be formed by alternately and repeatedly depositing the sacrificial layers HL1 and HL2 and the insulating layers 110 on the substrate 100 . . Specifically, the stacked structures ST1 and ST2 may include a first stacked structure ST1 on the substrate 100 and a second stacked structure ST2 on the first stacked structure ST1 . The first stacked structure ST1 may include first sacrificial layers HL1 , and the second stacked structure ST2 may include second sacrificial layers HL2 .

For example, the sacrificial layers HL1 and HL2 may be formed to have the same thickness. As another example, the lowermost and uppermost sacrificial layers HL1 and HL2 of the sacrificial layers HL1 and HL2 may be formed to be thicker than the sacrificial layers HL1 and HL2 disposed therebetween. The insulating layers 110 may have the same thickness, or some of the insulating layers 110 may have different thicknesses.

The sacrificial films HL1 and HL2 and the insulating films 110 are thermal chemical vapor deposition (Thermal CVD), plasma enhanced chemical vapor deposition (Plasma enhanced CVD), physical chemical vapor deposition (physical CVD) or atomic layer deposition ( It may be deposited using an atomic layer deposition (ALD) process. The sacrificial layers HL1 and HL2 may be formed of a silicon nitride layer, a silicon oxynitride layer, or a silicon layer. The sacrificial layers HL1 and HL2 may include a polycrystalline structure or a single crystal structure. The insulating layers 110 may be formed of a silicon oxide layer.

In addition, a lower insulating layer 105 may be formed between the substrate 100 and the first stacked structure ST1 . The lower insulating layer 105 may be formed of a material having a high selectivity with respect to the sacrificial layers HL1 and HL2 and the insulating layers 110 . For example, the lower insulating layer 105 may include a high dielectric layer such as a silicon nitride layer, an aluminum oxide layer, or a hafnium oxide layer. The lower insulating layer 105 may be formed to have a thickness smaller than that of the sacrificial layers HL1 and HL2 and the insulating layers 110 .

2 and 5 , channel holes CH exposing the substrate 100 through the stacked structures ST1 and ST2 may be formed. The channel holes CH may be disposed like the channel layers 135 described above with reference to FIGS. 2 and 3 .

Forming the channel holes CH includes forming a mask pattern having openings defining regions in which the channel holes CH will be formed on the stack structures ST1 and ST2, and etching the mask pattern. It may include etching the stacked structures ST1 and ST2 as a mask. After that, the mask patterns may be removed. Meanwhile, during the etching process, the upper surface of the substrate 100 may be over-etched. Accordingly, the upper surface of the substrate 100 may be recessed.

2 and 6 , a gate insulating layer 145 and a channel layer 135 may be formed to sequentially cover inner walls of each of the channel holes CH. For example, the gate insulating layer 145 may include a tunnel insulating layer and a charge storage layer. As another example, the gate insulating layer 145 may further include a blocking insulating layer. In this case, the blocking insulating layer may be interposed between the sacrificial layers HL1 and HL2 and the charge storage layer. The gate insulating layer 145 and the channel layer 135 may be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD), respectively. Subsequently, a filling insulating pattern 150 completely filling each of the channel holes CH may be formed.

2 and 7 , a first lower layer ULa1 and a first photoresist pattern PR1 may be formed on the second stacked structure ST2 . The first lower layer ULa1 may be formed to cover the entire surface of the second stacked structure ST2 . The first photoresist pattern PR1 may be formed on the cell array region CAR in which the channel layers 135 are positioned and the second contact region CTR2 adjacent to the cell array region CAR. there is. The first photoresist pattern PR1 may not vertically overlap the first contact region CTR1 spaced apart from the cell array region CAR with the second contact region CTR2 interposed therebetween.

Specifically, forming the first lower layer ULa1 may include coating an organic composition on the second stacked structure ST2 . The first lower layer ULa1 may have a first thickness TH1. The organic composition may include a novolac-based organic polymer. The organic composition may further include a crosslinking agent including a compound of Formula 1 below.

[Formula 1]

wherein at least two of R ₄ OOC(CX ₂ ) _n -, R ₅ - and R ₆ OOC(CX ₂ ) _m - may be different acid or ester groups, and R ₄ , R5, R6 and X are each independently hydrogen or non-hydrogen substituents. wherein the non-hydrogen substituent is substituted or unsubstituted C1-10 alkyl, substituted or unsubstituted C2-10 alkenyl or C2-10 alkynyl (eg, allyl, etc.), substituted or unsubstituted C1-10 alkanoyl , substituted or unsubstituted C1-10 alkoxy (eg methoxy, propoxy, butoxy, etc.), epoxy, substituted or unsubstituted C1-10 alkylthio, substituted or unsubstituted C1-10 alkylsulfinyl, substituted or unsubstituted C1-10 alkylsulfonyl, substituted or unsubstituted carboxy, substituted or unsubstituted -COO-C1-8 alkyl, substituted or unsubstituted C6-12 aryl (eg phenyl, naphthyl, etc.); Or it may be a substituted or unsubstituted 5- to 10-membered heteroalicyclic or heteroaryl group (eg, methylphthalimide, N-methyl-1,8-phthalimide, etc.). n and m may be equal to or different from each other and each may be an integer greater than zero.

Furthermore, the organic composition may further include a solvent, an acid (or an acid generator).

The solvent may include, for example, at least one of oxybutyric acid esters, glycol ethers, ethers having a hydroxyl group, esters, dibasic esters, propylene carbonates, and gamma-butyrolactones. .

The acid is, for example, p-toluenesulfonic acid, dodecylbenzenesulfonic acid, oxalic acid, phthalic acid, phosphoric acid, camphorsulfonic acid, 2,4,6-trimethylbenzenesulfonic acid, triisonaphthalenesulfonic acid, 5-nitro -o-Toluenesulfonic acid, 5-sulfosalicylic acid, 2,5-dimethylbenzylsulfonic acid, 2-nitrobenzenesulfonic acid, 3-chlorobenzenesulfonic acid, 3-bromobenzenesulfonic acid, 2-fluorocaprylsulfonic acid at least one of phonic acid, 1-naphthol-5-sulfonic acid, and 2-methoxy-4-hydroxy-5-benzoylbenzenesulfonic acid.

The acid generator may be a photoacid generator or a thermal acid generator. The photoacid generator is, for example, onium salt-based, nitrobenzyl-based, sulfonic acid ester-based, diazomethane-based, glyoxime-based, N-hydroxyimide sulfonic acid ester-based and halotriazine-based agents. may include at least one of The thermal acid generator may promote or enhance a crosslinking reaction during curing of the first lower layer ULa1. For example, the thermal acid generator is cyclohexyl p-toluenesulfonate, methyl p-toluenesulfonate, cyclohexyl 2,4,6-triisopropylbenzene sulfonate, 2-nitrobenzyl tosylate, tris(2 ,3-dibromopropyl)-1,3,5-triazine-2,4,6-trione, alkylesters of organic sulfonic acid and their salts, triethylamine salt of dodecylbenzenesulfonic acid, p -It may include at least one of the ammonium salt of toluenesulfonic acid.

Additionally, the organic composition may further include a surfactant, a leveling agent, a dye compound, and the like.

Forming the first photoresist pattern PR1 includes preparing a photoresist composition, applying the photoresist composition on the entire surface of the substrate 100 to form a photoresist film, and exposing the photoresist film and developing the first photoresist pattern PR1 .

The photoresist composition may contain silicon. Specifically, the photoresist composition is a polymer compound having a chemical formula of (R ₁ SiO _3/2 ) _l (R ₂ SiO _3/2 ) _m (R ₃ SiO _3/2 ) _n using siloxane as a backbone. may include In the above formula, R ₁ to R ₃ may each independently be hydrogen, or a substituted or unsubstituted hydrocarbon group having 1 to 20 carbon atoms (hydrocarbyl group). 1 may be an integer of 1 to 10, m may be an integer of 1 to 10, and n may be an integer of 1 to 10. The polymer compound may have a weight average molecular weight of 1,000 to 100,000. Finally, the amount of silicon in the first photoresist pattern PR1 may be 10 wt% to 40 wt%.

More specifically, in the polymer compound, the (R ₁ SiO _{3 / 2} ) _l unit, the (R ₂ SiO _3/2 ) _m unit, and the (R ₃ SiO _{3 / 2} ) _n unit are each independently represented by Formula 5 can have units of

[Formula 5]

In Formula 5, R ₁₀ is hydrogen, C1-C10 alkyl, C1-C10 alkenyl, C1-C10 alkynyl, C6-C10 aryl, adamantyl, C1-C5 alkyl-adamantyl, or It may be a C2-C6 lactone. The t may be an integer from 1 to 10.

For example, the polymer compound may include a polymer of Formula 6 below.

[Formula 6]

The ratio of l:m:n in Formula 6 is 40:30:30. The polymer of Formula 7 has a weight average molecular weight (Mw) of 20,000.

In addition, the photoresist composition may further include a radiation-sensitive acid-generating compound, an auxiliary resin, a plasticizer, a stabilizer, a colorant, a surfactant, and the like.

The first photoresist pattern PR1 may have a second thickness TH2 . In this case, the first thickness TH1 may be 10 to 30 times the second thickness TH2.

2 and 8 , a first lower pattern UL1 may be formed by anisotropically etching the first lower layer ULa1 using the first photoresist pattern PR1 as an etch mask. Accordingly, the first lower pattern UL1 may expose the first contact region CTR1 .

During the etching process of forming the first lower pattern UL1 , all of the first photoresist pattern PR1 may be removed. During the anisotropic etching process, an etch selectivity ratio of the first photoresist pattern PR1 to the first lower layer ULa1 may be 1:2 to 1:30. By adjusting the second thickness TH2 in consideration of the etching selectivity, all of the first photoresist pattern PR1 may be removed during the etching process. If the first photoresist pattern PR1 remains after the etching process, the first photoresist pattern PR1 that additionally conducts current may be removed.

Since the first photoresist pattern PR1 and the first lower layer ULa1 have a high etch selectivity to each other, the second thickness of the first photoresist pattern PR1 is Although TH2 is very small compared to the first thickness TH1, the first lower pattern UL1 may be formed. Furthermore, the sidewall of the first lower pattern UL1 may have a cross-sectional profile close to vertical due to the thin first photoresist pattern PR1 .

2 and 9 , the insulating layer 110 of the uppermost layer of the second contact region CTR2 and the second sacrificial layer HL2 of the uppermost layer are sequentially formed using the first lower pattern UL1 as an etch mask. can be etched with The etched insulating layer 110 and the etched second sacrificial layer HL2 may expose the other insulating layer 110 and the other second sacrificial layer HL2 below them.

2 and 10 , a trimming process may be performed on the first lower pattern UL1 . That is, an isotropic etching process may be performed on the first lower pattern UL1 . Accordingly, the width and height of the first lower pattern UL1 may be reduced. Specifically, during the trimming process, the width of the first lower pattern UL1 may be reduced by the first length T1 and the height may be reduced by the second length T2 .

The trimming process may be performed using an etchant capable of selectively removing the first lower pattern UL1. Due to the characteristics of the wet etching, a length in which a height of the first lower pattern UL1 is reduced may be greater than a length in which a width of the first lower pattern UL1 is reduced. This is because the exposed area of the upper surface of the first lower pattern UL1 is larger than the exposed area of the sidewall of the first lower pattern UL1.

Meanwhile, when the novolak-based organic polymer according to embodiments of the present invention is used, a decrease in the height of the first lower pattern UL1 may be minimized. Specifically, the second length T2 reduced during the trimming process may be greater than the first length T1 and less than 1.5 times the first length T1 .

The steps described above with reference to FIGS. 9 and 10 may constitute one cycle for forming the sidewall of the second contact region CTR2 in a stepped structure. That is, in the cycle, at least one of the insulating layers 110 and at least one of the second sacrificial layers exposed by the first lower pattern UL1 using the first lower pattern UL1 as a mask etching the HL2 ) and trimming the first lower pattern UL1 to reduce the width and height thereof. It is described below that the cycle is repeated.

2 and 11 , the uppermost insulating layer 110 may be etched using the first lower pattern UL1, which has been reduced in size, as an etch mask. At the same time, the uppermost insulating layer 110 and the insulating layer 110 exposed by the second sacrificial layer HL2 may be etched together. Subsequently, the uppermost second sacrificial layer HL2 may be etched using the first lower pattern UL1 as an etch mask. At the same time, the lower second sacrificial layer HL2 exposed by the uppermost second sacrificial layer HL2 may be etched together. The etched insulating layers 110 and the etched second sacrificial layers HL2 may expose the other insulating layer 110 and the other second sacrificial layer HL2 below them.

2 and 12 , a trimming process may be performed again on the first lower pattern UL1. During the trimming process, the width of the first lower pattern UL1 may be reduced by the first length T1 and the height may be reduced by the second length T2 . Accordingly, it can be confirmed that the cycle is repeated once more.

2 and 13 , the cycle may be repeated until the insulating layer 110 and the second sacrificial layer HL2 of the lowermost layer of the second contact region CTR2 are etched. Accordingly, a portion of the upper surface of the insulating layer 110 of the uppermost layer of the first contact region CTR1 may be exposed.

Through repetition of the cycle using the first lower pattern UL1 , one end of the second stack structure ST2 (ie, the second contact region CTR2 ) may have a stepped structure. In addition, the size of the first photoresist pattern PR1 may be very small due to the repeated trimming process.

2 and 14 , after the remaining first lower pattern UL1 is removed, a second lower layer ULa2 covering the stacked structures ST1 and ST2 may be formed. The second lower layer ULa2 may be formed by coating the above-described organic composition on the stack structures ST1 and ST2. Since the second lower layer ULa2 may have a uniform thickness, it may be inclined on the second contact region CTR2 . The second lower layer ULa2 may have a third thickness TH3.

A second photoresist pattern PR2 may be formed on the second lower layer ULa2 . The second photoresist pattern PR2 may be formed on the cell array region CAR, the second contact region CTR2 , and the first contact region CTR1 . The second photoresist pattern PR2 may be formed using the above-described photoresist composition containing silicon. The second photoresist pattern PR2 may have a fourth thickness TH4, and in this case, the third thickness TH3 may be 10 to 30 times the fourth thickness TH4.

2 and 15 , the second lower layer ULa2 may be anisotropically etched using the second photoresist pattern PR2 as an etch mask to form a second lower pattern UL2 . The second lower pattern UL2 may expose the insulating layers 110 and the first sacrificial layers HL1 outside the first contact region CTR1 . During the etching process of forming the second lower pattern UL2 , the second photoresist pattern PR2 may be completely removed.

2 and 16 , the insulating layer 110 of the uppermost layer and the first sacrificial layer HL1 of the uppermost layer of the first contact region CTR1 are sequentially formed using the second lower pattern UL2 as an etch mask. can be etched with The etched insulating layer 110 and the etched first sacrificial layer HL1 may expose the other insulating layer 110 and the other first sacrificial layer HL1 below them.

2 and 17 , a trimming process may be performed on the second lower pattern UL2 . During the trimming process, the width of the second lower pattern UL2 may be reduced by the first length T1 and the height may be reduced by the second length T2 .

That is, the steps described above with reference to FIGS. 16 and 17 may be the same as one cycle described with reference to FIGS. 9 and 10 above. The cycle can then be repeated.

Referring to FIGS. 2 and 18 , the uppermost insulating layer 110 may be etched using the second lower pattern UL2, which has been reduced in size once, as an etch mask. At the same time, the uppermost insulating layer 110 and the insulating layer 110 exposed by the first sacrificial layer HL1 may be etched together. Subsequently, the uppermost first sacrificial layer HL1 may be etched using the second lower pattern UL2 as an etch mask. At the same time, the lower first sacrificial layer HL1 exposed by the uppermost first sacrificial layer HL1 may be etched together.

2 and 19 , a trimming process may be performed again on the second lower pattern UL2. Accordingly, it can be confirmed that the cycle is repeated once more.

2 and 20 , the cycle may be repeated until the insulating layer 110 and the first sacrificial layer HL1 of the lowermost layer of the first contact region CTR1 are etched. Accordingly, a portion of the upper surface of the lower insulating layer 105 may be exposed. Through repetition of the cycle using the second lower pattern UL2 , one end of the first stacked structure ST1 (ie, the first contact region CTR1 ) may have a stepped structure. In addition, the size of the second lower pattern UL2 may be very small due to the repeated trimming process.

2 and 21 , after the remaining second lower pattern UL2 is removed, a first interlayer insulating layer 180 covering the stacked structures ST1 and ST2 is formed on the substrate 100 . can The first interlayer insulating layer 180 may be formed to cover the first and second contact regions CTR1 and CTR2 . The first interlayer insulating layer 180 may be planarized to expose a top surface of the second stacked structure ST2 .

Subsequently, by patterning the stack structures ST1 and ST2 , trenches TR exposing the substrate 100 may be formed between adjacent channel holes CH. Specifically, forming the trenches TR includes forming mask patterns defining planar positions at which the trenches TR are to be formed on the stack structures ST1 and ST2, and forming the mask patterns It may include etching the stacked structures ST1 and ST2 using an etch mask.

The trenches TR may be formed to expose sidewalls of the sacrificial layers HL1 and HL2 and the insulating layers 110 . In a vertical depth, the trenches TR may be formed to expose a sidewall of the lower insulating layer 105 . Also, although not shown, the trenches TR may have different widths according to a vertical distance from the substrate 100 by an anisotropic etching process.

As the trenches TR are formed, the stacked structures ST1 and ST2 may be divided into a plurality. Each of the stack structures ST1 and ST2 may have a line shape extending in the second direction D2 . One of the stack structures ST1 and ST2 may be penetrated by the plurality of channel layers 135 .

2 and 22 , recess regions 155 may be formed by selectively removing the sacrificial layers HL1 and HL2 exposed by the trenches TR. The recess regions 155 may correspond to regions from which the sacrificial layers HL1 and HL2 have been removed. When the sacrificial layers HL1 and HL2 include a silicon nitride layer or a silicon oxynitride layer, the removal process of the sacrificial layers HL1 and HL2 may be performed using an etching solution containing phosphoric acid. A portion of a sidewall of the gate insulating layer 145 may be exposed by the recess regions 155 .

2 and 23 , gate electrodes LSL, WL1, WL2, and USL filling the recess regions 155 may be formed. Specifically, in forming the gate electrodes LSL, WL1, WL2, and USL, a conductive layer filling the recess regions 155 is formed, and then the conductive layer formed outside the recess regions 155 is formed. removing the membrane.

After the gate electrodes LSL, WL1, WL2, and USL are formed, common source regions CSL may be formed on the substrate 100 . The common source regions CSL may be formed through an ion implantation process, and may be formed in the substrate 100 exposed by the trenches TR. The common source regions CSL may form a PN junction with the substrate 100 . Subsequently, drain regions DR may be respectively formed on the channel layers 135 through an ion implantation process.

If the gate insulating layer 145 includes a tunnel insulating layer and a charge storage layer, blocking filling a portion of the recess regions 155 before forming the gate electrodes LSL, WL1, WL2, and USL An insulating film (not shown) may be additionally formed. Thereafter, the gate electrodes LSL, WL1, WL2, and USL completely filling the recess regions 155 may be formed on the blocking insulating layer.

Referring back to FIGS. 2 and 3 , a buried insulating layer 170 filling the trenches TR may be formed. The buried insulating layer 170 may include a silicon oxide layer.

Conductive pads 160 contacting top surfaces of the channel layers 135 may be formed, respectively. Subsequently, a second interlayer insulating layer 190 covering the filling insulating layer 170 , the conductive pads 160 , and the first interlayer insulating layer 180 may be formed. Bit line plugs BPLG in contact with the conductive pads 160 may be formed through the second interlayer insulating layer 190 .

Meanwhile, first contact plugs PLG1 respectively connected to the gate electrodes LSL and WL1 of the first contact region CTR1 may be formed through the second interlayer insulating layer 190 . Second contact plugs PLG2 respectively connected to the gate electrodes WL2 and USL of the second contact region CTR2 may be formed through the second interlayer insulating layer 190 .

Bit lines BL extending in the first direction D1 may be formed on the second interlayer insulating layer 190 . Each of the bit lines BL may connect a plurality of the bit line plugs BPLG to each other. In addition, first and second connection lines CL1 and CL2 contacting the first and second contact plugs PLG1 and PLG2, respectively, may be formed on the second interlayer insulating layer 190 .

According to embodiments of the present invention, a lower pattern with improved dispersion may be formed using a bi-layer process of the photoresist pattern and the lower layer. Furthermore, since the lower pattern can be formed thickly, a large number of step structures can be formed through a single photoresist process, thereby achieving an efficient process.

24 to 26 are cross-sectional views for explaining a method of manufacturing a 3D semiconductor memory device according to embodiments of the present invention, and are cross-sectional views taken along line I-I' of FIG. 2 . In this embodiment, a detailed description of technical features overlapping with the method of manufacturing a semiconductor device described above with reference to FIGS. 4 to 23 will be omitted, and differences will be described in detail.

2 and 24 , a third photoresist pattern PR3 may be formed on the resultant of FIG. 6 . Unlike FIG. 7 described above, the first lower layer ULa1 may be omitted, and the third photoresist pattern PR3 may directly cover the upper surface of the second stacked structure ST2 . Specifically, the third photoresist pattern PR3 may be formed on the cell array region CAR and the second contact region CTR2 . The third photoresist pattern PR3 may expose the first contact region CTR1 .

Specifically, forming the third photoresist pattern PR3 includes preparing a photoresist composition, applying the photoresist composition on the entire surface of the substrate 100 to form a photoresist film, and the photoresist composition It may include exposing and developing the resist layer to form the third photoresist pattern PR3 .

Here, the photoresist composition may include an organic polymer based on poly(4-hydroxystyrene) (PHS), unlike the photoresist composition described above with reference to FIG. 7 . Specifically, preparing the photoresist composition involves performing a polymerization reaction on a mixture containing substituted or unsubstituted 4-hydroxystyrene and acrylate to synthesize a copolymer. may include 4-hydroxystyrene or acrylate may be substituted with a hydrocarbon to be described later. Here, before the polymerization reaction, the weight ratio of 4-hydroxystyrene: acrylate in the mixture may be 95:5 to 60:40. More specifically, the weight ratio of 4-hydroxystyrene: acrylate in the mixture may be 90:10 to 80:20.

The synthesized copolymer may include units of Chemical Formulas 2 and 3 below. The synthesized copolymer may optionally further include a unit represented by the following formula (4).

[Formula 2]

[Formula 3]

[Formula 4]

In Formulas 2 to 4, R ₇ to R ₉ may each independently be hydrogen or a substituted or unsubstituted hydrocarbon group having 1 to 20 carbon atoms (hydrocarbyl group). The hydrocarbon may be selected from the group consisting of alkyl, alkenyl, alkynyl, cycloalkyl, cycloalkyl substituted with alkyl, aryl, aralkyl and alkaryl. The hydrocarbon may be substituted with -OR ₁₁ . and R ₁₁ is C1-C10 alkyl, C2-C10 alkenyl, C2-C10 alkynyl, C6-C10 aryl or C3-C10 cycloalkyl. For example, the hydrocarbon may be substituted with alkoxy. The hydrocarbon may be an alkyl ether having one or more alkyl ether groups or alkylene oxy groups. The alkyl ether group may be selected from the group consisting of ethoxy, propoxy and butoxy. Wherein p may be an integer of 1 to 10, q may be an integer of 1 to 10, and r may be an integer of 1 to 10. The fraction of p (p/(p+q+r)) may be 0.4 to 0.6, the fraction of q (q/(p+q+r)) may be 0.5 to 0.2, and the fraction of r (r/(p+q+r)) may be 0.2 to 0.4. The copolymer may have a weight average molecular weight of 1,000 to 100,000.

For example, the copolymer may include a polymer of Formula 7 below.

[Formula 7]

The ratio of P:q:r in Formula 7 is 55:15:30. The copolymer of Formula 7 has a weight average molecular weight (Mw) of 15,000. The copolymer of Formula 7 may be prepared by free radical polymerization, but is not limited thereto. As another example, the copolymer may be prepared by anion polymerization.

Preparing the photoresist composition may include mixing the synthesized copolymer with a radiation-sensitive acid-generating compound and a tertiary aliphatic amine compound in an organic solvent. can

The radiation-sensitive acid generator may be a compound that is dissociated by irradiation with actinic rays to generate an acid. The radiation-sensitive acid generator may be an onium salt compound having a fluoroalkylsulfonic acid ion having 1 to 10 carbon atoms as an anion. For example, the radiation-sensitive acid generator is diphenyliodonium trifluoromethanesulfonate and nonafluorobutanesulfonate (diphenyliodonium trifluoromethanesulfonate and nonafluorobutanesulfonate), or bis (4-tert-butylphenyl) iodine tri fluoromethanesulfonate and nonafluorobutanesulfonate (bis(4-tert-butylphenyl)iodonium trifluoromethanesulfonate and nonafluorobutanesulfonate).

The tertiary aliphatic amine compound may improve the cross-sectional profile of the photoresist pattern after exposure to actinic rays and improve stability thereof. For example, the tertiary aliphatic amine compound is trimethylamine, triethylamine, tri-n-propylamine, triisopropylamine, tri-n-butylamine, triisobutylamine, tri-tert-butylamine, tripentylamine amine, triethanolamine, tributanolamine, or combinations thereof.

In the photoresist composition, the amount of the radiation-sensitive acid generator may be 1 to 10 parts by weight, and the tertiary aliphatic amine compound may be 0.01 to 1 part by weight based on 100 parts by weight of the copolymer.

In addition, in order to improve the performance of the photoresist film, an auxiliary resin, a plasticizer, a stabilizer, a colorant and a surfactant may be further added to the photoresist composition.

2 and 25 , the insulating layer 110 of the uppermost layer and the second sacrificial layer HL2 of the uppermost layer of the second contact region CTR2 are formed using the third photoresist pattern PR3 as an etch mask. It can be etched sequentially. The etched insulating layer 110 and the etched second sacrificial layer HL2 may expose the other insulating layer 110 and the other second sacrificial layer HL2 below them.

2 and 26 , a trimming process may be performed on the third photoresist pattern PR3 . That is, an isotropic etching process may be performed on the third photoresist pattern PR3 . Accordingly, the width and height of the third photoresist pattern PR3 may be reduced. Specifically, during the trimming process, the width of the third photoresist pattern PR3 may be reduced by the third length T3 and the height may be reduced by the fourth length T4 .

The trimming process may be performed using an etchant capable of selectively removing the third photoresist pattern PR3 . Meanwhile, when the PHS-based photoresist composition according to the embodiments of the present invention is used, a decrease in the height of the third photoresist pattern PR3 may be minimized. Specifically, the fourth length T4 reduced during the trimming process may be greater than the third length T3 and less than 1.5 times the third length T3 . This may be similar to the result of the trimming process of the first lower pattern UL1 described above with reference to FIG. 10 .

The steps described above with reference to FIGS. 25 and 26 may constitute one cycle for forming the sidewall of the second contact region CTR2 in a stepped structure. Subsequently, the cycle may be repeated until the insulating layer 110 and the second sacrificial layer HL2 of the lowermost layer of the second contact region CTR2 are etched. Thereafter, the same process as described above with reference to FIGS. 14 to 23 may be performed.

When the PHS-based third photoresist pattern PR3 according to the present embodiment is used, the sidewall of the second contact region CTR2 may be formed in a stepped structure without an additional lower layer. Accordingly, a more efficient process can be achieved. However, when the stepwise structure is subsequently formed on the sidewall of the first contact region CTR1 , the above-described double layer process of the photoresist pattern and the lower layer may be used. This is because pattern distribution may be poor due to the stepped structure of the second contact region CTR2, and the combination process may improve pattern distribution.

Claims (10)

forming a laminate structure including insulating films and sacrificial films alternately and repeatedly laminated on a substrate;
forming a first lower layer and a first photoresist pattern on the laminate structure;
forming a first lower pattern by etching the first lower layer using the first photoresist pattern as a mask; and
Etching one end of the stacked structure using the first lower pattern as a mask to form the one end in a step shape,
The first lower layer includes a novolac-based organic polymer,
The first photoresist pattern includes a polymer including a unit represented by the following Chemical Formula 5,
[Formula 5]

In Formula 5, R ₁₀ is hydrogen, C1-C10 alkyl, C1-C10 alkenyl, C1-C10 alkynyl, C6-C10 aryl, adamantyl, C1-C5 alkyl-adamantyl, or C2-C6 lactone;
Wherein t is an integer from 1 to 10,
The method of manufacturing a semiconductor device, wherein the silicon-containing polymer has a weight average molecular weight of 1,000 to 100,000.
delete According to claim 1,
The method of manufacturing a semiconductor device in which silicon in the first photoresist pattern is 10 wt% to 40 wt%.
According to claim 1,
The method of manufacturing a semiconductor device, wherein the first lower layer further comprises a crosslinking agent containing a compound of Formula 1:
[Formula 1]

In Formula 1, at least two of R ₄ OOC(CX ₂ ) _n -, R ₅ -, and R ₆ OOC(CX ₂ ) _m - are different acid or ester groups,
R ₄ , R ₅ , R ₆ and X are each independently hydrogen or a non-hydrogen substituent;
The non-hydrogen substituent is substituted or unsubstituted C1-10 alkyl, substituted or unsubstituted C2-10 alkenyl or C2-10 alkynyl, substituted or unsubstituted C1-10 alkanoyl, substituted or unsubstituted C1 -10 alkoxy, epoxy, substituted or unsubstituted C 1-10 alkylthio, substituted or unsubstituted C 1-10 alkylsulfinyl, substituted or unsubstituted C 1-10 alkylsulfonyl, substituted or unsubstituted carboxy, substituted or an unsubstituted -COO-C1-8 alkyl, a substituted or unsubstituted C6-12 aryl, or a substituted or unsubstituted 5-10 membered heteroalicyclic or heteroaryl group;
n and m are equal to or different from each other and each is an integer greater than 0.
According to claim 1,
Forming the one end in the step shape includes repeating the cycle by using the following steps as one cycle:
etching the at least one insulating layer exposed by the first lower pattern using the first lower pattern as a mask;
etching at least one of the sacrificial layers under the at least one insulating layer; and
trimming the first lower pattern to reduce its width and height.
6. The method of claim 5,
Trimming the first lower pattern comprises:
reducing the width by a first length; and
reducing the height by a second length;
The second length is greater than the first length and less than 1.5 times the first length.
6. The method of claim 5,
The cycle is repeated until the insulating layer and the sacrificial layer of the lowermost layer of the stacked structure are etched.
According to claim 1,
One end of the stacked structure includes a first contact region adjacent to the cell array region, and a second contact region spaced apart from the cell array region with the first contact region interposed therebetween;
The first contact region is formed in the step shape by the first lower pattern,
The preparation method is:
forming a second lower pattern including a novolak-based organic polymer on the laminate structure; and
and etching the second contact region using the second lower pattern as a mask to form the second contact region in a step shape.
According to claim 1,
One end of the stacked structure includes a first contact region adjacent to the cell array region, and a second contact region spaced apart from the cell array region with the first contact region interposed therebetween;
The second contact region is formed in the step shape by the first lower pattern,
The preparation method is:
forming a second photoresist pattern on the laminate structure; and
The method further comprising: etching the first contact region using the second photoresist pattern as a mask to form the first contact region in a step shape;
The second photoresist pattern includes units of Chemical Formulas 2 and 3, and optionally, a method of manufacturing a semiconductor device containing a copolymer including units of Chemical Formula 4:
[Formula 2]

[Formula 3]

[Formula 4]

In Formulas 2 to 4, R ₇ to R ₉ are each independently hydrogen, a hydrocarbon having 1 to 20 carbon atoms, or a hydrocarbon having 1 to 20 carbon atoms substituted with -OR ₁₁ ,
wherein R ₁₁ is C1-C10 alkyl, C2-C10 alkenyl, C2-C10 alkynyl, C6-C10 aryl or C3-C10 cycloalkyl;
Wherein p is an integer from 1 to 10, q is an integer from 1 to 10, and r is an integer from 1 to 10,
The copolymer has a weight average molecular weight of 1,000 to 100,000.
According to claim 1,
forming channel holes exposing the substrate through a cell array region of the stacked structure; and
The method of manufacturing a semiconductor device further comprising sequentially forming a gate insulating film and a channel film covering an inner wall thereof in each of the channel holes.

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