KR102387349B1 - Display device - Google Patents

Abstract

The display device of the present invention includes first and second data lines, an odd gate line, an even gate line, a data driver, and a gate driver. The first data line is disposed between the first column line and the second column line, the second data line is disposed between the first and second column lines and is adjacent to the first data line, and the lower end thereof is disposed between the first data line and the first data line. connected The odd gate lines are respectively connected to the odd-th pixel of the first column line and the even-th pixel of the second column line. The even gate lines are respectively connected to the even-th pixel of the first column line and the odd-numbered pixel of the second column line. The data driver supplies a data voltage to the first data line. The gate driver includes a gate driver that generates a gate pulse synchronized with the data voltage.

Description

display device {DISPLAY DEVICE}

The present invention relates to a display device to which a time division method is applied.

Liquid Crystal Display Device (LCD), Organic Light Emitting Diode Display (OLED Display), Plasma Display Panel (PDP), Electrophoretic Display Device (EPD) Various flat panel display devices are being developed. A liquid crystal display displays an image by controlling an electric field applied to liquid crystal molecules according to a data voltage. In an active matrix driving type liquid crystal display device, a thin film transistor (hereinafter, referred to as “TFT”) is formed for each pixel. The liquid crystal display includes a liquid crystal display panel, a backlight unit irradiating light to the liquid crystal display panel, a source drive integrated circuit (hereinafter referred to as "IC") for supplying data voltages to data lines of the liquid crystal display panel, and liquid crystal display. A gate drive IC for supplying a gate pulse (or scan pulse) to the gate lines (or scan lines) of the display panel, a control circuit for controlling the ICs, a light source driving circuit for driving a light source of a backlight unit, etc. be prepared

In recent years, as the display panel is realized with a large screen and high resolution, the power consumption of the liquid crystal display is increasing. Various methods are being tried to reduce power consumption, but in this process, a problem in which the display quality of the display device is deteriorated occurs.

An object of the present invention is to provide a display device capable of improving image quality while reducing power consumption.

The display device of the present invention includes first and second data lines, an odd gate line, an even gate line, a data driver, and a gate driver. The first data line is disposed between the first column line and the second column line, the second data line is disposed between the first and second column lines and is adjacent to the first data line, and the lower end thereof is disposed between the first data line and the first data line. connected The odd gate lines are respectively connected to the odd-th pixel of the first column line and the even-th pixel of the second column line. The even gate lines are respectively connected to the even-th pixel of the first column line and the odd-numbered pixel of the second column line. The data driver supplies a data voltage to the first data line. The gate driver includes a gate driver that generates a gate pulse synchronized with the data voltage.

The display device of the present invention can be driven by a horizontal one dot and a vertical one dot inversion method while reducing the number of polarity changes of the data voltage. As a result, the present invention can improve display quality while reducing power consumption.

1 is a view showing a display device according to the present invention.
2 is a view showing a pixel array of a display panel according to the present invention;
3 is a view showing a gate driver according to the present invention.
Fig. 4 is a diagram showing the timing of signals for driving pixels according to the present invention;
5 is a diagram illustrating a data voltage output timing of a data driver according to the present invention.
6 is a diagram illustrating polarities of data voltages applied to pixels according to the present invention;

Hereinafter, with reference to the accompanying drawings, a preferred embodiment of the present invention will be described. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, the component names used in the following description may be selected in consideration of ease of writing the specification, and may be different from the component names of the actual product.

Although the embodiment to be described below is mainly described with respect to a liquid crystal display device (LCD), the present invention is not limited thereto, and an organic light emitting diode display (OLED display), a plasma display panel, and the like. It may be applied to (Plasma Display Panel: PDP), Electrophoretic Display Device (EPD), and the like.

1 is a diagram illustrating a display device according to the present invention, and FIG. 2 is a diagram illustrating a pixel array structure of a display panel. In FIG. 2 , each gate line is denoted by a reference number that is distinguished according to a location, but a generic reference number is used in FIG. 1 . As such, in the description of each configuration, reference numerals will be collectively referred to in the common description irrespective of the position and order.

1 and 2 , the display device of the present invention includes a display panel 100 , a timing controller 110 , a data driver 120 , and gate drivers 130 and 150 . A backlight unit for irradiating light to the display panel 100 may be disposed under the display panel 100 .

The display panel 100 includes an upper substrate and a lower substrate facing each other with a liquid crystal layer interposed therebetween. The display panel 100 includes a display unit 100A in which a pixel array is formed to display an image, and a non-display unit 100B in which various signal wires are disposed outside the display unit 100A. The pixel array of the display panel 100 includes pixels connected to the data line DL and the gate line GL.

The lower substrate of the display panel 100 has data lines DL, gate lines GL, TFTs, a pixel electrode 1 connected to the TFT, and a storage capacitor connected to the pixel electrode 1 . , Cst) and the like. Each of the pixels adjusts the amount of light transmission by using liquid crystal molecules driven by the voltage difference between the pixel electrode 1 that charges the data voltage through the TFT and the common electrode 2 to which the common voltage Vcom is applied. Displays images of video data. A color filter array including a black matrix and a color filter is formed on the upper substrate of the display panel 100 . The common electrode 2 is formed on the upper substrate in the case of vertical electric field driving methods such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode, IPS (In-Plane Switching) mode and FFS (Fringe Field Switching) In the case of a horizontal electric field driving method such as mode, it may be formed on the lower substrate together with the pixel electrode. A polarizing plate is attached to each of the upper and lower substrates of the display panel 100 , and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed.

In FIG. 2 , “HL1 to HLm” denote horizontal lines arranged in a horizontal direction (X-axis direction in FIG. 1 ) in the display panel 100 , and COL1 to COLn denote a vertical direction (in FIG. 1 ) in the display panel 100 . Y-axis direction) represents a column line. The pixel array according to the present invention includes m*n pixels P arranged along m (m is a natural number) horizontal lines HL1 to HLm and n (n is a natural number) column lines COL1 to COLn. do. Hereinafter, a pixel disposed where the m-th horizontal line and the n-th column line intersect is denoted by 'P[m,n]'.

Each pixel P of the pixel array is any one of R pixel, G pixel, B pixel and W pixel. R pixels, G pixels, B pixels, and W pixels are sequentially arranged on each horizontal line. R pixels, G pixels, B pixels, and W pixels are sequentially arranged in the first horizontal line HL1 from the first column to the fourth column. On the second horizontal line HL2 , B pixels, W pixels, R pixels, and G pixels are sequentially arranged from the first column to the fourth column. As a result, two color pixels are alternately arranged in each column line, and R pixels, G pixels, B pixels, and W pixels are arranged in regions where two adjacent column lines and two horizontal lines intersect, respectively. .

An odd-numbered data line and an even-numbered data line are disposed between the odd-numbered column line and the even-th column line. For example, pixels arranged in the first odd column line (P[1,1] to P[m,1]) and pixels arranged in the first even column line (P[1,2] to P[ m, 2]), a first data line DL1 and a second data line DL2 are disposed. One end of the odd-numbered data line is connected to the data driver, and the odd-numbered data line and the even-th data line are connected to each other at the lower end. The odd-numbered data line and the even-numbered data line may be connected in the non-display unit 100B.

The odd-numbered data line is connected to odd-numbered pixels in an adjacent odd-numbered column line and even-numbered pixels in an adjacent even-th column line. For example, the first data line DL1 includes odd-numbered pixels P[1,1], P[3,1]...P[m-1,1] in the first column line COL1. and connected to even-numbered pixels P[2,2], P[2,2]...P[m,2] on the second column line COL2.

The even-th data line is connected to even-numbered pixels in an adjacent odd-numbered column line and odd-numbered pixels in an adjacent even-numbered column line. For example, the second data line DL2 is connected to even-numbered pixels P[2,1], P[4,1]...P[m,1] in the first column line COL1 . and is connected to the odd-numbered pixels P[1,2], P[3,2]...P[m-1,2] on the second column line COL2 .

An odd gate line and an even gate line are disposed in each of the horizontal lines HL1 to HLm. For example, a first odd gate line GL_O1 and a first even gate line GL_E1 are disposed on the first horizontal line HL1 , and an m-th odd gate line GL_Om and An m-th even gate line GL_Em is disposed. Each odd gate line is connected to odd-numbered pixels, and an even gate line is connected to even-th pixels. For example, the first odd gate line GL_O1 is the odd-numbered pixels P[1,1], P[1,3]...P[1,n-1] in the first horizontal line HL1 . ) and the first even gate line GL_E1 is the even-numbered pixels P[1,2], P[1,4]...P[1,n] in the first horizontal line HL1 . is connected with

The timing controller 110 converts RGB data of an input image received from a host system (not shown) into RGBW data and transmits it to the data driver 120 . The timing controller 110 receives timing signals synchronized with input image data from the host system. The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a dot clock DCLK. The timing controller 110 controls operation timings of the data driver 120 and the gate drivers 130 and 150 based on the timing signals Vsync, Hsync, DE, and DCLK received together with the pixel data of the input image. The timing controller 110 may transmit a polarity control signal POL for controlling the polarity of the pixel array to each of the source drive ICs of the data driver 120 .

The data driver 120 receives data of an input image from the timing controller 110 . Digital video data sent to the source drive ICs includes R data, G data, B data, and W data. The source drive ICs convert RGBW digital video data of an input image into positive/negative gamma compensation voltages under the control of the timing controller 110 to output positive/negative data voltages. The data driver 120 outputs the data voltage in a half column inversion method. For example, the data driver 120 outputs a data voltage of positive polarity (negative polarity) for 1/2 frame and outputs a data voltage of negative polarity (positive polarity) for 1/2 frame. The data driver 120 supplies a data voltage to each of the pixels P through the odd-numbered data lines DL1 and DL3 to D[m-1]. The data driver 120 provides a data voltage to the pixels P arranged on a pair of adjacent horizontal lines HL for one horizontal period in a time division manner. As a result, since the data driver 120 can provide the data voltage to the pixels P arranged in two column lines through two single output channels, the number of channels outputting the data voltage can be reduced.

The gate drivers 130 and 150 include a level shifter 130 and a shift register 150 . The shift register 150 includes first and second shift registers 151 and 153 as shown in FIG. 3 .

The level shifter 130 converts the transistor-transistor-logic (TTL) logic level voltages of the first and second gate clocks CLK1 and CLK2 input from the timing controller 110 to a gate high voltage VGH and a gate low voltage. Level shift to (VGL). The level shifter 130 applies the first gate clock CLK1 applied from the timing controller 110 to the first shift register 151 , and the second gate clock CLK2 to the second shift register 153 . approve

The first shift register 151 includes stages that sequentially output a carry signal and a gate pulse by shifting the first gate start pulse VST1 in accordance with the first gate clock CLK1.

To this end, the first shift register 151 includes m stages (STG1 to STGm, where m is a natural number equal to or greater than 2) that are cascadedly connected. Each of the stages STG1 to STGm outputs any one of the first to mth gate pulses G1 to G[m], respectively. In the first shift register 151 , the kth (1<k<m) stage STGk outputs the kth gate pulse G[k]. The kth gate pulse G[k] is applied to the kth odd gate line GL_Ok, and at the same time becomes a carry signal transferred to the k+1th stage STG[k+1].

The second shift register 153 includes stages that shift the second gate start pulse VST2 according to the second gate clock CLK2 to sequentially output a carry signal and a gate pulse.

To this end, the second shift register 153 includes m stages (STG[m+1] to STG[2m], where m is a natural number equal to or greater than 2) that are cascadedly connected. Each of the stages STG[m+1] to STG[2m] outputs any one of [m+1] to 2m-th gate pulses G [m+1] to G[2m], respectively. In the second shift register 153 , the jth ([m+1]<j<2m) stage STGj outputs the jth gate pulse G[j]. The j-th gate pulse G[j] is applied to the j-th even gate line GL_Ej, and at the same time becomes a carry signal transferred to the j+1th stage STG(j+1).

The first and second shift registers 151 and 153 may be directly formed on the lower substrate of the display panel 100 together with the pixel array.

4 is a diagram illustrating signal timing for driving pixels of a pixel array. Referring to FIGS. 1 to 4 , the charging order of pixels according to the present invention is as follows. In FIG. 4 , the output timing of the data voltage indicates the output timing of the data voltage provided to the first and second column lines COL1 and COL2 connected to the first and second data lines DL1 and DL2 .

The first shift register 151 shifts the first gate clock CLK1 applied after the first gate start pulse VST1 to output the first gate pulses G1 to the mth gate pulses Gm. The first shift register 151 outputs a pair of gate pulses for one horizontal period (1H). For example, the first shift register 151 outputs the first gate pulse G1 and the second gate pulse G2 for one horizontal period 1H. As a result, the first shift register 151 outputs the first gate pulses G1 to the mth gate pulses Gm during the 1/2 frame period.

While the first gate pulse G1 is output, the data driver 120 outputs a positive data voltage. As a result, a positive data voltage is charged to the odd-numbered pixels ((P[1,1], P[1,3]...P[1,n-1]) in the first horizontal line 1HL. For example, while the first gate pulse G1 is output, the first pixel P[1,1] in the first column line COL1 is charged with a positive data voltage.

While the second gate pulse G2 is output, the data driver 120 outputs a positive data voltage. As a result, a positive data voltage is charged to even-numbered pixels ((P[2,2],P[2,4]?P[2,n]) in the second horizontal line HL2. For example, While the second gate pulse G2 is output, the positive data voltage of the second pixel P[2,2] in the second column line COL2 is charged.

In this way, while the first shift register 151 sequentially outputs the first to mth gate pulses G1 to Gm, the first odd gate lines GL_O1 to m odd gate lines GL_Om The connected pixels are sequentially supplied with the data voltage. Since the odd gate lines GL_O1 to GL_Om are connected to pixels that are not adjacent to each other in the horizontal or vertical direction, the data driver outputs the data voltage of the same polarity, whereas the pixels adjacent to each other are not charged with the same polarity. does not

Before the output of the mth gate pulse Gm is terminated, the second shift register 153 receives the second start signal VST2 and shifts the second gate clock CLK2 to thereby shift the (m+1)th gate pulse Gm. The gate pulses G[m+1] to the 2m-th gate pulses G2m are sequentially output.

The second shift register 153 outputs a pair of gate pulses for one horizontal period (1H). For example, in the second shift register 153, the (m+1)th gate pulse G[m+1] and the (m+2)th gate pulse G[m+2 ]) is printed. As a result, the second shift register 153 outputs (m+1)th gate pulses G[m+1] to 2mth gate pulses G2m during the 1/2 frame period. While the gate pulse G[m+1] is being output, the data driver 120 outputs a negative data voltage As a result, the odd-numbered pixels P[m, 1],P[m,3]...P[m,n-1]) is charged with the negative data voltage.

For example, while the (m+1)th gate pulse G[m+1] is output, the mth pixel P[m,1] in the first column line COLm is charged with a negative data voltage do. And while the [m+2]th gate pulse G[m+2] is output, the data driver 120 outputs a negative data voltage. As a result, although not shown in the drawing, even-numbered pixels ((P[m-1,2],P[m-1,4].. The positive data voltage is charged to .P[m-1,n]) For example, (m-1) in the second column line while the (m+2)th gate pulse (G[m+2]) is output. )-th pixel (P[m-1,2]) is charged with a negative data voltage.

In this way, while the second shift register 153 sequentially outputs (m+1)th to 2mth gate pulses, the (m+1)th even gate lines GL_E[m+1) to Pixels connected to the 2m even gate lines GL_E2m receive a data voltage. Since the even gate lines GL_E[m+1] to GL_E2m are connected to pixels that are not adjacent to each other in the horizontal or vertical direction, the data driver outputs the data voltage of the same polarity, whereas the pixels adjacent to each other They are not charged with the same polarity.

5 is a diagram illustrating the polarity of a data voltage output from the data driver, and FIG. 6 is a diagram illustrating the polarity of charging pixels by the data voltage illustrated in FIG. 5 .

As shown in FIG. 5 , the data driver 120 outputs a data voltage of a positive polarity for 1/2 frame through each channel and outputs a data voltage of a negative polarity during a subsequent 1/2 frame. The data driver 120 inverts the polarity of the data voltage output from each channel once during one frame. That is, since the data driver 120 is driven by the half column inversion method, the polarity change of the data voltage is less than that of the dot inversion method. Since a large amount of power is consumed when the data driver 120 changes the polarity of the data voltage, power consumption can be reduced if the number of times the polarity of the data voltage is changed is reduced as in the present invention.

And, the positive data voltage is supplied to the odd-numbered pixels of the odd horizontal line and the even-th pixels of the even horizontal line through the odd data lines DL1, DL3.... The negative data voltage is supplied to the even-th pixels of the odd horizontal line and the odd-numbered pixels of the even horizontal line through the even data lines DL2, DL4...DLn connected to the odd data lines DL1, DL3... .

As a result, the pixel array is driven in a horizontal 1-dot and vertical 1-dot inversion manner. That is, according to the present invention, power consumption is reduced by reducing the number of polarity changes of the data voltage, and display quality can be improved because the pixel array is displayed in a horizontal 1-dot and vertical 1-dot inversion method.

Those skilled in the art from the above description will be able to see that various changes and modifications are possible without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 110: timing controller
130: level shifter 150: shift register

Claims (7)

a first data line disposed between the first column line and the second column line;
a second data line disposed adjacent to the first data line between the first and second column lines and having a lower end connected to the first data line;
odd-numbered gate lines, each connected to the odd-th pixel of the first column line and the even-th pixel of the second column line;
even gate lines, each connected to an even-th pixel of the first column line and an odd-numbered pixel of a second column line;
a data driver supplying a data voltage to the first data line; and
a gate driver generating a gate pulse synchronized with the data voltage;
the first data line is connected to an odd-numbered pixel of the first column line and an even-th pixel of the second column line;
The second data line is connected to an even-th pixel of the first column line and an odd-numbered pixel of the second column line. The method of claim 1,
The data driver is configured to supply a data voltage to pixels arranged in two adjacent horizontal lines for one horizontal period. 3. The method of claim 2,
The data driver
supplying the data voltage to the pixels connected to the odd gate lines during a first period after 1/2 frame has elapsed from the start of the frame;
A display device for supplying the data voltage to the pixels connected to the even gate lines during a second period from the time of the 1/2 frame to the end of the frame. 4. The method of claim 3,
The data driver
During the first period, the data voltage is supplied in order from pixels disposed on one horizontal line to pixels disposed on a last horizontal line;
During the second period, the data voltage is supplied in an order from pixels disposed on a last horizontal line to pixels disposed on a first horizontal line. 4. The method of claim 3,
The data driver
During the first period, a data voltage of the same polarity is output;
During the second period, the display device outputs a data voltage having a polarity opposite to that of the data voltage output in the first period. 4. The method of claim 3,
The gate driver
a first gate driver configured to output gate pulses in an order from the odd gate line of the first horizontal line to the odd gate line of the last horizontal line during the first period; and
and a second gate driver configured to output gate pulses in an order from an even gate line of a last horizontal line to an even gate line of a first horizontal line during the second period. The method of claim 1,
Red pixels and blue pixels are sequentially disposed on the first column line,
A display device in which green pixels and white pixels are sequentially disposed on the second column line.

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