KR102383912B1 - Fan-out packages and methods of forming the same - Google Patents

Abstract

Embodiments include forming an interposer having reinforcing structures disposed within a core layer of the interposer. The interposer may be attached to the packaged device by electrical connectors. The reinforcing structures provide rigidity and heat dissipation to the packaged device. Some embodiments may include an interposer having an opening in the upper core layer of the interposer for a recessed bond pad. Some embodiments also use connectors between the interposer and the package device, wherein the solder material connected to the interposer surrounds a metal pillar connected to the package device.

Description

FAN-OUT PACKAGES AND METHODS OF FORMING THE SAME

<Priority claim and cross-reference>

This application claims the benefit of U.S. Provisional Application No. 62/738,918, filed September 28, 2018, which U.S. application is hereby incorporated by reference herein.

<background>

The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.). In most cases, improvements in integration density have resulted from iterative reductions in the minimum feature size, which allows more components to be integrated in a given area. The growing demand for shrinking electronic devices has created a need for smaller and more creative packaging techniques of semiconductor dies. One example of such packaging systems is Package-on-Package (PoP) technology. In a PoP device, a top semiconductor package is stacked over a bottom semiconductor package to provide a high level of integration and component density. PoP technology generally makes it possible to create semiconductor devices on a printed circuit board (PCB) with improved functions and small footprints.

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.
1-13 illustrate various intermediate steps in processes of forming an interposer, in accordance with some embodiments.
14-30 illustrate various intermediate steps in processes of forming an interposer, in accordance with some embodiments.
31-35 illustrate various intermediate steps in the process of forming a fan-out bottom package, in accordance with some embodiments.
36-45 illustrate various intermediate steps in a process of forming a package structure including a fan-out bottom package and an interposer, in accordance with some embodiments.
46 and 47 include a fan-out bottom package and a second device without an interposer, but attached to each other using connectors surrounding a metal pillar, in accordance with some embodiments. I'm exemplifying the views of the package.
48-50 illustrate various intermediate steps in a process of forming a package structure including an interposer and a fan-out bottom package with an adhesive formed therebetween, in accordance with some embodiments.
51-54 illustrate various intermediate steps in a process of forming a package structure including an interposer and a fan-out underlying package on which a molding compound is previously formed, in accordance with some embodiments. are exemplifying
55-70 illustrate various intermediate steps in a process of forming a package structure including a fan-out bottom package and an interposer having a cavity or through-hole formed therein, in accordance with some embodiments; there is.
71-79 form a package structure including an interposer having a fan-out bottom package and an upper core layer having a recessed bond pad formed therein, in accordance with some embodiments; Various intermediate steps in the process are illustrated.

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These, of course, are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, wherein the first feature and the second feature are formed in direct contact. Embodiments may also include wherein additional features may be formed between the first and second features, such that the second feature may not be in direct contact. In addition, this disclosure may repeat reference numbers and/or letters in the various examples. This repetition is for the sake of simplicity and clarity, and in itself does not affect the relationship between the various embodiments and/or configurations being discussed.

Furthermore, spatially relative words, such as "beneath," "below," "lower," "above," "upper," and the like. terms) may be used herein to describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the drawings, for convenience of description. Spatial relative terms are intended to encompass different orientations of a device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Some embodiments include a fan-out bottom package comprising a die and an interposer attached thereto. The interposer may include reinforcing structures disposed through a core layer of the interposer. Reinforcing structures can help provide support, stiffness, and thermal dissipation. Package handling risks may be reduced due to the added stiffness of the interposer with reinforcing structures. Additionally, package warpage can be better controlled using the support provided by the interposer, providing a better dynamic random access memory (DRAM) or surface mount technology (SMT) joint window. can do. In some embodiments, the interposer may have a cavity or through hole disposed therein, the cavity or through hole aligned to a die of the fan-out lower package, the die disposed at least partially within the cavity or through hole , can reduce the overall thickness of the package. In some embodiments, an adhesive may be used between the interposer and the die of the fan-out bottom package.

In some embodiments, the interposer may have a second core layer disposed over the first core layer, and recessed bond pads may be disposed between the first core layer and the second core layer. Recessed bond pads are exposed through the second core layer to provide a deep recess for a connector to an overlying device or package, thereby reducing overall package height. Recessed bond pads also provide good alignment to the overlying device. In some embodiments, the interposer may have a second core layer and reinforcing structures disposed within one or both of the core layers. In some embodiments, the interposer may have a cavity or through hole disposed therein, the cavity or through hole being aligned with a die of the fan-out lower package, the die being disposed at least partially within the cavity or through hole can

In some embodiments, a stepped bond pad may be used between the fan-out bottom package and an overlying top package, such as an interposer or second device. Stepped bond pads, which may otherwise suffer cracking due to distortion of the overlying top package, provide improved and solid joint reliability. The stepped bond pad also supports fine pitch processes for reduced pitch between connectors. The stepped bond pad also provides a controlled joint standoff between the fan-out bottom package and the overlying top package. The stepped bond pads also provide good self-alignment for bonding the overlying top package. The stepped bond pad may be used with any of the other embodiments described herein, including any of the interposers discussed herein. A stepped bond pad may be used in embodiments where the overlying package is a device package that does not include an interposer and is bonded to a fan-out underlying package.

These embodiments will be discussed in detail using the description of the accompanying drawings. It should be understood, however, that features of each of the embodiments discussed in detail herein may be combined in any suitable manner, even where such combinations are not explicitly disclosed.

1-30 are cross-sectional views of intermediate steps in a process for forming interposer substrate 100 ( FIGS. 1-13 ) or interposer substrate 200 ( FIGS. 14-30 ), in accordance with some embodiments. are exemplifying Interposer substrate 100 includes one core layer as further described below and interposer substrate 200 includes more than one core layer as further described below. Although the formation of one interposer substrate 100 is shown, for example, in FIGS. 1 to 12 , and the formation of one interposer substrate 200 is shown, for example, in FIGS. 13 to 29 . However, a plurality of interposer substrates 100 or a plurality of interposer substrates 200 may be simultaneously formed using the same wafer or substrate, and subsequently individual interposer substrates 100 or interposer substrates may be formed. It may be singulated to form substrates 200 .

1-13 illustrate cross-sectional views of intermediate steps of a process for forming the interposer substrate 100 . 1 , a carrier substrate 102 is provided, and a release layer 104 is formed on the carrier substrate 102 . The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 102 may be a wafer such that multiple packages may be simultaneously formed on the carrier substrate 102 . The release layer 104 may be formed of a polymer-based material, which may be removed along with the carrier substrate 102 from overlying structures to be formed in subsequent steps. In some embodiments, the release layer 104 is an epoxy-based heat dissipating material that loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating. -based thermal-release material). In other embodiments, the release layer 104 may be an ultraviolet (UV) glue, which loses its adhesive properties when exposed to UV light. The release layer 104 may be dispensed as a liquid and cured, may be a laminate film laminated onto the carrier substrate 102 , or the like. A top surface of the release layer 104 may be leveled.

A conductive layer 105 may be formed over the release layer 104 . Conductive layer 105 may be one or more layers of copper, titanium, nickel, aluminum, compositions thereof, or the like, and may be formed by foil, chemical vapor deposition (CVD), physical vapor deposition (PVD), and the like. As such, it may be formed using any suitable process.

Referring now to FIG. 2 , conductive layer 105 may be patterned using acceptable photolithography techniques to form a conductive pattern of conductive lines 106 . For example, a photoresist may be deposited over the conductive layer 105 , the photoresist may be developed to expose a negative of the conductive pattern, and the exposed portions of the conductive layer 105 may be subjected to an acceptable etching technique. can be removed by A conductive pattern of conductive lines 106 may be applied across the surface of the subsequently formed interposer core layer, eg, from one via through the core layer to another via in the core layer, a signal, power, and/or ground line. can be routed.

In some embodiments, the process of forming the conductive pattern of the conductive lines 106 is performed to form a redistribution structure, such as a redistribution structure 306 discussed below with respect to FIG. 32 . It can be repeated several times. In such embodiments, as discussed below with respect to redistribution structure 306 , dielectric layers may be used to isolate different layers of conductive lines 106 .

Referring to FIG. 3 , one or more substrate cores are formed over conductive lines 106 . For convenience of reference, these will be referred to collectively as the substrate core 110 . The substrate core 110 may be formed of a pre-impregnated composite fiber (“prepreg”), an insulating film or build-up film, paper, glass fiber, It may be formed of a non-woven glass fabric, silicone, or the like. In some embodiments, the substrate core 110 is formed of a prepreg including glass fibers and a resin. In some embodiments, the substrate core 110 is formed of a copper-clad epoxy-impregnated glass-cloth laminate, a copper-clad polyimide impregnated glass-cloth laminate; copper-clad polyimide-impregnated glass-cloth laminate), or the like. The substrate core 110 may have a thickness T ₁ of from 20 μm to about 200 μm, such as about 100 μm, although other thicknesses are contemplated and may be used. The substrate core 110 may consist of several distinct layers.

A conductive layer 112 may be formed over the substrate core 110 . The conductive layer 112 may be one or more layers of copper, titanium, nickel, aluminum, compositions thereof, or the like, and may include metal foil lamination, chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. ) can be formed using any suitable process, such as by In some embodiments, conductive layer 112 may be a foil that is thermally laminated to substrate core 110 .

In FIG. 4 , openings 114 are formed through the conductive layer 112 into the substrate core 110 . In some embodiments, the openings 114 are formed by laser drilling. Other processes may also be used to form the openings 114 , such as mechanical drilling using a drill bit. Any other suitable process may be used to form the openings 114 . The openings 114 may have any top-view shape, such as polygonal, circular, or the like. A cleaning process may then be performed to clean areas near the openings 114 that may have been smeared with the removed material of the substrate core 110 . The openings 114 may have a width W ₁ of from about 50 μm to about 250 μm, such as about 100 μm, although other values are contemplated and may be used. In some embodiments, the openings 114 may be formed in a regular pattern, with a pitch P ₁ of from 100 μm to about 300 μm, such as about 230 μm, although other values are contemplated and can be used In some embodiments, the widths W ₁ of the openings 114 may be different in different portions of the substrate core 110 . For example, FIG. 9 illustrates irregular reinforcement structures 122 resulting from corresponding irregular openings 114 . In some embodiments, the pattern of the openings 114 for the subsequently formed reinforcement structures relative to the conductive vias may be different. In some embodiments, the openings 114 for the subsequently formed reinforcement structures relative to the conductive vias may be random.

5 , conductive vias 116 are formed in some of the openings 114 and reinforcing structures 120 are formed in the remaining openings 114 . The conductive layer 112 is also used to form conductive lines 113 on the substrate core 110 .

With respect to conductive vias 116 and conductive lines 113 , conductive vias 116 may be formed of a conductive material such as copper, titanium, tungsten, aluminum, or the like. In some embodiments, conductive vias 116 and conductive lines 113 may be formed of the same material or different materials, and may be formed by the same process or different processes. In other embodiments, the conductive vias 116 are formed by a first process and the conductive lines 113 are formed by a second process.

With respect to the reinforcing structures 120 , in some embodiments, the reinforcing structures 120 may be formed in the same or a different process as the conductive vias 116 . In embodiments where the reinforcing structures 120 are formed in the same process as the conductive vias 116 , the reinforcing structures 120 and the conductive vias 116 may be formed of the same conductive material, although the reinforcing structures The conductive material at 120 is uncoupled and electrically floats. In embodiments where the reinforcing structures 120 are formed in a different process than the conductive vias 116 , the reinforcing structures 120 may be formed using the same or different materials as the conductive vias 116 . In such embodiments, either the conductive vias 116 or the reinforcement structures 120 may be formed first.

Referring to the formation of conductive vias 116 and conductive lines 113 , conductive vias 116 and conductive lines 113 may be formed by any suitable process. For example, in some embodiments, the openings 114 , which will subsequently become the reinforcement structures 120 , are masked, while the openings 114 , which will become the conductive vias 116 , are exposed.

In a process in which the conductive vias 116 and the conductive lines 113 are separately formed, seed layers (not shown) may be formed in the exposed openings 114 . A plating process, such as electroplating or electroless plating, may be used to deposit a conductive material in the openings 114 , thereby forming the conductive vias 116 . To form the conductive lines 113 , a photoresist is formed over the conductive layer 112 , exposing portions of the conductive layer 112 that are not included in the pattern of the conductive lines 113 . 113) may be patterned as an inverse image. Exposed portions of conductive layer 112 may then be removed by a suitable etching process, such as by wet or dry etching, for example, to form conductive lines 113 . The photoresist may be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. The conductive lines 113 may be formed before or after the formation of the conductive vias 116 . An exemplary structure resulting from this process is shown enlarged in FIG. 5 (left enlargement).

In a process in which the conductive vias 116 and the conductive lines 113 are formed in the same process, seed layers (not shown) formed in the exposed openings 114 are of the conductive layer 112 that will become conductive lines. It may also extend over the parts. A photoresist is formed over the conductive layer 112 and the seed layer, and may be patterned with the image of the conductive lines 113 to expose portions of the seed layer included in the pattern of the conductive lines 113 . A plating process may be used to deposit a conductive material on the seed layer that is in the openings 114 to form conductive vias 116 and is exposed through photoresist to form conductive material 112p . After plating, the photoresist may be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. The exposed portions of the seed layer may then be removed, followed by the exposed portions of the conductive layer 112 . Removal of the seed layer and portions of the conductive layer 112 may be by an acceptable etching process, such as by wet or dry etching. An exemplary structure resulting from this process is shown enlarged in FIG. 5 (right enlarged view).

The photoresist used above may be formed by spin coating or the like, and may be exposed to light for patterning. The pattern of photoresist corresponds to the conductive pattern of conductive lines 113 or the inverse of the conductive pattern of conductive lines 113, depending on the process used, as described above.

In some embodiments, the process of forming the conductive lines 113 may be repeated any number of times to form a redistribution structure, such as the redistribution structure 306 discussed below with respect to FIG. 32 . . In such embodiments, as discussed below with respect to redistribution structure 306 , dielectric layers may be used to isolate different layers of conductive lines 113 .

Referring now to reinforcement structures 120 , reinforcement structures 120 are formed in some of the openings 114 . In some embodiments, the reinforcing structures 120 are made of a material having a high thermal conductivity of between about 10 W/m·K and 475 W/m·K, such as, for example, about 400 W/m·K. may be formed, but other values are contemplated and may be used. In some embodiments, the reinforcing structures 120 may be formed of a material having a high stiffness (Young's modulus) of about 10 GPa to about 380 GPa, such as, for example, about 120 GPa, Other values are contemplated and may be used. In some embodiments, the reinforcing structures 120 may include, for example, a substrate core ( 110), although other values are contemplated and may be used. Reinforcing structures 120 may be selected to have one or more of high thermal conductivity, high stiffness, and a specific CTE.

In some embodiments, the material of the reinforcing structures 120 may be a metallic material, such as copper, titanium, tungsten, aluminum, or the like. In some embodiments, the reinforcing structures 120 may be formed of a ceramic, such as aluminum oxide, zirconia, or the like. In other embodiments, the reinforcing structures 120 may be formed of polymeric materials, graphite materials, silicon materials, or a metal or non-metal conductive film. In some embodiments, the reinforcing structures 120 may be formed from composites or combinations of any of the above.

Reinforcing structures 120 improve heat dissipation and at the same time reduce warping. The reinforcing structures 120 having a larger Young's modulus may improve the strength of the substrate core 110 . In general, the greater the density of the reinforcing structures 120 in the substrate core 110 , the less warping occurs in subsequent thermal processes. When the reinforcing structures 120 have both a greater Young's modulus and a higher thermal conductivity, heat is applied to the heat-generating components ( It is dissipated away from the heat generating components.

The reinforcement structures 120 may be electrically floating, not electrically coupled to any other connector. The reinforcement structures 120 may have different shapes and sizes in plan view (eg, see FIG. 9 which illustrates the reinforcement structures 122 ), and may be laid out in any pattern or randomly.

In other embodiments, the conductive vias 116 are formed in different processes. The reinforcing structures 120 may be formed using any suitable process, depending on the material of the reinforcing structures 120 . For example, the metal may be formed in a manner similar to that described above with respect to the conductive vias 116 . Other materials may be formed by masking the other openings 114 or conductive vias 116 using photolithography, and exposing the openings 114 to form corresponding reinforcement structures 120 . can The photoresist may be formed, for example, by spin coating or laminating, and then patterned by exposing to a suitable light source to expose the openings 114 to be used for the reinforcement structures 120 . After exposing the openings 114 to light, the reinforcing structures 120 may be formed by electroplating or electroless plating to metal materials or the like. After forming the reinforcement structures 120 , the photoresist may be removed by wet and/or dry techniques, such as by an ashing technique. In another example where the reinforcement structures 120 are formed of ceramic, the ceramic may be deposited using a CVD process. In another example in which the reinforcement structures 120 are formed from a polymer, the polymer may be deposited and cured using a spin on or dispensing technique. Other deposition methods are contemplated and may be used.

In some embodiments, a removal process, such as a planarization process, is performed to level the top of the reinforcement structures 120 flush with another layer of the interposer substrate 100 , for example. It can be used to remove parts of the material of In embodiments in which the reinforcing structures 120 are formed prior to the formation of the conductive layer 112 , the top of the reinforcement structures 120 may be leveled to the same height as the top of the substrate core 110 . In other embodiments, the top of the reinforcement structures may be leveled flush with the top of the conductive lines 113 or flush with the top of the conductive vias 116 . In some embodiments, the same removal process or a separate removal process, such as a planarization process, may be used to level the tops of the conductive lines 113 to the same height as the tops of the conductive vias 116 .

6 , the carrier substrate 102 is removed. The carrier substrate 102 may be detached (or “de-bonded”) from the substrate core 110 . In some embodiments, de-bonding is performed by applying light, such as laser light or UV light, to the release layer 104 such that the release layer 104 decomposes due to the heat of the light and the carrier substrate 102 can be removed. ), including projection onto

Solder resist layers 124 are formed on the conductive lines 106 and the conductive lines 113 on opposite sides of the substrate core 110 . The solder resist layers 124 protect regions of the substrate core 110 from external damage. In some embodiments, the solder resist layers 124 are formed by depositing a photosensitive dielectric layer, exposing the photosensitive material to an optical pattern, and developing the exposed layer to form openings 124o. . In some embodiments, the solder resist layers 124 are formed by depositing a non-photosensitive dielectric layer (eg, silicon oxide, or silicon nitride, or the like) and a dielectric using acceptable photolithography and etching techniques. It is formed by patterning the layer to form openings 124o. The openings 124o are underlying conductive lines 113 and 106 which may be used as connector pads or underbump metallizations in subsequent processes. ) parts are exposed. The openings 124o are tapered to have a smaller width W ₂ at the deepest portion of the opening 124o compared to the larger width W ₃ at the shallowest portion of the opening 124o . The width W ₂ may be from about 55 μm to about 320 μm, such as about 180 μm, although other dimensions are contemplated and may be used. The width W ₃ can be from about 70 μm to about 350 μm, such as about 210 μm, although other dimensions are contemplated and may be used. The thickness T ₂ of each solder resist layer may be from about 5 μm to about 50 μm, such as about 25 μm, although other thicknesses are contemplated. The overall thickness T ₃ of the interposer substrate 100 may be from about 50 μm to about 300 μm, such as about 100 μm, although other thicknesses are contemplated.

In FIG. 7 , conductive connectors 126 are formed in openings 124o (see FIG. 6 ). The conductive connectors 126 may contact exposed portions of the conductive lines 106 . Conductive connectors 126 include ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel (ENEPIG) -electroless palladium-immersion gold technique) forming bumps, or the like. The conductive connectors 126 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors 126 are soldered through commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. eutectic connectors formed by initially forming a layer of eutectic material. Once the layer of solder has been formed on the structure, a reflow may be performed to shape the material into desired bump shapes. In another embodiment, the conductive connectors 126 include metal pillars (such as copper pillars) formed by printing, electroplating, electroless plating, chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. The metal pillars are solder free and may have substantially vertical sidewalls.

8 and 9 are horizontal cross-sectional views through the substrate core 110 of the interposer substrate 100 in accordance with various embodiments. In the embodiment of the interposer substrate 100 illustrated in FIG. 8 , the reinforcement structures 120 are formed at various locations throughout the interposer substrate 100 . The reinforcing structures 120 may have approximately the same size or different sizes as the conductive vias 116 . The reinforcing structures 120 may be formed in the same pattern as the pattern of the conductive vias 116 or in a different pattern. In some embodiments, the reinforcement structures 120 may be randomly distributed. The embodiment of the interposer substrate 100 illustrated in FIG. 9 illustrates reinforcing structures 122 having irregular shapes and comprising an area that is about 2 to 100 times the area of the other of the reinforcing structures 120 . However, the area may be less than twice or greater than 100 times the area of the reinforcing structures 120 . Reinforcement structures 122 may be positioned and designed to correspond to a particular device or hot spot within the attached package, and may help dissipate heat from the attached package.

8 and 9 illustrate the line A-A showing the cross section taken with respect to FIG. 7 . In the views illustrated in FIGS. 8 and 9 , the total area of the reinforcement structures 120 and all of the reinforcement structures 122 in a plan view can be from about 5% to about 80% of the total area of the interposer substrate 100 . there is. The total volume of the reinforcement structures 120 and all of the reinforcement structures 122 may be from about 5% to about 80% of the volume of the substrate core 110 of the interposer substrate 100 .

10 illustrates a top view, a middle view, and a bottom view of the interposer substrate 100 . As illustrated in FIG. 10 , conductive vias 116 may be located in a peripheral area of the interposer substrate 100 , and conductive lines 113 may be separated from one conductive via 116 to another. Routing to conductive vias 116 may be provided. The reinforcement structures 120 and/or 122 may be formed through the middle of the substrate core 110 .

11 illustrates an interposer substrate 100 having a cavity 130 disposed therein, in accordance with some embodiments. Cavity 130 may be formed by removing portions of substrate core 110 and solder resist layers 124 before or after forming conductive connectors 126 . Removal of material to form cavity 130 may be accomplished by a mechanical drilling process using computer numeric control (CNC). In such embodiments, material is removed by a mechanical drill, and the position of the drill is controlled by a computer or controller. Removal may also be accomplished by other processes, such as a laser cutting process, a laser drilling process, or the like. The remaining portions of the material form the interposer substrate 100 . Cavity 130 may have a height H ₁ from about 20 μm to about 270 μm, such as about 50 μm, although other values are contemplated and may be used. In such embodiments, the reinforcement structures 120 and/or 122 may be disposed in a thin portion of the interposer substrate 100 and/or in peripheral portions of the interposer substrate 100 . Accordingly, some of such reinforcing structures 120 and/or 122 may likewise be thinned when cavity 130 is formed. To reduce the overall thickness of the package that is formed when the interposer substrate 100 is attached to the bottom fan out package, the cavity 130 is formed in the lower fan out package (discussed in more detail below) The cavity 130 may be formed at a position of the interposer substrate 100 to be aligned with a mounted device.

12 illustrates the interposer substrate 100 having a through hole 140 disposed therein to provide a ring shape, in accordance with some embodiments. In some embodiments, the cavity 130 may be formed completely penetrating the substrate core layer 110 and the solder resist layer 124 to form the through hole 140 . In such embodiments, the reinforcement structures 120 and/or 122 may be disposed within peripheral portions of the interposer substrate 100 . To reduce the overall thickness of the package formed when the interposer substrate 100 is attached to the lower fan out package, a through hole 140 is aligned with the mounted device of the lower fan out package (discussed in more detail below). The through-hole 140 may be formed at a position of the interposer substrate 100 to make it possible.

FIG. 13 illustrates a horizontal cross-sectional view through the substrate core 110 of a ring-shaped interposer substrate 100 as illustrated in FIG. 12 , in accordance with some embodiments. Lines A-A represent the cross-section taken for FIG. 12 . The reinforcing structures 120 are formed at various locations throughout the interposer substrate 100 . The reinforcing structures 120 may have approximately the same size or different sizes as the conductive vias 116 . The reinforcing structures 120 may be formed in the same pattern as the pattern of the conductive vias 116 or in a different pattern. In some embodiments, the reinforcement structures 120 may be randomly distributed. Although not shown in this view, reinforcement structures 122 (see FIG. 9 ) may be included. The total area of the reinforcing structures 120 and all of the reinforcing structures 122 may be about 5% to about 80% of the total area of the interposer substrate 100 . The total volume of the reinforcement structures 120 and all of the reinforcement structures 122 may be from about 5% to about 80% of the volume of the substrate core 110 of the interposer substrate 100 .

14-30 illustrate various embodiments of an interposer substrate 200 including one or more additional substrate core 210 layers. 14 illustrates a second substrate core 210 formed over the substrate core 110 and the conductive lines 113, in accordance with some embodiments. After the formation of the conductive vias 116 and the conductive lines 113 of FIG. 5 , the second substrate core 210 may be laminated to the first substrate core 110 and the conductive lines 113 . The second substrate core 210 may be formed using materials and processes similar to those discussed above with respect to the substrate core 110 , which are not repeated. The conductive lines 212 may be formed on the second substrate core 210 . Conductive lines 212 are first formed using processes and materials similar to those discussed above with respect to conductive layer 112 , followed by forming a conductive layer as previously discussed in patterning of conductive lines 113 . may be formed by patterning the conductive layer to create conductive lines 212 using processes and materials similar to , which is not repeated. As illustrated in FIG. 14 , in some embodiments, neither the substrate core 110 nor the substrate core 210 may have reinforcement structures disposed therein. In some embodiments, the process of forming the conductive lines 212 may be repeated any number of times to form a redistribution structure, such as the redistribution structure 306 discussed below with respect to FIG. 32 . . In such embodiments, as discussed below with respect to redistribution structure 306 , dielectric layers may be used to isolate different layers of conductive lines 212 .

15 illustrates a second substrate core 210 formed over the substrate core 110 and the conductive lines 113, in accordance with some embodiments. After the formation of the conductive vias 116 , the conductive lines 113 , and the reinforcement structures 120 of FIG. 5 , the second substrate core 210 is connected to the first substrate core 110 and the conductive lines 113 . ) can be laminated to The second substrate core 210 and conductive lines 212 may be formed in a manner similar to that discussed with respect to the second substrate core 210 of FIG. 14 . As illustrated in FIG. 15 , in some embodiments, the substrate core 210 may be formed over the substrate core 110 after the reinforcement structures 120 are disposed within the substrate core 110 , although the reinforcement structures are not there may not be

16 illustrates a second substrate core 210 formed over the substrate core 110 and the conductive lines 113 in accordance with some embodiments. After the formation of the conductive vias 116 , the conductive lines 113 , and the reinforcement structures 120 of FIG. 5 , the second substrate core 210 is connected to the first substrate core 110 and the conductive lines 113 . ) can be laminated to In some embodiments, the reinforcing structures 220 may be formed in the second substrate core 210 . In some embodiments, some or all of the reinforcing structures 220 may be aligned with respective reinforcing structures 120 , while in other embodiments, none of the reinforcing structures 220 are reinforcing structures. (120) is not aligned. In some embodiments, the reinforcing structures 220 may include irregularly shaped reinforcing structures similar to the reinforcing structures 122 discussed above. Reinforcing structures 220 may be formed using processes and materials similar to those previously discussed in the formation of reinforcing structures 120 and/or 122 , which are not repeated.

17 to 21 illustrate various intermediate processes in completing the interposer substrate 200 . Although FIGS. 17-21 are illustrated based on an interposer substrate 200 as depicted in FIG. 14 , embodiments of the interposer substrate 200 consistent with those depicted in FIGS. 15 and 16 are also exemplified. It should be understood that applicable.

FIG. 17 shows the interposer substrate of FIG. 14 after recesses 250 are formed in the second substrate core 210 to expose a recessed bond pad 113p corresponding to a portion of the conductive lines 113 . is exemplifying In some embodiments, the recesses 250 are formed by laser drilling. Other processes may also be used to form the recesses 250 , such as mechanical drilling using a drill bit. Any other suitable process may be used to form the recesses 250 . The recesses 250 may have any top view shape, such as polygonal, circular, or the like. A cleaning process may then be performed to clean areas near the recesses 250 that may have smeared with the removed material of the substrate core 210 . The recesses 250 may have a width W ₄ of from about 70 μm to about 350 μm, such as about 210 μm, although other values are contemplated and may be used. In some embodiments, the recesses 250 may be formed in a regular pattern, with a pitch P ₄ of from 70 μm to about 400 μm, such as about 260 μm, although other values are contemplated and used. . In some embodiments, the width W ₄ at the top of the recesses 250 may be wider than the width W ₅ at the bottom of the recesses 250 , such that the recesses 250 adopt a tapered shape. can have The width W ₅ may be from about 55 μm to about 320 μm, such as about 180 μm. The recesses 250 may have a height H ₄ of from about 20 μm to about 300 μm, such as about 30 μm, although other values are contemplated and may be used.

18 , the carrier substrate 102 is removed. The carrier substrate 102 may be separated (or “debonded”) from the substrate core 110 . In some embodiments, debonding involves projecting light, such as laser light or UV light, onto the release layer 104 such that the release layer 104 decomposes due to heat of the light and the carrier substrate 102 can be removed. include that In some embodiments, additional substrate core layers may be added in a manner similar to that discussed above with respect to substrate core 210 , with conductive lines, vias, and reinforcing structures in a manner consistent with that discussed above. may be disposed therein, and a topmost substrate core may have recesses 250 formed therein.

In FIG. 19 , solder resist layers 124 are formed on the conductive lines 106 and the conductive lines 212 , over opposite sides of the substrate core 110 and the substrate core 210 . The solder resist layers 124 protect the substrate core 110 and regions of the substrate core 210 from external damage. Solder resist layers 124 may be formed using processes and materials similar to those discussed above with respect to FIG. 6 , which are not repeated. Openings may be made in the solder resist layers 124 in a manner similar to that previously discussed. The thickness T ₄ of each solder resist layer can be from about 5 μm to about 50 μm, such as about 25 μm, although other thicknesses are contemplated. The overall thickness T ₅ of the interposer substrate 200 may be from about 30 μm to about 1500 μm, such as about 200 μm, although other thicknesses are contemplated.

20 , an optional metal liner 260 may be formed, wherein the metal liner 260 lines the recesses 250 of the second substrate core 210 to provide underbump metallization. ). In some embodiments, the metal liner 260 is applied while the carrier substrate 102 is still attached and prior to the formation of the solder resist layers 124 , eg, in the formation of the recesses 250 in FIG. 17 . Thereafter, it can be formed. In other embodiments, the metal liner 260 may be formed after formation of the solder resist layers 124 . The metal liner 260 may be one or more layers of copper, titanium, nickel, aluminum, compositions thereof, or the like, and may be any, such as by foil, chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. It can be formed using an appropriate process of Although metal liner 260 is depicted in the figures discussed below including interposer substrate 200 , it should be understood that metal liner 260 is optional.

In some embodiments, a seed layer (not shown) may first be formed over the substrate core 210 to form the metal liner 260 . A photoresist (not shown) is then formed over the seed layer and patterned to expose recesses 250 . A metal liner 260 may then be formed in the recesses 250 . After formation of the metal liner 260 , the photoresist may be removed, such as by ashing, and the currently exposed portions of the seed layer may be removed, such as by wet or dry etching.

In other embodiments, a metal layer may be formed over the substrate core 210 and a photoresist (not shown) may be deposited over the metal layer to form the metal liner 260 . The photoresist may be patterned to expose portions of the metal layer that should not be retained, and those portions may be removed, such as by wet or dry etching. The photoresist may be removed, such as by ashing, and the remaining portions of the metal layer may become a metal liner 260 .

In FIG. 21 , conductive connectors 126 are formed in openings in the solder resist layers 124 . The conductive connectors 126 may be formed using processes and materials similar to any of those discussed above with respect to the conductive connectors 126 of FIG. 7 .

22-25 illustrate an interposer substrate 200 having a cavity 230 ( FIGS. 22-24 ) or a through hole 240 ( FIG. 25 ) disposed therein, in accordance with some embodiments . Cavity 230 or through hole 240 may be formed using any of the processes previously discussed with respect to cavity 130 and through hole 140 , which are not repeated. Cavity 230 may have a height H ₂ from about 20 μm to about 1470 μm, although other heights are contemplated and may be used. 22 illustrates an embodiment in which the cavity 230 is formed such that the height H ₂ of the removed portion corresponds to the thickness of the substrate core 110 . 23 illustrates an embodiment in which the cavity 230 is formed such that the height H ₂ of the removed portion is smaller than the thickness of the substrate core 110 . 24 shows that the cavity 230 is formed such that the height H ₂ of the removed portion is greater than the thickness of the substrate core 110 and extends into the second substrate core 210 but does not completely penetrate the second substrate core 210 . An example that is not extended is illustrated. 25 illustrates an embodiment in which the through hole 240 extends completely through the substrate core 110 and the second substrate core 210 .

26 illustrates an interposer substrate 200 having reinforcing structures 120 and reinforcing structures 220 disposed therein, eg, which may follow from the intermediate process illustrated in FIG. 16 . . It should be understood that the reinforcing structures 220 are optional, as discussed above.

27-30 illustrate an interposer substrate 200 having a cavity 230 ( FIGS. 27-29 ) or a through hole 240 ( FIG. 30 ) disposed therein, in accordance with some embodiments . Cavity 230 or through hole 240 may be formed using any of the processes previously discussed with respect to cavity 130 and through hole 140 , which are not repeated. 27-30 have reinforcing structures 120 (and/or reinforcing structures 122 ) and/or reinforcing structures 220 disposed within their respective substrate cores.

27 illustrates an embodiment in which the cavity 230 is formed such that the height H ₂ of the removed portion corresponds to the thickness of the substrate core 110 . Reinforcement structures 120 may be disposed within a peripheral portion of substrate core 110 , reinforcement structures 220 may be disposed within a portion of second substrate core 210 aligned with cavity 230 and/or Alternatively, it may be disposed within a peripheral portion of the second substrate core around the cavity 230 .

28 illustrates an embodiment in which the cavity 230 is formed such that the height H ₂ of the removed portion is smaller than the thickness of the substrate core 110 . The reinforcement structures 120 may be disposed within a peripheral portion of the substrate core 110 and/or within a portion of the substrate core 110 aligned with the cavity 230 and thinned by a process forming the cavity 230 . can be The reinforcement structures 220 may be disposed within a portion of the second substrate core 210 that is aligned with the cavity 230 and/or may be disposed within a peripheral portion of the second substrate core around the cavity 230 .

29 shows that the cavity 230 is formed such that the height H ₂ of the removed portion is greater than the thickness of the substrate core 110 and extends into the second substrate core 210 but does not completely penetrate the second substrate core 210 . An example that is not extended is illustrated. The reinforcing structures 120 may be disposed within a peripheral portion of the substrate core 110 . The reinforcement structures 220 may be disposed within a peripheral portion of the second substrate core 210 surrounding the cavity 230 and/or may be disposed within a portion of the second substrate core aligned with the cavity 230 . and may be thinned by a process of forming the cavity 230 .

30 illustrates an embodiment in which the through hole 240 extends completely through the substrate core 110 and the second substrate core 210 . The reinforcement structures 120 may be disposed in a peripheral portion of the substrate core 110 , and the reinforcement structures 220 may be disposed in a peripheral portion of the second substrate core 210 .

31-79 illustrate cross-sectional views of intermediate steps in a process for packaging interposer substrate 100 or interposer substrate 200 with other devices to form various package components, in accordance with some embodiments. are doing The package components may include multiple regions, and one interposer substrate 100 or interposer substrate 200 is packaged within each region. One area of package components is illustrated.

31-42 illustrate cross-sectional views of intermediate steps of a process for forming the bottom fan-out package 300 , in accordance with some embodiments. The formation of the lower fan-out package 300 may be used in any of the embodiments discussed below. 31 , a carrier substrate 302 is provided, and a release layer 304 is formed on the carrier substrate 302 . The carrier substrate 302 can be similar to any of the candidates for the carrier substrate 102 , and the release layer 304 is one of the candidates for the release layer 104 , each discussed above with respect to FIG. 1 . It may be similar to anything. The upper surface of the release layer 304 may be leveled and may have a high degree of coplanarity.

In FIG. 32 , a first redistribution structure 306 is formed on the release layer 304 . The first redistribution structure 306 includes dielectric layers 308 , 312 , 316 , and 320 ; and metallization patterns 310 , 314 , and 318 . The metallization patterns may also be referred to as redistribution layers or redistribution lines. A first redistribution structure 306 is shown as an example. More or fewer dielectric layers and metallization patterns may be formed in the first redistribution structure 306 . If fewer dielectric layers and metallization patterns are to be formed, the steps and process discussed below may be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be repeated.

As an example for forming the first redistribution structure 306 , a dielectric layer 308 is deposited on the release layer 304 . In some embodiments, dielectric layer 308 may be patterned using a lithographic mask, polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or It is formed of a photosensitive material such as the like. The dielectric layer 308 may be formed by spin coating, lamination, CVD, the like, or a combination thereof. Dielectric layer 308 is then patterned. The patterning forms openings exposing portions of the release layer 304 . The patterning may be accomplished by exposing the dielectric layer 308 to light when the dielectric layer 308 is a photosensitive material, or by an acceptable process, such as etching using, for example, anisotropic etching. If the dielectric layer 308 is a photosensitive material, the dielectric layer 308 may be developed after exposure.

A metallization pattern 310 is then formed. The metallization pattern 310 includes conductive lines on and extending along a major surface of the dielectric layer 308 . The metallization pattern 310 further includes conductive vias extending through the dielectric layer 308 . To form the metallization pattern 310 , a seed layer is formed over the dielectric layer 308 and in openings extending through the dielectric layer 308 . In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD, or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and exposed to light for patterning. The photoresist pattern corresponds to the metallization pattern 310 . The patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may include a metal, such as copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and the underlying portions of the seed layer forms the metallization pattern 310 . Portions of the seed layer where no conductive material has been formed and the photoresist are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching.

A dielectric layer 312 is deposited over the metallization pattern 310 and the dielectric layer 308 . Dielectric layer 312 may be formed in a similar manner to dielectric layer 308 and may be formed of the same material as dielectric layer 308 .

A metallization pattern 314 is then formed. The metallization pattern 314 includes conductive lines on and extending along a major surface of the dielectric layer 312 . The metallization pattern 314 further includes conductive vias extending through the dielectric layer 312 to physically and electrically connect to the metallization pattern 310 . The metallization pattern 314 may be formed in a similar manner to the metallization pattern 310 , and may be formed of the same material as the metallization pattern 310 . The conductive vias of the metallization pattern 314 have a smaller width than the conductive vias of the metallization pattern 310 . Accordingly, when patterning the dielectric layer 312 for the metallization pattern 314 , the width of the openings in the dielectric layer 312 is smaller than the width of the openings in the dielectric layer 308 .

A dielectric layer 316 is deposited over the metallization pattern 314 and the dielectric layer 312 . Dielectric layer 316 may be formed in a similar manner to dielectric layer 308 and may be formed of the same material as dielectric layer 308 .

A metallization pattern 318 is then formed. The metallization pattern 318 includes conductive lines on and extending along a major surface of the dielectric layer 316 . The metallization pattern 318 further includes conductive vias extending through the dielectric layer 316 to physically and electrically connect to the metallization pattern 314 . The metallization pattern 318 may be formed in a similar manner to the metallization pattern 310 , and may be formed of the same material as the metallization pattern 310 . The conductive vias of the metallization pattern 318 have a smaller width than the conductive vias of the metallization pattern 310 . Accordingly, when patterning the dielectric layer 316 for the metallization pattern 314 , the width of the openings in the dielectric layer 316 is smaller than the width of the openings in the dielectric layer 308 .

A dielectric layer 320 is deposited over the metallization pattern 318 and the dielectric layer 316 . Dielectric layer 320 may be formed in a similar manner to dielectric layer 308 and may be formed of the same material as dielectric layer 308 .

In FIG. 33 , UBMs 322 are formed on and extend through dielectric layer 320 . As an example for forming the UBMs 322 , the dielectric layer 320 may be patterned to form openings exposing portions of the metallization pattern 318 . The patterning may be accomplished by exposing the dielectric layer 320 to light when the dielectric layer 320 is a photosensitive material, or by an acceptable process, such as etching using, for example, anisotropic etching. If dielectric layer 320 is a photosensitive material, dielectric layer 320 may be developed after exposure. In some embodiments, the openings for the UBMs 322 may be wider than the openings for the conductive via portions of the metallization patterns 310 , 314 , and 318 . In some embodiments, the openings for the UBMs 322 may be narrower or approximately the same width as the openings for the conductive via portions of the metallization patterns 310 , 314 , and 318 . A seed layer is formed over the dielectric layer 320 and in the openings. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and exposed to light for patterning. The pattern of photoresist corresponds to the UBMs 322 . The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may include a metal, such as copper, nickel, titanium, tungsten, aluminum, or the like. Then, portions of the seed layer where no conductive material has been formed and the photoresist are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form UBMs 322 . In embodiments where the UBMs 322 are formed differently, more photoresist and patterning steps may be used.

Not all UBMs 322 may have the same width. In some embodiments, the first subset of UBMs 322 in the first region 306A of the first redistribution structure 306 has a first width W ₆ , A second subset of UBMs 322 in second region 306B has a second width W ₇ . The first width W ₆ can be different from the second width W ₇ , and in some embodiments the first width W ₆ is greater than the second width W ₇ . The width W ₆ can be from about 100 μm to about 250 μm, such as about 170 μm, although other values are contemplated and may be used. The width W ₇ may be from about 30 μm to about 70 μm, such as about 48 μm, although other values are contemplated and may be used.

34 , some or all of the UBMs 322 of the first region 306A may instead be formed in the conductive pillars 322p, according to some embodiments. Conductive pillars 322p push the UBMs 322 of the first region 306A through the photoresist until they reach a desired height H ₈ , such as about 60 μm, such as about 10 μm to about 150 μm. Although conductive pillars 322p may be formed by plating, other values are contemplated and may be used. In some embodiments, the width W ₈ of the conductive pillars may correspond to openings in the dielectric layer 320 that are patterned to expose portions of the metallization pattern 318 . In some embodiments, width W ₈ may be wider or narrower than the openings in dielectric layer 320 . The width W ₈ can be from about 80 μm to about 230 μm, such as about 150 μm, although other values are contemplated and may be used.

35 , some or all of the UBMs 322 of the first region 306A may have conductive pillars 322p disposed thereon, according to some embodiments. After forming the UBMs 322 , another photoresist may be formed by spin coating or the like and exposed to light for patterning. The pattern of photoresist corresponds to the pattern for the conductive pillars 322p. The patterning forms openings in the photoresist to expose the UBMs 322 . Plating, such as electroplating or electroless plating, or the like, until the conductive pillars 322p reach a desired height H ₉ , such as about 60 μm, such as about 10 μm to about 150 μm, or the like. Although the conductive material of fields 322p may be formed, other values are contemplated and may be used. The width W ₉ of the conductive pillars corresponds to the width of the openings in the pattern of photoresist. The width W ₉ may be from about 80 μm to about 230 μm, such as about 150 μm, although other values are contemplated and may be used. The conductive material may include a metal, such as copper, titanium, tungsten, aluminum, or the like. The photoresist is then removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. The resulting structure may have a shoulder 322s of UBMs 322 surrounding the base of the conductive pillars 322p.

Although the remaining figures illustrate conductive pillars 322p configured as described with respect to FIG. 35 , unless otherwise noted, where appropriate, configured as described with respect to FIG. 34 (i.e., UBM ( It should be understood that the conductive pillars 322p (without 322) may be substituted.

36-45 illustrate various intermediate steps in a process of forming a package structure including a fan-out bottom package and an interposer, in accordance with some embodiments. In FIG. 36 , the integrated circuit die 324 is disposed over the first redistribution structure 306 . The integrated circuit die 324 may include a logic die (eg, a central processing unit, a microcontroller, etc.), a memory die (eg, a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (eg, For example, a power management integrated circuit (PMIC) die, a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (eg, a digital signal processing (DSP) die), a front It may be a front-end die (eg, an analog front-end (AFE) die), the like, or a combination thereof (eg, a system-on-chip (SoC)).

The integrated circuit die 324 includes a semiconductor substrate in which devices such as transistors, diodes, capacitors, resistors, etc. are formed in and/or on the semiconductor substrate. Devices may be interconnected, for example, by interconnect structures formed by metallization patterns in one or more dielectric layers on a semiconductor substrate to form an integrated circuit. The integrated circuit die 324 further includes pads 326, such as aluminum pads, to which external connections are made. Pads 326 are on what may be referred to as respective active sides of integrated circuit die 324 and may be in uppermost layers of interconnect structures. Because the active side of the integrated circuit die 324 faces towards the first redistribution structure 306 , the first redistribution structure 306 may also be referred to as a front-side redistribution structure. And because the active side of the integrated circuit die 324 faces down towards the first redistribution structure 306 , the resulting package may be referred to as a bottom fan-out package. Conductive connectors 328 may be formed on the pads 326 . The conductive connectors 328 may be formed of a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors 328 are solder connectors.

The integrated circuit die 324 may be aligned and placed using, for example, a pick-and-place tool. An integrated circuit die 324 is disposed on the redistribution structure 306 such that the conductive connectors 328 are aligned with the UBMs 322 in the second region 306B. After the integrated circuit die 324 is placed, the conductive connectors 328 are reflowed to form joints between the corresponding UBMs 322 and the pads 326, so that the integrated circuit die 324 ) physically and electrically connected to the first redistribution structure 306 .

An underfill 330 may be formed between the integrated circuit die 324 and the first redistribution structure 306 to surround the conductive connectors 328 . As such, the conductive connectors 328 may be protected from mechanical forces. The underfill 330 may be formed by a capillary flow process after the integrated circuit die 324 is attached, or may be formed by a suitable deposition method before the integrated circuit die 324 is attached.

In FIG. 37 , the interposer substrate 100 (eg, see FIG. 7 ) is conductive to couple the conductive connectors 126 to respective conductive pillars of the conductive pillars 322p, according to some embodiments. aligned to pillars 322p. The interposer substrate 100 may be aligned and positioned using, for example, a pick-and-place tool. The interposer substrate 100 is disposed on the redistribution structure 306 such that the conductive connectors 126 are aligned with the UBMs 322 and/or the conductive pillars 322p in the first region 306A.

In FIG. 38 , after the interposer substrate 100 is disposed, the conductive connectors 126 are reflowed to form junctions between the corresponding conductive pillars 322p and the conductive lines 106 , so that the interposer substrate Physically and electrically connecting 100 to the first redistribution structure 306 . An encapsulant 334 is formed on the various components. The encapsulant 334 may be a molding compound, epoxy, or the like, and may be applied by compression molding, transfer molding, or the like. An encapsulant 334 may be formed over the first redistribution structure 306 so that the integrated circuit die 324 is buried or covered and a space between the interposer substrate 100 and the redistribution structure 306 is filled. The encapsulant 334 is then cured. In some embodiments, an encapsulant 334 is also formed between the first redistribution structure 306 and the integrated circuit die 324 , for example, in embodiments where the underfill 330 is omitted.

In some embodiments, such as illustrated in FIG. 39 , conductive connectors 126 may be reflowed to form around conductive pillars 322p . After the integrated circuit die 100 is placed, the conductive connectors 126 are reflowed to form junctions between the corresponding conductive pillars 322p and the conductive lines 106 to form the interposer substrate 100 . physically and electrically connected to the first redistribution structure 306 . In such embodiments, the conductive connectors 126 have a material extending down the entire length of the conductive pillar 322p to contact the shoulder 322s portion of the UBMs 322, thereby providing the conductive pillar 322p. may be formed of an amount of material to be embedded in the material of the conductive connectors. The shoulder 322s portion of the UBMs 322 may also be referred to as a “step”. The box drawn with dashed lines is enlarged in FIG. 40 .

In FIG. 40 , an enlarged view of the connections of FIG. 39 is provided, in accordance with some embodiments. 39 , after reflow, the material of the conductive connector 126 extends down along the conductive pillar 322p, covering the top and sidewalls of the conductive pillar 322p. The material of the conductive connector 126 extends to the shoulder 322s of the UBM 322 surrounding the conductive pillar 322p. The material of the conductive connector 126 is formed within lateral extents of the UBM 322 . As the material of the conductive connector 126 reflows, the conductive pillar 322p causes the material to flow around, forming a substantially uniform layer of material on the sidewalls of the conductive pillar 322p. It functions as a template. The shoulder 322s or step of the UBMs 322 serves as a template that defines the limits of the outer width of the reflowed conductive connector 126 . Conductive pillar 322p has a width D ₁ , which can be from about 80 μm to about 230 μm, and a height D ₂ , which can be from about 10 μm to about 150 μm. The conductive connector 126 may have a width D ₃ surrounding the conductive pillar 322p of about 100 μm to about 250 μm, where D ₃ is greater than D ₁ . In some embodiments, the width D ₄ above the conductive pillar 322p may be equal to the width D ₃ surrounding the conductive pillar 322p , resulting in a ratio D ₄ /D ₃ =1. In some embodiments, D ₄ may be smaller or greater than D ₃ , wherein the ratio of D ₄ /D ₃ is from about 0.8 to about 1.4. The height D ₅ of the conductive connector 126 after reflow corresponds to the space between the substrate core 110 of the interposer substrate 100 and the redistribution structure 306 , and may be about 80 μm to about 180 μm. . It should be understood that these dimensions are examples and other dimensions may be used where appropriate.

Because the conductive pillar 322p is encapsulated by the material of the conductive connector 126 , there is a CTE mismatch between the differently formed structures, such as the interposer substrate 100 and the redistribution structure 306 . ), a strong joint is formed that can better withstand the torsional stresses induced by Withstanding torsion stresses reduces joint failure and reduces warpage. The process of forming the junction between the conductive pillar 322p and the conductive connector 126 is bridging to other connectors because the conductive pillar 322p and the shoulder 322s serve as templates for controlling reflow. ) also has the advantage of providing a reduced risk of This process allows good self-alignment despite also enabling fine-pitch joints. A solid joint provides a high joint rate and joint reliability. This process also provides a controlled bonding standoff using conductive pillars 322p.

In Figure 41, the carrier substrate 302 is removed. The carrier substrate 302 may be separated (or “debonded”) from the redistribution structure 306 . In some embodiments, debonding involves projecting light, such as laser light or UV light, onto the release layer 304 such that the release layer 304 can decompose due to the heat of the light and the carrier substrate 302 can be removed. include that This structure is then flipped over and placed on the tape. The debonding exposes the metallization patterns 310 of the redistribution structure 306 .

In FIG. 42 , conductive connectors 352 are formed over the redistribution structure 306 . The conductive connectors 352 contact exposed portions of the metallization patterns 310 . In some embodiments, a passivation layer is used over the metallization patterns 310 and may be patterned to expose portions of the metallization patterns 310 prior to forming the conductive connectors 352 . In some embodiments, UBMs may be formed over exposed portions of the metallization patterns 310 . In such embodiments, the UBMs may be formed using processes and materials similar to the UBMs 322 . Conductive connectors 352 are formed by ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG). bumps, or the like. The conductive connectors 352 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors 352 are formed by initially forming a layer of solder via commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. Solder connectors that become Once a layer of solder has been formed on this structure, reflow may be performed to shape the material into desired bump shapes. In another embodiment, the conductive connectors 352 include metal pillars (such as copper pillars) formed by printing, electroplating, electroless plating, chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. The metal pillars are solder free and may have substantially vertical sidewalls. After forming the conductive connectors 352 , the structure can be turned over and placed on a tape or secured by the conductive connectors 352 . In some embodiments, package 300 may be singulated directly with dies on tape after forming conductive connectors 352 (not shown).

43 , the device 500 may be mounted on the interposer substrate 100 to form a 3D package 600 . Device 500 may include integrated circuit dies or other interposer. The device 500 may include an optional redistribution structure 506 and a device substrate 510 . The redistribution structure 506 may be formed using processes and materials similar to those discussed above with respect to the redistribution structure 306 . The device substrate 510 may include integrated circuit dies including antennas, memory dies, RF dies, passive devices, or combinations thereof, and the like. Integrated circuit dies include a semiconductor substrate, in which devices such as transistors, diodes, capacitors, resistors, etc. are formed in and/or on the semiconductor substrate. Devices may be interconnected, for example, by interconnect structures formed by metallization patterns in one or more dielectric layers on a semiconductor substrate to form an integrated circuit. Device 500 may include conductive connectors 536 formed on redistribution structure 506 . The conductive connectors 536 may be formed of a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. Device 500 may be mounted to interposer substrate 100 by coupling conductive connectors 536 through solder resist layer 124 to exposed portions of conductive lines 113 . In some embodiments, the conductive connectors 536 are reflowed to attach the device 500 to the conductive lines 113 .

In FIG. 44 , a package 600 (eg, see FIG. 43 ) may be mounted on a package substrate 650 using conductive connectors 352 to form a 3D package 700 . The package substrate 650 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, and the like can also be used. Additionally, the package substrate 650 may be a silicon-on-insulator (SOI) substrate. In general, an SOI substrate includes a layer of semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon-genanium-on-insulator (SGOI), or combinations thereof. The package substrate 650, in one alternative embodiment, is based on an insulating core, such as a fiberglass reinforced resin core. One exemplary core material is a fiberglass resin such as FR4. Alternatives to the core material include bismaleimide-triazine (BT) resin, or alternatively, other PCB materials or films. Build-up films such as Ajinomoto Build-up film (ABF), multi-layer core (MLC) substrate, or other laminates may be used for package substrate 650 .

The package substrate 650 may include active and passive devices (not shown). As one of ordinary skill in the art will recognize, a wide variety of devices, such as transistors, capacitors, resistors, combinations thereof, and the like, are structural and functional in design for package substrate 650 . It can be used to create requirements. The devices may be formed using any suitable methods.

The package substrate 650 may also include metallization layers and vias (not shown) and bond pads 664 over the metallization layers and vias. Metallization layers can be formed over active and passive devices and are designed to connect various devices to form functional circuitry. The metallization layers may be formed of alternating layers of a dielectric material (eg, low-k dielectric material) and a conductive material (eg, copper) having vias interconnecting the layers of conductive material (eg, deposition, damascene) ), dual damascene, or the like) may be formed through any suitable process. In some embodiments, the package substrate 650 is substantially free of active and passive devices.

In some embodiments, the conductive connectors 352 are reflowed to attach the package 600 ( FIG. 43 ) to the bond pads 664 of the package substrate 650 . The conductive connectors 352 electrically and/or physically couple the package substrate 650 , including metallization layers in the package substrate 650 , to the redistribution structure 306 of the package 300 . In some embodiments, passive devices (eg, not illustrated, surface mount devices (SMDs)) are to be attached to the package 300 (eg, a redistribution structure) prior to mounting on the package substrate 650 . to the surface of 306). In such embodiments, passive devices may be bonded to the same surface of package 300 as conductive connectors 352 .

In some embodiments, an underfill (not shown) may be formed between the package 300 and the package substrate 650 and surrounding the conductive connectors 352 . The underfill may be formed by a capillary flow process after package 600 (FIG. 43) is attached, or may be formed by a suitable deposition method before package 600 is attached.

Other features and processes may also be included. For example, testing structures may be included to aid in 3D packaging or verification testing of 3DIC devices. The test structures may include test pads formed in a redistribution layer or on a substrate, enabling, for example, 3D packaging or testing of 3DIC, the use of probes and/or probe cards, and the like. may include Verification tests can be performed on the final structures as well as the intermediate structures. Additionally, the structures and methods disclosed herein can be used in connection with test methodologies that include interim verification of known good dies to increase yield and reduce cost.

45 shows that package 300 is formed as previously discussed with respect to FIG. 39 , i.e., with conductive connectors 126 extending down along conductive pillar 322p and contacting shoulder 322s. Except that it illustrates a package 700 that is similar to the package 700 of FIG. 44 .

46 and 47 illustrate views of a package that does not have an interposer, but includes a fan-out bottom package and a second device attached to each other using connectors surrounding a metal pillar, in accordance with some embodiments. . Figure 46 illustrates a package 700' similar to the package 700 of Figure 45, except that the interposer substrate 100 is not included. As discussed above, one of the purposes of the interposer substrate 100 may be to provide support to reduce warpage and reduce the likelihood of failing joints between packages. Conductive connectors 126 , such as discussed above with respect to FIGS. 39 and 40 , provide a strong connection so that the interposer substrate 100 can be omitted in some embodiments. In such embodiments, device 500 attaches to conductive pillars 322p in a manner similar to mounting interposer substrate 100 to conductive pillars 322p, discussed above with respect to FIGS. 39 and 40 . can be mounted.

47 illustrates a package 700 ′ similar to package 700 ′ of FIG. 46 , except that an adhesive layer 332 may be used between the device 500 and the integrated circuit die 324 , and there is. Adhesive layer 332 may be any suitable adhesive, epoxy, underfill, die attach film (DAF), thermal interface material, or the like. An adhesive layer 332 may be applied to the backside of the integrated circuit dies 324 , or, for each integrated circuit die 324 , may be applied to a die attach area of the device 500 . . For example, an adhesive layer 332 may be applied to the backside of the integrated circuit dies 324 prior to singulating to separate the integrated circuit dies 324 , or to separate the device 500 . It may be applied to the front surface of the device 500 prior to singulating for the purpose. In some embodiments, the adhesive layer 332 may be added in a separate process to either the integrated circuit dies 324 or the device 500 immediately prior to bonding the device 500 to the conductive pillars 322p. can

48-79 illustrate embodiments that are variations on previously discussed embodiments, including different and/or additional features. 48-50 illustrate various intermediate steps in a process of forming a package structure including an interposer and a fan-out bottom package with an adhesive formed therebetween, in accordance with some embodiments. FIG. 48 illustrates an embodiment as discussed above with respect to FIG. 37 . 48 , an adhesive layer 332 may be disposed on the interposer substrate 100 and/or integrated circuit dies 324 prior to bonding the interposer substrate 100 to the conductive pillars 322p. . Adhesive layer 332 may be any suitable adhesive, epoxy, underfill, die attach film (DAF), thermal interface material, or the like. An adhesive layer 332 may be applied to the backside of the integrated circuit dies 324 , or, for each integrated circuit die 324 , may be applied to the die attach region of the interposer substrate 100 . For example, an adhesive layer 332 may be applied to the backside of the integrated circuit dies 324 prior to singulating to separate the integrated circuit dies 324 , or to separate the interposer substrate 100 . It may be applied to the entire surface of the interposer substrate 100 before singulating for the purpose.

48 , interposer substrate 100 is aligned with conductive pillars 322p, in accordance with some embodiments. The interposer substrate 100 may be aligned and positioned using, for example, a pick-and-place tool. The interposer substrate 100 is disposed on the redistribution structure 306 such that the conductive connectors 126 are aligned with the UBMs 322 and/or the conductive pillars 322p in the first region 306A.

49 , after the interposer substrate 100 is disposed, the conductive connectors 126 are reflowed to form junctions between the corresponding conductive pillars 322p and the conductive lines 106 , so that the interposer substrate Physically and electrically connecting 100 to the first redistribution structure 306 . As discussed above with respect to FIG. 38 , an encapsulant 334 may be formed.

In FIG. 50 , as discussed above with respect to FIG. 41 , the carrier substrate 302 is removed. As discussed above with respect to FIG. 42 , conductive connectors 352 are formed over the redistribution structure 306 . Device 500 may be mounted on interposer substrate 100 to form package 600 , as discussed above with respect to FIG. 43 . As discussed above with respect to FIG. 44 , package 600 may be mounted to package substrate 650 .

FIG. 51 illustrates an embodiment as discussed above with respect to FIG. 36 . After mounting the integrated circuit dies 324 , an encapsulant 334 may be formed over the redistribution structure 306 to laterally surround the integrated circuit dies 324 and the conductive pillars 322p . In some embodiments, encapsulant 334 may also extend over top surfaces of integrated circuit dies 324 and/or conductive pillars 322p. An upper portion of the encapsulant 334 may then be removed by a removal process to level the upper surfaces of the conductive pillars 322p relative to each other. In some embodiments, the top surfaces of the conductive pillars 322p may also be leveled flush with the top surface of the integrated circuit dies 324 by a removal process. The removal process may be, for example, a CMP and/or etch-back process. Encapsulant 334 may be formed using processes and materials similar to those discussed above with respect to FIG. 38 .

52 , prior to bonding interposer substrate 100 to conductive pillars 322p , an adhesive layer 332 may be disposed on interposer substrate 100 and/or integrated circuit dies 324 . . The adhesive layer 332 may be similar to the adhesive layer 332 of FIG. 48 . The interposer substrate 100 is aligned with the conductive pillars 322p. The interposer substrate 100 may be aligned and positioned using, for example, a pick-and-place tool. The interposer substrate 100 is disposed on the encapsulant 334 such that the conductive connectors 126 are aligned with the conductive pillars 322p in the first region 306A.

53 , after the interposer substrate 100 is disposed, the conductive connectors 126 are reflowed to form junctions between the corresponding conductive pillars 322p and the conductive lines 106 , so that the interposer substrate Physically and electrically connecting 100 to the first redistribution structure 306 . An adhesive layer 332 may be interposed between the interposer substrate 100 and the integrated circuit dies 324 to contact both the interposer substrate 100 and the integrated circuit dies 324 .

In FIG. 54 , as previously discussed in connection with FIG. 41 , the carrier substrate 302 is removed. As discussed above with respect to FIG. 42 , conductive connectors 352 are formed over the redistribution structure 306 . Device 500 may be mounted on interposer substrate 100 to form package 600 , as discussed above with respect to FIG. 43 . As discussed above with respect to FIG. 44 , package 600 may be mounted to package substrate 650 .

55-70 illustrate various intermediate steps in a process of forming a package structure including a fan-out bottom package and an interposer having a cavity or through hole formed therein, in accordance with some embodiments; there is. In FIG. 55 , an interposer substrate 100 having a cavity 124c formed in a solder resist layer 124 is provided. Cavity 124c may be formed in a manner similar to the formation of cavity 130 discussed above with respect to FIG. 11 . Once the interposer substrate 100 is mounted to the conductive pillars 322p and/or the UBMs 322 , the reinforcement structures 120 and/or the reinforcement structures 122 are attached to the integrated circuit dies 324 . Cavity 124c may be formed such that cavity 124c is aligned with integrated circuit dies 324 to be proximate. In some embodiments, cavity 124c may be sized and positioned to allow integrated circuit dies 324 to recess into cavity 124c upon mounting. This may help to reduce the overall height of the finished package as well as provide better heat dissipation from the integrated circuit dies 324 to the reinforcement structures 120 and/or the reinforcement structures 122 .

According to some embodiments, the interposer substrate 100 is aligned with the conductive pillars 322p. The interposer substrate 100 may be aligned and positioned using, for example, a pick-and-place tool. The interposer substrate 100 is disposed on the redistribution structure 306 such that the conductive connectors 126 are aligned with the UBMs 322 and/or the conductive pillars 322p in the first region 306A.

In Fig. 56, after the interposer substrate 100 is disposed, the conductive connectors 126 are reflowed to form junctions between the corresponding conductive pillars 322p and the conductive lines 106, so that the interposer substrate Physically and electrically connecting 100 to the first redistribution structure 306 . As discussed above with respect to FIG. 38 , an encapsulant 334 may be formed. In some embodiments, the encapsulant 334 is an integrated circuit die such that the encapsulant 334 is disposed between the top surface of the integrated circuit dies 324 and the bottom of the substrate core 110 of the interposer substrate 100 . It may flow into the space between the 324 and the interposer substrate 100 .

In FIG. 57 , as previously discussed in connection with FIG. 41 , the carrier substrate 302 is removed. As discussed above with respect to FIG. 42 , conductive connectors 352 are formed over the redistribution structure 306 . Device 500 may be mounted on interposer substrate 100 to form package 600 , as discussed above with respect to FIG. 43 . As discussed above with respect to FIG. 44 , package 600 may be mounted to package substrate 650 .

In FIG. 58 , an interposer substrate 100 is provided having an opening 124o formed in the solder resist layer 124 , as previously discussed in connection with FIG. 55 . Prior to bonding the interposer substrate 100 to the conductive pillars 322p , an adhesive layer 332 may be disposed on the interposer substrate 100 and/or the integrated circuit dies 324 . The adhesive layer 332 may be similar to the adhesive layer 332 of FIG. 48 . The interposer substrate 100 is aligned with the conductive pillars 322p. The interposer substrate 100 may be aligned and positioned using, for example, a pick-and-place tool. The interposer substrate 100 is disposed on the redistribution structure 306 such that the conductive connectors 126 are aligned with the conductive pillars 322p in the first region 306A.

In FIG. 59 , after the interposer substrate 100 is disposed, the conductive connectors 126 are reflowed to form junctions between the corresponding conductive pillars 322p and the conductive lines 106 , so that the interposer substrate Physically and electrically connecting 100 to the first redistribution structure 306 . An adhesive layer 332 may be interposed between the interposer substrate 100 and the integrated circuit dies 324 to contact both the interposer substrate 100 and the integrated circuit dies 324 .

In FIG. 60 , the carrier substrate 302 is removed, as previously discussed in connection with FIG. 41 . As discussed above with respect to FIG. 42 , conductive connectors 352 are formed over the redistribution structure 306 . Device 500 may be mounted on interposer substrate 100 to form package 600 , as discussed above with respect to FIG. 43 . As discussed above with respect to FIG. 44 , package 600 may be mounted to package substrate 650 .

In FIG. 61 , an interposer substrate 100 is provided having a cavity 130 (see FIG. 11 ) formed in a substrate core 110 . Once the interposer substrate 100 is mounted to the conductive pillars 322p and/or the UBMs 322 , the cavity 130 is positioned such that the integrated circuit dies 324 are at least partially disposed within the cavity 130 . Cavity 130 may be formed to align with dies 324 . This can help reduce the overall height of the finished package. The reinforcement structures 120 and/or the reinforcement structures 122 may also provide support and heat dissipation of the integrated circuit dies 324 .

According to some embodiments, the interposer substrate 100 is aligned with the conductive pillars 322p. The interposer substrate 100 may be aligned and positioned using, for example, a pick-and-place tool. The interposer substrate 100 is disposed on the redistribution structure 306 such that the conductive connectors 126 are aligned with the conductive pillars 322p in the first region 306A.

In FIG. 62 , after the interposer substrate 100 is disposed, the conductive connectors 126 are reflowed to form junctions between the corresponding conductive pillars 322p and the conductive lines 106 , so that the interposer substrate Physically and electrically connecting 100 to the first redistribution structure 306 . As discussed above with respect to FIG. 38 , an encapsulant 334 may be formed. In some embodiments, the encapsulant 334 is disposed between the top surface of the integrated circuit dies 324 and the bottom of the substrate core 110 of the interposer substrate 100 in the cavity 130 . ) may flow into the space between the integrated circuit dies 324 and the interposer substrate 100 .

In some embodiments, after bonding the interposer substrate 100 to the conductive pillars 322p , the integrated circuit dies 324 may be disposed at least partially within the cavity 130 (see FIG. 61 ).

In FIG. 63 , the carrier substrate 302 is removed, as previously discussed with respect to FIG. 41 . As discussed above with respect to FIG. 42 , conductive connectors 352 are formed over the redistribution structure 306 . Device 500 may be mounted on interposer substrate 100 to form package 600 , as discussed above with respect to FIG. 43 . As discussed above with respect to FIG. 44 , package 600 may be mounted to package substrate 650 .

In FIG. 64 , an interposer substrate 100 is provided having a cavity 130 formed therein, as previously discussed with respect to FIG. 61 . Prior to bonding the interposer substrate 100 to the conductive pillars 322p , an adhesive layer 332 may be disposed on the interposer substrate 100 and/or the integrated circuit dies 324 . The adhesive layer 332 may be similar to the adhesive layer 332 of FIG. 48 . The interposer substrate 100 is aligned with the conductive pillars 322p. The interposer substrate 100 may be aligned and positioned using, for example, a pick-and-place tool. The interposer substrate 100 is disposed on the redistribution structure 306 such that the conductive connectors 126 are aligned with the conductive pillars 322p in the first region 306A.

65 , after the interposer substrate 100 is disposed, the conductive connectors 126 are reflowed to form junctions between the corresponding conductive pillars 322p and the conductive lines 106 , so that the interposer substrate Physically and electrically connecting 100 to the first redistribution structure 306 . An adhesive layer 332 may be interposed between the interposer substrate 100 and the integrated circuit dies 324 to contact both the interposer substrate 100 and the integrated circuit dies 324 .

In some embodiments, after bonding the interposer substrate 100 to the conductive pillars 322p , the integrated circuit dies 324 may be disposed at least partially within the cavity 130 (see FIG. 64 ).

In FIG. 66 , the carrier substrate 302 is removed, as previously discussed in connection with FIG. 41 . As discussed above with respect to FIG. 42 , conductive connectors 352 are formed over the redistribution structure 306 . Device 500 may be mounted on interposer substrate 100 to form package 600 , as discussed above with respect to FIG. 43 . Package 600 may be mounted on package substrate 650 to form package 700 , as discussed above with respect to FIG. 44 .

In FIG. 67 , an interposer substrate 100 having a through hole 140 (see FIG. 12 ) formed in the substrate core 110 is provided. Once the interposer substrate 100 is mounted to the conductive pillars 322p and/or the UBMs 322 , the through hole 140 is formed such that the integrated circuit dies 324 are at least partially disposed within the through hole 140 . A through hole 140 may be formed to align with the integrated circuit dies 324 . In some embodiments, the integrated circuit dies 324 are mounted within the through hole 140 such that the top surface of the integrated circuit dies 324 is flush with or lower than the level of the top surface of the interposer substrate 100 . can be This can reduce the overall height of the finished package. The reinforcing structures 120 and/or the reinforcing structures 122 may be disposed within a peripheral portion of the interposer substrate 100 .

According to some embodiments, the interposer substrate 100 is aligned with the conductive pillars 322p or UBMs 322 . The interposer substrate 100 may be aligned and positioned using, for example, a pick-and-place tool. The interposer substrate 100 is disposed on the redistribution structure 306 such that the conductive connectors 126 are aligned with the conductive pillars 322p or UBMs 322 in the first region 306A.

In FIG. 68 , after the interposer substrate 100 is disposed, the conductive connectors 126 are reflowed to form junctions between the corresponding conductive pillars 322p or UBMs 322 and the conductive lines 106 . formed to physically and electrically connect the interposer substrate 100 to the first redistribution structure 306 . As discussed above with respect to FIG. 38 , an encapsulant 334 may be formed. In some embodiments, the encapsulant 334 is an integrated circuit such that the encapsulant 334 is interposed between the sides of the integrated circuit dies 324 and sidewalls of the through hole 140 of the interposer substrate 100 . It can flow around the dies 324 and the interposer substrate 100 . The encapsulant 334 may also flow over the top surface of the interposer. The encapsulant 334 is leveled to have a top surface flush with the top surface of the interposer substrate 100 and/or the integrated circuit dies 324 using a removal process, such as a CMP and/or etch-back process. can be

In some embodiments, after bonding the interposer substrate 100 to the conductive pillars 322p or UBMs 322 , the integrated circuit dies 324 may be at least partially disposed within the through hole 140 . There is (see FIG. 67).

69 , the carrier substrate 302 is removed, as previously discussed with respect to FIG. 41 . As discussed above with respect to FIG. 42 , conductive connectors 352 are formed over the redistribution structure 306 . Device 500 may be mounted on interposer substrate 100 to form package 600 , as discussed above with respect to FIG. 43 . Package 600 may be mounted on package substrate 650 to form package 700 , as discussed above with respect to FIG. 44 .

70 , an adhesive layer 332 may be disposed on device 500 and/or integrated circuit dies 324 prior to bonding interposer substrate 100 to conductive pillars 322p . The adhesive layer 332 may be similar to the adhesive layer 332 of FIG. 47 . The adhesive layer 332 may provide better stability and help reduce warpage due to CTE mismatch. The adhesive layer 332 may also be a thermal compound to help dissipate heat from the integrated circuit dies 324 . The interposer substrate 100 is aligned with the conductive pillars 322p or UBMs 322 in the first region 306A. The interposer substrate 100 may be aligned and positioned using, for example, a pick-and-place tool. The interposer substrate 100 is disposed on the redistribution structure 306 such that the conductive connectors 126 are aligned with the conductive pillars 322p or UBMs 322 in the first region 306A.

71-79 illustrate various embodiments similar to those discussed above with respect to FIGS. 44-70, except that an interposer substrate 200 is used. As previously discussed, interposer substrate 200 includes at least two core substrate layers having recessed bond pads formed therein, eg, substrate core 110 and substrate core 210 as illustrated in FIG. 71 . ) has 71 shows that the interposer substrate 200 has recesses 250 formed through the upper substrate core 210, and the recesses 250 expose an underlying recessed bond pad 113p. also exemplifies The interposer substrate 200 is also illustrated with a metal liner 260 lining the recesses 250 , as discussed above with respect to FIG. 21 . Although metal liner 260 is depicted in the figures discussed below, it should be understood that metal liner 260 is optional. The reinforcing structures 120 and the reinforcing structures 220 are illustrated, for example, as being formed in the interposer substrate 200 in FIG. 71 . As discussed above with respect to FIGS. 17-25 , any of the reinforcing structures 120 , 122 , and/or 220 may be optionally omitted. Although reinforcing structures 120 and 220 are illustrated for context, it should be understood that embodiments that do not include reinforcing structures 120 , 122 , and/or 220 are included.

The recesses 250 in the interposer substrate 200 reduce the overall package height when an additional device or package is bonded to the recessed bond pads 113p. Deep recesses also provide good alignment for bonding additional devices or packages. Interposer substrate 200 , even without optional reinforcement structures 120 , 122 , or 220 , still provides some structural support and helps to reduce warpage.

71 , interposer substrate 200 is aligned with conductive pillars 322p, in accordance with some embodiments. The interposer substrate 200 may be aligned and positioned using, for example, a pick-and-place tool. The interposer substrate 200 is disposed on the redistribution structure 306 such that the conductive connectors 126 are aligned with the conductive pillars 322p in the first region 306A.

After the interposer substrate 200 is disposed, the conductive connectors 126 are reflowed to form junctions between the conductive lines 106 and the corresponding conductive pillars 322p and/or UBMs 322 . , physically and electrically connecting the interposer substrate 200 to the first redistribution structure 306 . In some embodiments, the conductive connectors 126 may extend from the interposer substrate 200 to the UBM 322 , as illustrated by the conductive connector 126a in FIG. 71 . As discussed above with respect to FIG. 38 , an encapsulant 334 may be formed.

In FIG. 72 , the carrier substrate 302 is removed, as previously discussed in connection with FIG. 41 . As discussed above with respect to FIG. 42 , conductive connectors 352 are formed over the redistribution structure 306 . Device 500 may be mounted on interposer substrate 200 to form package 600 , as discussed above with respect to FIG. 43 . Package 600 may be mounted on package substrate 650 to form package 800 , as discussed above with respect to FIG. 44 .

73 , an adhesive layer 332 may be disposed on device 500 and/or integrated circuit dies 324 prior to bonding interposer substrate 200 to conductive pillars 322p . The adhesive layer 332 may be similar to the adhesive layer 332 of FIG. 47 .

In Fig. 74, an interposer substrate 200 having a cavity 230 formed therein is provided (see Figs. 27-29). The cavity 230 is aligned with the integrated circuit dies 324 such that the integrated circuit dies 324 are at least partially disposed within the cavity 230 once the interposer substrate 200 is mounted to the conductive pillars 322p. A cavity 230 may be formed. This can help reduce the overall height of the finished package. The height of the cavity 230 may vary as discussed above with respect to FIGS. 22-24 and 27-29 . Reinforcing structures 120 and/or reinforcing structures 122 and/or reinforcing structures 220 may also provide support and heat dissipation of integrated circuit dies 324 .

According to some embodiments, the interposer substrate 200 is aligned with the conductive pillars 322p. The interposer substrate 200 may be aligned and positioned using, for example, a pick-and-place tool. The interposer substrate 200 is disposed on the redistribution structure 306 such that the conductive connectors 126 are aligned with the conductive pillars 322p in the first region 306A.

After the interposer substrate 200 is disposed, the conductive connectors 126 are reflowed to form junctions between the corresponding conductive pillars 322p and the conductive lines 106 to form the interposer substrate 200 . physically and electrically connected to the first redistribution structure 306 . As discussed above with respect to FIG. 38 , an encapsulant 334 may be formed. In some embodiments, the encapsulant 334 is disposed between the top surfaces of the integrated circuit dies 324 and the bottom of the substrate core 110 of the interposer substrate 200 in the cavity 230 . 334 may flow into the space between the integrated circuit dies 324 and the interposer substrate 200 .

In some embodiments, after bonding the interposer substrate 200 to the conductive pillars 322p , the integrated circuit dies 324 may be disposed at least partially within the cavity 230 .

In FIG. 75 , as discussed above with respect to FIG. 41 , the carrier substrate 302 is removed. As discussed above with respect to FIG. 42 , conductive connectors 352 are formed over the redistribution structure 306 . Device 500 may be mounted on interposer substrate 200 to form package 600 , as discussed above with respect to FIG. 43 . Because interposer substrate 200 has recessed bond pads 113p, device 500 is securely attached using larger conductive connectors 536 than if the bond pads were not recessed. Recessed bond pads 113p may also help to reduce the overall package height. As discussed above with respect to FIG. 44 , package 600 may be mounted to package substrate 650 .

76 , an adhesive layer 332 may be disposed on device 500 and/or integrated circuit dies 324 prior to bonding interposer substrate 200 to conductive pillars 322p . The adhesive layer 332 may be similar to the adhesive layer 332 of FIG. 47 .

In FIG. 77 , an interposer substrate 200 having a through hole 240 formed therein is provided (see, eg, FIG. 25 or 30 ). Once the interposer substrate 200 is mounted to the conductive pillars 322p and/or the UBMs 322 , the through hole 240 is formed such that the integrated circuit dies 324 are at least partially disposed within the through hole 240 . A through hole 140 may be formed to align with the integrated circuit dies 324 . This can help reduce the overall height of the finished package. In some embodiments, the integrated circuit dies 324 are mounted within the through hole 240 such that the top surface of the integrated circuit dies 324 is flush with or lower than the level of the top surface of the interposer substrate 200 . can be Reinforcing structures 120 and/or reinforcing structures 122 and/or reinforcing structures 220 may be disposed within a peripheral portion of interposer substrate 200 and support and heat the integrated circuit dies 324 . Dissipation can be provided.

According to some embodiments, the interposer substrate 200 is aligned with the conductive pillars 322p and/or the UBMs 322 . The interposer substrate 200 may be aligned and positioned using, for example, a pick-and-place tool. The interposer substrate 200 is disposed on the redistribution structure 306 such that the conductive connectors 126 are aligned with the conductive pillars 322p and/or UBMs 322 in the first region 306A.

After the interposer substrate 200 is disposed, the conductive connectors 126 are reflowed to form junctions between the conductive lines 106 and the corresponding conductive pillars 322p and/or UBMs 322 . , physically and electrically connecting the interposer substrate 200 to the first redistribution structure 306 . As discussed above with respect to FIG. 38 , an encapsulant 334 may be formed. In some embodiments, the encapsulant 334 may flow around and over the integrated circuit dies 324 as described above with respect to FIG. 68 .

In some embodiments, after bonding the interposer substrate 200 to the conductive pillars 322p and/or UBMs 322 , the integrated circuit dies 324 are disposed at least partially within the through hole 240 . can be

78 , the carrier substrate 302 is removed, as previously discussed with respect to FIG. 41 . As discussed above with respect to FIG. 42 , conductive connectors 352 are formed over the redistribution structure 306 . Device 500 may be mounted on interposer substrate 200 to form package 600 , as discussed above with respect to FIG. 43 . Because interposer substrate 200 has recessed bond pads 113p, device 500 is securely attached using larger conductive connectors 536 than if the bond pads were not recessed. Recessed bond pads can also help reduce overall package height. As discussed above with respect to FIG. 44 , package 600 may be mounted to package substrate 650 .

79 , prior to bonding interposer substrate 200 to conductive pillars 322p and/or UBMs 322 , an adhesive layer 332 is applied to device 500 and/or integrated circuit dies 324 . may be placed on the The adhesive layer 332 may be similar to the adhesive layer 332 of FIG. 47 .

Embodiments provide an interposer bonded to a packaged device, wherein the interposer includes reinforcement structures 120 , irregular reinforcement structures 122 , reinforcement structures 220 , or combinations thereof. Reinforcing structures provide stiffness, heat dissipation, and help reduce stress, and warpage of the package. An adhesive layer may be used between the interposer and the integrated circuit die to improve adhesion and/or heat dissipation. In some embodiments, the molding compound may be formed prior to bonding the interposer to the package device, while in other embodiments, the molding compound may be formed after bonding the interposer to the package device.

In some embodiments, the cavity or through hole is aligned with the integrated circuit die of the packaged device such that the integrated circuit die is at least partially disposed within the cavity or through hole to help reduce the overall height of the package. A through hole may be formed in the interposer. If a cavity is used, an adhesive layer may be used between the interposer and the integrated circuit die. If a through hole is used, an adhesive layer may be used between the integrated circuit die and the overlying device that is bonded to the top of the interposer.

In some embodiments, the interposer may have at least a second core substrate layer such that a recess bond pad may be formed between the two core substrate layers. The recessed bond pads provide a strong interface point for mounting the device over the interposer. Recessed bond pads also help to reduce the overall height of the finished package. An optional layer of adhesive may be used between the interposer and the device mounted over the interposer. In some embodiments, the recessed bond pad may also include a metal liner lining the opening in the interposer to the recessed bond pad. In embodiments having at least a second core layer, reinforcing structures may be omitted from the interposer.

Each of these embodiments may include a coupling technique for coupling the interposer to a packaged device using stepped bond pads that embed metal pillars in solder material from the interposer. In some embodiments, a coupling technique using stepped bond pads may be used to directly mount the device to a packaged device without the use of an interposer.

Embodiments provide various ways to increase the stiffness and strength of a finished package using an interposer and a lower fan-out package, including, for example, reinforcement structures, recessed bond pads, and stepped bond pads. provide them Some embodiments advantageously also use techniques to reduce the overall height of the package to help save space and provide more efficient heat dissipation through thinner components.

Efforts have been made to describe variations to embodiments, however, such that the techniques described in the embodiments discussed herein combine aspects from one embodiment with aspects from one or more other embodiments. It should be understood that they may be combined to create variations on the embodiments. Such combinations should not be considered undue burdensome, not require undue experimentation, and should be considered to be within the scope of the present disclosure.

One embodiment is a method comprising forming an opening in a core layer of an interposer. A reinforcing structure is formed within the opening, the reinforcing structure extending from a first surface of the interposer to a second surface of the interposer, wherein the reinforcing structure is electrically isolated from the conductive features of the interposer. First connectors are formed on the interposer at a first surface of the interposer. The first connectors of the interposer are bonded to second connectors of the first packaged device. A molding compound is formed between the interposer and the first package device.

Another embodiment is a method comprising aligning first connectors of a first package element to second connectors of a second package element, the first connectors comprising solder materials, each of the second connectors comprising a metal step It includes a metal pillar protruding from the (metal step). The first connectors contact the second connectors and the solder materials reflow, where the solder materials flow to surround each of the metal pillars and contact each of the metal steps. The portion of solder materials surrounding the metal pillars is within the lateral extent of the metal step.

Another embodiment is a structure including a first device package, the first device package including an integrated circuit die having an active side facing downward. The first device package also includes a redistribution structure coupled to one or more contacts of the integrated circuit die and first contacts disposed on a top surface of the redistribution structure. The structure also includes an interposer, the interposer including a substrate core layer having one or more metal vias disposed in the substrate core layer and one or more reinforcing structures disposed in the substrate core layer. The one or more reinforcing structures are electrically decoupled. Second contacts are disposed on the lower surface of the interposer, and the first contacts are coupled to respective second contacts of the second contacts.

The foregoing outlines features of some embodiments so that those skilled in the art may better understand aspects of the present disclosure. A person skilled in the art will readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. You have to recognize that you can. Those skilled in the art can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure, and that such equivalent constructions do not depart from the spirit and scope of the present disclosure. It should also be known that

<bookkeeping>

1. A method comprising:

forming an opening in the core layer of the interposer;

forming a reinforcing structure within the opening, the reinforcing structure extending from a first surface of the interposer to a second surface of the interposer, the reinforcing structure being electrically isolated from conductive features of the interposer; ;

forming first connectors on the interposer at the first surface of the interposer;

bonding the first connectors of the interposer to second connectors of a first packaged device; and

forming a molding compound between the interposer and the first package device;

A method comprising

2. according to clause 1,

and forming an adhesive layer between the interposer and the integrated circuit die of the first packaged device, the adhesive layer in contact with both the integrated circuit die and the interposer.

3. according to clause 1,

and forming a cavity in the core layer of the interposer, wherein after bonding the first connectors to the second connectors, the integrated circuit die is at least partially disposed within the cavity.

4. The method of clause 3, wherein the cavity extends completely through the interposer to form a through hole.

5. The method of clause 1, wherein the core layer of the interposer is a first core layer, the method comprising:

forming a second core layer of the interposer; and

forming a second opening in the second core layer of the interposer, the second opening exposing a recess bond pad disposed between the first core layer and the second core layer; Way.

6. according to claim 5,

and forming a metal film within the second opening, wherein the metal film lines sidewalls and a bottom of the second opening.

7. The method of claim 1, wherein bonding the first connectors of the interposer to second connectors of a first package device comprises:

aligning the first connectors to the second connectors; and

reflowing eutectic material to couple the first connectors to the second connectors.

8. The eutectic material of clause 7, wherein the eutectic material laterally encapsulates a first vertical portion of the second connectors and contacts a second horizontal portion of the second connectors, the first vertical portion being a metal and a metal pillar, and wherein the second horizontal portion includes a step through which the metal pillar protrudes.

9. The method of claim 8, wherein the eutectic material is within lateral extents of the second horizontal portion.

10. A method comprising:

aligning the first connectors of the first package element to second connectors of the second package element, the first connectors comprising solder materials, each of the second connectors protruding from a metal step including metal pillars;

contacting the first connectors to the second connectors; and

reflowing the solder materials.

wherein the solder materials flow to surround each of the metal pillars and are in contact with each of the metal steps, wherein a portion of the solder materials surrounding the metal pillars is within a lateral extent of the metal step. .

11. The method of claim 10, wherein the first package element comprises an interposer or integrated circuit die and the second package corresponds to a bottom fan out package.

12. Paragraph 10,

after reflowing the solder materials, depositing a molding compound between the first package element and the second package element, the molding compound surrounding the solder materials.

13. The method of clause 12, wherein the second package element is coupled to the first package element at a first surface of the first package element, the method comprising:

and coupling a third package element to a second surface of the first package element, wherein the second surface is opposite the first surface.

14. Paragraph 10,

and forming a thermal adhesive layer between the first package element and the second package element, wherein the thermal adhesive layer is in contact with an integrated circuit die of the first package element and the second package element.

15. The method of clause 10, wherein the first package element comprises one or more core substrate layers having reinforcing structures disposed therein, each of the reinforcing structures being electrically floating.

16. A structure comprising:

a first device package; and

interposer

including,

The first device package,

an integrated circuit die having an active side, the active side facing downward;

a redistribution structure coupled to one or more contacts of the integrated circuit die, and

first contacts disposed on the upper surface of the redistribution structure;

The interposer is

substrate core layer,

one or more metal vias disposed within the substrate core layer;

one or more reinforcing structures disposed within the substrate core layer, wherein the one or more reinforcing structures are electrically decoupled; and

second contacts disposed on a lower surface of the interposer, wherein the first contacts are coupled to respective second contacts of the second contacts.

17. The method of 16, wherein the interposer comprises:

a metallization formed on the substrate core layer, the metallization including bond pads;

a second substrate core layer formed over the metallization; and

and third contacts formed through the second substrate core layer and coupled to the bond pads.

18. The method of clause 17, wherein the interposer further comprises a metal liner layer surrounding a side and a bottom of each of the third contacts, the metal liner interposed between the third contacts and the bond pads. being a struct.

19. The structure of clause 16, wherein, in plan view, the total area of the one or more reinforcing structures is between 5% and 80% of the total area of the substrate core layer.

20. The system of clause 16, wherein each of the second contacts comprises a metal pillar disposed on a top of a metal shoulder, each of the first contacts a respective metal via of the one or more metal vias. and solder material electrically coupled to the solder material, wherein the solder material encapsulates the metal pillars, and wherein a lateral extent of the solder material is within a lateral extent of the metal shoulder.

Claims (10)

In the package forming method,
forming an opening in the first core layer of the interposer;
forming a first reinforcing structure within the opening, the first reinforcing structure extending from a first surface of the first core layer to a second surface of the first core layer, the first reinforcing structure comprising the interposer electrically isolated from the conductive features of -;
forming first connectors on the interposer at the first surface of the first core layer;
bonding the first connectors of the interposer to second connectors of a first packaged device;
forming a molding compound between the interposer and the first package device;
forming a second core layer of the interposer over the second surface of the first core layer; and
forming a second reinforcing structure within the second core layer of the interposer;
at least a portion of the first reinforcing structure is located outside the integrated circuit die of the first packaged device in plan view;
and at least a portion of the second reinforcing structure is not aligned with the first reinforcing structure. According to claim 1,
and forming an adhesive layer between the integrated circuit die and the interposer, the adhesive layer in contact with both the integrated circuit die and the interposer. 3. The method of claim 2,
and forming a cavity in the first core layer of the interposer, wherein after bonding the first connectors to the second connectors, the integrated circuit die is at least partially disposed within the cavity. Formation method. According to claim 1,
forming a second opening in the second core layer of the interposer, the second opening exposing a recess bond pad disposed between the first core layer and the second core layer Phosphorus, a method of forming a package. The method of claim 1 , wherein bonding the first connectors of the interposer to second connectors of a first package device comprises:
aligning the first connectors to the second connectors; and
and reflowing a eutectic material to couple the first connectors to the second connectors. 6. The metal pillar of claim 5, wherein the eutectic material laterally encapsulates a first vertical portion of the second connectors and contacts a second horizontal portion of the second connectors, the first vertical portion being a metal pillar. and a metal pillar, wherein the second horizontal portion includes a step through which the metal pillar protrudes. In the package structure,
a first device package; and
interposer
including,
The first device package,
an integrated circuit die having an active side, the active side facing downward;
a redistribution structure coupled to one or more contacts of the integrated circuit die, and
first contacts disposed on the upper surface of the redistribution structure;
The interposer is
a first substrate core layer;
one or more metal vias disposed within the first substrate core layer;
one or more first reinforcement structures disposed within the first substrate core layer, the one or more first reinforcement structures being electrically decoupled, and at least a portion of the one or more first reinforcement structures located outside the integrated circuit die in plan view Ham -,
a second substrate core layer formed over the first substrate core layer;
one or more second reinforcement structures disposed within the second substrate core layer, wherein at least a portion of the one or more second reinforcement structures are not aligned with the first reinforcement structures;
second contacts disposed on a lower surface of the interposer, wherein the first contacts are coupled to respective second contacts of the second contacts. The method of claim 7, wherein the interposer,
a metallization formed between the first substrate core layer and the second substrate core layer, the metallization including bond pads; and
and third contacts formed through the second substrate core layer and coupled to the bond pads. 9. The method of claim 8, wherein the interposer further comprises a metal liner layer surrounding a side and a bottom of each of the third contacts, the metal liner interposed between the third contacts and the bond pads. package structure. 8. The method of claim 7, wherein each of the second contacts includes a metal pillar disposed on top of a metal shoulder, each of the first contacts electrically connected to a respective metal via of the one or more metal vias. and a solder material coupled to the solder material, wherein the solder material encapsulates the metal pillars, wherein a lateral extent of the solder material is within a lateral extent of the metal shoulder.

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