KR102381193B1 - Method and Apparatus for Improving Memory Reliability Based on Memory Buffer - Google Patents

Abstract

Disclosed are a method and an apparatus for improving memory reliability based on a memory buffer. The present embodiment provides a method and an apparatus for improving memory reliability, in which a memory system includes a plurality of dynamic random access memories (DRAMs) and a memory buffer (e.g., a registered clock driver (RCD)), wherein in order to cope with a row hammer (RH) in which data of adjacent rows is lost by intensively activating a specific row, an activation count is counted for each row constituting the DRAM, a carry, which occurs due to count of lower bits by the memory buffer, is transmitted to a DRAM side, and upper bits are counted based on the carry of the DRAM to detect a row that is intensively accessed. According to the present embodiment, it is possible to reduce energy consumed by the entire memory system and a required silicon area.

Description

Method and Apparatus for Improving Memory Reliability Based on Memory Buffer

The present disclosure relates to a memory buffer-based memory reliability improvement method and apparatus. More specifically, in a memory system including a host, a plurality of DRAMs, and a memory buffer (eg, RCD (Registering Clock Driver)), in order to cope with RH (Row Hammer), the number of activations per row constituting the DRAM is The present invention relates to a method and apparatus for improving memory reliability by counting, but transferring a carry generated by a memory buffer counting a low-order bit to a DRAM side, and the DRAM counting a high-order bit based on the carry.

The content described below merely provides background information related to the present invention and does not constitute the prior art.

The RH (Row Hammer) problem is due to the fundamental limitation of DRAM (Dynamic Random Access Memory) having 1T-1C (One Transistor-One Capacitor) as a basic device (cell). Despite successful process scaling, DRAM has recently encountered the following limitations. First, as the size of a storage capacitor that stores data in DRAM is reduced, the amount of charge stored in a unit cell is reduced to the level of a charge of hundreds of electrons. Second, as the interval between adjacent memory devices decreases, the intensity of interference to unselected cells increases even when adjacent memory cells are selected, and thus the charge of the memory cells is lost and the probability of data errors increases. has increased The RH (Row Hammer) problem caused by this limitation causes a problem in terms of the reliability of DRAM. For example, concerns about the possibility of hackers using RH to cause the entire computer system to fall into Denial of Service (DoS), that is, the possibility of a security problem, have been raised throughout the semiconductor-related industry. Accordingly, efforts to prevent RH problems are continuing in a wide range of areas including DRAM manufacturers and CPU (Central Processing Unit) companies.

The solution to RH can be divided into a SW (Software) method and a HW (Hardware) method. Hereinafter, the prior art and the present invention focus on the HW method. HW methods include stochastic correspondence and deterministic correspondence. The former probabilistically reduces the probability of data errors according to RH, and the latter completely eliminates the possibility of data errors. aim for Hereinafter, a deterministic response based on HW will be described.

When one row is intensively opened (corresponding to open or Activate) (these rows are hereinafter referred to as hot rows), RH may occur in adjacent rows. In the case of a hot row that has been intensively accessed, the charge level may be restored because data is written back to the cell when the row is closed (corresponding to precharge) depending on the operating characteristics of the DRAM. However, in the case of the neighboring row of the hot row, even though the charge is lost little by little due to the interference received from the hot row, there is no way to restore it, so ultimately an error may occur due to data loss. Here, the hot row is called the aggressor row in the sense of attack, and the adjacent row is called the victim row (hereafter, the victim row) in the sense of being attacked. There are two victim rows for one hot (= aggressor) row. However, if the hot row is the first or last row, there can be only one victim row.

DRAM is manufactured using a special advanced process so that the leakage current in the internal node of the storage capacitor that stores the charge is controlled below a certain level. Even so, leakage current is still present, and since it usually has a Gaussian distribution for all of the bulk DRAM cells, the charge is lost quickly in the case of a weak cell and slowly in the case of a strong cell. can In order to prevent such charge loss, DRAM reads and rewrites data from all cells at a cycle of 64 ms, which is called refresh. A very weak cell that does not satisfy the refresh criterion is detected using a test, and is replaced with a healthy cell using a redundant cell additionally present in the DRAM (referred to as repair). Normally, this Refresh command is performed once every 7.8 μs, so 8 K (K is equivalent to 2 ¹⁰ ) refresh commands can be executed during a period of 64 ms. The time consumed to execute the Refresh command once varies depending on the type of DRAM, but is on the order of several hundred ns. The RH problem is a state in which leakage current that cannot be tolerated by such periodic refresh occurs. To solve the problem of leakage current according to RH, after finding the victim row, an additional Refresh command is executed on the found victim row so that the amount of charge lost can be recovered.

Therefore, in the additional refresh, the hot row is detected first, and the Refresh command is performed on the next adjacent victim row (usually two). To detect a hot row, after the Activate command, which is a command to open a row, is counted by row, the counted value for each row is compared with a specific threshold (hereinafter, TRR_Threshold) determined based on the DRAM process. A Refresh command is performed on the victim row adjacent to the hot row that has reached a specific threshold, and this is expressed as a TRR (Targeted Row Refresh) command to distinguish it from periodic refresh.

Meanwhile, RH_Threshold, which is determined based on the process, and TRR_Threshold, which is a criterion for generating TRR by counting the Activate command, may be different. For example, after a hacker understands the DRAM topology, two aggressor rows can cause one victim row to be attacked from both sides (expressed as two-sided RH). A value divided by can be set as the TRR Threshold. Normally, 'TRR_Threshold = RH_Threshold/N (N is a natural number)' is set. If two-sided RH is considered, N=2, but considering other additional influences, N may be a larger value.

In order to cope with RH, as illustrated in FIG. 10 , there is a method in which the MC (Memory Controller) located inside the CPU of the host 1050 performs two functions of hot row counting and victim row refreshing (Patent Document) see 1). First of all, this method has a problem that it is possible to protect against RH only probabilistically because the address of the victim row is incorrect. TRR can be performed using basic information on which topology can access a specific row in DRAM provided by major DRAM manufacturers (eg, TRR provides the address of the victim row and Activate/Precharge may be implemented as a combination of commands). However, since most DRAMs perform the repair as described above, in most cases, the address of an adjacent row is changed differently from the setting according to the basic phase, so the TRR provided by the host 1050 to the memory subsystem 1000 side The command may not correctly specify the adjacent victim row. Since protection against RH is possible only in a probabilistic manner, the command provided by the host 1050 in this method is expressed as pseudo-TRR, that is, pTRR (Pseudo-TRR).

In addition, there is a problem that the area occupied by the MC in the CPU of the host 1050 may become excessive. Since the hot row counting and victim row refresh processes are usually performed for each bank, which is the constituent unit of DRAM, the number of banks that one MC has to handle increases with the high density of DRAM, resulting in an excessive portion of the CPU area. there is. For example, from the MC's point of view, for DDR5 (Double Data Rate 5), there may be banks corresponding to the product of #Channel, #DIMM, #Rank, #Logical Rank, #Bank Group, and #Bank (# is the number of banks). means). In recent trends in the increase in the number of cores included in the CPU, it may become increasingly difficult for the CPU area to accommodate the circuit for RH.

As another way to cope with RH, as illustrated in FIG. 11 , a way in which the two functions of hot row counting and victim row refresh are moved into the DRAM internal side of the memory subsystem 1100 may be considered. In this way, DRAM manufacturers can establish RH countermeasures customized to their RH process characteristics, and compared to the example of FIG. 10 , the number of TRR blocks covered by one DRAM is reduced, and adjacent rows according to row repair It has the advantage that TRR can be performed on the physically adjacent victim row by reflecting the address change of

However, this method has a problem in terms of energy consumption. For example, in the case of a Registered Dual In-line Memory Module (RDIMM) or a Load Reduced DIMM (LRDIMM), one rank is composed of a plurality of DRAMs, and the row addresses used in this case are generally the same. Accordingly, a situation may occur in which a plurality of DRAMs each perform the same operation of hot row counting. One DRAM can broadcast its status to all DRAMs to reduce energy waste due to redundant work, but for this, a bus for communication between DRAMs is required on the module, and the module From a point of view this also leads to a waste of silicon area. In addition, even if notification is possible, synchronization of the refresh cycle must be accompanied, and since the refresh cycle or policies may be different for each DRAM product, synchronization may be difficult.

After all, in the method illustrated in FIG. 11 , since defective rows are different for each DRAM die and repair information is different accordingly, it is advantageous to have a separate victim row refresh function, but the hot row counting function is unnecessary It causes a disadvantage of wasting energy and silicon area to perform redundant operations.

In order to overcome the above-described problems, there is a method for coping with RH as illustrated in FIG. 12 (Patent Document 2 and Patent Document 3). In this method, when a buffer between the memory and the host 150 CPU (eg, RCD (Registering Clock Driver) included in (L)RDIMM) exists in the memory subsystem 1100, hot row counting is performed in the buffer By doing so, it is possible to deal with the problem according to the schemes illustrated in Figs. 10 and 11. However, this scheme has a problem that DRAM commands may collide during operation. When sending a TRR command to a specific bank, if the host 150 wants to access the bank, a conflict may occur between the commands of the RCD and the host 150 .

In addition, this method has a problem that repair information of each DRAM included in the module must be provided to the RCD in order to perform TRR. Repair information may be stored in a memory inside the RCD at the time of module manufacturing. However, for this purpose, a non-volatile memory in which all repair information can be recorded must exist inside the RCD, and the non-volatile memory is scanned every time the Activate command is received to physically adjacent victims. An arithmetic circuit to find a row must also be included, all of which can be a factor in increasing the silicon area.

It is also possible to transmit repair information from each DRAM to the RCD side according to a preset protocol whenever the power is turned on instead of at the time of module manufacturing. No, the host must be used. In addition, when PPR (Post-Package Repair) is performed, the RCD detects (snooping) it and programs the updated repair information in the non-volatile memory inside the RCD, but this may not be possible during normal operation (eg, foundry (Foundry) Some of the non-volatile memory IP (Intellectual Property) provided by manufacturers require high voltage for programming, or programming may not be possible during normal operation other than during the initial module manufacturing process).

In performing the RH coping function in the memory subsystem 1100, as illustrated in FIG. 13 , there is a method in which TRR is performed inside the DRAM and only hot row counting is performed in the RCD (refer to Non-Patent Document 1). In this method, unlike the TRR providing the address of the victim row, the RCD provides the address of the hot row to the DRAM side. In the method using ARR, instead of refreshing the row corresponding to the provided address, each DRAM uses internal repair information to find an adjacent row of the provided row address and then executes the Refresh command. This method has the advantages of reducing energy wastage due to redundant performance of the same operation by a plurality of DRAMs, reducing the size of DRAM, inducing a decrease in price, and indirectly supporting process miniaturization.

However, the method using ARR has the same problem as that caused by pTRR as illustrated in FIG. 10 when hot row counting is first performed in RCD. Since hot row counting is performed in units of banks, there is a hot row counter corresponding to the product of #Channel (# means number), #Rank, #Logical Rank, #Bank Group, and #Bank inside one RCD. Should be. For example, in the case of a module including DRAM corresponding to Case 1 illustrated in Table 1, 2×2×16×8×4 = 2,048 hot row counters are required, which would have taken into account the silicon area of the conventional RCD. when it is impossible to implement.

In addition, this method has a problem in that the area of the RCD can be increased because periodic refresh for each DRAM is not synchronized even though there are as many rows having the same address as the number of DRAMs. Since periodic refresh limits the number of hot row counters to a certain level or less, it is known that a small sized RH prevention circuit can be made (refer to Non-Patent Document 1). However, in each DRAM, the refresh time may deviate up to 64 ms for a row having the same address, which increases the number of rows to be monitored as a target of RH, which in turn increases the area of the RCD. can

Also, this method has a problem in that it depends on RH_Threshold, which is a process characteristic. RH_Threshold differs by DRAM manufacturer and is a secret that cannot be disclosed externally. In the absence of accurate information on RH_Threshold, the RCD manufacturer may need to implement a hot row counting function.

Finally, this method also has a problem that DRAM commands may collide during operation. Even in the method using the ARR, the RCD must issue a command to provide the entire row address to a specific bank of the DRAM. However, when access to the corresponding bank is desired, a conflict may occur between the command of the RCD and the host 150 . In order to avoid such command conflicts, it may be necessary to change not only the rules between RCD manufacturers and DRAM manufacturers, but also the entire standards including CPU manufacturers.

Therefore, there is a need for a countermeasure against RH based on a memory buffer capable of solving such a problem.

Patent Document 1: US Patent No. US 9117544 B2 (Row hammer refresh command, 2015.08.25, registered). Patent Document 2: Korean Application No. KR 10-2018-0111012 (Memory module including register clock driver detecting address frequently accessed, 2018.09.17, filed). Patent Document 3: US Application No. US 2020-0090729 (Memory module including register clock driver detecting address frequently accessed, 2019.03.28, filed).

Non-Patent Document 1: E. Lee, I. Kang, S. Lee, and J. H. Ahn, TWiCe: Preventing Row-hammering by Exploiting Time Window Counters. ISCA, 2019. Non-Patent Document 2: "DDR5 Full Spec Draft Rev0.1". JEDEC committee JC42.3. December 4, 2017. Retrieved July 19, 2020.

According to the present disclosure, in a memory system including a host, a plurality of DRAMs, and a memory buffer (eg, a Registering Clock Driver (RCD)), Row (Row RH) in which data of an adjacent row is lost by intensively activating a specific row Hammer), the number of activations is counted for each row constituting DRAM, but the memory buffer counts the lower bits and delivers the carry to the DRAM side, and the DRAM counts the upper bits based on the carry and concentrates It is a primary object to provide a method and apparatus for improving memory reliability by detecting a row being accessed.

According to an embodiment of the present disclosure, on a memory subsystem including a dynamic random access memory (DRAM) and a memory buffer located between a host and the DRAM, an address provided from the host ( address) for one row on the DRAM specified based on information, counting the number of occurrences of an Activate command to access the one row improves the reliability of the DRAM What is claimed is: 1. A method comprising: counting, by the memory buffer, a lower bit group of the number of occurrences using a lower counter; transferring, by the memory buffer, a carry for the low-order bit group generated by the low-order counter to the DRAM; and performing, by the DRAM, counting on a higher bit group of the number of occurrences using an upper counter based on the carry.

According to another embodiment of the present disclosure, when the value obtained by performing the counting of the upper bit group with respect to the one row is equal to a predetermined first threshold, the DRAM finds a row physically adjacent to the one row Then, there is provided a method characterized by further comprising the step of performing a Refresh command on the adjacent row.

According to another embodiment of the present disclosure, in a memory subsystem including a dynamic random access memory (DRAM) and a memory buffer positioned between a host and the DRAM, the memory buffer includes A lower counter performing counting on a lower bit group, wherein the lower counter is in one row on the DRAM specified based on address information provided from the host , generating a carry by performing counting on the lower bit group among the number of occurrences of the Activate command to access the one row; and an upper counter included in the DRAM and configured to count a higher bit group of the number of occurrences based on the carry transferred from the memory buffer. provides

According to another embodiment of the present disclosure, the DRAM further includes a controller, wherein the controller is configured to: when a value obtained by counting the upper bit group for the one row is equal to a preset first threshold, the one There is provided an apparatus for improving memory reliability, characterized in that after finding a row physically adjacent to a row of , a Refresh command is performed on the adjacent row.

As described above, according to this embodiment, in a memory system including a host, a plurality of DRAMs, and a memory buffer (eg, RCD), the number of activations is counted for each row constituting the DRAM, but the memory buffer receives the lower bit By providing a method and apparatus for improving memory reliability that transfers the counted carry to the DRAM side, and the DRAM counts the upper bit based on the carry and detects the row that is accessed intensively, the DRAM manufacturer related to RH and repair information is kept secret. It has the effect of being able to cope with RH while it is still there.

In addition, according to this embodiment, the number of activations is counted for each row constituting the DRAM, the memory buffer counts the lower bits and transfers the carry generated to the DRAM side, and the DRAM counts the upper bits based on the carry and the row to be accessed intensively By providing a method and apparatus for improving memory reliability for detecting RH, it is possible to reduce the burden on the DRAM side for coping with RH, and to reduce the energy consumed by the entire memory system and the required silicon area.

In addition, according to this embodiment, the number of activations is counted for each row constituting the DRAM, the memory buffer counts the lower bits and transfers the carry generated to the DRAM side, and the DRAM counts the upper bits based on the carry and the row to be accessed intensively By providing a method and apparatus for improving memory reliability for detecting

1 is a schematic block diagram of a memory system according to an embodiment of the present disclosure.
2 is a schematic block diagram of a lower counter according to an embodiment of the present disclosure.
3 is an exemplary diagram conceptually illustrating a CAM hit during an operation of a lower counter according to an embodiment of the present disclosure.
4 is an exemplary diagram conceptually illustrating a CAM miss during operation of a lower counter according to an embodiment of the present disclosure.
5 is an exemplary diagram conceptually illustrating a periodic monitoring process during operation of a lower counter according to an embodiment of the present disclosure.
6 is a flowchart of a method for improving memory reliability according to an embodiment of the present disclosure.
7 is a simplified timing diagram for a DDR5 DRAM.
8 is a schematic block diagram of a memory system according to another embodiment of the present disclosure.
9 is a schematic block diagram of a memory system according to another embodiment of the present disclosure.
10 is a schematic block diagram of a method of performing an RH coping function in a CPU.
11 is a schematic block diagram of a method for performing a RH coping function in DRAM.
12 is a schematic block diagram of a method of performing an RH coping function in a memory buffer.
13 is a schematic block diagram of a method of performing a part of an RH coping function in a memory buffer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to the components of each drawing, it should be noted that the same components are given the same reference numerals as much as possible even though they are indicated on different drawings. In addition, in the description of the present embodiments, if it is determined that a detailed description of a related well-known configuration or function may obscure the gist of the present embodiments, the detailed description thereof will be omitted.

Also, in describing the components of the present embodiments, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, or order of the elements are not limited by the terms. Throughout the specification, when a part 'includes' or 'includes' a certain element, this means that other elements may be further included, rather than excluding other elements, unless otherwise stated. . In addition, the '... Terms such as 'unit' and 'module' mean a unit that processes at least one function or operation, which may be implemented as hardware or software or a combination of hardware and software.

DETAILED DESCRIPTION The detailed description set forth below in conjunction with the appended drawings is intended to describe exemplary embodiments of the present invention and is not intended to represent the only embodiments in which the present invention may be practiced.

The present embodiment discloses a method and apparatus for improving memory reliability based on a memory buffer. More specifically, in a memory system including a host, a plurality of DRAMs, and a memory buffer (eg, a Registering Clock Driver (RCD)), the data of an adjacent row is lost by intensively activating a specific row. To cope with RH (Row Hammer), the number of activations is counted for each row constituting DRAM (Dynamic Random Access Memory), but the memory buffer counts the lower bits and transfers the carry to the DRAM side. A method and apparatus for improving memory reliability by counting high-order bits based on .

Hereinafter, terms and assumptions related to the size of DRAM will be described from the standpoint of RCD based on DDR5.

RA (Row Address) represents a row address of a bank, which is a unit of an aggregate of memory cells included in DRAM.

CA (Column Address) represents the column address of the bank.

BA (Bank Address) indicates the address of the bank included in the BG (Bank Group).

BG includes a plurality of banks.

A DRAM die includes a plurality of BGs.

The logical rank includes a plurality of DRAM dies, and is represented by a Chip Identifier (CID) or a Die ID (DID). CID is an identifier for each chip in a package in which DRAM chips are stacked in a 3DS (3 dimensional stack) form using TSV (Through Silicon Via). DID is an identifier for each die when two dies are packaged together without using TSV, and packaging of up to two dies is possible.

A DRAM package typically includes up to a logical rank.

A rank is a unit for generating an 8-byte (or 9-byte) output including a plurality of DRAM chips.

From the RCD's point of view, a channel usually includes two ranks.

A dual in-line memory module (DIMM) typically includes two channels. Since most DRAM operations (ie, RCD control) are performed independently between channels, in the case of DDR5, two identical control structures exist within the RCD.

Hereinafter, commands related to the operation of the DRAM will be briefly described.

The Activate command is a command to open the row by transferring RA for one bank to the DRAM side.

The precharge command is a command for charging all rows in one bank with a preset value. Since the precharge command is executed before the Read command for a new row, it also closes the previous row.

The Refresh command is a command to read and rewrite data of all cells in DRAM at regular intervals to prevent charge loss.

The Read command is a command to read the data of the cell by transferring the CA for an open row in one bank.

The Write command is a command to write data to the corresponding cell by sending CA for an open row in one bank.

Hereinafter, a memory system in which a method for improving memory reliability by coping with RH is implemented will be described using the illustrations of FIGS. 1 and 2 .

1 is a schematic block diagram of a memory system according to an embodiment of the present disclosure.

A method of improving memory reliability in accordance with the present disclosure is performed on the memory system illustrated in FIG. 1 . The memory system includes a host 150 and a memory subsystem 100, wherein the memory subsystem 100 includes a memory buffer 110 (eg, RCD, hereinafter buffer) and a plurality of memories 120 (hereinafter DRAM). . The host 150 may activate the corresponding row in the DRAM 120 by transmitting an Activate command including the address to be accessed based on the buffer 110 . In counting the number of activations for each row of DRAM, the buffer 110 transfers the carry generated by counting the lower bits to the DRAM 120 side, and the DRAM 120 counts the upper bits based on the carry and concentrates The row being accessed can be detected.

In order to count the number of activations per row, the buffer 110 includes a hot row lower counter 112 (lower counter), and the DRAM 120 includes a hot row upper counter 122 (lower counter hereinafter). The DRAM 120 further includes a TRR controller 124, which, when the value of the upper counter 122 corresponding to a specific row reaches TRR_Threshold, adds additional information to the adjacent row(s) of the corresponding row. Execute the Refresh command.

In counting the number of activations, the lower counter 112 on the buffer 100 according to the present disclosure does not count up to TRR_Threshold (or ARR_Threshold, RH_Threshold), but counts up to a preset value (eg, 1,000, lower_Threshold), and the value When , the highest carry of the lower counter 112 occurs, it is transferred to the DRAM 120 side. The upper counter 122 on the DRAM 120 may count whether the TRR_Thrshold is reached only for a row included in a candidate group that is likely to become a hot row. As described above, in the present disclosure illustrated in FIG. 1 , unlike the prior art illustrated in FIGS. 10 to 13 , not all of the hot row counter but only a part of the hot row counter is implemented on the buffer 110 side.

On the other hand, the maximum number of hot rows is limited because of the refresh that is performed periodically every 64 ms, and thus the candidate group that can become a hot row may be limited. Accordingly, compared to the case where the entire counting is performed inside the DRAM 120 , power consumption can be reduced as the frequency at which the upper counter 122 operates decreases.

It is sufficient for the upper counter 122 to include an RH memory capable of counting the difference between the TRR_Threshold and the Lower_Threshold (eg, 1,000) that the carry provided by the buffer 110 means. For example, if the carry of the buffer 110 represents 1,000 (~ 2 ¹⁰ ), and the TRR_Threshold is 100 K (~ 2 ¹⁷ ), the upper counter 122 sets the upper bit group from 0000001 to 1111111 (~ 2 ⁷ ). should be counted. If TRR_Threshold is decreased, the number of hot row candidates may increase, so the capacity of the RH memory in the upper counter 122 is changed. If the process characteristic RH_Threshold is about 139 K, it is known that the maximum number of hot rows is about 20 (see Non-Patent Document 1), so even if RH_Threshold is reduced by half, the number of hot rows becomes 40.

If the above is described in terms of the circuit, per one bank, the upper counter 122 is a CAM (Content Addressable Memory) having a size of 40 for storing an input of 18 bits corresponding to the width of the RA, and these You only need to include 40 high-order bit group counters (corresponding to 320 bits of memory) in units of 8 bits for each. In addition, the TRR operation may be performed in units of more than one bank by combining several banks.

As described above, according to the present embodiment, the buffer transfers the carry generated by counting the lower bits to the DRAM side, and the DRAM counts the upper bits based on the carry to detect the intensively accessed row. By providing RH and repair information, there is an effect that it is possible to cope with RH while maintaining the secrets of DRAM manufacturers related to RH and repair information.

2 is a schematic block diagram of a lower counter according to an embodiment of the present disclosure.

The lower counter 112 according to the present disclosure includes a RH CAM 202 and a RH memory 204 . The RH CAM 202 is a memory for managing and storing the address included in the Activate command transmitted from the host 150 . The RH memory 204 stores a timer (Timer j, j is a natural number) that stores an input time point for each row constituting the RH CAM 202 and a low-order bit group counter (Frequency j) that stores the number of Activate commands. include

After acquiring the Activate command, the lower counter 112 searches the RH CAM 202 to check whether there is a line matching the address included in the Activate command, and then hits the CAM (hit: there is a line with the same address) Performs an action according to /miss (there is no line matching the address). In addition, the lower counter 112 periodically updates the contents of the RH memory 204 regardless of the Activate command.

Hereinafter, an operation of the lower counter 112 will be described using the examples of FIGS. 3 to 5 . The lower counter 112 may include a threshold controller 206 , a periodic monitor 208 and a monitor timer 210 to perform CAM hit/miss and periodic monitoring.

3 is an exemplary diagram conceptually illustrating a CAM hit during an operation of a lower counter according to an embodiment of the present disclosure.

In the case of a CAM hit, the output of the RH CAM 202 corresponds to an address that selects a row in the RH memory 204 . Threshold controller 206 of lower counter 112 when j-th row is selected. After reading the lower bit group counter Frequency j from the corresponding row in the RH memory 204 and incrementing it by 1, Lower_Threshold and Compare. If Frequency j + 1 < Lower_Threshold, the value of Frequency j + 1 is stored in Frequency j. On the other hand, if Frequency j + 1 = Lower_Threshold, the threshold controller 206 transmits a carry using a command decoder (CMDDEC), thereby causing the DRAM 120 to determine the corresponding upper bit group counter value included in the upper counter 122. By increasing by one, and resetting Master j of the RH CAM 202 to 0, Address j is deallocated.

4 is an exemplary diagram conceptually illustrating a CAM miss during operation of a lower counter according to an embodiment of the present disclosure.

In the case of CAM miss, the lower counter 112 stores the input address as a new candidate in one row (eg, Address k) of the empty RH CAM 202 , sets Master k to 1, and RH Both the values of Timer k and Frequency k of the k-th row of the memory 204 are initialized to 1.

5 is an exemplary diagram conceptually illustrating a periodic monitoring process during operation of a lower counter according to an embodiment of the present disclosure.

Irrespective of the Activate command, the period monitor 208 of the lower counter 112 periodically updates the timer values, and determines whether the address is still achievable in the RH CAM 202 / RH memory 204 . For example, if the total period is T, the period monitor 208 sequentially reads the timer/counter value for one address according to the T/(#Row) time interval generated by the monitor timer 210 and performs the necessary operation. carry out If the output of the RH CAM 202 is m (m is a natural number) bits, the #Row of the RH CAM 202 is 2 ^m . The RH memory 204 also includes the same number of Timer 0 to Timer (2 ^m -1) and Frequency 0 to Frequency (2 ^m -1) as #Row. Here, T may be set to 7.8 μ, which is the refresh cycle of the DRAM (see Non-Patent Document 1). Also, m is a design parameter that can be determined according to a trade-off between the operating performance of the lower counter and the silicon area.

Period monitor 208 monitors Timer 0, Frequency 0 at time t0 and monitors Timer 1, Frequency 1 at time t1 = t0 + T/(#Row). Period monitor 208 finally monitors Timer (#Row -1), Frequency (#Row - 1) at time t(#Row -1) = t0 + T/(#Row)×(#Row - 1) and according to the deallocation rule for each timer and low bit group counter Decide on retention or release. Here, as an example of the release rule, when the Timer k value and the Frequency k value are read, if the Frequency k value is less than the deallocation threshold, 'Timer k×(TRR_Threshold×T/64)', the corresponding row is discarded, and vice versa. If it is equal to or greater than the release threshold, a method of maintaining the corresponding row in the RH_CAM 202/RH memory 204 may be used. Period monitor 208 resets Master k to 0 when discarding, and increments Timer k value by 1 when holding.

The introduction of the lower counter 112 according to the present disclosure makes it possible to deal with a problem that may occur because the 64 ms refresh period is shifted between DRAMs. As illustrated in FIG. 13 , when counting up to ARR_Threshold, the memory buffer does not know when the refresh of the corresponding row is performed from -64 ms to +64 ms based on the monitoring time point. From the point of view of the freeing rule, it may be safer to continuously monitor as many rows as possible by setting the release threshold to be low compared to the value of the hot row counter, which may increase the area of the memory buffer.

In contrast, in the present disclosure, when the number of Lower_Threshold is reached, the lower counter 112 transfers the carry to the DRAM 120 side. From the point of view of the release rule, even if the carry generation condition for the row is more stringently set by setting the release threshold compared to the Frequency k value higher than that of the conventional method, the DRAM 120 stores the refresh cycle, so the hot row may not be a major problem in detecting Accordingly, by reducing the number of candidate rows monitored by the buffer 110 by setting the release threshold high, the size of the buffer 110 and energy consumed in the buffer 110 may be reduced.

On the other hand, during the time the buffer (see Non-Patent Document 1) as illustrated in FIG. 13 sends one ARR command after detecting the hot row, in the present disclosure, ARR_Threshold/Lower_Threshold (eg, 2 ¹⁷ /2 ¹⁰ = 2 ⁷ = 128), the lower counter 112 transmits the carry to the upper counter 122 as many times. In the case of the conventional method, when an ARR command is received, the DRAM 120 must immediately find the victim row and perform additional TRR refresh, so the status of refresh periodically performed inside each of a plurality of DRAMs constituting the same rank is individually monitored. difficult to reflect On the other hand, in the present disclosure, each DRAM 120 asynchronously refreshes at different times based on the upper counter 122 and each refresh cycle (by bank or bank group) included in each DRAM 120 . By doing so, it is possible to fundamentally avoid the problem that the refresh cycle is not synchronized between DRAMs.

6 is a flowchart of a method for improving memory reliability according to an embodiment of the present disclosure.

The lower counter 112 included in the buffer 110 acquires the Activate command and then searches for the RH CAM (S600). The lower counter 112 searches the RH CAM and checks whether there is a line matching the address included in the Activate command.

The lower counter 112 checks whether it is a CAM hit/miss (S602). If it is a CAM hit (a row with a matching address exists), the lower bit group counter for the corresponding row is incremented by 1 (S604).

On the other hand, when the lower counter 112 is a CAM miss (there is no row with the same address), the lower counter 112 adds the row as a new candidate to the RH CAM 202 (S606), and ends the process.

The lower counter 112 compares the value of the lower bit group counter with the Lower_Threshold (S608), and when the value of the lower bit group counter is smaller than the Lower_Threshold (eg, 1,000), the process ends.

When the value of the lower bit group counter reaches the Lower_Threshold, the lower counter 112 transfers a carry to the upper counter 122 included in the DRAM 120, and resets the lower bit group counter (S610).

When a carry is obtained, the upper counter 122 increments the corresponding upper bit group counter by one (S612).

The high-order counter 122 compares the value of the high-order bit group counter with the TRR_Threshold (S614), and when the value of the high-order bit group counter is smaller than the TRR_Threshold, the process ends.

When the value of the upper bit group counter reaches TRR_Threshold, the DRAM 120 performs a Refresh command on a row adjacent to the corresponding row.

Hereinafter, in the structure in which the lower counter 112 detects a hot row based on the RH CAM 202 and the RH Memory 204 , the silicon area required by the buffer 110 including the lower counter 112 is determined. Describe ways to minimize it. According to a common practice, when one sub-counter 112 for each bank counts the hot row, 2,048 sub-counters must be implemented on the buffer 110 . In the case of DDR5 DRAM, #Channel is 2, #Rank per channel is 2, and the maximum value of #Bank for each rank can be calculated as shown in Table 1.

In Table 1, each case represents a package in which a different number of chips or dies are packaged. For example, 4H-3DS indicates that 4 chips are packaged in 3DS format.

Implementing the lower counter 112 according to the number of banks as shown in Table 1 may cause a fundamental area overhead limit in integrating the buffer 110 .

In the present disclosure, it is proposed to implement the lower counter 112 by combining up to a bank, a bank group, or a logical rank. When a bank, a group of banks, a logical rank, or a combination of logical ranks share one sub-counter 112, the time margin in which the sub-counter 112 must operate, that is, the allowed response time (in other words, is #ACT Max bandwidth) is as shown in Table 2.

Here, the timing diagram showing the relationship between the timing parameters presented in Table 2 is as exemplified in FIG. 7 . In the examples of Table 2 and Figure 7, tRC is the interval between Activate and Activate in the same bank, and tRRD is the interval between Activate and Activate in different banks. In addition, tRCD is the interval between Activate and Read/Write, and tFAW is the time corresponding to 4 Activate windows.

In the case of placing the lower counter 112 for each bank, the search for the RH CAM 202 and the control of the RH memory 204 need only be performed once during tRC = 45 ns, so the lower counter 112 operates slowly accordingly. can do. For reference, 45 ns corresponds to 72 CK (clock) based on DDR4-3200 or 144 CK based on DDR5-6400.

On the other hand, if the lower counter 112 is implemented by combining banks, bank groups, or logical ranks, the response time can be determined according to tFAW or tRRD, so the response time is 45 ns to 1.25 ns (2 CK based on DDR4-3200) , it can be reduced to 4 CK based on DDR5-6400). If a medium combination is selected and the lower counter 112 is set aside for each bank group, the response time is 5 ns, which corresponds to 8 CK and 16 CK for DDR4-3200 and DDR5-6400, respectively.

Depending on the combination as shown in Table 2, it can be determined how fast the RH CAM 202 is required, and the high-speed requirement of the RH CAM 202 is implemented in a memory buffer with relatively good transistor performance compared to DRAM. It may exist within a possible range. Since the description of the specific design method of the RH CAM is out of the scope of the present disclosure, further detailed description thereof will be omitted.

Hereinafter, the effect of bonding as shown in Table 2 on the silicon area will be described. When the lower counter 112 is provided for each bank (case 1 in Table 1), 2K counters are required in all, so when the area of one lower counter 112 is A, the total area is (2,048×A).

When combined by the following logical ranks, the number of lower counters 112 is required as many as #Channel×#Rank×#Logical Rank, but the size of the lower counter 112 increases, so the total area is called A' instead of A' becomes (2x2x16xA'). At this time, the difference between A' and A may be determined according to the ratio of the maximum number of Activate commands coming in per unit time. 7.8 μs As a standard, in the case of each bank, as shown in Table 2, 165 Activate commands can come in, but in the case of a logical rank, 18 times more can come in, so A' = 18×A. Therefore, the total area required is (64×18×A) = (1152×A).

In the case of combining up to logical ranks, if the example in Table 2 is equally applied, the size of the lower counter 112 is A'' = 36×A, and the number of the lower counters 112 is #Channel×#Rank = 2×2= Since there are 4, the total area required is (4×A'') = (144 x A). Accordingly, in contrast to the case where the lower counter 112 is provided for each bank, the total area of the lower counter 112 may be reduced to approximately 1/14 when combining up to a logical rank.

As described above, according to this embodiment, the number of activations is counted for each row constituting the DRAM, but the memory buffer counts the lower bits and transfers the carry generated to the DRAM side, and the DRAM counts the upper bits based on the carry. By providing a method and apparatus for improving memory reliability for detecting rows that are intensively accessed, it is possible to reduce the burden on the DRAM side for coping with RH, and to reduce energy consumed by the entire memory system and silicon area required there is

Hereinafter, a method of transferring carry information between the lower counter 112 and the upper counter 122 will be described.

In the present disclosure, without considering changes in the Joint Electron Device Engineering Council (JEDEC) standard according to the addition of additional new commands such as TRR or ARR, from the lower counter 112 on the buffer 110 to the DRAM 120 internal Carry information may be transferred to the upper counter 122 of the . Unlike the case of TRR or ARR, the carry information transmitted by the lower counter 112 to the lower counter 112 may be independent of the timing at which the TRR is actually performed in the DRAM. Therefore, when an Activate command is received from the host 150 , the buffer 110 only needs to inform the DRAM 120 that the corresponding Activate command has been executed for a candidate of a hot row. When transmitting a command to the DRAM 120 , the buffer 110 may use one of the command and address (CA) pins as a flag bit for informing of this fact.

In fact, information such as Auto Precharge (AP) and Burst Length (BL) is transmitted from the host to the DRAM side using the On the Fly (OTF) method. However, after obtaining the Activate command from the host 150, the buffer 110 buffers and transmits the command to the DRAM 120 side only about 1 ns, so the RH CAM 202 A necessary process such as retrieval of , reading of the RH memory 204 cannot be completed. In addition, as shown in the DDR5 command table (including only a part of the entire command, see Non-Patent Document 2 for the entire command table) presented in Table 3, since all CA pins are in use, the buffer 110 transmits the Activate command. When carrying information can not be loaded.

Nevertheless, since the row is open for at least tRC (= 45 ns), the DRAM 120 maintains the address. Accordingly, it is sufficient if the carry information is transmitted within the tRC period. In addition, if the DRAM 120 stores the corresponding address information until the next Activate command comes, carry information may be transmitted when the next Activate command comes. Based on this basis, two methods in which the lower counter 112 transmits carry information to the upper counter 122 side will be described.

The lower counter 112 according to the present disclosure may transmit carry information after the Activate command, for example, a Read or Write command. Since the Read or Write command input after the Activate command is given at least after tRCD (= 12 ns), during this time, the lower counter 112 refers to the RH CAM (202) and RH Memory (204) and refers to the upper counter ( 122) can decide whether to send carry information to the side. Table 4 shows the changed DDR5 instruction table in consideration of these flag bits.

In the example in Table 4, the Read and Write commands include the RH flag bit. As in the example of Case 1, CA9 of the second cycle may be used as the RH flag bit in the Read or Write command, which is a 2-cycle command. In addition, since the CA12 pin can also be used for this purpose, more information may be transmitted using a combination of the CA9 and CA12 pins as needed, as in the example of case 2. If no pins are available, by changing the standard (for new products, by adding pins that take this information into account). It is possible to employ the OTF control scheme as described above.

Meanwhile, in rare cases, the host 150 may transmit the Precharge command without transmitting the Read or Write command after transmitting the Activate command. In the case of the precharge command for each bank, as shown in Table 3, all CA pins are used and there is no remaining pin, so it cannot be used for carrying carry information. Also, for a Precharge All Bank (precharge all groups of banks) or Precharge Same Bank commands (perform a precharge on one bank per bank group), multiple rows opened by multiple Activate commands rather than one Activate command. , it cannot be determined which bank it represents, and therefore cannot be used for carrying carry information. Of course, if TRR is applied to all banks or the same bank, the problem can be solved, but according to the internal policy of each DRAM product or DRAM manufacturer, the refresh granularity, that is, the number of rows refreshed by one Refresh command Since it is decided, we cannot guarantee that the problem will be solved.

In the present disclosure, it is possible to respond to the case where the Precharge command is transmitted after the Activate command in the following way. When an Activate command that can cause carry is received (eg, the 1,000th command), when the next Activate command of the same bank is received, the buffer 110 sets the CA1 pin to 1 (High) to deliver carry information. can In this case, RA does not necessarily have to be the address of the hot row. For reference, this change of the Activate command may be possible because there is no case in which the CA0 and CA1 pins are 0 (Low) at the same time other than the Activate command on the DDR5 command table (refer to Non-Patent Document 2).

In order to transmit carry information, the two methods as described above may be used in parallel, or only the latter method may be used. In the case of TRR or ARR, unlike the standard that has to be changed to resolve the possibility of command conflicts with the host, if the OTF bit method, which has been used for a long time in DRAM, is used, carry information transfer is a customer-specific characteristic between the DRAM manufacturer and the buffer manufacturer. (customized feature) can be implemented. The TRR or ARR delivers the address of the hot row or the victim row, but in the present disclosure, since it is sufficient to transfer the 1-bit carry generated by the lower counter 112 to the upper counter 122 side, the OTF method may be used.

As described above, according to this embodiment, the number of activations is counted for each row constituting the DRAM, but the memory buffer counts the lower bits and transfers the carry generated to the DRAM side, and the DRAM counts the upper bits based on the carry. By providing a method and apparatus for improving memory reliability for detecting rows that are accessed intensively, there is an effect that it becomes possible to solve a problem of conflict with a host command system in an existing method of coping with RH.

The above has shown an embodiment that can be implemented according to the present disclosure, and this embodiment can be applied to various cases depending on the situation.

8 is a schematic block diagram of a memory system according to another embodiment of the present disclosure.

8 shows an example of a memory system similar to (L)RDIMM. When the MMU (Memory Control Unit) sends a physical address to the MC (Memory Controller) at the request of the CPU core in the host 150 , the MC interprets the address in an address format (hereinafter referred to as the memory address) that can be interpreted by DRAM. (memory address): Consists of CSB (Chip Select Bar), CID, BG, BA, RA, CA, etc.). The host 150 transfers the DRAM address converted to the memory address format to the memory subsystem 100 , and using this, hot row counting may be attempted in the memory subsystem 100 to prevent RH.

9 is a schematic block diagram of a memory system according to another embodiment of the present disclosure.

The illustration of FIG. 9 relative to the illustration of FIG. 8 shows a more generalized memory system. For example, in the case of a more general memory system such as a hybrid memory cube (HMC), some functions of a memory controller (MC) generally present in the CPU may be transferred to the memory buffer side and implemented. Even when a kind of MC indicated by MC2 in the diagram of FIG. 9 exists in the memory buffer, the embodiment according to the present disclosure may also be applied. In the example of FIG. 8, the physical address is used after being converted to a memory address format, but in the example of FIG. 9 without this conversion (the host 150 can provide either a physical address or a memory address) memory subsystem 100 Hot row counting can be performed in

In another embodiment of the present disclosure, even when the integration of 2.5D using an interposer, etc. or 3D type using TSV, etc. is applied in manufacturing a chip, the configuration of the memory buffer as described above and Functions can be widely applied.

Although it is described that each process is sequentially executed in each flowchart according to the present embodiment, the present invention is not limited thereto. In other words, since it may be applicable to change and execute the processes described in the flowchart or to execute one or more processes in parallel, the flowchart is not limited to a time-series order.

The above description is merely illustrative of the technical idea of this embodiment, and a person skilled in the art to which this embodiment belongs may make various modifications and variations without departing from the essential characteristics of the present embodiment. Accordingly, the present embodiments are intended to explain rather than limit the technical spirit of the present embodiment, and the scope of the technical spirit of the present embodiment is not limited by these embodiments. The protection scope of this embodiment should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be interpreted as being included in the scope of the present embodiment.

100, 1000, 1100, 1200, 1300: memory subsystem
150, 1050: host
110: memory buffer 112: hot row low counter
120: memory (DRAM)
122: Hot row upper counter 124: TRR controller
202: RH CAM 204: RH memory

Claims (13)

On a memory subsystem including a dynamic random access memory (DRAM), and a memory buffer located between a host and the DRAM, a specified based on address information provided from the host In the method of improving the reliability of the DRAM by counting the number of occurrences of an Activate command to access the one row for one row on the DRAM,
performing, by the memory buffer, counting on a lower bit group of the number of occurrences using a lower counter;
transferring, by the memory buffer, a carry for the low-order bit group generated by the low-order counter to the DRAM; and
A process in which the DRAM counts the higher bit group of the number of occurrences using a higher counter based on the carry
A method comprising a. The method of claim 1,
When the value obtained by performing the counting of the upper bit group with respect to the one row is equal to a predetermined first threshold, the DRAM finds a row physically adjacent to the one row, and then provides a Refresh command for the adjacent row Method characterized in that it further comprises the process of performing. According to claim 1,
The memory buffer is
When the counted value of the lower bit group is equal to a preset second threshold, the carry is generated. The method of claim 1,
The method of performing the counting of the lower bit group is performed in units of a bank constituting the DRAM, or a unit of a bank or more including the bank. The method of claim 1,
The delivery process is
At least one of a command and address (CA) pin used for transmission of a Read or Write command following the Activate command is used as a flag bit for transmitting the carry. According to claim 1,
The delivery process is
When the DRAM maintains the address according to the Activate command until the next Activate command is obtained, at least one of the CA pins used for transmission of the next Activate command is used as a flag bit for transmitting the carry How to. The method of claim 1,
The address information is
The method according to claim 1, wherein the format is a physical address or a memory address converted by the host to fit the DRAM structure. 8. The method of claim 7,
When the physical address is obtained from the host, the memory buffer performs counting on the low-order bit group using the low-order counter based on the physical address, and converts the physical address into the memory address how to do it with 8. The method of claim 7,
When the memory address is obtained from the host, the memory buffer counts the lower bit group using the lower counter based on the memory address. A memory subsystem comprising a dynamic random access memory (DRAM) and a memory buffer located between a host and the DRAM, the memory subsystem comprising:
A lower counter included in the memory buffer to perform counting on a group of lower bits, wherein the lower counter is one of the lower bits on the DRAM specified based on address information provided from the host. generating a carry by performing counting on the lower bit group among the number of occurrences of the Activate command to access the one row for a row; and
An upper counter included in the DRAM and performing counting on a higher bit group of the number of occurrences based on a carry transferred from the memory buffer
It comprises a memory reliability (reliability) improvement apparatus, characterized in that. 11. The method of claim 10,
The DRAM further comprises a controller,
The controller searches for a row physically adjacent to the one row and provides a Refresh command for the adjacent row when a value obtained by counting the upper bit group with respect to the one row is equal to a preset first threshold Memory reliability improvement device, characterized in that performing. 11. The method of claim 10,
The lower counter is
and generating the carry when the counted value of the lower bit group is equal to a preset second threshold. 11. The method of claim 10,
The lower counter is
The apparatus for improving memory reliability, characterized in that the counting of the lower bit group is performed in units of a bank constituting the DRAM, or in units of a bank or more including the bank.

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