KR102347412B1 - Display Panel For Display Device and Test Method therefor - Google Patents

Abstract

The present invention relates to a display panel for a display device and an inspection method therefor, and more particularly, includes an auto probe inspection region for performing an array test, wherein the inspection region includes a test enable switching element for each color And, by having a single test data input line commonly connected to all test enable switching elements, the width of the auto probe inspection area is reduced, and a display panel having an auto probe inspection area that does not require a separate contact hole or jumping hole is to provide

Description

Display Panel For Display Device and Test Method therefor

The present invention relates to a display panel for a display device and an inspection method therefor, and more particularly, to a display panel including an auto probe inspection area for performing an array test, and an inspection method using the same.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. Various display devices such as an organic light emitting diode display device (OLED) are being used.

Among these display devices, a liquid crystal display (LCD) includes an array substrate including thin film transistors, an upper substrate including a color filter and/or a black matrix, and a liquid crystal material layer formed therebetween, and a pixel The arrangement state of the liquid crystal layer is adjusted according to the electric field applied between both electrodes of the region, and the transmittance of light is adjusted accordingly to display an image.

In addition, an OLED display device includes a first substrate including thin film transistors such as switching transistors and driving transistors, first and second electrodes, an organic light emitting material layer disposed therebetween, and a second substrate bonded thereto. is a device for displaying an image by controlling the degree of light emission of an organic material according to the magnitude of a voltage or current applied between both electrodes of a pixel region.

On the other hand, after the manufacturing process of the display panel or the array substrate for the display panel is completed, an inspection process of inspecting whether there are defects such as electrical characteristics of the display panel is performed. In this inspection process, a signal is simultaneously applied to all data pads to electrically It may include a so-called Array Test process to check whether there is no disconnection or short circuit.

This inspection process is performed by applying a test signal to the auto probe inspection area formed on the display panel using an auto probe device, and then checking whether the test signal is transmitted to the gate line or data line inside the display panel. can be

To this end, the non-display area of the display panel, more specifically, between the D-IC input bumper pad area and the D-IC output bumper pad area, which is the area where the data IC (D-IC), which is the data driving circuit, is mounted, is inspected as described above. An auto probe inspection area for the process is formed.

The auto probe inspection area is largely divided into three test data input lines for applying a test data signal to each data line of each sub-pixel for each R, G, and B color, and test data input for each color is delivered to the corresponding data line. It includes three enable circuit sections as a switching circuit for

The three enable circuits (R Enable, G Enable, and B Enable) are to be implemented with an R enable transistor, a G enable transistor, and a B enable transistor, which are thin film transistors (Tr) having a gate electrode, a source and a drain electrode. A test enable signal for testing a pixel of a corresponding color is input to the gate electrode of the enable transistor for each color, the source electrode is electrically connected to the test data input line of the corresponding color, and the drain electrode is the corresponding color. It is electrically connected to the data line.

As such, this auto probe inspection area requires one enable circuit section and one test data input line section for each R, G, and B color, and therefore requires a total of 6 sections, so that the auto probe test area becomes larger. There were downsides.

In addition, in the section of the test data input line for each color, the test data input line for each color and the source electrode of the corresponding enable transistor must be electrically connected, so the source connection wiring between the test data input line and the source electrode of the enable transistor has to be formed in a different layer, so a separate contact hole or jumping hole had to be formed to connect the test data input line and the corresponding source connection wiring.

Therefore, since the size (width) of the auto probe inspection area increases, it becomes an obstacle to achieving a narrow bezel, and since it is necessary to form a separate contact hole, electrical characteristics (resistance, etc.) are reduced or the possibility of occurrence of defects increases, etc. there was a problem with

Against this background, it is an object of the present invention to provide a display panel capable of reducing the size of an auto probe inspection area formed in a non-display area of a display panel for auto probe inspection and simplifying the structure thereof.

Another object of the present invention is to provide a display panel in which the auto probe inspection area of the display panel includes only one test data input line, thereby reducing the width of the auto probe inspection area and minimizing the bezel under the display panel.

Another object of the present invention is to form one test data input line on the same layer as the source connection wiring extending to the source electrode of the auto probe enable transistor for each color, so that a separate contact hole or jumping hole is not required for auto probe inspection. To provide a display panel having an area.

Another object of the present invention is to provide a single test input line in a method for inspecting a display panel having an auto probe enable transistor for each color and one single test data input line to prevent color mixing in the testing process for each color. An object of the present invention is to provide a test method to include a ground signal section of a predetermined time section between test data for each color input through the .

In order to achieve the above object, according to an embodiment of the present invention, the display area A/A including a plurality of pixels defined in the intersection area of the gate line and the data line is disposed in the non-display area NA A display panel comprising an inspection region for inspecting electrical characteristics of pixels or data lines, wherein the inspection region includes at least one test enable switching element for each of two or more colors, and one of the test enable switching elements. Provided is a display panel including a single test data line commonly connected to an electrode to input test data.

In another embodiment of the present invention, the R enable transistor, the G enable transistor, and the B enable transistor disposed in the non-display area of the display panel are commonly connected to certain terminals of the enable transistors to apply test data. A display panel inspection method using a single test data line, comprising: a first step of applying a first test enable ON signal to a corresponding enable transistor during an inspection period (T) for a first color; An ON signal of the first test data for the first color is applied to the single test data line during a first period T1 of Provided is a display panel inspection method comprising: a second step of applying an OFF signal of data to the single test data line; and a third step of repeatedly performing the first and second steps for a second color.

As described above, according to the present invention, since the auto probe inspection region of the display panel includes only one test data input line, the width of the auto probe inspection region can be reduced, thereby reducing the bezel under the display panel.

In addition, by forming one single test data line in the same layer as the source electrode of the enable transistor for each color of RGB and the source connection wiring thereto, there is no need for a separate contact hole or jumping hole, thereby simplifying the structure, and It has the effect of improving a characteristic and reducing the possibility of a defect.

In addition, in the test process through a single test data input line, by including the ground signal section of a certain time period between the test data for each color to completely discharge the charged charges of the color that has been tested, the color mixing phenomenon in the test process for each color can prevent

1 is a diagram schematically illustrating a plan view of an array substrate or a display panel for a conventional display device.
2 shows the structure and equivalent circuit of a typical auto probe inspection area.
3 is an enlarged view of the auto probe inspection area shown in FIG. 2 , in which an upper view is a plan view and a lower view is a cross-sectional view.
4 is a plan view of an auto probe inspection area of a display panel according to an exemplary embodiment of the present invention.
5 is a cross-sectional view of an auto probe inspection area according to the embodiment of FIG. 4 .
FIG. 6 is a timing diagram of a test signal according to the embodiment of FIG. 2 and shows both a timing diagram of a test enable signal and test data for each color.
7 illustrates a color mixing phenomenon in the case of using the conventional test signal timing diagram in the embodiment of FIG. 4 .
8 is a timing diagram illustrating an auto probe test process according to an embodiment of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms. When it is described that a component is “connected”, “coupled” or “connected” to another component, the component may be directly connected or connected to the other component, but other components may be interposed between each component. It should be understood that each component may be “interposed” or “connected”, “coupled” or “connected” through another component.

1 illustrates an example of a display panel or an array substrate of a general display device.

The display panel 100 that can be used as a display panel of such a liquid crystal display (LCD) or a display panel of an OLED display includes an active area (AA) providing an image to a user and a periphery of the active area (AA). The display panel is defined as a non-active area (NA), which is an area, and a display panel has a first substrate, which is an array substrate, on which thin film transistors are formed and a pixel area is defined, and a black matrix and/or a color filter layer. A second substrate as an upper substrate is bonded and manufactured.

Of course, in the case of an OLED display panel, the second substrate may only function as a protective substrate.

The array substrate or the first substrate on which the thin film transistor is formed includes a plurality of gate lines GL extending in a first direction and a plurality of data lines DL extending in a second direction perpendicular to the first direction. and one pixel area (Pixel; P) is defined by each gate line and data line. One or more thin film transistors are formed in one pixel region P, and a gate or source electrode of each thin film transistor may be connected to a gate line and a data line, respectively.

A data pad serving as a signal pad for applying a data signal is formed at an end of each data line DL in a non-display area of the upper or lower portion of the display panel 100 , and a source for driving the data line is formed under the display panel 100 . A D-IC, which is a data driving circuit that generates and provides an output signal, is mounted.

On the other hand, after the manufacturing process of the array substrate is completed, a so-called array test process or an auto probe inspection process for inspecting whether the panel has defects such as electrical characteristics is performed. In this inspection process, a specific data line and a gate line By simultaneously applying a signal to and inspecting whether the corresponding pixel is turned on or off, it is inspected whether each line or wiring is electrically disconnected or short-circuited.

This inspection process may be performed by applying a test signal to the auto probe inspection area formed on the display panel using an auto probe device. is formed.

In this specification, the auto probe inspection area should be interpreted as including all types of inspection patterns formed in the non-display area of the display panel in order to test the electrical characteristics of the display panel in contact with the auto probe device, etc. It is not limited to the expression area, and other terms such as a test area, an inspection area, and a shorting bar area may be used.

The enlarged view on the right of FIG. 1 is an enlarged view of a non-display area including a design area for auto probe inspection. The design area 120 for auto probe inspection is a D-IC output pad area 110 formed in the non-display area. ) and the D-IC input bumper pad region 130 . In addition, the test pad area 120 ′ in which signal input pins for auto probe test are disposed may be formed on the left and right sides of the design area 120 for the auto probe test.

After the test process of the array substrate or the display panel is completed and the corresponding D-IC is mounted, a predetermined control signal or data signal is input to the D-IC input bumper pad area 130 and the input signal is the D-IC The display device is driven by applying the signal output after being processed to the display area of the display panel via the D-IC output pad area 110 .

FIG. 2 shows a structure and an equivalent circuit of such a typical auto probe inspection area, and FIG. 3 is an enlarged view of the auto probe inspection area of FIG.

2 and 3, a typical auto probe inspection area includes a test data line section 240 for applying a test data signal for each color, and a test-in section for switching the test data signal to a corresponding data line (pad). It may include an enable device section 230 .

The test enable device section 230 again includes an R enable section 232 , a G enable section 234 , and a B enable section 236 , and in the enable section for each color, a thin film switched for each color R enable Tr (231), G enable Tr (233), and B enable Tr (235) which are switching elements like a transistor are formed.

In addition, the test data line section 240 for applying the test data signal for each color also includes an R test data line 242 , a G test data line 244 , and a B test data line 246 .

Referring to FIG. 3 , an R enable transistor 310 is formed in the R enable section, and the R enable transistor 310 includes a gate electrode 312 to which an R enable signal is applied, and a lower portion formed therein. It may include a source electrode 316 electrically connected to the R test data line 340 and a drain electrode 318 electrically connected to an upper data pad 320 . Of course, a semiconductor layer 314 switched by a gate voltage or a source voltage is also formed as an active layer.

On the other hand, a source connection wiring 332 and a drain connection wiring 322 extending integrally with the source electrode 316 and the drain electrode 318 of the R enable transistor 310 are formed, and the drain connection wiring 322 is The drain electrode 318 of the R enable transistor 310 is connected to the corresponding R data line or R data pad 320 , and the source connection line 332 is the source electrode 316 of the R enable transistor 310 . is connected to the R test data line 340 .

For simplicity, only the R enable transistor 310 is illustrated in FIG. 3 , but the enable transistors having the same structure should be formed for G and B as well. That is, in the G enable section of FIG. 3 , a G enable transistor having the same structure as that of the R enable transistor is formed, and the source electrode of the G enable transistor is connected to the G test data line 350 below.

In addition, test data input pads 344 , 354 , 364 are formed at one end of each of the R, G, and B test data lines 340 , 350 , and 360 .

Schematically looking at the test process using the auto probe inspection region having the above structure, when a signal is applied to the R test data line 340 using the auto probe device and the R enable transistor is turned on at the same time, all R data lines When a signal is applied to and a corresponding gate line output signal is also applied at the same time, all red (R) pixels are turned on, so that the red pixel can be inspected, and then the G and B pixels are also inspected in the same way. .

On the other hand, a typical auto probe inspection area as shown in FIGS. 2 and 3 consists of a total of six sections because a test enable section for each color of R, G, and B and a test data input section for each color must be formed separately. Accordingly, there is a disadvantage in that the width of the auto probe inspection area is increased, and as a result, the bezel under the display panel becomes large due to the increase in the non-display area.

In addition, in a typical auto probe inspection area as shown in FIGS. 2 and 3 , the source electrode of each color enable transistor and its connection wiring are formed in a vertical direction in the source/drain layer, and each of the connection wirings is located in the horizontal direction below. It should be selectively connected to the test data line for each color extending to .

For example, although not shown in FIG. 3 , the source electrode of the G enable transistor next to the R enable transistor 310 and the source connection wiring therefrom extend in the longitudinal direction and are located below the R test data line 340 . It must be connected to the G test data line 350 , and its structure must extend across the R test data line 340 .

However, since the source electrode of the G enable transistor and the source connection wiring therefrom must not contact the R test data line 340 , as a result, the test data lines 340 , 350 , 360 for each color are connected to the corresponding enable transistors. It is inevitably formed in a layer different from that of the source electrode and the source connection wiring 332 .

Accordingly, as shown in FIG. 3 , the test data line for each color is formed on the gate metal layer, and the source electrode and the source connection wiring of the enable transistor for each color are formed on the source/drain layer, which is a different metal layer. do.

Therefore, in order to connect the source electrode and the source connection line of the enable transistor for each color to the corresponding test data line, a certain contact hole 334 or a jumping hole must be formed above the test data line.

That is, the contact hole 334 should be formed by removing some regions such as the gate insulating layer 302 applied on the test data line 340 , which is the gate layer, and a source/drain layer should be deposited thereon.

Therefore, in the structure of a typical auto probe inspection area as shown in FIGS. 2 and 3 , a contact hole or a jumping hole must be formed, so the manufacturing process of the array substrate or display panel is complicated, and the resistance between the enable transistor and the test data line is increased. Accordingly, there were disadvantages such as a decrease in electrical characteristics.

Accordingly, in one embodiment of the present invention, in the inspection area of the display panel or array substrate, one or more test enable switching elements for each color corresponding to each of two or more colors and one electrode of the one or more test enable switching elements for each color are common. We propose a structure in which a single test data line connected to each other to input a test signal is formed.

Hereinafter, a specific configuration of the present invention will be described with reference to FIGS. 4 to 8 .

4 is a plan view illustrating the structure of an auto probe inspection area according to an embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along line I-I' of FIG. 4 .

4 , in the display panel according to an exemplary embodiment of the present invention, the display area A/A including a plurality of pixels defined in the intersection area of the gate line and the data line is disposed in the non-display area NA and includes an inspection region for inspecting electrical characteristics of a pixel or data line, wherein the inspection region includes an R enable transistor 440, G as a test enable switching element for two or more colors, for example, R, G, and B The enable transistor 450 , the B enable transistor 460 , and one terminal or one electrode of the three enable transistors, for example, a single test data line commonly connected to a source electrode to input test data (480) is included.

The above-described test enable switching element may include, but is not limited to, an R enable transistor, a G enable transistor, and a B enable transistor. and may be grouped according to a certain criterion, not by color.

That is, for example, an enable transistor for an even data line and an enable transistor for an odd data line may be provided for each group of a plurality of data lines for each predetermined test criterion.

As shown in FIG. 4 , each enable transistor 440 , 450 , 460 includes gate electrodes 442 , 452 , 462 formed on a gate metal layer, a semiconductor layer 463 thereon, and source/drain electrodes on the semiconductor layer. It is configured to include source electrodes 444 , 454 , and 464 and drain electrodes 446 , 456 , and 466 formed to be spaced apart from each other in layers.

A manufacturing process of such an enable transistor will be described in more detail below with reference to FIG. 5 .

Meanwhile, the single test data line 480 is electrically connected to all of the source electrodes 444 , 454 , and 464 of each enable transistor 440 , 450 , and 460 , and as shown in FIG. 4 , the single test data line 480 . is connected to the source electrode 464 of the B enable transistor through the second source connecting line 474 , and the source electrode 464 of the B enable transistor is G enable through the first source connecting line 472 again. It is connected to the source electrode 454 of the transistor, and the source electrode 454 of the G enable transistor is connected to the source electrode 444 of the R enable transistor through a first source connection line 472 .

The source electrodes 444, 454, and 464 of the R enable transistor, the G enable transistor, and the B enable transistor, the first source connection wiring 472, the second source connection wiring 474, and the single test data line 480 ) are integrally extended and formed on the same layer, more specifically, the source/drain metal layer.

Therefore, according to the embodiment of FIG. 4, a contact hole required to connect the source electrode of the enable transistor and the corresponding test data line in the same manner as in FIGS. 2 and 3 is not required, so the structure of the auto probe inspection area is not only simplified, but also concerns about the increase in resistance and the possibility of defects occurring due to the formation of the contact hole are eliminated.

In addition, in the embodiment of FIG. 4 , the auto probe inspection area includes an enable area 410 including three sections: an R enable section 412 , a G enable section 414 , and a B enable section 416 , and Since it consists of a total of four sections of the test data line section 410 consisting of one section, the width or length of the inspection area is reduced compared to the method of FIGS. 2 and 3 requiring a total of six sections, so that the narrow bezel ( Narrow Bezel) becomes possible.

In the embodiment of FIG. 4 , drain electrodes 446 , 456 , and 466 of each enable transistor are electrically connected to a corresponding data line or data pad 430 , respectively.

The gate electrode of each enable transistor may be implemented in the form of a gate electrode line extending horizontally with a predetermined width from the gate metal layer. Therefore, when an enable signal is applied to the corresponding gate electrode line, the enable transistor of the corresponding color All of them can be turned ON at the same time.

In addition, a test data pad 482 for contacting a terminal of the auto probe device is formed at one end of the single test data line 480 .

When describing the test process through the test region, first, the R test enable signal is applied to the gate electrode of the R enable transistor for a predetermined test period T in order to test the R pixel or the data line for the R pixel, At the same time, test data (ON signal) is applied to a single test data line.

Then, the test ON signal is applied to the source electrode of the R enable transistor through a single test data line, and since the R enable transistor is in the ON state, the ON signal, which is the test data, is applied to the corresponding data line through the drain electrode. , all R pixels are driven at the same time, and the pixels are inspected in that state.

On the other hand, in the inspection area structure as shown in FIGS. 2 and 3 , since test data is input for each color separately, all enable transistors may be always turned on throughout the inspection period, and thus the gate electrode lines of all enable transistors are formed in one pattern. can be formed with That is, in the method of FIGS. 2 and 3 , all of the gate electrodes of the R, G, and B enable transistors may be electrically connected.

However, in the embodiment of FIG. 4 , since the corresponding enable transistors must be driven separately during the inspection period for each color, the gate electrodes of the R enable transistor, the G enable transistor, and the B enable transistor should not be electrically connected to each other. . Accordingly, as shown in FIG. 4 , the gate electrode lines 442 , 453 , and 462 of the enable transistor are spaced apart from each other to extend in parallel and are disposed not to be electrically connected.

5 is a cross-sectional view of an auto probe inspection area according to an embodiment of the present invention, and is a view taken along line I-I' of FIG. 4 .

A process of forming an auto-probe inspection area according to an embodiment of the present invention will be described with reference to FIG. 5 .

First, on a transparent insulating substrate, for example, a substrate made of glass or plastic, a low-resistance metal material such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo) and molybdenum alloy (MoTi) ) by depositing a gate metal material composed of one or more of two or more materials on the entire surface of the substrate to form a first metal layer, applying a photoresist to the first metal layer, exposure using a photomask, developing the exposed photoresist, the first The gate electrode 442 line of the R enable transistor and the gate of the G enable transistor are patterned by performing a mask process or photolithography process that includes a series of unit processes such as partial etching of a metal layer and a strip of photoresist. The electrode 452 line and the gate electrode 462 line of the B enable transistor are formed.

Of course, in this process, a gate line (not shown) connected to each pixel region and a gate electrode of the driving TFT or the pixel TFT are simultaneously formed.

Next, after placing a mask having a transmission region in a required region, a gate insulating layer made of an inorganic insulating material ( 402) is formed.

Of course, although the gate insulating layer 402 is shown as a single layer in FIG. 5 , it may have a structure of two or more layers made of different materials.

Next, as an oxide semiconductor material on the gate insulating layer 402 , a zinc oxide (ZnO)-based oxide, for example, any one of Indium Gallium Zinc Oxide (IGZO), Zinc Tin Oxide (ZTO), and Zinc Indium Oxide (ZIO) By depositing or applying to form an oxide semiconductor material layer, and patterning the oxide semiconductor material layer (not shown) through a mask process, an island-shaped active layer or semiconductor layer ( 463) is formed.

The semiconductor layer 463 may be formed of polysilicon, but is not limited thereto, and may be formed of an oxide semiconductor or one of pure and impurity amorphous silicon.

Thereafter, an ohmic contact layer is formed on the semiconductor layer 463 to reduce contact resistance, and a source/drain electrode layer is formed thereon.

More specifically, after the semiconductor layer 463 and/or the ohmic contact layer is formed, copper (Cu), chromium (Cr), molybdenum (Mo), titanium (Ti), tantalum (Ta), molybdenum alloy (Mo) alloy) is deposited on the entire surface of the substrate to form a second metal layer, and the second metal layer is patterned through a mask process or a photolithography process to form the source electrodes 444, 454, 464 , drain electrodes 446 , 456 , and 466 , a single test data line 480 , source connection wirings 472 and 474 , and a test data pad 482 are simultaneously formed.

Of course, in this process, a data line (not shown) and a data pad 430 that are simultaneously connected to each pixel area may be formed together.

That is, as shown in FIG. 5 , since the source/drain electrodes of the enable transistor and the test data line 480 are formed in the same layer, a conventional contact hole used to connect the two is not needed.

Embodiments of the present invention are not applied only to liquid crystal display panels, but may be applied to all types of display panels such as organic electroluminescent display panels, electrophoretic displays, and plasma display panels.

That is, if an array substrate including an array substrate in which pixels are defined by a plurality of gate lines (scan lines) and data lines (source lines), and an auto probe process is to be performed in order to inspect the electrical characteristics of the array substrate or the pixels, It may be applied to all types of display panels.

6 is a timing diagram of a test signal according to the embodiment of FIG. 2 and shows both a timing diagram of a test enable signal and test data for each color.

As shown in (a) of FIG. 6 , in the auto probe inspection structure of FIGS. 2 and 3 , an enable ON signal is applied to the gate electrode of the enable transistor of the corresponding color during the inspection period T for each color. Turn on the enable transistor to be switched on. At the same time, the test ON data is applied through the test data line of the corresponding color during the corresponding inspection period so that the test signal is inputted to the data line of the corresponding color.

In this state, when a gate output signal is applied to the gate line, all pixels of a corresponding color are driven, and an auto probe inspection process is performed on the pixels of the first color by examining the pixels.

During the next inspection period, the inspection process is performed on the pixel of the second color, which is the next color, in the same manner.

Meanwhile, in the auto probe inspection structure of FIGS. 2 and 3 , since test data for each color is separately applied during the inspection period of each color, as a result, the enable transistor may be always ON.

That is, as shown in (b) of FIG. 6, in the state that the ON signal is always applied to the gate electrodes of the R, G, and B enable transistors to drive the transistor, test data of the corresponding color is input during the inspection period for each color. so that you can check it.

Accordingly, in the inspection region structure shown in FIGS. 2 and 3 , the gate electrodes of the enable transistors for each color may be electrically connected to each other, and all the enable transistors may be switched on throughout the entire inspection process.

7 illustrates a color mixing phenomenon in the case of using the conventional test signal timing diagram in the embodiment of FIG. 4 .

In the auto probe inspection area as shown in FIGS. 4 and 5 , since a single test data line is formed, it is impossible to input test data divided by color.

Accordingly, as shown in FIG. 7 , an R enable signal (an On signal is applied during T) is applied to the R enable transistor during the inspection period of the first color R, and at the same time, during the inspection period, R through a single test data line. Test data is applied. When the next inspection period of the second color (G) is reached, the R enable signal is turned OFF, the G enable signal (ON) is input to the G enable transistor, and a single test data line has a test for the second color, G. Data is entered.

As a result, during the inspection period of a specific color, the enable transistor of the corresponding color is separately controlled ON/OFF, but the test signal input through a single test data line is always applied in the ON state. That is, as shown in (a) of FIG. 7 , the test data is always an ON signal, but only the purpose of each color is classified for each inspection period.

On the other hand, if the pixel of the first color is driven during the inspection period of the first color and the inspection period of the second color is progressed, the phenomenon in which the charges charged in the pixel of the first color are gradually discharged during a predetermined period of the inspection period of the second color Occurs.

That is, some pixels of the first color are turned on for a certain period of time before the inspection cycle of the second color, so that the first color and the second color are seen as mixed. have.

As shown in (b) of FIG. 7 , even if the R pixel enters the G inspection period (T′) through the R inspection period (T), the charge driving the R pixel is gradually discharged, so that the R and G mixed color section 710 ) may occur. Similarly, the mixed color section 720 in which G and B are mixed may occur even at the beginning of the B inspection period (T″) after the G inspection period (T′).

In order to prevent such a color mixing phenomenon, an auto probe inspection process as shown in FIG. 8 may be used.

That is, using the R enable transistor, the G enable transistor, and the B enable transistor disposed in the non-display area of the display panel, and a single test data line commonly connected to certain terminals of the enable transistors to apply test data. A display panel inspection method comprising: a first step of applying a first test enable ON signal to a corresponding enable transistor during an inspection period (T) for a first color; and a first period (T1) of the inspection period (T) An ON signal of the first test data for a first color is applied to the single test data line during the period T, and an OFF signal of the first test data is applied to the single test data during the remaining second period T2 of the inspection period T. It may include a second step of applying to the line, and a third step of repeatedly performing the first and second steps with respect to the second color.

In addition, in the first step, the first test enable ON signal is applied to the gate electrode of the corresponding enable transistor, and the first test data input through the single test data line is applied to the source electrode of the corresponding enable transistor. do.

That is, as shown in FIG. 8 , the R enable ON signal is continuously applied to the R enable transistor during the R test period T, but when the R test data is applied through a single test data line, the During the first period (T1), the R test data is input as ON, and then, during the remaining second period (T2), the R test data is applied as an OFF signal.

Therefore, as each color becomes a kind of ground or ground during the second period T2, which is the second half of the inspection period of each color, all the charges that have driven the R pixel are instantly discharged, and thus the color mixing phenomenon as shown in FIG. 7 does not occur. .

As described above, according to an embodiment of the present invention, since the auto probe inspection area of the display panel includes only one test data input line, the width of the auto probe inspection area is reduced, such as the size of the bezel and the D-IC at the edge of the display panel. has the effect of reducing

In fact, in the auto probe inspection area as shown in FIGS. 2 and 3, a total of 6 sections including three enable transistor areas and three test data line sections were included, so a space of about 500 μm was required for the width of the test area. As a result of implementing the inspection area in the examples of 4 and 5 , the width was reduced to about 270 μm. As a result, it was confirmed that the width of the auto probe inspection area was reduced by nearly 50%.

In addition, by forming one single test data input line in the same layer as the source electrode of the enable transistor for each color of R, G, and B and the source connection wiring thereto, there is no need for a separate contact hole or jumping hole, so the structure is improved. It is simplified, and electrical characteristics are improved and the possibility of defects is reduced.

In addition, in the inspection process through a single test data input line, by including the ground signal or OFF signal period of a certain time period between the test data for each color to completely discharge the charged charge of the color that has been tested, in the test process for each color It has the effect of preventing color mixing.

The above description and the accompanying drawings are merely illustrative of the technical idea of the present invention, and those of ordinary skill in the art to which the present invention pertains can combine configurations within a range that does not depart from the essential characteristics of the present invention. , various modifications and variations such as separation, substitution and alteration will be possible. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

440, 450, 460 : R, G, B enable transistors
442, 452, 462: gate electrode 444, 454, 464: source electrode
446, 456, 466: drain electrodes 472, 474: first and second source connection wiring
480: single test data line 482: test data pad

Claims (9)

A display panel comprising: a display area A/A including a gate line, a data line, and a plurality of pixels; and an inspection area disposed in the non-display area NA to inspect electrical characteristics of pixels or data lines, The inspection area is
a test enable switching element provided with one or more for each of two or more colors;
a single test data line commonly electrically connected to one electrode of the test enable switching element to input test data;
The test enable switching device includes a gate electrode to which a test enable signal for each color is applied, a source electrode electrically connected to the single test data line, and a drain electrode electrically connected to the corresponding data line. display panel. According to claim 1,
The test enable switching element includes an R enable transistor, a G enable transistor, and a B enable transistor. 3. The method of claim 2,
Source electrodes of the R enable transistor, the G enable transistor, and the B enable transistor are electrically connected to the single test data line through a source connection line. 4. The method of claim 3
The source connection wiring includes a first source connection wiring connecting the source electrode of the enable transistor of the first color and the source electrode of the enable transistor of the second color, and the source electrode of the enable transistor of the outermost color and the single test. A display panel including a second source connecting wire connecting the data line. delete 3. The method of claim 2,
and gate electrodes of the R enable transistor, the G enable transistor, and the B enable transistor are not electrically connected to each other. An R enable transistor, a G enable transistor, and a B enable transistor disposed in a non-display area of the display panel and including a drain electrode electrically connected to a data line included in the display panel, and a source electrode of the enable transistors. A display panel inspection method using a single test data line that is commonly electrically connected to apply test data, comprising:
a first step of applying a first test enable ON signal to a gate electrode of the corresponding enable transistor during a test period (T) for a first color;
During a first period T1 of the inspection period T, an ON signal of the first test data for the first color is applied to the single test data line, and the remaining second period T2 of the inspection period T a second step of applying an OFF signal of the first test data to the single test data line;
and a third step of repeatedly performing the first and second steps with respect to a second color. 8. The method of claim 7,
In the first step, the first test enable ON signal is applied to the gate electrode of the corresponding enable transistor, and the first test data input through the single test data line is applied to the source electrode of the corresponding enable transistor. How to inspect the display panel. 8. The method of claim 7,
A display panel inspection method in which the pixel charging charge corresponding to the first color is discharged during the second period (T2) so that the color is not mixed with the second color in the third step.

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