KR102303653B1 - Memory device and memory system including the same - Google Patents

Abstract

The memory device includes memory groups and a boosting interface.
The boosting interface includes a variable input decoder. Memory groups store data. The boosting interface transmits data by determining a data transfer path according to the command and the access address. The variable input decoder programs a program command among the commands based on the command setting mode and the input/output setting mode. The memory device according to the present invention may improve performance by programming a program command in the variable input decoder based on the command setting mode and the input/output setting mode.

Description

MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME

The present invention relates to a semiconductor device, and more particularly, to a memory device and a memory system including the same.

Recently, with the development of technologies related to electronic devices, high performance of memory devices is progressing. Various studies are being conducted to improve the performance of memory devices.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory device capable of improving performance by programming a program command in a variable input decoder based on a command setting mode and an input/output setting mode.

SUMMARY OF THE INVENTION One object of the present invention is to provide a memory system capable of improving performance by programming a program command in a variable input decoder based on a command setting mode and an input/output setting mode.

An object of the present invention to solve the above problems is to provide a computing system capable of improving performance by programming a program command in a variable input decoder based on a command setting mode and an input/output setting mode.

In order to achieve one object of the present invention, a memory device according to embodiments of the present invention includes memory groups and a boosting interface. The boosting interface includes a variable input decoder. The memory groups store data. The boosting interface determines a transfer path of the data according to a command and an access address and transfers the data. The variable input decoder programs a program command among the commands based on a command setting mode and an input/output setting mode.

In an exemplary embodiment, the boosting interface may include a buffer and a fixed input decoder. The buffer may transfer the data between the memory controller and the memory groups based on a data output enable signal and a data input enable signal. The fixed input decoder may embed a fixed command among the commands in hardware.

In an exemplary embodiment, the variable input decoder may include a write command decoder and a read command decoder. When the input/output setting mode is an input mode, a write command among the program commands may be programmed in a write command decoder. When the input/output setting mode is an output mode, a read command among the program commands may be programmed in a read command decoder.

In an exemplary embodiment, the write command decoder may include a write latch and a write comparator. The write command may be programmed into the write latch. The write comparator may compare the write command programmed in the write latch and the command provided from the memory controller to provide a write comparison signal.

In an exemplary embodiment, when the memory controller provides the input mode among the command setting mode and the input/output setting mode, the memory controller may program the write command into the write latch.

In an exemplary embodiment, the memory controller may further program an enable bit for determining whether to activate the write command in the write latch.

In an exemplary embodiment, when the enable bit is in a first state and the write comparison signal is in a first state, the data input enable signal may be activated.

In an exemplary embodiment, when the enable bit is in the second state, the data input enable signal may be deactivated.

In an exemplary embodiment, when the write comparison signal is in the second state, the data input enable signal may be deactivated.

In an exemplary embodiment, the boosting interface may further include an anti-fuse for storing the program command.

In an exemplary embodiment, when the memory device is powered on, the program command stored in the antifuse may be programmed into the variable input decoder.

In an exemplary embodiment, the read command decoder may include a read latch and a read comparator. The read command may be programmed into the read latch. The read comparator may provide a read comparison signal by comparing the read command programmed in the read latch and the command provided from the memory controller.

In an exemplary embodiment, when the memory controller provides the output mode among the command setting mode and the input/output setting mode, the memory controller may program the read command into the read latch.

In an exemplary embodiment, the memory controller may further program an enable bit for determining whether to activate the read command in the read latch.

In an exemplary embodiment, when the enable bit is in a first state and the read comparison signal is in a first state, the data output enable signal may be activated.

In an exemplary embodiment, when the enable bit is in the second state, the data output enable signal may be deactivated.

In an exemplary embodiment, when the read comparison signal is in the second state, the data output enable signal may be deactivated.

In order to achieve one object of the present invention, a memory system according to embodiments of the present invention includes a memory controller, memory groups, and a boosting interface. The boosting interface includes a variable input decoder. The memory controller may provide a command and an access address. The memory groups may store data. The boosting interface determines a transfer path of the data according to the command and the access address and transfers the data. The variable input decoder may program a program command among the commands based on a command setting mode and an input/output setting mode.

In an exemplary embodiment, the memory groups may include a three-dimensional memory cell array.

In order to achieve one object of the present invention, a computing system according to embodiments of the present invention includes a host, a memory controller, memory groups, and a boosting interface. The boosting interface includes a variable input decoder. The host provides a host signal. The memory controller provides a command and an access address based on the host signal. The memory groups store data. The boosting interface determines a transfer path of the data according to the command and the access address and transfers the data. The variable input decoder programs a program command among the commands based on a command setting mode and an input/output setting mode.

The memory device according to the present invention may improve performance by programming a program command in the variable input decoder based on the command setting mode and the input/output setting mode.

1 is a block diagram illustrating a memory device according to embodiments of the present invention.
FIG. 2 is a diagram for explaining an operation of the memory device of FIG. 1 .
3 is a diagram illustrating a memory device according to an embodiment of the present invention.
4 is a diagram illustrating an example of a buffer included in the memory device of FIG. 3 .
FIG. 5 is a diagram for explaining an operation of a fixed input decoder included in the memory device of FIG. 3 .
6 and 7 are diagrams for explaining an operation of a variable input decoder included in the memory device of FIG. 3 .
8 is a diagram illustrating a conventional memory device including a boosting interface.
9 is a block diagram illustrating an example of a write command decoder included in the variable input decoder of FIG. 3 .
10 is a block diagram illustrating another example of a write command decoder included in the variable input decoder of FIG. 3 .
11 is a diagram illustrating an example of a boosting interface included in the memory device of FIG. 3 .
12 is a block diagram illustrating an example of a read command decoder included in the variable input decoder of FIG. 3 .
13 is a block diagram illustrating another example of a read command decoder included in the variable input decoder of FIG. 3 .
14 is a diagram for explaining an operation of a buffer included in the memory device of FIG. 3 .
15 is a diagram illustrating a memory system according to embodiments of the present invention.
16 is a block diagram illustrating a memory device included in the memory system of FIG. 15 .
17 is a diagram illustrating an example of a memory cell array included in the memory device of FIG. 16 .
18 is a diagram illustrating another example of a memory cell array included in the memory device of FIG. 16 .
19 is a diagram illustrating a computing system according to embodiments of the present invention.
20 is a block diagram illustrating an example of applying a memory device according to embodiments of the present invention to a mobile system.
21 is a block diagram illustrating an example of applying a memory device according to embodiments of the present invention to a computing system.

With respect to the embodiments of the present invention disclosed in the text, specific structural or functional descriptions are only exemplified for the purpose of describing the embodiments of the present invention, and the embodiments of the present invention may be embodied in various forms. It is not to be construed as being limited to the embodiments described in .

Since the present invention can have various changes and can have various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention.

Terms such as first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The above terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component.

When a component is referred to as being “connected” or “connected” to another component, it is understood that the other component may be directly connected or connected to the other component, but other components may exist in between. it should be On the other hand, when it is said that a certain element is "directly connected" or "directly connected" to another element, it should be understood that no other element is present in the middle. Other expressions describing the relationship between elements, such as "between" and "immediately between" or "neighboring to" and "directly adjacent to", should be interpreted similarly.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present application, terms such as “comprise” or “have” are intended to designate that the described feature, number, step, operation, component, part, or combination thereof exists, and includes one or more other features or numbers. , it is to be understood that it does not preclude the possibility of the presence or addition of steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as meanings consistent with the context of the related art, and unless explicitly defined in the present application, they are not to be interpreted in an ideal or excessively formal meaning. .

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and repeated descriptions of the same components are omitted.

FIG. 1 is a block diagram illustrating a memory device according to embodiments of the present invention, and FIG. 2 is a diagram for explaining an operation of the memory device of FIG. 1 .

1 and 2 , the memory device 10 includes memory groups 300 and a boosting interface 100 . The boosting interface 100 includes a variable input decoder 130 . The memory groups 300 store data DATA. For example, the memory groups 300 may include a first memory group 310 and a second memory group 330 . The first memory group 310 may include a plurality of memory cell arrays, and the second memory group 330 may include a plurality of memory cell arrays. The plurality of memory cell arrays may include flash memory cells.

The variable input decoder 130 programs the program command P_CMD among the commands CMD based on the command setting mode CSMS and the input/output setting mode IOM. For example, the memory controller 15 may provide a command setting mode (CSMS) and an input/output setting mode (IOM). When the memory controller 15 provides the command setting mode CSMS and the input/output setting mode IOM, the memory controller 15 may program the program command P_CMD in the variable input decoder 130 .

The boosting interface 100 transmits the data DATA by determining a transfer path of the data DATA according to the command CMD and the access address ADDR. For example, the variable input decoder 130 compares the command CMD provided from the memory controller 15 and the program command P_CMD programmed in the variable input decoder 130 to obtain a data output enable signal DOUT_EN and A data input enable signal DIN_EN may be provided. In an exemplary embodiment, the data output enable signal DOUT_EN provided from the variable input decoder 130 may be enabled. When the data output enable signal DOUT_EN provided from the variable input decoder 130 is enabled, the data transfer path may be the first path P1 . When the transfer path of the data DATA is the first path P1 , the data DATA may be transferred from the memory groups 300 to the memory controller 15 . In an exemplary embodiment, the data input enable signal DIN_EN provided from the variable input decoder 130 may be enabled. When the data input enable signal DIN_EN provided from the variable input decoder 130 is enabled, the data transfer path may be the second path P2 . When the data DATA transfer path is the second path P2 , the data DATA may be transferred from the memory controller 15 to the memory groups 300 .

The performance of the memory device 10 according to the present invention may be improved by programming the program command P_CMD in the variable input decoder 130 based on the command setting mode CSMS and the input/output setting mode IOM.

3 is a diagram illustrating a memory device according to an embodiment of the present invention, and FIG. 4 is a diagram illustrating an example of a buffer included in the memory device of FIG. 3 .

3 and 4 , the memory device 10 includes memory groups 300 and a boosting interface 100 . The boosting interface 100 includes a buffer 110 , a fixed input decoder 150 , and a variable input decoder 130 . The memory groups 300 store data DATA. The boosting interface 100 transmits the data DATA by determining a transfer path of the data DATA according to the command CMD and the access address ADDR. For example, the command CMD and the access address ADDR may be provided from the memory controller 15 . The variable input decoder 130 programs the program command P_CMD among the commands CMD based on the command setting mode CSMS and the input/output setting mode IOM.

The buffer 110 may transfer data DATA between the memory controller 15 and the memory groups 300 based on the data output enable signal DOUT_EN and the data input enable signal DIN_EN. For example, the buffer 110 may include a first buffer 111 and a second buffer 112 .

The first buffer 111 may be enabled based on the data output enable signal DOUT_EN. When the data output enable signal DOUT_EN is enabled, the first buffer 111 may be enabled. When the first buffer 111 is enabled, a transmission path of the data DATA may be the first path P1 . When the transfer path of the data DATA is the first path P1 , the data DATA may be transferred from the memory groups 300 to the memory controller 15 . Also, when the data output enable signal DOUT_EN is disabled, the first buffer 111 may be disabled. When the first buffer 111 is disabled, the data DATA may not be transferred from the memory groups 300 to the memory controller 15 .

The second buffer 112 may be enabled based on the data input enable signal DIN_EN. When the data input enable signal DIN_EN is enabled, the second buffer 112 may be enabled. When the second buffer 112 is enabled, the data DATA transfer path may be the second path P2 . When the data DATA transfer path is the second path P2 , the data DATA may be transferred from the memory controller 15 to the memory groups 300 . Also, when the data input enable signal DIN_EN is disabled, the second buffer 112 may be disabled. When the second buffer 112 is disabled, the data DATA cannot be transferred from the memory controller 15 to the memory groups 300 .

An output of the fixed input decoder 150 may include a fixed decoder read signal FD_R and a fixed decoder write signal FD_W. For example, when the read command CMD_R stored in the fixed input decoder 150 and the command CMD provided from the memory controller 15 are the same, the fixed decoder read signal FD_R may be enabled. Also, when the write command CMD_W stored in the fixed input decoder 150 and the command CMD provided from the memory controller 15 are the same, the fixed decoder write signal FD_W may be enabled.

An output of the variable input decoder 130 may include a variable decoder read signal RD_R and a variable decoder write signal RD_W. For example, when the read command CMD_R programmed in the variable input decoder 130 and the command CMD provided from the memory controller 15 are the same, the variable decoder read signal RD_R may be enabled. Also, when the write command CMD_W programmed in the variable input decoder 130 and the command CMD provided from the memory controller 15 are the same, the variable decoder write signal RD_W may be enabled.

The fixed decoder read signal FD_R and the variable decoder read signal RD_R may be provided to the first OR gate 171 . When the fixed decoder read signal FD_R or the variable decoder read signal RD_R is enabled, the data output enable signal DOUT_EN may be enabled. Also, the fixed decoder write signal FD_W and the variable decoder write signal RD_W may be provided to the second OR gate 172 . When the fixed decoder write signal FD_W or the variable decoder write signal RD_W is enabled, the data input enable signal DIN_EN may be enabled. The performance of the memory device 10 according to the present invention may be improved by programming the program command P_CMD in the variable input decoder 130 based on the command setting mode CSMS and the input/output setting mode IOM.

FIG. 5 is a diagram for explaining an operation of a fixed input decoder included in the memory device of FIG. 3 , and FIGS. 6 and 7 are diagrams for explaining an operation of a variable input decoder included in the memory device of FIG. 3 .

3 and 5 to 7 , the boosting interface 100 may include a fixed input decoder 150 and a variable input decoder 130 . In an exemplary embodiment, a fixed command F_CMD among the commands CMD may be embedded in the fixed input decoder 150 as hardware. The fixed input decoder 150 may include a hard-wired circuit 151 . The fixed command F_CMD may be implemented as hardware in the hard-wired circuit 151 . For example, the fixed command F_CMD may include first to third commands CMD1 , CMD2 , and CMD3 . The first command CMD1 may be embedded in the fixed input decoder 150 as hardware. Since the first command CMD1 is embedded in the input decoder as hardware, the first command CMD1 included in the fixed input decoder 150 cannot be reprogrammed. Also, the second command CMD2 may be embedded in the fixed input decoder 150 as hardware. Since the second command CMD2 is embedded in the input decoder as hardware, the second command CMD2 included in the fixed input decoder 150 cannot be reprogrammed. Also, the third command CMD3 may be embedded in the fixed input decoder 150 as hardware. Since the third command CMD3 is embedded in the input decoder as hardware, the third command CMD3 included in the fixed input decoder 150 cannot be reprogrammed.

The variable input decoder 130 may include a write command decoder 131 and a read command decoder 136 . A write command CMD_W among the program commands P_CMD may be programmed in the write command decoder 131 based on the command setting mode CSMS and the input/output setting mode IOM. For example, the memory controller 15 may provide a command setting mode (CSMS). After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM is the input mode IN_M, the write command CMD_W among the program commands P_CMD may be programmed in the write command decoder 131 .

The program command P_CMD may be a command CMD programmed in the variable input decoder 130 among commands CMD provided by the memory controller 15 . The write command CMD_W may be used for a write operation of the memory device 10 . For example, the write command CMD_W among the program commands P_CMD may include a first write command CMD_W1 , a second write command CMD_W2 , and a third write command CMD_W3 . The memory controller 15 may provide a command setting mode (CSMS). After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM provided by the memory controller 15 is the input mode IN_M, the memory controller 15 sends the first write command CMD_W1 among the program commands P_CMD to the write command decoder 131 . can be programmed. Thereafter, the memory controller 15 may provide the command setting mode CSMS again. After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM provided by the memory controller 15 is the input mode IN_M, the memory controller 15 transmits the second write command CMD_W2 among the program commands P_CMD to the write command decoder 131 . can be programmed. Thereafter, the memory controller 15 may provide the command setting mode CSMS again. After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM provided by the memory controller 15 is the input mode IN_M, the memory controller 15 sends the third write command CMD_W3 among the program commands P_CMD to the write command decoder 131 . can be programmed.

While the memory device 10 is being used, it may be required to add a new command CMD. When the addition of a new command CMD is required while the memory device 10 is being used, the memory controller 15 varies the program command P_CMD based on the command setting mode CSMS and the input/output setting mode IOM. It can be programmed in the input decoder 130 .

The read command CMD_R among the program commands P_CMD may be programmed in the read command decoder 136 based on the command setting mode CSMS and the input/output setting mode IOM. For example, the memory controller 15 may provide a command setting mode (CSMS). After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM is the output mode OUT_M, the read command CMD_R among the program commands P_CMD may be programmed in the read command decoder 136 .

The program command P_CMD may be a command CMD programmed in the variable input decoder 130 among commands CMD provided by the memory controller 15 . The read command CMD_R may be used for a read operation of the memory device 10 . For example, the read command CMD_R among the program commands P_CMD may include a first read command CMD_R1 , a second read command CMD_R2 , and a third read command CMD_R3 . The memory controller 15 may provide a command setting mode (CSMS). After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM provided by the memory controller 15 is the output mode OUT_M, the memory controller 15 transmits the first read command CMD_R1 among the program commands P_CMD to the read command decoder 136 . can be programmed. Thereafter, the memory controller 15 may provide the command setting mode CSMS again. After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM provided by the memory controller 15 is the output mode OUT_M, the memory controller 15 transmits the second read command CMD_R2 among the program commands P_CMD to the read command decoder 136 . can be programmed. Thereafter, the memory controller 15 may provide the command setting mode CSMS again. After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM provided by the memory controller 15 is the output mode OUT_M, the memory controller 15 transmits the third read command CMD_R3 among the program commands P_CMD to the read command decoder 136 . can be programmed.

While the memory device 10 is being used, it may be required to add a new command CMD. When the addition of a new command CMD is required while the memory device 10 is being used, the memory controller 15 varies the program command P_CMD based on the command setting mode CSMS and the input/output setting mode IOM. It can be programmed in the input decoder 130 .

In an exemplary embodiment, the boosting interface 100 may include a buffer 110 and a fixed input decoder 150 . The buffer 110 may transfer data DATA between the memory controller 15 and the memory groups 300 based on the data output enable signal DOUT_EN and the data input enable signal DIN_EN. The fixed input decoder 150 may embed the fixed command F_CMD among the commands CMD as hardware.

The performance of the memory device 10 according to the present invention may be improved by programming the program command P_CMD in the variable input decoder 130 based on the command setting mode CSMS and the input/output setting mode IOM.

8 is a diagram illustrating a conventional memory device including a boosting interface.

5, 6 and 8 , the conventional memory device 10a includes memory groups 300 and a boosting interface 100 . The boosting interface 100 includes a buffer 110 and a fixed input decoder 150 . The memory groups 300 store data DATA. For example, the memory groups 300 may include a first memory group 310 and a second memory group 330 . The first memory group 310 may include a plurality of memory cell arrays, and the second memory group 330 may include a plurality of memory cell arrays. The plurality of memory cell arrays may include flash memory cells.

The fixed input decoder 150 may include a fixed command F_CMD among the commands CMD as hardware. For example, the fixed command F_CMD may include first to third commands CMD1 , CMD2 , and CMD3 . The first command CMD1 may be embedded in the fixed input decoder 150 as hardware. Since the first command CMD1 is embedded in the input decoder as hardware, the first command CMD1 included in the fixed input decoder 150 cannot be reprogrammed. Also, the second command CMD2 may be embedded in the fixed input decoder 150 as hardware. Since the second command CMD2 is embedded in the input decoder as hardware, the second command CMD2 included in the fixed input decoder 150 cannot be reprogrammed. Also, the third command CMD3 may be embedded in the fixed input decoder 150 as hardware. Since the third command CMD3 is embedded in the input decoder as hardware, the third command CMD3 included in the fixed input decoder 150 cannot be reprogrammed.

The boosting interface 100 transmits the data DATA by determining a transfer path of the data DATA according to the command CMD and the access address ADDR. The buffer 110 may transfer data DATA between the memory controller 15 and the memory groups 300 based on the data output enable signal DOUT_EN and the data input enable signal DIN_EN. For example, the buffer 110 may include a first buffer 111 and a second buffer 112 .

For example, the first buffer 111 may be enabled based on the data output enable signal DOUT_EN. The read command CMD_R provided from the memory controller 15 may be the same as the first command CMD1 . When the memory controller 15 provides the read command CMD_R, the fixed input decoder 150 may enable the data output enable signal. When the data output enable signal DOUT_EN is enabled, the first buffer 111 may be enabled. When the first buffer 111 is enabled, a transmission path of the data DATA may be the first path P1 . When the transfer path of the data DATA is the first path P1 , the data DATA may be transferred from the memory groups 300 to the memory controller 15 .

Also, the second buffer 112 may be enabled based on the data input enable signal DIN_EN. The write command CMD_W provided from the memory controller 15 may be the same as the second command CMD2 . When the memory controller 15 provides the write command CMD_W, the fixed input decoder 150 may enable the data input enable signal. When the data input enable signal DIN_EN is enabled, the second buffer 112 may be enabled. When the second buffer 112 is enabled, the data DATA transfer path may be the second path P2 . When the data DATA transfer path is the second path P2 , the data DATA may be transferred from the memory controller 15 to the memory groups 300 .

On the other hand, in the case of the conventional memory device 10a, since only the fixed input decoder 150 built in hardware is used, the first write command CMD_W1 not included in the fixed input decoder 150 is applied to the memory controller 15 . ), the existing memory device 10a cannot perform an operation corresponding to the first write command CMD_W1. In the memory device 10 according to the present invention, when a new command CMD is required to be added while the memory device 10 is being used, the memory controller 15 performs a command setting mode (CSMS) and an input/output setting mode (IOM). Based on , the program command P_CMD may be programmed in the variable input decoder 130 . Accordingly, the performance of the memory device 10 according to the present invention may be improved by programming the program command P_CMD in the variable input decoder 130 based on the command setting mode CSMS and the input/output setting mode IOM.

9 is a block diagram illustrating an example of a write command decoder included in the variable input decoder of FIG. 3 .

Referring to FIG. 9 , the write command decoder 131a may include a write latch 132a and a write comparator 133 . A write command CMD_W may be programmed into the write latch 132a. For example, the write command CMD_W among the program commands P_CMD may include a first write command CMD_W1 , a second write command CMD_W2 , and a third write command CMD_W3 . The memory controller 15 may provide a command setting mode (CSMS). After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM provided by the memory controller 15 is the input mode IN_M, the memory controller 15 sends the first write command CMD_W1 among the program commands P_CMD to the write command decoder 131a. can be programmed. Thereafter, the memory controller 15 may provide the command setting mode CSMS again. After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM provided by the memory controller 15 is the input mode IN_M, the memory controller 15 transmits the second write command CMD_W2 among the program commands P_CMD to the write command decoder 131a. can be programmed. Thereafter, the memory controller 15 may provide the command setting mode CSMS again. After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM provided by the memory controller 15 is the input mode IN_M, the memory controller 15 sends the third write command CMD_W3 among the program commands P_CMD to the write command decoder 131a. can be programmed.

The write comparator 133 may compare the write command CMD_W programmed in the write latch 132a and the command CMD provided from the memory controller 15 to provide the write comparison signal CS_W. For example, the command CMD provided from the memory controller 15 may be the first write command CMD_W1 . When the command CMD provided from the memory controller 15 is the first write command CMD_W1 , the write comparator 133 performs the first write command CMD_W1 programmed in the write latch 132a and the memory controller 15 . The first write command CMD_W1 provided from . When the first write command CMD_W1 programmed in the write latch 132a and the first write command CMD_W1 provided from the memory controller 15 are the same, the write comparator 133 enables the write comparison signal CS_W. can do. When the write comparison signal CS_W is enabled, the variable decoder write signal RD_W may be enabled. When the variable decoder write signal RD_W is enabled, the data input enable signal DIN_EN may be enabled. When the data input enable signal DIN_EN is enabled, the data transfer path may be the second path P2 . When the data DATA transfer path is the second path P2 , the data DATA may be transferred from the memory controller 15 to the memory groups 300 .

For example, the command CMD provided from the memory controller 15 may be the third write command CMD_W3 . When the command CMD provided from the memory controller 15 is the third write command CMD_W3 , the write comparator 133 performs the third write command CMD_W3 programmed in the write latch 132a and the memory controller 15 . The third write command CMD_W3 provided from . When the third write command CMD_W3 programmed in the write latch 132a and the third write command CMD_W3 provided from the memory controller 15 are the same, the write comparator 133 enables the write comparison signal CS_W. can do. When the write comparison signal CS_W is enabled, the variable decoder write signal RD_W may be enabled. When the variable decoder write signal RD_W is enabled, the data input enable signal DIN_EN may be enabled. When the data input enable signal DIN_EN is enabled, the data transfer path may be the second path P2 . When the data DATA transfer path is the second path P2 , the data DATA may be transferred from the memory controller 15 to the memory groups 300 .

In an exemplary embodiment, when the memory controller 15 provides the input mode IN_M among the command setting mode CSMS and the input/output setting mode IOM, the memory controller 15 writes the write command CMD_W. The latch 132a can be programmed. The performance of the memory device 10 according to the present invention may be improved by programming the program command P_CMD in the variable input decoder 130 based on the command setting mode CSMS and the input/output setting mode IOM.

10 is a block diagram illustrating another example of a write command decoder included in the variable input decoder of FIG. 3 .

Referring to FIG. 10 , the write command decoder 131b may include a write latch 132b , a write comparator 133 , and a first logical product gate 134 . The first logical product gate 134 may be an AND gate. A write command CMD_W and an enable bit EN_B may be programmed in the write latch 132b. For example, the write command CMD_W among the program commands P_CMD may include a first write command CMD_W1 , a second write command CMD_W2 , and a third write command CMD_W3 . The memory controller 15 may provide a command setting mode (CSMS). After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM provided by the memory controller 15 is the input mode IN_M, the memory controller 15 provides the write command decoder 131b with the first write command CMD_W1 among the program commands P_CMD and The first enable bit EN_B1 may be programmed. Thereafter, the memory controller 15 may provide the command setting mode CSMS again. After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM provided by the memory controller 15 is the input mode IN_M, the memory controller 15 provides the write command decoder 131b with the second write command CMD_W2 among the program commands P_CMD and The second enable bit EN_B2 may be programmed. Thereafter, the memory controller 15 may provide the command setting mode CSMS again. After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM provided by the memory controller 15 is the input mode IN_M, the memory controller 15 provides the write command decoder 131b with a third write command CMD_W3 among the program commands P_CMD and The third enable bit EN_B3 may be programmed.

The write comparator 133 may compare the write command CMD_W programmed in the write latch 132b and the command CMD provided from the memory controller 15 to provide the write comparison signal CS_W. The write comparison signal CS_W and the enable bit EN_B may be provided to the first logical product gate 134 . For example, when the write comparison signal CS_W is enabled and the enable bit EN_B is '1', the variable decoder write signal RD_W may be enabled. Also, when the enable bit EN_B is '0', the variable decoder write signal RD_W may be disabled.

In an exemplary embodiment, the memory controller 15 may further program an enable bit EN_B for determining whether to activate the write command CMD_W in the write latch 132b. When the enable bit EN_B is in the first state and the write comparison signal CS_W is in the first state, the data input enable signal DIN_EN may be activated. For example, when the enable bit EN_B is in the first state, the value of the enable bit EN_B may be '1'. When the write comparison signal CS_W is in the first state, the write comparison signal CS_W may be activated.

In an exemplary embodiment, when the enable bit EN_B is in the second state, the data input enable signal DIN_EN may be inactivated. For example, when the enable bit EN_B is in the second state, the value of the enable bit EN_B may be '0'.

In an exemplary embodiment, when the write comparison signal CS_W is in the second state, the data input enable signal DIN_EN may be inactivated. For example, when the write comparison signal CS_W is in the second state, the write comparison signal CS_W may be inactivated.

11 is a diagram illustrating an example of a boosting interface included in the memory device of FIG. 3 .

3 and 11 , the memory device 10 includes memory groups 300 and a boosting interface 100 . The boosting interface 100 includes a buffer 110 , a fixed input decoder 150 , and a variable input decoder 130 . The memory groups 300 store data DATA. The boosting interface 100 transmits the data DATA by determining a transfer path of the data DATA according to the command CMD and the access address ADDR. For example, the command CMD and the access address ADDR may be provided from the memory controller 15 . The variable input decoder 130 programs the program command P_CMD among the commands CMD based on the command setting mode CSMS signal.

In an exemplary embodiment, the boosting interface 100 may further include an anti-fuse 140 for storing the program command P_CMD. The program command P_CMD may be stored in the antifuse 140 before the memory device 10 operates. For example, when the memory device 10 is powered on, the program command P_CMD stored in the antifuse 140 may be programmed in the variable input decoder 130 . The performance of the memory device 10 according to the present invention may be improved by programming the program command P_CMD in the variable input decoder 130 based on the command setting mode CSMS and the input/output setting mode IOM.

12 is a block diagram illustrating an example of a read command decoder included in the variable input decoder of FIG. 3 .

12 , the read command decoder 136a may include a read latch 137a and a read comparator 138 . A read command CMD_R may be programmed in the read latch 137a. For example, the read command CMD_R among the program commands P_CMD may include a first read command CMD_R1 , a second read command CMD_R2 , and a third read command CMD_R3 . The memory controller 15 may provide a command setting mode (CSMS). After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM provided by the memory controller 15 is the output mode OUT_M, the memory controller 15 transmits the first read command CMD_R1 among the program commands P_CMD to the read command decoder 136a. can be programmed. Thereafter, the memory controller 15 may provide the command setting mode CSMS again. After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM provided by the memory controller 15 is the output mode OUT_M, the memory controller 15 transmits the second read command CMD_R2 among the program commands P_CMD to the read command decoder 136a. can be programmed. Thereafter, the memory controller 15 may provide the command setting mode CSMS again. After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM provided by the memory controller 15 is the output mode OUT_M, the memory controller 15 transmits the third read command CMD_R3 among the program commands P_CMD to the read command decoder 136a. can be programmed.

The read comparator 138 may provide a read comparison signal CS_R by comparing the read command CMD_R programmed in the read latch 137a and the command CMD provided from the memory controller 15 . For example, the command CMD provided from the memory controller 15 may be the first read command CMD_R1 . When the command CMD provided from the memory controller 15 is the first read command CMD_R1 , the read comparator 138 includes the first read command CMD_R1 programmed in the read latch 137a and the memory controller 15 . The first read command CMD_R1 provided from . When the first read command CMD_R1 programmed in the read latch 137a and the first read command CMD_R1 provided from the memory controller 15 are the same, the read comparator 138 enables the read comparison signal CS_R. can do. When the read comparison signal CS_R is enabled, the variable decoder read signal RD_R may be enabled. When the variable decoder read signal RD_R is enabled, the data output enable signal DOUT_EN may be enabled. When the data output enable signal DOUT_EN is enabled, the data transfer path may be the first path P1 . When the data DATA transfer path is the first path P1 , the data DATA may be transferred from the memory groups 300 to the memory controller 15 .

For example, the command CMD provided from the memory controller 15 may be the second read command CMD_R2 . When the command CMD provided from the memory controller 15 is the second read command CMD_R2 , the read comparator 138 includes the second read command CMD_R2 programmed in the read latch 137a and the memory controller 15 . The second read command CMD_R2 provided from . When the second read command CMD_R2 programmed in the read latch 137a and the second read command CMD_R2 provided from the memory controller 15 are the same, the read comparator 138 enables the read comparison signal CS_R. can do. When the read comparison signal CS_R is enabled, the variable decoder read signal RD_R may be enabled. When the variable decoder read signal RD_R is enabled, the data output enable signal DOUT_EN may be enabled. When the data output enable signal DOUT_EN is enabled, the data transfer path may be the first path P1 . When the data DATA transfer path is the first path P1 , the data DATA may be transferred from the memory groups 300 to the memory controller 15 .

In an exemplary embodiment, when the memory controller 15 provides the output mode OUT_M among the command setting mode CSMS and the input/output setting mode IOM, the memory controller 15 reads the read command CMD_R. The latch 137a can be programmed. The performance of the memory device 10 according to the present invention may be improved by programming the program command P_CMD in the variable input decoder 130 based on the command setting mode CSMS and the input/output setting mode IOM.

13 is a block diagram illustrating another example of a read command decoder included in the variable input decoder of FIG. 3 , and FIG. 14 is a diagram for describing an operation of the buffer 110 included in the memory device of FIG. 3 .

13 and 14 , the read command decoder 136b may include a read latch 137b , a read comparator 138 , and a second logical product gate 139 . The second logical product gate 139 may be an AND gate. A read command CMD_R and an enable bit EN_B may be programmed in the read latch 137b. For example, the read command CMD_R among the program commands P_CMD may include a first read command CMD_R1 , a second read command CMD_R2 , and a third read command CMD_R3 . The memory controller 15 may provide a command setting mode (CSMS). After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM provided by the memory controller 15 is the output mode OUT_M, the memory controller 15 provides the read command decoder 136b with a first read command CMD_R1 and The first enable bit EN_B1 may be programmed. Thereafter, the memory controller 15 may provide the command setting mode CSMS again. After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM provided by the memory controller 15 is the output mode OUT_M, the memory controller 15 provides the read command decoder 136b with a second read command CMD_R2 and The second enable bit EN_B2 may be programmed. Thereafter, the memory controller 15 may provide the command setting mode CSMS again. After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM provided by the memory controller 15 is the output mode OUT_M, the memory controller 15 provides the read command decoder 136b with a third read command CMD_R3 and The third enable bit EN_B3 may be programmed.

The read comparator 138 may compare the read command CMD_R programmed in the read latch 137b and the command provided from the memory controller 15 to provide the read comparison signal CS_R. The read comparison signal CS_R and the enable bit EN_B may be provided to the second logical product gate 139 . For example, when the read comparison signal CS_R is enabled and the enable bit EN_B is '1', the variable decoder read signal RD_R may be enabled. Also, when the enable bit EN_B is '0', the variable decoder read signal RD_R may be disabled.

In an exemplary embodiment, the memory controller 15 may further program an enable bit EN_B for determining whether to activate the read command CMD_R in the write latch 132b. When the enable bit EN_B is in the first state and the read comparison signal CS_R is in the first state, the data output enable signal DOUT_EN may be activated. For example, when the enable bit EN_B is in the first state, the value of the enable bit EN_B may be '1'. When the read comparison signal CS_R is in the first state, the read comparison signal CS_R may be activated.

In an exemplary embodiment, when the enable bit EN_B is in the second state, the data output enable signal DOUT_EN may be inactivated. For example, when the enable bit EN_B is in the second state, the value of the enable bit EN_B may be '0'.

In an exemplary embodiment, when the read comparison signal CS_R is in the second state, the data output enable signal DOUT_EN may be inactivated. For example, when the read comparison signal CS_R is in the second state, the read comparison signal CS_R may be deactivated.

When the data output enable signal DOUT_EN is activated, the data DATA may be transferred from the memory groups 300 to the memory controller 15 through the first path P1 . Also, when the data input enable signal DIN_EN is activated, the data DATA may be transferred from the memory controller 15 to the memory groups 300 through the second path P2 .

15 is a diagram illustrating a memory system according to embodiments of the present invention.

Referring to FIG. 15 , the memory system 20 includes a memory controller 15 and a memory device 10 . The memory device 10 includes memory groups 300 and a boosting interface 100 . The boosting interface 100 includes a fixed input decoder 150 and a variable input decoder 130 . The memory controller 15 may provide a command CMD, an address, and data DATA. The memory groups 300 store data DATA. The memory groups 300 may include a three-dimensional memory cell array. For example, the memory groups 300 may include a first memory group 310 and a second memory group 330 . The first memory group 310 may include a plurality of memory cell arrays, and the second memory group 330 may include a plurality of memory cell arrays. The plurality of memory cell arrays may include flash memory cells. The memory groups 300 include a three-dimensional memory cell array.

The fixed input decoder 150 may include a fixed command F_CMD among the commands CMD as hardware. For example, the fixed command F_CMD may include first to third commands CMD1 , CMD2 , and CMD3 . The first command CMD1 may be embedded in the fixed input decoder 150 as hardware. Since the first command CMD1 is embedded in the input decoder as hardware, the first command CMD1 included in the fixed input decoder 150 cannot be reprogrammed. Also, the second command CMD2 may be embedded in the fixed input decoder 150 as hardware. Since the second command CMD2 is embedded in the input decoder as hardware, the second command CMD2 included in the fixed input decoder 150 cannot be reprogrammed. Also, the third command CMD3 may be embedded in the fixed input decoder 150 as hardware. Since the third command CMD3 is embedded in the input decoder as hardware, the third command CMD3 included in the fixed input decoder 150 cannot be reprogrammed.

The variable input decoder 130 programs the program command P_CMD among the commands CMD based on the command setting mode CSMS and the input/output setting mode IOM. For example, the memory controller 15 may provide a command setting mode (CSMS) and an input/output setting mode (IOM). When the memory controller 15 provides the command setting mode CSMS and the input/output setting mode IOM, the memory controller 15 may program the program command P_CMD in the variable input decoder 130 .

The variable input decoder 130 may include a write command decoder 131 and a read command decoder 136 . A write command CMD_W among the program commands P_CMD may be programmed in the write command decoder 131 based on the command setting mode CSMS and the input/output setting mode IOM. For example, the memory controller 15 may provide a command setting mode (CSMS). After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM is the input mode IN_M, the write command CMD_W among the program commands P_CMD may be programmed in the write command decoder 131 .

The program command P_CMD may be a command CMD programmed in the variable input decoder 130 among commands CMD provided by the memory controller 15 . The write command CMD_W may be used for a write operation of the memory device 10 . For example, the write command CMD_W among the program commands P_CMD may include a first write command CMD_W1 , a second write command CMD_W2 , and a third write command CMD_W3 . The memory controller 15 may provide a command setting mode (CSMS). After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM provided by the memory controller 15 is the input mode IN_M, the memory controller 15 sends the first write command CMD_W1 among the program commands P_CMD to the write command decoder 131 . can be programmed. Thereafter, the memory controller 15 may provide the command setting mode CSMS again. After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM provided by the memory controller 15 is the input mode IN_M, the memory controller 15 transmits the second write command CMD_W2 among the program commands P_CMD to the write command decoder 131 . can be programmed. Thereafter, the memory controller 15 may provide the command setting mode CSMS again. After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM provided by the memory controller 15 is the input mode IN_M, the memory controller 15 sends the third write command CMD_W3 among the program commands P_CMD to the write command decoder 131 . can be programmed.

While the memory device 10 is being used, it may be required to add a new command CMD. When the addition of a new command CMD is required while the memory device 10 is being used, the memory controller 15 varies the program command P_CMD based on the command setting mode CSMS and the input/output setting mode IOM. It can be programmed in the input decoder 130 .

The read command CMD_R among the program commands P_CMD may be programmed in the read command decoder 136 based on the command setting mode CSMS and the input/output setting mode IOM. For example, the memory controller 15 may provide a command setting mode (CSMS). After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM is the output mode OUT_M, the read command CMD_R among the program commands P_CMD may be programmed in the read command decoder 136 .

The program command P_CMD may be a command CMD programmed in the variable input decoder 130 among commands CMD provided by the memory controller 15 . The read command CMD_R may be used for a read operation of the memory device 10 . For example, the read command CMD_R among the program commands P_CMD may include a first read command CMD_R1 , a second read command CMD_R2 , and a third read command CMD_R3 . The memory controller 15 may provide a command setting mode (CSMS). After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM provided by the memory controller 15 is the output mode OUT_M, the memory controller 15 transmits the first read command CMD_R1 among the program commands P_CMD to the read command decoder 136 . can be programmed. Thereafter, the memory controller 15 may provide the command setting mode CSMS again. After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM provided by the memory controller 15 is the output mode OUT_M, the memory controller 15 transmits the second read command CMD_R2 among the program commands P_CMD to the read command decoder 136 . can be programmed. Thereafter, the memory controller 15 may provide the command setting mode CSMS again. After the memory controller 15 provides the command setting mode CSMS, the memory controller 15 may provide the input/output setting mode IOM. When the input/output setting mode IOM provided by the memory controller 15 is the output mode OUT_M, the memory controller 15 transmits the third read command CMD_R3 among the program commands P_CMD to the read command decoder 136 . can be programmed.

While the memory device 10 is being used, it may be required to add a new command CMD. When the addition of a new command CMD is required while the memory device 10 is being used, the memory controller 15 varies the program command P_CMD based on the command setting mode CSMS and the input/output setting mode IOM. It can be programmed in the input decoder 130 . The performance of the memory device 10 according to the present invention may be improved by programming the program command P_CMD in the variable input decoder 130 based on the command setting mode CSMS and the input/output setting mode IOM.

16 is a block diagram illustrating a memory device included in the memory system of FIG. 15 .

Referring to FIG. 16 , the memory device 100 may be a flash memory device, and may include a memory cell array 110 , a page buffer unit 120 , a row decoder 130 , a voltage generator 140 , and a control circuit 150 . includes

The memory cell array 110 includes a plurality of memory cells respectively connected to a plurality of word lines and a plurality of bit lines. The plurality of memory cells may be NAND or NOR flash memory cells, respectively, and may be arranged in a two-dimensional array structure or a three-dimensional vertical array structure.

The plurality of memory cells may be single-level memory cells (SLCs) each storing one data bit or multi-level memory cells (MLCs) storing a plurality of data bits. . In the case of a multi-level memory cell, various programming methods such as a shadow program method, a reprogram method, or an on-chip buffered program method may be applied as a programming method in the write mode.

The page buffer unit 120 is connected to the plurality of bit lines and stores write data to be programmed in the memory cell array 110 or read data sensed from the memory cell array 110 . That is, the page buffer unit 120 may operate as a write driver or a sense amplifier according to an operation mode of the flash memory device 100 . For example, the page buffer unit 120 may operate as a write driver in the write mode and as a sense amplifier in the read mode.

The row decoder 130 may be connected to the plurality of word lines and select at least one of the plurality of word lines in response to a row address. The voltage generator 140 may generate word line voltages such as a program voltage, a pass voltage, a verify voltage, an erase voltage, and a read voltage under the control of the control circuit 150 . The control circuit 150 may control the page buffer unit 120 , the row decoder 130 , and the voltage generator 140 to perform data storage, erasing, and reading operations on the memory cell array 110 .

17 is a diagram illustrating an example of a memory cell array included in the memory device of FIG. 16 , and FIG. 18 is a diagram illustrating another example of a memory cell array included in the memory device of FIG. 16 .

17 is a circuit diagram illustrating an example of a memory cell array included in a NAND flash memory device, and FIG. 18 is a circuit diagram illustrating an example of a memory cell array included in a vertical flash memory device.

Referring to FIG. 17 , the memory cell array 110b may include string select transistors SST, ground select transistors GST, and memory cells MC2 . The string select transistors SST may be connected to the bit lines BL(1), ..., BL(m), and the ground select transistors GST may be connected to the common source line CSL. The memory cells MC2 arranged in the same column may be arranged in series between one of the bit lines BL(1), ..., BL(m) and the common source line CSL, and arranged in the same row. The memory cells MC2 may be commonly connected to one of the word lines WL(1), WL(2), WL(3), ..., WL(n-1), WL(n). . That is, the memory cells MC2 may be connected in series between the string select transistors SST and the ground select transistor GST, and between the string select line SSL and the ground select line GSL, there are 16 and 32 memory cells. A plurality of or 64 word lines may be arranged.

The string select transistors SST are connected to the string select line SSL to be controlled according to a level of a voltage applied from the string select line SSL, and the ground select transistors GST are connected to the ground select line GSL. connected, and may be controlled according to a level of a voltage applied from the ground selection line GSL. The memory cells MC2 may be controlled according to the level of a voltage applied to the word lines WL(1), ..., WL(n).

The NAND-type flash memory device including the memory cell array 110b may perform a write operation and a read operation in units of pages 111b, and may perform an erase operation in units of blocks 112b. Meanwhile, according to an embodiment, each of the page buffers may have one even-numbered bit line and one odd-numbered bit line connected thereto. In this case, the even-numbered bit lines form an even-numbered page, the odd-numbered bit lines form an odd-numbered page, and a write operation on the memory cells MC2 may be sequentially performed alternately between the even-numbered pages and the odd-numbered pages.

Referring to FIG. 18 , the memory cell array 110c may include a plurality of strings 113c having a vertical structure. A plurality of strings 113c may be formed along the second direction to form a string column, and the plurality of string columns may be formed along the third direction to form a string array. The plurality of strings 113c are ground select transistors GSTV that are disposed in series along the first direction between the bit lines BL(1), ..., BL(m) and the common source line CSL. , memory cells MC3 and string select transistors SSTV may be included, respectively.

The ground select transistors GSTV are respectively connected to the ground select lines GSL11, GSL12, ..., GSLi1, GSLi2, and the string select transistors SSTV are the string select lines SSL11, SSL12, ..., SSLi1 , SSLi2) can be connected respectively. The memory cells MC3 arranged on the same layer may be commonly connected to one of the word lines WL(1), WL(2), ..., WL(n-1), WL(n). The ground selection lines GSL11, ..., GSLi2 and the string selection lines SSL11, ..., SSLi2 may extend in the second direction and may be formed in plurality along the third direction. The word lines WL(1), ..., WL(n) may extend in the second direction and may be formed in plurality in the first direction and the third direction. The bit lines BL(1), ..., BL(m) may extend in the third direction and may be formed in plurality along the second direction. The memory cells MC3 may be controlled according to the level of a voltage applied to the word lines WL(1), ..., WL(n).

Since the vertical flash memory device including the memory cell array 110c includes NAND flash memory cells, write and read operations are performed in units of pages and erase operations are performed in units of blocks, similar to the NAND flash memory device. .

According to an embodiment, two string select transistors included in one string 113c are connected to one string select line, and two ground select transistors included in one string are connected to one ground select line. may be Also, according to an embodiment, one string may be implemented including one string select transistor and one ground select transistor. In one embodiment, the memory cell array 110C may be a three-dimensional memory cell array. In an embodiment of the present invention, the 3D memory cell array may be included in the memory device 10 . The following patent documents describe configurations for three-dimensional memory arrays: U.S. Pat. Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and US Pat. Pub. No. 2011/0233648.

19 is a diagram illustrating a computing system according to embodiments of the present invention.

Referring to FIG. 19 , the computing system 30 includes a host 17 , a memory controller 15 , memory groups 300 , and a boosting interface 100 . The boosting interface 100 includes a variable input decoder 130 . The host 17 provides a host signal HS. The memory controller 15 provides the command CMD and the access address ADDR based on the host signal HS. The memory groups 300 store data DATA. The boosting interface 100 transmits the data DATA by determining a transfer path of the data DATA according to the command CMD and the access address ADDR. The variable input decoder 130 programs the program command P_CMD among the commands CMD based on the command setting mode CSMS and the input/output setting mode IOM. The performance of the memory device 10 according to the present invention may be improved by programming the program command P_CMD in the variable input decoder 130 based on the command setting mode CSMS and the input/output setting mode IOM.

20 is a block diagram illustrating an example of applying a memory device according to embodiments of the present invention to a mobile system.

Referring to FIG. 20 , the mobile system 700 may include a processor 710 , a memory device 720 , a storage device 730 , an image sensor 760 , a display device 740 , and a power supply 750 . have. The mobile system 700 may further include ports capable of communicating with a video card, a sound card, a memory card, a USB device, or the like, or communicating with other electronic devices.

Processor 710 may perform certain calculations or tasks. According to an embodiment, the processor 710 may be a micro-processor or a central processing unit (CPU). The processor 710 may communicate with the memory device 720 , the storage device 730 , and the display device 740 through an address bus, a control bus, and a data bus. have. Depending on the embodiment, the processor 710 may also be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus. The memory device 720 may store data necessary for the operation of the mobile system 700 . For example, the memory device 720 may include DRAM, mobile DRAM, SRAM, PRAM, FRAM, RRAM, and/or MRAM. can be The storage device 730 may include a solid state drive, a hard disk drive, a CD-ROM, and the like. The mobile system 700 may further include input means such as a keyboard, keypad, mouse, and the like, and output means, such as a printer. The power supply 750 may supply an operating voltage necessary for the operation of the mobile system 700 .

The image sensor 760 may be connected to the processor 710 through the buses or other communication links to perform communication. The image sensor 900 may be integrated together with the processor 710 in one chip, or may be integrated in different chips, respectively.

Components of the mobile system 700 may be implemented in various types of packages. For example, at least some components of the mobile system 700 may include Package on Package (PoP), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), and Plastic Dual In-Line Package. (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board(COB), Ceramic Dual In-Line Package(CERDIP), Plastic Metric Quad Flat Pack(MQFP), Thin Quad Flatpack(TQFP), Small Outline( SOIC), Shrink Small Outline Package(SSOP), Thin Small Outline(TSOP), Thin Quad Flatpack(TQFP), System In Package(SIP), Multi Chip Package(MCP), Wafer-level Fabricated Package(WFP), Wafer- It may be mounted using packages such as Level Processed Stack Package (WSP).

Meanwhile, the mobile system 700 should be interpreted as any mobile system using the memory system according to embodiments of the present invention. For example, the mobile system 700 may include a digital camera, a mobile phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a smart phone, or the like.

21 is a block diagram illustrating an example in which a memory device according to embodiments of the present invention is applied to a computing system.

Referring to FIG. 21 , the computing system 800 includes a processor 810 , an input/output hub 820 , an input/output controller hub 830 , at least one memory module 840 , and a graphics card 850 . According to an embodiment, the computing system 800 includes a personal computer (PC), a server computer, a workstation, a laptop, a mobile phone, and a smart phone. , personal digital assistant (PDA), portable multimedia player (PMP), digital camera (Digital Camera), digital TV (Digital Television), set-top box (Set-Top Box), music player (Music Player), a portable game console (portable game console), may be any computing system, such as a navigation (Navigation) system.

The processor 810 may execute various computing functions, such as specific calculations or tasks. For example, the processor 810 may be a microprocessor or a central processing unit (CPU). According to an embodiment, the processor 810 may include one processor core (Single Core) or a plurality of processor cores (Multi-Core). For example, the processor 1510 may include a multi-core such as a dual-core, a quad-core, or a hexa-core (Hexa-Core). Also, although the computing system 800 including one processor 810 is illustrated in FIG. 18 , the computing system 800 may include a plurality of processors according to an embodiment. Also, according to an embodiment, the processor 810 may further include a cache memory located inside or outside.

The processor 810 may include a memory controller 811 that controls the operation of the memory module 840 . The memory controller 811 included in the processor 810 may be referred to as an integrated memory controller (IMC). The memory interface between the memory controller 811 and the memory module 840 may be implemented as one channel including a plurality of signal lines or as a plurality of channels. Also, one or more memory modules 840 may be connected to each channel. According to an embodiment, the memory controller 811 may be located in the input/output hub 820 . The input/output hub 820 including the memory controller 811 may be referred to as a memory controller hub (MCH).

The memory module 840 may include a plurality of memory devices for storing data provided from the memory controller 811 and a buffer chip for overall managing operations of the plurality of memory devices. Each of the plurality of memory devices may store data processed by the processor 810 or may operate as a working memory. For example, each of the memory devices may be a dynamic random access memory such as DDR SDRAM, LPDDR SDRAM, GDDR SDRAM, RDRAM, or any volatile memory device requiring a refresh operation. The buffer chip included in the memory module 840 may be configured like the buffer chip 300 of FIG. 3 , and may generally manage operations of a plurality of memory devices including the memory manager 310 of FIG. 4 .

The input/output hub 820 may manage data transmission between devices such as the graphic card 850 and the processor 810 . The input/output hub 820 may be connected to the processor 810 through various interfaces. For example, the input/output hub 820 and the processor 810 may include a Front Side Bus (FSB), a System Bus, a HyperTransport, and a Lightning Data Transport; LDT), QuickPath Interconnect (QPI), and Common System Interface (CSI) may be connected through various standard interfaces.

The input/output hub 820 may provide various interfaces with devices. For example, the input/output hub 820 may include an Accelerated Graphics Port (AGP) interface, a Peripheral Component Interface-Express (PCIe), a Communications Streaming Architecture (CSA) interface, and the like. can provide

The graphic card 850 may be connected to the input/output hub 820 through AGP or PCIe. The graphic card 850 may control a display device (not shown) for displaying an image. The graphic card 850 may include an internal processor for processing image data and an internal semiconductor memory device. According to an embodiment, the input/output hub 820 may include a graphics device inside the input/output hub 820 together with the graphics card 850 located outside the input/output hub 820 or instead of the graphics card 850 . can The graphic device included in the input/output hub 820 may be called integrated graphics. Also, the input/output hub 820 including the memory controller and the graphic device may be referred to as a graphics and memory controller hub (GMCH).

The input/output controller hub 830 may perform data buffering and interface arbitration so that various system interfaces operate efficiently. The input/output controller hub 830 may be connected to the input/output hub 820 through an internal bus. For example, the input/output hub 820 and the input/output controller hub 830 may be connected through a direct media interface (DMI), a hub interface, an enterprise southbridge interface (ESI), PCIe, or the like. .

The input/output controller hub 830 may provide various interfaces with peripheral devices. For example, the input/output controller hub 830 may include a Universal Serial Bus (USB) port, a Serial Advanced Technology Attachment (SATA) port, a General Purpose Input/Output (GPIO), and a low pin count (Low Pin Count; LPC) bus, Serial Peripheral Interface (SPI), PCI, PCIe, etc. can be provided.

According to an embodiment, the processor 810 , the input/output hub 820 , and the input/output controller hub 830 may be implemented as separate chipsets or integrated circuits, respectively, or the processor 810 , the input/output hub 820 , or the input/output controller hub Two or more components of 830 may be implemented as one chipset.

The memory device according to the present invention can improve performance by programming a program command in the variable input decoder based on the command setting mode and the input/output setting mode, and thus can be applied to a memory system.

Although the present invention has been described with reference to preferred embodiments, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the present invention as set forth in the following claims. you will understand that you can

Claims (10)

memory groups for storing data; and
and a boosting interface for transferring the data by determining a transfer path of the data according to a command and an access address,
The boosting interface is
a variable input decoder configured to program a program command among the commands based on a command setting mode and an input/output setting mode;
a buffer for transferring the data between a memory controller and the memory groups based on a data output enable signal and a data input enable signal; and
a fixed input decoder that embeds a fixed command among the commands in hardware;
The variable input decoder,
a write command decoder configured to program a write command among the program commands when the input/output setting mode is an input mode; and
and a read command decoder configured to program a read command among the program commands when the input/output setting mode is an output mode. delete delete The method of claim 1, wherein the write command decoder comprises:
a write latch into which the write command is programmed; and
and a write comparator configured to provide a write comparison signal by comparing the write command programmed in the write latch and the command provided from the memory controller. 5. The method of claim 4,
when the memory controller provides the input mode among the command setting mode and the input/output setting mode, the memory controller programs the write command into the write latch;
and the memory controller further programs an enable bit for determining whether to activate the write command in the write latch. 6. The method of claim 5,
When the enable bit is in the first state and the write comparison signal is in the first state, the data input enable signal is activated;
When the enable bit is in the second state, the data input enable signal is deactivated,
The memory device of claim 1 , wherein the data input enable signal is deactivated when the write comparison signal is in a second state. According to claim 1, wherein the boosting interface,
Further comprising an anti-fuse for storing the program command,
When the memory device is powered on, the program command stored in the antifuse is programmed in the variable input decoder. The method of claim 1, wherein the read command decoder comprises:
a read latch in which the read command is programmed; and
and a read comparator configured to provide a read comparison signal by comparing the read command programmed in the read latch and the command provided from the memory controller. 9. The method of claim 8,
when the memory controller provides the output mode among the command setting mode and the input/output setting mode, the memory controller programs the read command into the read latch;
the memory controller further programs an enable bit for determining whether to activate the read command in the read latch;
When the enable bit is in the first state and the read comparison signal is in the first state, the data output enable signal is activated;
When the enable bit is in the second state, the data output enable signal is deactivated,
The memory device of claim 1 , wherein the data output enable signal is deactivated when the read comparison signal is in a second state. a memory controller that provides commands and access addresses;
memory groups for storing data; and
and a boosting interface for transferring the data by determining a transfer path of the data according to the command and the access address,
The boosting interface is
a variable input decoder configured to program a program command among the commands based on a command setting mode and an input/output setting mode;
a buffer transferring the data between the memory controller and the memory groups based on a data output enable signal and a data input enable signal; and
a fixed input decoder that embeds a fixed command among the commands in hardware;
The memory groups include a three-dimensional memory cell array,
The variable input decoder,
a write command decoder configured to program a write command among the program commands when the input/output setting mode is an input mode; and
and a read command decoder configured to program a read command among the program commands when the input/output setting mode is an output mode.

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