KR102302366B1 - Apparatus and method for channel encoding/decoding in communication or broadcasting system - Google Patents

Abstract

The present disclosure relates to a 5G or pre-5G communication system for supporting a higher data rate after a 4G communication system such as LTE. The present invention provides a method for encoding a channel in a communication or broadcasting system, the method comprising: checking an input bit size; The process of determining the size (Z) of the block; determining an LDPC sequence to perform LDPC encoding; LDPC encoding based on the LDPC sequence and block size; It is characterized in that it includes.

Description

Channel encoding/decoding method and apparatus in a communication or broadcasting system

The present invention relates to a method and apparatus for channel encoding/decoding in a communication or broadcasting system.

Efforts are being made to develop an improved 5G communication system or pre-5G communication system in order to meet the increasing demand for wireless data traffic after the commercialization of the 4G communication system. For this reason, the 5G communication system or the pre-5G communication system is called a system after the 4G network (Beyond 4G Network) communication system or after the LTE system (Post LTE).

In order to achieve a high data rate, the 5G communication system is being considered for implementation in a very high frequency (mmWave) band (eg, such as a 60 gigabyte (60 GHz) band). In order to mitigate the path loss of radio waves and increase the propagation distance of radio waves in the ultra-high frequency band, in the 5G communication system, beamforming, massive MIMO, and Full Dimensional MIMO (FD-MIMO) are used. ), array antenna, analog beam-forming, and large scale antenna technologies are being discussed.

In addition, for network improvement of the system, in the 5G communication system, an evolved small cell, an advanced small cell, a cloud radio access network (cloud RAN), and an ultra-dense network (ultra-dense network) , Device to Device communication (D2D), wireless backhaul, moving network, cooperative communication, Coordinated Multi-Points (CoMP), and interference cancellation Technology development is underway.

In addition, in the 5G system, FQAM (Hybrid FSK and QAM Modulation) and SWSC (Sliding Window Superposition Coding), which are advanced coding modulation (ACM) methods, and FBMC (Filter Bank Multi Carrier), which are advanced access technologies, NOMA (non-orthogonal multiple access), and sparse code multiple access (SCMA) are being developed.

In a communication or broadcast system, link performance may be significantly degraded by various kinds of noise of a channel, a fading phenomenon, and inter-symbol interference (ISI). Therefore, in order to implement high-speed digital communication or broadcasting systems requiring high data throughput and reliability, such as next-generation mobile communication, digital broadcasting, and portable Internet, it is required to develop a technology for overcoming noise, fading, and inter-symbol interference. As part of research to overcome noise, etc., recently, research on error-correcting codes has been actively conducted as a method to increase communication reliability by efficiently restoring information distortion.

The present invention provides an LDPC encoding/decoding method and apparatus capable of supporting various input lengths and code rates.

The present invention provides a design method, encoding/decoding method, and apparatus for an LDPC code that has a short information word length of about 100 bits and is suitable for a case where a code rate is determined.

The present invention proposes a method for designing an LDPC code that can support various lengths and code rates by considering a lifting method and a trapping set characteristic at the same time.

The present invention proposes a method for designing a dedicated LDPC code suitable for a case where the number of information bits is small and a code rate is fixed.

The present invention can support the LDPC code for a variable length and a variable rate.

1 is a structural diagram of a systematic LDPC codeword.
2 is a diagram illustrating a graph representation method of an LDPC code.
3A and 3B are exemplary diagrams for explaining cycle characteristics of a QC-LDPC code.
4 is a block diagram of a transmitting apparatus according to an embodiment of the present invention.
5 is a block diagram of a receiving device according to an embodiment of the present invention.
6A and 6B are message structure diagrams illustrating message passing operations in arbitrary check nodes and variable nodes for LDPC decoding.
7 is a block diagram illustrating a detailed configuration of an LDPC encoder according to an embodiment of the present invention.
8 is a block diagram illustrating a configuration of a decoding apparatus according to an embodiment of the present invention.
9 is a structural diagram of an LDPC decoder according to another embodiment of the present invention.
10 is a structural diagram of a transport block according to another embodiment of the present invention.
11, 11A, and 11B are exemplary diagrams of an LDPC code exponent matrix according to an embodiment of the present invention.
12, 12A, and 12B are other exemplary diagrams of an LDPC code exponent matrix according to an embodiment of the present invention.
13, 13A, and 13B are other exemplary diagrams of an LDPC code exponent matrix according to an embodiment of the present invention.
14, 14A, and 14B are other exemplary diagrams of an LDPC code exponent matrix according to an embodiment of the present invention.
15, 15A, and 15B are other exemplary diagrams of an LDPC code exponent matrix according to an embodiment of the present invention.
16, 16A, and 16B are other exemplary diagrams of a basic matrix of an LDPC code according to an embodiment of the present invention.
17, 17A, and 17B are other exemplary diagrams of an LDPC code exponent matrix according to an embodiment of the present invention.
18, 18A, and 18B are other exemplary diagrams of an LDPC code exponent matrix according to an embodiment of the present invention.
19, 19A, and 19B are other exemplary diagrams of an LDPC code exponent matrix according to an embodiment of the present invention.
20, 20A, and 20B are other exemplary diagrams of an LDPC code exponent matrix according to an embodiment of the present invention.
21, 21A, and 21B are other exemplary diagrams of an LDPC code exponent matrix according to an embodiment of the present invention.
22, 22A, and 22B are other exemplary diagrams of an LDPC code exponent matrix according to an embodiment of the present invention.
23, 23A, and 23B are other exemplary diagrams of an LDPC code exponent matrix according to an embodiment of the present invention.
24, 24A and 24B are other exemplary diagrams of an LDPC code exponent matrix according to an embodiment of the present invention.
25, 25a, 25b, 25c, 25d, 25e, 25f, 25g, 25h and 25i are other exemplary diagrams of an LDPC code base matrix according to an embodiment of the present invention.
26, 26a, 26b, 26c, 26d, 26e, 26f, 26g, 26h and 26i are other exemplary diagrams of an LDPC code exponent matrix according to an embodiment of the present invention.
27 is another exemplary diagram of an LDPC code exponent matrix according to an embodiment of the present invention.
28 is another exemplary diagram of an LDPC code exponent matrix according to an embodiment of the present invention.
29 is another exemplary diagram of an LDPC code exponent matrix according to an embodiment of the present invention.
30 is another exemplary diagram of an LDPC code exponent matrix according to an embodiment of the present invention.
31 is another exemplary diagram of an LDPC code exponent matrix according to an embodiment of the present invention.
32 is another exemplary diagram of an LDPC code exponent matrix according to an embodiment of the present invention.
33 is another exemplary diagram of an LDPC code exponent matrix according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. And, in describing the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. In addition, the terms described below are terms defined in consideration of functions in the present invention, which may vary according to intentions or customs of users and operators. Therefore, the definition should be made based on the content throughout this specification.

The main gist of the present invention is applicable to other systems having a similar technical background with slight modifications within a range that does not significantly depart from the scope of the present invention, which is determined by a person skilled in the art of the present invention. It will be possible.

Advantages and features of the present invention, and a method for achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the art to which the present invention pertains. It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.

The Low Density Parity Check (LDPC) code, first introduced by Gallager in the 1960s, has been forgotten for a long time due to its complexity that is difficult to implement at the technical level at the time. However, as the turbo code proposed by Berrou, Glavieux, and Thitimajshima in 1993 showed a performance close to Shannon's channel capacity, many interpretations of the performance and characteristics of the turbo code were made and iterative decoding ( A lot of research has been done on iterative decoding) and graph-based channel encoding. With this as an opportunity, as the LDPC code was re-researched in the late 1990s, the LDPC code was decoded by applying iterative decoding based on the sum-product algorithm on the Tanner graph corresponding to the LDPC code. It was also found to have performance close to that of Shannon's channel capacity.

The LDPC code is generally defined as a parity-check matrix and may be expressed using a bipartite graph commonly referred to as a Tanner graph.

1 is a diagram illustrating a structural diagram of a systematic LDPC codeword.

(102)를 LDPC 부호화하면, 부호어

(100)가 생성된다. 즉, 정보어 및 부호어는 다수의 비트로 구성되어 있는 비트열이며, 정보어 비트 및 부호어 비트는 정보어 및 부호어를 구성하는 각각의 비트를 의미한다. 통상적으로 부호어가

와 같이 정보어를 포함하고 있을 경우 시스테메틱(systemetic) 부호라 한다. 여기에서,

는 패리티 비트(104)이고, 패리티 비트의 개수 N_parity는 N_parity=N_ldpc - K_ldpc 로 나타낼 수 있다.1, the LDPC code receives _{an information word 102 composed of K ldpc} bits or symbols and performs LDPC encoding to generate a codeword 100 composed of _{N ldpc bits or symbols.} do. For convenience of description, it is assumed that the codeword 100 composed of _{N ldpc} bits is generated by receiving the information word 102 including _{K ldpc bits.} That is, information words that are _{K ldpc input bits}

If (102) is LDPC encoded, the codeword

(100) is created. That is, the information word and the code word are bit strings composed of a plurality of bits, and the information word bit and the code word bit mean each bit constituting the information word and the code word. Usually the codeword is

When an information word is included, it is called a systemetic code. From here,

Is a parity bit 104, the number N _parity of the parity bits is N = N _{parity ldpc} - can be represented by K _ldpc.

The LDPC code is a type of linear block code and includes a process of determining a codeword satisfying the condition shown in Equation 1 below.

[Equation 1]

이다. From here,

am.

In Equation 1, H denotes a parity check matrix, C denotes a codeword, c _i denotes the i-th bit of the codeword, and N _ldpc denotes an LDPC codeword length. Here, h _i means the i-th column of the parity check matrix (H).

The parity check matrix H is composed of _{N ldpc} columns equal to the number of bits of the LDPC codeword. Since Equation 1 means that the sum of the product of the i-th column (h _i ) and the i-th codeword bit c _i of the parity check matrix becomes '0', the i-th column (h _i ) is the i-th codeword bit c means that it is related to _{i .}

A graph representation method of the LDPC code will be described with reference to FIG. 2 .

_{FIG. 2 is a diagram illustrating an example of a parity check matrix H 1} of an LDPC code having 4 rows and 8 columns, and a Tanner graph thereof. Referring to FIG. 2 , since the parity check matrix H ₁ has 8 columns, a codeword having a length of 8 is generated, a code generated through H1 means an LDPC code, and each column is 8 coded corresponds to the bit.

Referring to FIG. 2 , the Tanner graph of the LDPC code that is encoded and decoded based on the _{parity check matrix H 1 includes 8 variable nodes, that is, x 1} (202), x ₂ (204), x ₃ ( 206), x ₄ (208), x ₅ (210), x ₆ (212), x ₇ (214), x ₈ (216) and four check nodes (218, 220, 222, 224) is composed of Here, the i-th column and the j-th row of the parity check matrix H _{1 of the LDPC code correspond to the variable node x i} and the j-th check node, respectively. In addition, the value of 1 at the point where the j-th column and the j-th row of the parity check matrix H _{1 of the LDPC code intersect, that is, the meaning of the non-zero value, is the variable node x i} and the j-th check on the Tanner graph as shown in FIG. 2 . It means that there is an edge connecting the nodes.

In the Tanner graph of the LDPC code, the degree of the variable node and the check node means the number of line segments connected to each node, which is 0 in the column or row corresponding to the node in the parity check matrix of the LDPC code equal to the number of non-entries. For example, in FIG. 2 the variable nodes x ₁ (202), x ₂ (204), x ₃ (206), x ₄ (208), x ₅ (210), x ₆ (212), x ₇ (214) ), x ₈ (216) has the order of 4, 3, 3, 3, 2, 2, 2, 2, respectively, and the order of the check nodes 218, 220, 222, 224 is 6 in order, respectively. , 5, 5, 5. _{In addition, the number of non-zero elements in each column of the parity check matrix H 1} of FIG. 2 corresponding to the variable node of FIG. 2 is equal to the above-described orders 4, 3, 3, 3, 2, 2, 2, 2 _{The number of non-zero elements in each row of the parity check matrix H 1} of FIG. 2 corresponding to the check nodes of FIG. 2 coincides with the above-described orders 6, 5, 5, and 5 in order .

The LDPC code may be decoded using an iterative decoding algorithm based on a sum-product algorithm on the bipartite graph listed in FIG. 2 . Here, the sum and product algorithm is a kind of message passing algorithm. The message passing algorithm exchanges messages through edges on a bipartite graph and calculates an output message from messages input to a variable node or a check node. Represents the update algorithm.

Here, the value of the i-th encoding bit may be determined based on the message of the i-th variable node. The value of the i-th encoding bit can be both a hard decision and a soft decision. _{Therefore, the performance of c i} , which is the i-th bit of the LDPC codeword, corresponds to the performance of the i-th variable node of the Tanner graph, which may be determined according to the position and number of 1's in the i-th column of the parity check matrix. In other words, _{the performance of the N ldpc} codeword bits of the codeword may be affected by the position and number of 1s in the parity check matrix, which means that the performance of the LDPC code is greatly affected by the parity check matrix. do. Therefore, in order to design an LDPC code with excellent performance, a method for designing a good parity check matrix is required.

A parity check matrix used in communication and broadcast systems is a quasi-cyclic LDPC code (or QC-LDPC code, hereinafter QC-LDPC code) using a parity check matrix of a quasi-cyclic type for ease of implementation. is used a lot

The QC-LDPC code is characterized by having a parity check matrix composed of a zero matrix having the form of a small square matrix or circulant permutation matrices. In this case, the permutation matrix means a matrix in which all elements of the square matrix are 0 or 1, and each row or column includes only one 1. In addition, the cyclic permutation matrix means a matrix in which each element of the identity matrix is cyclically moved to the right.

Hereinafter, the QC-LDPC code will be specifically described.

크기의 순환 순열 행렬

을 정의한다. 여기서

는 행렬 상기 행렬 P에서의 i번째 행(row), j번째 열(column)의 원소(entry)를 의미한다.(0 ≤i, j < L) First, as in Equation 2

size cyclic permutation matrix

to define here

denotes an entry of the i-th row and j-th column in the matrix P. (0 ≤ i, j < L)

[Equation 2]

(0 ≤ i < L)는

크기의 항등 행렬(identity matrix)의 각 원소들을 i 번 만큼 오른쪽 방향으로 순환 이동(circular shift) 시킨 형태의 순환 순열 행렬임을 알 수 있다. For the permutation matrix P defined as above,

(0 ≤ i < L) is

It can be seen that it is a circular permutation matrix in which each element of an identity matrix of size is circularly shifted to the right by i times.

The parity check matrix H of the simplest QC-LDPC code can be expressed in the form of Equation 3 below.

[Equation 3]

을

크기의 0-행렬이라 정의할 경우, 상기 수학식 3에서 순환 순열 행렬 또는 0-행렬의 각 지수

는 {-1, 0, 1, 2, ..., L-1} 값 중에 하나를 가지게 된다. 또한 상기 수학식 3의 패리티 검사 행렬 H는 열 블록(column block)이 n개, 행 블록이 m개이므로,

크기를 가지게 됨을 알 수 있다. if

second

When it is defined as a 0-matrix of size, each exponent of the cyclic permutation matrix or 0-matrix in Equation 3 above

has one of {-1, 0, 1, 2, ..., L-1} values. Also, since the parity check matrix H of Equation 3 has n column blocks and m row blocks,

It can be seen that it has a size.

If the parity check matrix of Equation 3 has a full rank, it is obvious that the size of the information word bit of the QC-LDPC code corresponding to the parity check matrix becomes (n-m)L. For convenience, (n-m) column blocks corresponding to information word bits are referred to as information word column blocks, and m column blocks corresponding to the remaining parity bits are referred to as parity column blocks.

크기의 이진(binary) 행렬을 패리티 검사 행렬 H의 모행렬(mother matrix) 또는 기본 행렬(base matrix) M(H)라 하고, 각 순환 순열 행렬 또는 0-행렬의 지수를 선택하여 수학식 4와 같이 얻은

크기의 정수 행렬을 패리티 검사 행렬 H의 지수 행렬 E(H)라 한다. In general, obtained by replacing each cyclic permutation matrix and 0-matrix with 1 and 0, respectively, in the parity check matrix of Equation 3

A binary matrix of size is called the mother matrix or base matrix M(H) of the parity check matrix H, and by selecting the exponent of each cyclic permutation matrix or 0-matrix, Equation 4 and got together

An integer matrix of size is called an exponential matrix E(H) of the parity check matrix H.

[Equation 4]

As a result, since one integer included in the exponential matrix corresponds to the cyclic permutation matrix in the parity check matrix, the exponential matrix may be expressed as a sequence of integers for convenience. (The sequence is also called an LDPC sequence or an LDPC code sequence to distinguish it from other sequences). In general, the parity check matrix can be expressed not only as an exponential matrix but also as a sequence having the same logarithmic characteristic. In the present invention, for convenience, the parity check matrix is expressed as an exponential matrix or a sequence indicating the position of 1 in the parity check matrix. Since it is various, it is not limited to the method expressed herein, and it can be represented in the form of various sequences which algebraically exhibit the same effect.

In addition, although the transceiver on the device may directly generate the parity check matrix to perform LDPC encoding and decoding, LDPC encoding and decoding may be performed using an exponential matrix or a sequence that has the same logarithmic effect as the parity check matrix according to implementation features. can also be performed. Therefore, although encoding and decoding using the parity check matrix are described for convenience in the present invention, it is considered that it can be implemented through various methods that can obtain the same effect as the parity check matrix on an actual device.

For reference, the algebraically identical effect means that two or more different expressions can be logically or mathematically explained or converted to be completely identical to each other.

의 합으로 포함되어 있을 때, 그 지수 행렬은 수학식 6과 같이 나타낼 수 있다. 상기 수학식 6을 살펴보면, 상기 복수 개의 순환 순열 행렬 합이 포함된 행 블록 및 열 블록에 대응되는 i 번째 행 및 j 번째 열에 2 개의 정수가 대응되는 행렬임을 알 수 있다. In the present invention, for convenience, only the case where there is one cyclic permutation matrix corresponding to one block has been described. However, the same invention can be applied to a case in which several cyclic permutation matrices are included in one block below. For example, as shown in Equation 5 below, two cyclic permutation matrices are located at the positions of one i-th row block and j-th column block.

When included as the sum of , the exponential matrix can be expressed as Equation (6). Referring to Equation 6, it can be seen that two integers correspond to the i-th row and j-th column corresponding to the row block and column block including the sum of the plurality of cyclic permutation matrices.

[Equation 5]

[Equation 6]

크기의 행렬을 순환 행렬(circulant matrix 또는 circulant)이라 한다.As in the above embodiment, in general, in the QC-LDPC code, a plurality of cyclic permutation matrices may correspond to one row block and one column block in a parity check matrix, but in the present invention, for convenience, one cyclic permutation matrix corresponds to one block. Although only the case is described, the gist of the invention is not limited thereto. For reference, as described above, a plurality of cyclic permutation matrices are duplicated in one row block and column block.

A matrix of size is called a circulant matrix or circulant.

On the other hand, the parent or base matrix for the parity check matrix and the exponent matrix of Equations 5 and 6 is similar to the definition used in Equation 3 above. It means a binary matrix obtained by replacement, and the sum of a plurality of recursive permutation matrices (ie, recursive matrix) included in one block is also simply replaced with 1.

Since the performance of the LDPC code is determined by the parity check matrix, it is necessary to design the parity check matrix for the LDPC code having excellent performance. In addition, there is a need for an LDPC encoding or decoding method capable of supporting various input lengths and code rates.

Lifting refers to a method used not only for efficient design of a QC-LDPC code, but also to generate a parity check matrix of various lengths from a given exponential matrix or to generate an LDPC codeword. That is, the lifting is applied to efficiently design a very large parity check matrix by setting an L value that determines the size of a cyclic permutation matrix or 0-matrix from a given small parent matrix according to a specific rule, or a given exponential matrix or its corresponding This refers to a method of generating a parity check matrix of various lengths or generating an LDPC codeword by applying an appropriate L value to a sequence to be used.

The existing lifting method and the characteristics of the QC-LDPC code designed through this lifting will be briefly described with reference to the following reference [Myung2006].

Reference [Myung2006]

S. Myung, K. Yang, and Y. Kim, "Lifting Methods for Quasi-Cyclic LDPC Codes," IEEE Communications Letters. vol. 10, pp. 489-491, June 2006.

는

크기의 지수 행렬

을 가지며 각 지수

들은 {-1, 0, 1, 2, ..., L_k - 1} 값 중에 하나로 선택된다. First, when the LDPC code C ₀ is given, S QC-LDPC codes to be designed through the lifting method are C ₁ , ..., C _S , and row blocks and column blocks of the parity check matrix of each QC-LDPC code. The value corresponding to the size of is called _{L k.} Here, C ₀ corresponds to the smallest LDPC code having the parent matrix of C ₁ , ..., _{CS code as a parity check matrix, and L 0} corresponding to the size of the row block and column block is 1. In addition, for convenience, the parity check matrix of _{each code C k}

Is

exponential matrix of magnitude

has and each exponent

are selected from one of the values {-1, 0, 1, 2, ..., L _{k - 1}.}

만 저장하고 있으면 리프팅 방식에 따라 다음 수학식 7을 이용하여 상기 QC-LDPC 부호 C₀, C₁, ..., C_S를 모두 나타낼 수 있다.The conventional lifting method consists of steps such as _{C 0} → C ₁ →...→ C _{S and L k +1} = q _{k + 1} L _k (q _{k +1} is a positive integer, k=0,1,..., S-1). In addition, the parity check matrix of _{C S} by the characteristics of the lifting process

Storing only the QC-LDPC code C _0, and according to the lifting scheme using the following Equation (7) If, and C _1, ..., can be represented both the C _S.

[Equation 7]

or

[Equation 8]

In this way, not only a method of designing a larger QC-LDPC code C ₁ , ..., C _{S from C 0 , but also a small code C i from a large code C k} using an appropriate method such as Equation 7 or Equation 8 The method of generating (i=k-1, k-2, ... 1, 0) is called lifting.

In the lifting method of Equation 7 or 8, _{L k} corresponding to the size of a row block or a column block in the parity check matrix _{of each QC-LDPC code C k} have a multiple of each other, so that the exponential matrix is also a specific method is selected by This conventional lifting method helps to easily design a QC-LDPC code with improved error floor characteristics by improving the algebraic or graph characteristics of each parity check matrix designed through lifting.

만을 가질 수 있다. 즉, 리프팅을 10 단계 적용할 경우(S=10) 패리티 검사 행렬의 크기는 총 10 가지를 생성할 수 있으며, 이는 곧 10 가지 종류의 길이를 가지는 QC-LDPC 부호를 지원할 수 있음을 의미한다. However, since each L _k value has a multiple relationship with each other, the length of each code is greatly limited. For example, assuming that a minimum lifting method such as L _{k +1} = 2×L _{k is applied to each L k} value, in this case, the size of the parity check matrix of each QC-LDPC code is

can have only That is, when 10 steps of lifting are applied (S=10), a total of 10 parity check matrix sizes can be generated, which means that it is possible to support QC-LDPC codes having 10 types of lengths.

For this reason, in designing a QC-LDPC code supporting various lengths, the existing lifting method has rather disadvantageous characteristics. However, a commonly used communication system requires a very high level of length compatibility in consideration of various types of data transmission. For this reason, the LDPC encoding technique based on the existing lifting method is difficult to apply in a communication system.

In order to solve this problem, the present invention uses the following lifting method.

라 하고, L 값에 따라 변환된 지수 행렬을

이라 할 때 일반적으로 다음과 수학식 9와 같은 변환식을 적용할 수 있다. In general, lifting may be considered as using the exponential matrix of FIG. 4 for LDPC encoding and decoding by changing the values of its elements for various L values. For example, the exponential matrix of FIG. 4 is

and the exponential matrix transformed according to the L value

In general, a conversion expression such as the following Equation 9 can be applied.

[Equation 9]

는 다양한 형태로 정의할 수 있는데 예를 들면 다음 수학식 10과 같은 정의들을 사용할 수도 있다. In Equation 9 above

can be defined in various forms, for example, definitions such as the following Equation 10 may be used.

[Equation 10]

In Equation 10, mod(a,b) denotes a modulo-b operation for a, and D denotes a predefined positive integer constant.

4 is a block diagram of a transmitting apparatus according to an embodiment of the present invention.

Specifically, as shown in FIG. 4 , the transmitting apparatus 400 processes the variable-length input bits, the segmentation unit 410 , the zero padding unit 420 , the LDPC encoding unit 430 , and the rate matching unit 440 . ), a modulator 450 , and the like. The rate matching unit 440 may include an interleaver 441 and a puncture/repetition/zero removal unit 442 .

Here, the components shown in FIG. 4 are components that perform encoding and modulation on variable-length input bits, and this is only an example, and in some cases, some of the components shown in FIG. 4 are omitted or changed. may be, and other components may be further added.

On the other hand, the transmitting device 400 determines necessary parameters (eg, input bit length, modulation and code rate (ModCod), parameters for zero padding (or shortening), code rate/codeword length of the LDPC code, interleaving) parameters, parameters for repetition, puncturing, and the like) are determined and encoded based on the determined parameters and transmitted to the receiving device 500 .

Since the number of input bits is variable, when the number of input bits is greater than a preset value, the segment may be segmented to have a length equal to or less than the preset value. In addition, each segmented block may correspond to one LDPC-coded block. However, when the number of input bits is less than or equal to a preset value, segmentation is not performed. The input bits may correspond to one LDPC coded block.

Meanwhile, the transmitter 400 may pre-store various parameters used for encoding, interleaving, and modulation. Here, the parameters used for encoding may be information on a code rate of an LDPC code, a codeword length, and a parity check matrix. In addition, a parameter used for interleaving may be information on an interleaving rule, and a parameter used for modulation may be information on a modulation scheme. Also, the information about puncturing may be a puncturing length. Also, the information on the repetition may be a repetition length. The information on the parity check matrix may store an exponent value of a circulating matrix when the parity matrix proposed in the present invention is used.

In this case, each component constituting the transmitting apparatus 400 may perform an operation using these parameters.

Meanwhile, although not shown, in some cases, the transmitting apparatus 400 may further include a controller (not shown) for controlling the operation of the transmitting apparatus 400 .

5 is a block diagram of a receiving device according to an embodiment of the present invention.

Specifically, as shown in FIG. 5 , the receiving apparatus 500 includes a demodulator 510 , a rate de-matching unit 520 , an LDPC decoding unit 530 , a zero removing unit 540 and It may include a desegmentation unit 550 and the like. The rate dematching unit 520 may include a log likelihood ratio (LLR) insertion unit 522 , an LLR combiner 523 , a deinterleaver 524 , and the like.

Here, the component shown in FIG. 5 is a component that performs a function corresponding to the component shown in FIG. 5, and this is only an example and some may be omitted or changed in some cases, and other components may be More may be added.

The parity check matrix in the present invention may be read using a memory, may be given in advance by the transmitting apparatus or the receiving apparatus, or may be directly generated by the transmitting apparatus or the receiving apparatus. In addition, the transmitter may store or generate a sequence or an exponential matrix corresponding to the parity check matrix and apply it to encoding. Likewise, it goes without saying that the receiving apparatus may store or generate a sequence or an exponential matrix corresponding to the parity check matrix and apply it to decoding.

Hereinafter, a detailed description will be given of the operation of the receiver based on FIG. 5 .

The demodulator 510 demodulates the signal received from the transmitter 400 .

Specifically, the demodulator 510 is a component corresponding to the modulator 450 of the transmitter 400 , demodulates a signal received from the transmitter 400 , and transmits bits from the transmitter 400 . values corresponding to .

To this end, the reception device 500 may pre-store information on the modulation scheme modulated according to the mode by the transmission device 400 . Accordingly, the demodulator 510 may generate values corresponding to the LDPC codeword bits by demodulating the signal received from the transmitter 400 according to the mode.

Meanwhile, a value corresponding to the bits transmitted from the transmitter 400 may be a Log Likelihood Ratio (LLR) value.

Specifically, the LLR value may be expressed as a value obtained by taking a logarithm of a ratio of a probability that a bit transmitted from the transmitter 400 is 0 and a probability that the bit is 1 . Alternatively, the LLR value may be a bit value itself, and the LLR value may be a representative value determined according to a section to which the probability that the bit transmitted from the transmitting apparatus 400 is 0 or 1 belongs.

The demodulator 510 includes a process of performing multiplexing (not shown) on the LLR value. Specifically, as a component corresponding to bit demux (not shown) of the transmitting apparatus 400 , an operation corresponding to bit demux (not shown) may be performed.

To this end, the receiving device 500 may pre-store information on parameters used by the transmitting device 400 for demultiplexing and block interleaving. Accordingly, the mux (not shown) reversely performs the demultiplexing and block interleaving operations performed in the bit demux (not shown) on the LLR value corresponding to the cell word, thereby converting the LLR value corresponding to the cell word in bit units. can be multiplexed with

The rate matcher 520 may insert the LLR value into the LLR value output from the demodulator 510 . In this case, the rate matcher 520 may insert previously agreed LLR values between the LLR values output from the demodulator 510 .

Specifically, the rate matching unit 520 is a component corresponding to the rate matching unit 440 of the transmitting apparatus 400 , and includes an interleaver 441 , and a zero removal and puncturing/repeat/zero removal unit 442 . ) can be performed.

First, the rate de-matching unit 520 performs deinterleaving to correspond to the interleaver 441 of the transmitter. The output values of the deinterleaver 524 may insert the LLR values corresponding to the zero bits at the positions where the zero bits were padded in the LDPC codeword in the LLR inserter 522 . In this case, the LLR values corresponding to the padded zero bits, that is, the shortened zero bits, may be ∞ or -∞. However, ∞ or -∞ is a theoretical value, and may actually be the maximum or minimum value of the LLR value used in the reception device 500 .

To this end, the reception device 500 may pre-store information about a parameter used by the transmission device 400 to pad the zero bits. Accordingly, the rate matcher 520 may determine a position where zero bits are padded in the LDPC codeword, and insert an LLR value corresponding to the shortened zero bits in the corresponding position.

Also, the LLR insertion unit 522 of the rate dematching unit 520 may insert LLR values corresponding to the punctured bits at positions of the punctured bits in the LDPC codeword. In this case, the LLR value corresponding to the punctured bits may be 0.

To this end, the receiving device 500 may pre-store information on parameters used for puncturing by the transmitting device 400 . Accordingly, the LLR inserter 522 may insert an LLR value corresponding thereto at a position where the LDPC parity bits are punctured.

The LLR combiner 523 may combine, that is, sum the LLR values output from the LLR inserter 522 and the demodulator 510 . Specifically, the LLR combiner 523 is a component corresponding to the puncturing/repeat/zero removal unit 442 of the transmitting device 400 , and performs an operation corresponding to the repeater 442 . can First, the LLR combiner 523 may combine an LLR value corresponding to the repeated bits with another LLR value. Here, the other LLR value may be an LLR value for bits based on generation of the repeated bits by the transmitter 400 , that is, LDPC parity bits selected as a repetition target.

That is, as described above, the transmitter 400 selects bits from the LDPC parity bits, repeats them between the LDPC information word bits and the LDPC parity bits, and transmits them to the receiver 500 .

Accordingly, the LLR values for the LDPC parity bits are the LLR values for the repeated LDPC parity bits and the LLR values for the non-repeat LDPC parity bits, that is, the LDPC parity bits generated by encoding. can be configured. Accordingly, the LLR combiner 523 may combine LLR values to the same LDPC parity bits.

To this end, the receiving device 500 may pre-store information about the parameters used for the repetition by the transmitting device 400 . Accordingly, the LLR combiner 523 may determine the LLR values for the repeated LDPC parity bits, and combine them with the LLR values for the LDPC parity bits that are the basis of the repetition.

Also, the LLR combiner 523 may combine an LLR value corresponding to retransmitted or incremental redundancy (IR) bits with another LLR value. Here, the other LLR values may be LLR values for bits selected for generation of LDPC codeword bits based on the generation of retransmitted or IR bits by the transmitting device 400 .

That is, as described above, when NACK occurs for HARQ, the transmitting apparatus 400 may transmit some or all of the codeword bits to the receiving apparatus 500 .

Accordingly, the LLR combiner 523 may combine LLR values for bits received through retransmission or IR with LLR values for LDPC codeword bits received through a previous frame.

To this end, the receiving device 500 may pre-store information on parameters used by the transmitting device 400 for retransmission or for generating IR bits. Accordingly, the LLR combiner 523 may determine the LLR value for the number of retransmission or IR bits, and combine it with the LLR value for the LDPC parity bits based on the generation of the retransmission bits.

The deinterleaver 524 may deinterleave the LLR values output from the LLR combiner 523 .

Specifically, the deinterleaver unit 524 is a component corresponding to the interleaver 441 of the transmitting apparatus 400 , and may perform an operation corresponding to the interleaver 441 .

To this end, the receiving device 500 may pre-store information on the parameters used by the transmitting device 400 for interleaving. Accordingly, the deinterleaver 524 reversely performs the interleaving operation performed by the interleaver 441 on the LLR values corresponding to the LDPC codeword bits to deinterleave the LLR values corresponding to the LDPC codeword bits. can

The LDPC decoding unit 530 may perform LDPC decoding based on the LLR value output from the rate dematching unit 520 .

Specifically, the LDPC decoder 530 is a component corresponding to the LDPC encoder 430 of the transmitting apparatus 400 , and may perform an operation corresponding to the LDPC encoder 430 .

To this end, the reception device 500 may pre-store information on parameters used by the transmission device 400 to perform LDPC encoding according to a mode. Accordingly, the LDPC decoding unit 530 may perform LDPC decoding based on the LLR value output from the rate dematching unit 520 according to a mode.

For example, the LDPC decoding unit 530 performs LDPC decoding based on the LLR value output from the rate dematching unit 520 based on an iterative decoding method based on a sum and product algorithm, and an error is corrected according to the LDPC decoding. Bits can be output.

The zero remover 540 may remove zero bits from the bits output from the LDPC decoder 530 .

Specifically, the zero removing unit 540 is a component corresponding to the zero padding unit 420 of the transmitting apparatus 400 , and may perform an operation corresponding to the zero padding unit 420 .

To this end, the reception device 500 may pre-store information on a parameter used for padding the zero bits by the transmission device 400 . Accordingly, the zero remover 540 may remove the zero bits padded by the zero padder 420 from the bits output from the LDPC decoder 530 .

The de-segmentation unit 550 is a component corresponding to the segmentation unit 410 of the transmitting apparatus 400 and may perform an operation corresponding to the segmentation unit 410 .

To this end, the reception device 500 may pre-store information on the parameters used by the transmission device 400 for segmentation. Accordingly, the de-segmentation unit 550 may reconstruct the bits before segmentation by combining segments of the bits output from the zero removing unit 540, that is, the variable-length input bits.

On the other hand, the LDPC code can be decoded using an iterative decoding algorithm based on the sum and product algorithm on the bipartite graph shown in FIG. 2 , and the sum and product algorithm is a type of message passing algorithm.

Hereinafter, a message passing operation generally used in LDPC decoding will be described with reference to FIGS. 6A and 6B .

6A and 6B show message passing operations in arbitrary check nodes and variable nodes for LDPC decoding.

6A shows a check node m 600 and a plurality of variable nodes 610 , 620 , 630 , and 640 connected to the check node m 600 . In addition, the illustrated Tn',m denotes a message passed from the variable node n' (610) to the check node m (600), and En,m denotes a message passed from the check node m (600) to the variable node n (630). indicates the message being Here, the set of all variable nodes connected to the check node m(600) is defined as N(m), and the set excluding the variable node n(630) from N(m) is defined as N(m)\n. do it with

In this case, the message update rule based on the sum and product algorithm can be expressed as Equation 11 below.

[Equation 11]

는 하기의 수학식 12와 같이 나타낼 수 있다. Here, Sign(E _n,m ) represents the sign of the message E _n,m , and |E _n,m | represents the magnitude of the message E _n,m. On the other hand, the function

can be expressed as in Equation 12 below.

[Equation 12]

Meanwhile, FIG. 6B shows a variable node x ( 650 ) and a plurality of check nodes ( 660 , 670 , 680 , and 690 ) connected to the variable node x ( 650 ). In addition, the illustrated E _{y ',x} represents a message passed from the check node y' (660) to the variable node x (650), and T _y,x is the variable node x (650) to the variable node y (680). Indicates a message passed to . Here, define the set of all variable nodes connected to the variable node x(650) as M(x), and define the set except the check node y(680) from M(x) as M(x)\y do it with In this case, the message update rule based on the sum and product algorithm can be expressed as Equation 13 below.

[Equation 13]

Here, E _x means the initial message value of the variable node x.

In addition, when the bit value of the node x is determined, it can be expressed as in Equation 14 below.

[Equation 14]

In this case, the encoding bit corresponding to the node x may be determined according to the _{P x value.}

Since the method described above with reference to FIGS. 6A and 6B is a general decoding method, a detailed description thereof will be omitted. However, in addition to the method described with reference to FIGS. 6A and 6B , other methods may be applied in determining the message value passed in the variable node and the check node, and detailed descriptions related thereto can be found in “Frank R. Kschischang, Brendan J. Frey, and Hans-Andrea Loeliger, "Factor Graphs and the Sum-Product Algorithm," IEEE TRANSACTIONS ON INFORMATION THEORY, VOL. 47, NO. 2, FEBRUARY 2001, pp498-519).

7 is a block diagram illustrating a detailed configuration of an LDPC encoder according to an embodiment of the present invention.

)을 구성할 수 있다. LDPC 부호화부(700)는 K_ldpc 개의 LDPC 정보어 비트들을 시스테매틱하게 LDPC 부호화하여, N_ldpc 개의 비트들로 구성된 LDPC 코드워드

=(c₀,c₁,..., c_Nldpc-1)=(i₀,i₁,..., i_Kldpc-1,p₀,p₁,...,p_{Nldpc-Kldpc-1})를 생성할 수 있다. K _{ldpc bits are K ldpc} LDPC information word bits for the LDPC encoder 700 _{I = (i 0} ,i ₁ ,...,

) can be configured. The LDPC encoder 700 systematically LDPC-encodes _{K ldpc} LDPC information word bits, and an LDPC codeword composed of _{N ldpc bits.}

=(c ₀ ,c ₁ ,..., c _Nldpc-1 )=(i ₀ ,i ₁ ,..., i _Kldpc-1 ,p ₀ ,p ₁ ,...,p _{Nldpc-Kldpc-1} ) can be created.

As described in Equation 1 above, the process includes determining a codeword such that the product of the LDPC codeword and the parity check matrix becomes a zero vector.

Referring to FIG. 7 , the encoding apparatus 700 includes an LDPC encoding unit 710 . The LDPC encoder 710 may generate an LDPC codeword by performing LDPC encoding on the input bits based on the parity check matrix or the exponential matrix or sequence corresponding thereto. In this case, the LDPC encoder 710 may perform LDPC encoding using parity check matrices defined differently according to a code rate (ie, a code rate of an LDPC code).

Meanwhile, the encoding apparatus 700 may further include a memory (not shown) for pre-storing information on a code rate, a codeword length, and a parity check matrix of an LDPC code, and the LDPC encoder 710 stores such information. LDPC encoding can be performed using The information on the parity check matrix may store information on the exponent value of the circulating matrix when the parity matrix proposed in the present invention is used.

8 is a block diagram illustrating a configuration of a decoding apparatus according to an embodiment of the present invention.

Referring to FIG. 8 , the decoding apparatus 800 may include an LDPC decoding unit 810 .

The LDPC decoding unit 810 performs LDPC decoding on the LDPC codeword based on a parity check matrix or an exponential matrix or a sequence corresponding thereto.

For example, the LDPC decoding unit 810 may generate information word bits by performing LDPC decoding by passing log likelihood ratio (LLR) values corresponding to LDPC codeword bits through an iterative decoding algorithm.

Here, the LLR value is a channel value corresponding to the LDPC codeword bits, and may be expressed in various ways.

For example, the LLR value may be expressed as a value obtained by taking the logarithm of the ratio of the probability that the bit transmitted through the channel at the transmitting side is 0 and the probability that it is 1. In addition, the LLR value may be the bit value itself determined according to the hard decision, or it may be a representative value determined according to the section to which the probability that the bit transmitted from the transmitting side is 0 or 1 belongs.

In this case, the transmitting side may generate an LDPC codeword by using the LDPC encoder 710 as shown in FIG. 7 .

In this case, the LDPC decoding unit 810 may perform LDPC decoding using parity check matrices defined differently according to a code rate (ie, a code rate of an LDPC code).

9 is a structural diagram of an LDPC decoder according to another embodiment of the present invention.

Meanwhile, as described above, the LDPC decoding unit 810 may perform LDPC decoding using an iterative decoding algorithm. In this case, the LDPC decoding unit 810 may have a structure as shown in FIG. 9 . However, since the iterative decoding algorithm is already known, the detailed configuration shown in FIG. 9 is only an example.

According to FIG. 9 , the decoding device 900 includes an input processor 901 , a memory 902 , a variable node operator 904 , a controller 906 , a check node operator 908 , and an output processor 910 . .

The input processor 901 stores an input value. Specifically, the input processor 901 may store an LLR value of a received signal received through a wireless channel.

The controller 904 determines the number of values input to the variable node operator 904 based on the parity check matrix corresponding to the block size (ie, the codeword length) and the code rate of the received signal received through the radio channel. and an address value in the memory 902 , the number of values input to the check node operator 908 , and an address value in the memory 902 .

The memory 902 stores input data and output data of the variable node operator 904 and the check node operator 908 .

The variable node operator 904 receives data from the memory 902 according to the address information of the input data received from the controller 906 and information on the number of input data, and performs a variable node operation. Thereafter, the variable node operator 904 stores the variable node operation results in the memory 902 based on the address information of the output data input from the controller 906 and information on the number of output data. In addition, the variable node operator 904 inputs a variable node operation result to the output processor 910 based on data received from the input processor 901 and the memory 902 . Here, the variable node operation has been described above with reference to FIG. 6 .

The check node operator 908 receives data from the memory 902 based on address information of the input data received from the controller 906 and information on the number of input data to perform a check node operation. Thereafter, the check node operator 908 stores the variable node operation results in the memory 902 based on the address information of the output data received from the controller 906 and information on the number of output data. Here, the check node operation has been described above with reference to FIG. 6 .

The output processor 910 hard determines whether the information word bits of the codeword of the transmitting side are 0 or 1 based on the data input from the variable node operator 904, and outputs the hard determination result, and the output processor ( 910) becomes the finally decoded value. In this case, a hard decision may be made based on the sum of all message values (the initial message value and all message values input from the check node) input to one variable node in FIG. 6 .

Meanwhile, the decoding apparatus 900 may further include a memory (not shown) for pre-storing information on the code rate, the codeword length, and the parity check matrix of the LDPC code, and the LDPC decoding unit 810 receives such information. LDPC encoding can be performed using However, this is only an example, and the corresponding information may be provided from the transmitting side.

10 is a structural diagram of a transport block according to another embodiment of the present invention.

Referring to FIG. 10 , <Null> bits may be added so that the segmented lengths are the same.

Also, <Null> bits may be added to match the information length of the LDPC code.

In the above, in a communication and broadcasting system supporting LDPC codes of various lengths, a method of applying various block sizes based on QC-LDPC codes has been described. Next, a method for further improving the encoding performance in the proposed method is proposed.

In general, if, as in the lifting method described in Equations 9 and 10, a sequence is appropriately converted and used for a very diverse block size L from one LDPC exponential matrix or sequence, one or a small number of sequences is implemented at the time of system implementation. It has many advantages because it only needs to be implemented for . However, as the number of types of block sizes to be supported increases, it is very difficult to design an LDPC code with good performance for all block sizes.

에 기반한 리프팅을 가정하여 설명을 진행하지만 반드시 이에 국한할 필요는 없다. In order to solve this problem, an efficient design method of the following QC LDPC code will be described. The present invention proposes a method of designing a parity check matrix having excellent performance in consideration of the lifting methods of Equations (9) and (10) and a trapping set characteristic on a parity check matrix of an LDPC code or a Tanner graph. In the present invention, for convenience, Equation 10

The description proceeds assuming lifting based on , but it is not necessarily limited thereto.

* Design method of variable length QC LDPC code

Step 1) In determining the noise threshold for decoding success of the channel code, the convergence criteria of the iteration number and density evolution are changed and density evolution analysis is performed to perform the basic Find the weight distribution of the matrix.

Step 2) If the weight distribution obtained in Step 1) can be improved through the Hill Climbing method, the improved weight distribution is set as the weight distribution of the final basic matrix.

Step 3) One basic matrix is obtained based on the weight distribution obtained in Step 2). In this case, the method of obtaining the default matrix may be designed through various known methods.

를 가정한다. 즉,

의 범위를 만족하는 L 값에 대해 모두 동일한 지수 행렬을 사용하여 부호화 및 복호화를 수행함을 가정한다. Step 3) Lifting of Equation 10

assume in other words,

It is assumed that encoding and decoding are performed using the same exponential matrix for all L values satisfying the range of .

의 범위를 만족하는 L 값에 따라 지수 행렬을 결정함에 있어 먼저 거스(girth, Tanner 그래프 상의 사이클 길이 중 가장 작은 값)를 최대화한 다음, 사전에 결정된 트랩핑 집합 제거 순서에 따라 트랩핑 집합이 순서대로 최대한 제거되는 지수 행렬을 결정한다. 여기서 상기 결정된 트랩핑 집합 제거 순서는 다음과 같다. Step 4)

In determining the exponential matrix according to the L value that satisfies the range of Determines the exponential matrix to be removed as much as possible. Here, the determined trapping set removal order is as follows.

1st place: (4,0) trapping set

2nd place: (3,1) trapping set

3rd place: (2,2) trapping set

4th place: (3,2) trapping set

Rank 5: (4,1) trapping set

6th place: (4,2) trapping set

Step 5) After repeating the steps 1) to 4) a predetermined number of times, the code with the best average performance is finally selected according to the L value through a computational experiment for each obtained code. Here, the average performance can be defined in various ways, for example, by finding the minimum signal to noise ratio (SNR) required to achieve the BLER (block error rate) required by the system according to the change in L value, and A code having the smallest average SNR may be finally selected.

It is obvious that the design method of the variable length QC LDPC code is only an embodiment and can be changed according to a requirement for a channel code. For example, Step 3) can be changed in consideration of the lifting method when the lifting method to be applied in the system is different. Also, in Step 4), the removal order of the trapping set may be changed according to the characteristics of the channel code required by the system. In addition, although the variable length QC LDPC code design method has been described with respect to the case where the length is variable, even when the length is fixed to one, only the lifting process in Step 3) and Step 4) is removed and applied.

For example, when the number of information bits is set to a small number and the code rate is low, the code may be designed assuming that some of the codeword bits obtained after channel encoding are repeated and transmitted in consideration of both complexity and performance. In this case, in Step 1) of the variable-length QC LDPC code design method, a portion of the initial value for density evolution analysis is increased by the number of repeated transmissions to determine the noise threshold. Also, if the code rate or length is fixed, the lifting process can be excluded from Step 3) and Step 4).

For reference, the details of the well-known density evolution analysis method and the characteristics of the trapping set are omitted because they are out of the gist of the present invention, and the following references Reference [RSU2001] and Reference [KaBa2012], respectively:

Reference [RSU2001]:

T. J. Richardson, M. A. Shokrollahi, , and R. L. Urbanke, “Design of capacity-approaching irregular low-density parity-check codes,” IEEE Trans. Inf. Theory, vol. 47, no. 2, pp. 619-637, Feb. 2001.

Reference [KaBa2012]:

M. Karimi and A. H. Banihashemi, “Efficient algorithm for finding dominant trapping sets of LDPC codes,” IEEE Trans. Inf. Theory, vol. 58, no. 11, pp. 6942-6958, Nov. 2012.

11 to 15 show an exponential matrix or an LDPC sequence of the parity check matrix designed through the design method of the present invention.

In addition, FIGS. 11A to 11B show the parity check matrix of FIG. 11 and each part is enlarged. Each part of FIG. 11 corresponds to a matrix corresponding to the reference number described in each part. Accordingly, one parity check matrix of the form shown in FIG. 11 may be configured by combining FIGS. 11A to 11B . Also, the same may be applied to FIGS. 12 to 15 . In the exponential matrix of FIGS. 11 to 15 , each empty block corresponds to a zero matrix of LxL size.

As a characteristic of the exponential matrix shown in FIG. 11, all of the partial matrices including the 7 rows and 17 columns from the front have a degree of 2 or more. In addition, another characteristic of the exponential matrix shown in FIG. 11 is that all of the 18th column to the 52nd column have a degree of 1. That is, the 35x52 exponential matrix composed of the 8th row to the 42nd row of the exponential matrices is characterized in that it corresponds to a large number of single parity-check codes. As a result, the exponential matrix shown in FIG. 11 includes an LDPC code having a parity check matrix composed of 7 row blocks and 17 column blocks of order 2 or more, a plurality of single check codes composed of 35 row blocks and 52 column blocks, and It can be seen that it corresponds to the parity check matrices of the concatenation type.

The parity check matrix to which the concatenation method with a single parity check code is applied has an advantage in applying the IR (Incremental Redundancy) technique because it is easily extensible. Since the IR technique is an important technique for HARQ (Hybrid Automatic Repeat reQuest) support, the efficient and excellent IR technique increases the efficiency of the HARQ system. In the LDPC codes based on the parity check matrices, a new parity is generated and transmitted using a portion extended to a single parity check code, so that an efficient and superior IR technique can be applied.

The first 10 columns in the exponential matrix of FIG. 11 correspond to information bits. Accordingly, the information bit may be determined to have a size equal to 10L according to the size L of the cyclic permutation matrix or the cyclic matrix in the parity check matrix. In general, an information bit length other than 10L can be supported through a method such as shortening. In addition, since the codeword bit length has 52 columns in the exponential matrix of FIG. 11, a size equal to 52L can be supported depending on the L value. In general, when the code rate is not 52L or the code rate is not 10/52, a part of the information bit is shortened, a part of the code bit is punctured, or both methods can be applied to support it.

11 is designed in consideration of the case of using the following L value, but it is not necessarily limited thereto.

L = {4, 5, 6, 7} {8, 9, 10, 11, 12, 13, 14, 15} {16, 18, 20, 22, 24, 26, 28, 30} {32, 36, 40, 44, 48, 52, 56, 60} {64, 72, 80, 88, 96, 104, 112, 120} {128, 144, 160, 176, 192, 208, 224, 240} {256}

The exponent matrix shown in FIGS. 12 to 15 is an exponent matrix for a case where L=16 is fixed and the number of sign bits is also fixed at 880.

In FIG. 12, the first six columns in the exponential matrix, in FIG. 13, in the first five columns, in FIG. 14, the first four columns in the exponential matrix, in FIG. 15, the first three columns in the exponential matrix It is characterized in that the column corresponds to the information bit. Accordingly, the information bits may be determined to be 96, 80, 64, 48, etc. according to the size L=16 of the cyclic permutation matrix or the cyclic matrix in the parity check matrix. In general, information bit lengths other than the 96, 80, 64, and 48 values can be supported through a method such as shortening. Also, in general, when the number of sign bits is not 880, it is possible to support by shortening a part of the information bit, puncturing a part of the sign bit, or applying both methods.

As another embodiment of the present invention, a method of applying a plurality of exponential matrices or LDPC sequences on one predetermined basic matrix is proposed. That is, there is one basic matrix, and LDPC encoding of variable length is obtained by obtaining an exponential matrix or a sequence of the LDPC code from the basic matrix, and applying lifting from the exponential matrix or sequence to the block size included in each block size group. and decryption. In other words, basic matrices of parity check matrices corresponding to exponential matrices or sequences of a plurality of different LDPC codes are the same. In this method, the elements or numbers constituting the exponential matrix of the LDPC code or the LDPC sequence may have different values, but the positions of the elements or numbers are exactly the same. As described above, the exponential matrix or LDPC sequence means the exponent of the cyclic permutation matrix, that is, a kind of cyclic permutation value for bits. is easy to understand

First, a block size Z to be supported is divided into a plurality of block size groups (or sets) as shown in Equation 15 below. Note that the block size Z is a value corresponding to the size ZxZ of the cyclic permutation matrix or the cyclic matrix in the parity check matrix of the LDPC code.

[Equation 15]

Z1 = {12, 24, 48, 96, 192}

Z2 = {11, 22, 44, 88, 176}

Z3 = {10, 20, 40, 80, 160}

Z4 = {9, 18, 36, 72, 144}

Z5 = {8, 16, 32, 64, 128, 256}

Z6 = {15, 30, 60, 120, 240}

Z7 = {14, 28, 56, 112, 224}

Z8 = {13, 26, 52, 104, 208}

라 하고, 상기 p번째 그룹에 포함된 Z 값에 대응되는 지수 행렬을

라 할 때,

를 이용하여 수학식 9와 같은 수열의 변환 방법을 적용한다고 하자. 즉, 예를 들어 블록 크기 Z가 Z = 28와 같이 결정된 경우에는 Z = 28이 포함되어 있는 7번째 블록 크기 그룹에 대응되는 지수 행렬

에 대해서 Z = 28에 대한 지수 행렬

의 각 원소

를 다음 수학식 16과 같이 얻을 수 있다. The block size groups in Equation (15) have different granularity, as well as a characteristic that the ratio of neighboring block sizes is the same integer. In other words, the block sizes included in one group have a divisor or multiple relationship with each other. Each of the exponential matrices corresponding to the p (p = 1, 2, …, 8)-th group

and the exponential matrix corresponding to the Z value included in the p-th group

When you say

Suppose that the conversion method of the sequence as in Equation 9 is applied using . That is, for example, when the block size Z is determined as Z = 28, the exponential matrix corresponding to the 7th block size group including Z = 28

Exponential matrix for Z = 28

each element of

can be obtained as in Equation 16 below.

[Equation 16]

The transformation as in Equation 16 is also simply expressed as Equation 17 below.

[Equation 17]

16 to 24 show the basic matrix and exponential matrix (or LDPC sequence) of the LDPC code designed in consideration of Equations 15 to 17 above. For reference, in the above description, it is assumed that the lifting or exponential matrix transformation method in Equation 9 or Equation 16 to Equation 17 is applied to the entire exponential matrix corresponding to the parity check matrix. is also applicable. For example, in general, a partial matrix corresponding to a parity bit of a parity check matrix often has a special structure for efficient encoding. In this case, the encoding method or complexity may be changed by lifting. Therefore, in order to maintain the same encoding method or complexity, lifting is not applied to a part of the exponential matrix for the partial matrix corresponding to parity in the parity check matrix, or the lifting method is applied to the exponential matrix for the partial matrix corresponding to the information word bit. Other lifting can be applied. In other words, the lifting method applied to the sequence corresponding to the information bit in the exponential matrix and the lifting method applied to the sequence corresponding to the parity bit may be set differently, and in some cases, a part of the sequence corresponding to the parity bit or Since lifting is not applied to the whole, a fixed value can be used without converting the sequence.

16 to 24 show an embodiment of a basic matrix or exponential matrix corresponding to a parity check matrix of an LDPC code designed using the QC LDPC code design method proposed by the present invention based on Equations 15 to 17 are shown sequentially. (Note that empty blocks in the basic matrix and exponential matrix of FIGS. 16 to 24 indicate a portion corresponding to a zero matrix of ZxZ size. In some cases, empty blocks in the basic matrix of FIG. 16 can be expressed as 0, In the exponential matrix of FIGS. 17 to 24, empty blocks can also be expressed as a specified value such as -1.) Exponential matrices of the LDPC code shown in FIGS. 17 to 24 have the same basic matrix.

The matrices of FIGS. 16 to 24 are diagrams illustrating a 42x52 basic matrix or an LDPC exponential matrix. Also, in each exponential matrix, the submatrix consisting of the top 5 rows and 15 columns from the front does not have a column of degree 1. In other words, the parity check matrix that can be generated by applying lifting from the partial matrix does not have a column or column block of order 1.

In addition, FIGS. 16A to 16B are enlarged views of the exponential matrix of FIG. 16 , and each part is enlarged. 16 corresponds to the matrix of the drawing corresponding to the reference number described in each part. Accordingly, FIGS. 16A to 16B may be combined to form one basic matrix.

In addition, FIGS. 17A to 17B are enlarged views of the exponential matrix of FIG. 17 by dividing each part. 17 corresponds to the matrix of the drawing corresponding to the reference number described in each part. Accordingly, one exponential matrix or LDPC sequence can be constructed by combining FIGS. 17A to 17B . Similarly, FIGS. 18 to 24 also show each part after dividing each exponential matrix in an enlarged manner.

Another characteristic of the exponential matrix shown in FIGS. 16 to 24 is that all of the 16th column to the 52nd column have a degree of 1. That is, the basic matrix or exponential matrix having a size of 37x52, which is composed of the 6th row to the 42nd row of the exponential matrices, is characterized in that it corresponds to a single parity-check code.

The exponential matrices shown in FIGS. 17 to 24 respectively correspond to LDPC codes designed in consideration of the block size group defined in Equation (15). However, it is not necessary to support all block sizes included in the block size group according to system requirements. As a result, the exponential matrices shown in FIGS. 17 to 24 can support the block size corresponding to the block size group (set) defined in Equation 15, and at least the block size corresponding to the subset of each group (set). can support

Also, depending on the system, the basic matrix and the exponential matrix shown in FIGS. 16 to 24 may be used as they are, or only a part thereof may be used. For example, a new exponential matrix is created by concatenating a partial matrix of 7x17 size and another exponential matrix of size 35x52 consisting of seven rows and 17 columns from the front of each of the basic matrices and exponential matrices of FIGS. 16 to 24 . Thus, LDPC encoding and decoding can be applied.

Similarly, in the basic matrix and exponent matrix shown in FIGS. 16 to 24, by concatenating a partial matrix of size 35x52 consisting of the 8th row to the last row and from the 1st column to the 52nd column and another submatrix of the size 7x17 in the basic matrix and exponential matrix shown above, a new exponential LDPC encoding and decoding may be performed by generating a matrix.

In general, LDPC encoding and decoding may be performed by applying a partial matrix formed by appropriately selecting rows and columns from the basic matrix of FIG. 16 as a new basic matrix. Similarly, LDPC encoding and decoding may be performed by applying a partial matrix formed by appropriately selecting a row block and a column block from the exponential matrix of FIGS. 17 to 24 as a new exponential matrix.

In general, the LDPC code can adjust the code rate by applying puncturing of codeword bits according to the code rate. When the LDPC code based on the basic matrix or the exponential matrix shown in FIGS. 16 to 24 punctures the parity bit corresponding to the column of order 1, the LDPC decoder can perform decoding without using the corresponding part in the parity check matrix. Therefore, there is an advantage in that the decoding complexity is reduced. However, when encoding performance is considered, there is a method for improving the performance of the LDPC code by adjusting the puncturing order of parity bits or the transmission order of the generated LDPC codewords.

For example, if information word bits corresponding to the first two columns of the basic matrix or exponential matrix corresponding to FIGS. 16 to 24 are punctured, and parity bits of order 1 corresponding to the 18th column to the 52nd column are all punctured. It is possible to transmit an LDPC codeword with a code rate of 10/15. In general, performance may be further improved if an LDPC codeword is generated using the base matrix and the exponential matrix corresponding to FIGS. 16 to 24 and then rate matching is appropriately applied. Of course, in consideration of the rate matching, the order of columns in the base matrix or the exponential matrix may be appropriately rearranged and applied to LDPC encoding and decoding.

Typically, in the LDPC encoding process, the size of an input bit (or code block) to which LDPC encoding is to be applied is first determined, and then a block size (Z) to which the LDPC encoding is to be applied is determined according to the size, and an appropriate size according to the block size is determined. After determining the LDPC exponential matrix or sequence, LDPC encoding is performed based on the block size Z and the determined exponential matrix or LDPC sequence. In this case, the LDPC index matrix or sequence may be applied to LDPC encoding without transformation, and in some cases, the LDPC index matrix or sequence may be appropriately transformed according to the block size (Z) to perform LDPC encoding.

Similarly, the LDPC decoding process determines the input bit (or code block) size for the transmitted LDPC codeword, then determines the block size (Z) to which LDPC decoding is applied according to the size, and an appropriate LDPC index according to the block size. After determining the matrix or sequence, LDPC decoding is performed based on the block size Z and the determined exponential matrix or LDPC sequence. In this case, the LDPC exponential matrix or sequence may be applied to LDPC decoding without transformation, and in some cases, the LDPC exponential matrix or sequence may be appropriately transformed according to the block size (Z) to perform LDPC decoding.

The basic matrix shown in FIG. 16 can be expressed in various forms. For example, it can be expressed using a sequence such as Equations 18 to 21 below.

Equation 18 represents the position of element 1 for each row in the 42x52 submatrix in the basic matrix of FIG. 16 . For example, in Equation 18, the second value 6 of the second sequence means that element 1 is present in the sixth column of the second row in the basic matrix. (In the above example, the starting order of elements in sequences and matrices is assumed to start from 0.)

Equation 19 represents the position of element 1 for each column in the 42x52 sub-matrix in the basic matrix of FIG. 16 . For example, in Equation 18, the meaning of the third value 10 of the third sequence means that element 1 is present in the tenth row of the third column of the basic matrix. (In the above example, the starting order of elements in sequences and matrices is assumed to start from 0.)

[Equation 18]

0 2 3 4 5 6 7 9 10 11

0 1 8 11 12

0 1 6 8 9 10 12 13

0 2 3 4 5 7 8 9 13 14

0 2 3 4 5 6 7 10 14

0 1 10 15

0 1 6 9 10 16

1 3 4 9 17

0 1 2 8 10 18

0 5 6 19

0 1 7 12 20

1 2 6 21

0 4 7 10 22

0 1 3 23

0 5 8 10 24

0 4 12 25

1 2 8 26

0 1 9 14 27

0 3 12 28

1 8 14 29

1 5 12 30

0 6 9 31

1 4 14 32

0 13 33

1 12 14 34

0 5 8 35

4 14 36

1 2 12 37

0 3 38

1 7 13 39

8 10 12 40

1 3 7 41

6 10 12 42

1 5 43

2 9 12 44

1 13 45

2 4 12 46

1 6 7 8 47

0 4 48

12 13 14 49

1 10 50

3 8 12 51

[Equation 19]

0 3 4 7 13 18 28 31 41

0 3 4 7 12 15 22 26 36 38

0 3 4 9 14 20 25 33

0 2 4 6 9 11 21 32 37

0 3 4 10 12 29 31 37

1 2 3 8 14 16 19 25 30 37 41

0 2 3 6 7 17 21 34

0 2 4 5 6 8 12 14 30 32 40

0 1

1 2 10 15 18 20 24 27 30 32 34 36 39 41

2 3 23 29 35 39

3 4 17 19 22 24 26 39

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

When there is a specific rule in the position of the basic matrix of FIG. 16 and the column of order 1, information on the corresponding position may be omitted as in Equations 20 and 21, respectively. Of course, it is assumed that the transmitting device and the receiving device know the specific rule.

When a certain rule is given for a part of the base matrix or the exponent matrix, the base matrix or the exponent matrix may be expressed more simply. For example, in the case of having a diagonal structure from the 15th column block to the last column block as in the basic matrix or exponential matrix of FIGS. 16 to 24, the position of an element or its index values are omitted, but the corresponding rule is known. Assume there is

As an example, Equation 20 or Equation 21 is an example in which the position of element 1 is omitted from the 15th column block to the last column block in Equations 18 and 19, respectively.

[Equation 20]

0 2 3 4 5 6 7 9 10 11

0 1 8 11 12

0 1 6 8 9 10 12 13

0 2 3 4 5 7 8 9 13 14

0 2 3 4 5 6 7 10 14

0 1 10

0 1 6 9 10

1 3 4 9

0 1 2 8 10

0 5 6

0 1 7 12

1 2 6

0 4 7 10

0 1 3

0 5 8 10

0 4 12

1 2 8

0 1 9 14

0 3 12

1 8 14

1 5 12

0 6 9

1 4 14

0 13

1 12 14

0 5 8

4 14

1 2 12

0 3

1 7 13

8 10 12

1 3 7

6 10 12

1 5

2 9 12

1 13

2 4 12

1 6 7 8

0 4

12 13 14

1 10

3 8 12

[Equation 21]

0 3 4 7 13 18 28 31 41

0 3 4 7 12 15 22 26 36 38

0 3 4 9 14 20 25 33

0 2 4 6 9 11 21 32 37

0 3 4 10 12 29 31 37

1 2 3 8 14 16 19 25 30 37 41

0 2 3 6 7 17 21 34

0 2 4 5 6 8 12 14 30 32 40

0 1

1 2 10 15 18 20 24 27 30 32 34 36 39 41

2 3 23 29 35 39

3 4 17 19 22 24 26 39

Equation 21 represents each element value for each row in the exponential matrix of 42x52 size in the exponential matrix of FIG. 17 . For example, in Equation 22, the second value 56 of the second sequence means that the value of the second element of the second row in the exponential matrix is 56, which is parity when considering Equations 16 and 18 above. It means that the index of the cyclic permutation matrix corresponding to the second row block and the sixth column block in the check matrix is 56.

If a certain rule is given for a part of the exponential matrix, the exponential matrix may be expressed more simply. For example, in the case of having a diagonal structure from the 15th column block to the last column block as in the exponential matrix of FIGS. 17 to 24 , the exponent values are omitted, but it is assumed that the rule is known.

As an example, Equation 23 below is an example in which the index 0 value is omitted from the 15th column block to the last column block.

[Equation 22]

157 77 187 94 180 112 163 155 1 0

10 24 17 0 0

24 104 56 88 46 0 0 0

69 11 14 92 53 88 66 26 0 0

18 102 173 45 112 168 45 1 0

157 101 135 0

188 91 185 98 175 0

79 24 86 107 0

150 36 129 107 106 0

110 76 189 0

147 16 151 186 0

24 64 100 0

74 185 67 89 0

88 58 181 0

29 47 63 34 0

189 172 85 0

73 21 145 0

125 112 120 37 0

3 10 98 0

9 154 58 0

136 84 5 0

118 89 147 0

98 100 161 0

37 143 0

131 138 157 0

118 41 87 0

188 146 0

190 15 12 0

112 180 0

41 191 76 0

139 33 132 0

110 8 127 0

102 4 69 0

150 92 0

82 146 14 0

51 41 0

154 83 48 0

61 2 165 81 0

151 132 0

63 152 86 0

0 151 0

79 144 33 0

[Equation 22]

157 77 187 94 180 112 163 155 1 0

10 24 17 0 0

24 104 56 88 46 0 0 0

69 11 14 92 53 88 66 26 0 0

18 102 173 45 112 168 45 1 0

157 101 135

188 91 185 98 175

79 24 86 107

150 36 129 107 106

110 76 189

147 16 151 186

24 64 100

74 185 67 89

88 58 181

29 47 63 34

189 172 85

73 21 145

125 112 120 37

3 10 98

9 154 58

136 84 5

118 89 147

98 100 161

37 143

131 138 157

118 41 87

188 146

190 15 12

112 180

41 191 76

139 33 132

110 8 127

102 4 69

150 92

82 146 14

51 41

154 83 48

61 2 165 81

151 132

63 152 86

0 151

79 144 33

As described above, the basic matrix and the exponential matrix can be expressed in various ways, and if column or row permutation is applied, by appropriately changing the position of the sequence or numbers in the sequence in Equations 18 to 23 above. can be expressed in the same way.

An example of designing a basic matrix and an exponential matrix through the design method proposed by the present invention will be described with reference to FIGS. 25 to 33 . The basic matrix and exponential matrix of FIGS. 25 to 33 are a basic matrix and an exponential matrix generated under the condition that a partial matrix of 22x32 size consisting of 22 rows from the top and 32 columns from the front in each basic matrix and exponential matrix is already fixed; is an exponential matrix. That is, the basic matrix of FIG. 25 is an example of a basic matrix designed by extending FIGS. 25G to 25I by applying the design method proposed by the present invention when FIGS. 25A to 25F are given and extending as shown in FIG. 25 . Similarly, in the case of FIGS. 26 to 33, it is an example of exponential matrices designed by extending through a method similar to that of FIG. As described above, it can be seen that the extended basic matrix or exponential matrix can be designed through the method proposed in the present invention even when a part of the basic matrix or the exponential matrix is fixed to a specific matrix or sequence in advance.

The basic matrix or exponential matrix of FIGS. 25 to 33 has a size of 42x52, and empty blocks of the exponential matrix typically correspond to a zero matrix of a ZxZ size, and may be expressed as a specific value such as -1.

Basically, each basic matrix and exponential matrices are designed in consideration of the conditions and methods such as Equations 15 to 17, but are not necessarily limited thereto. For example, the block size (Z) value included in the block size group of Equation 15 may be supported, and the block size group as shown in Equation 23 may be supported, and an appropriate part of Equation 23 A block size value included in the set may be used, or appropriate values may be added to the block size group (set) of Equation 15 or Equation 23 and used.

[Equation 23]

Z1'= {3, 6, 12, 24, 48, 96, 192, 384}

Z2'= {11, 22, 44, 88, 176, 352}

Z3'= {5, 10, 20, 40, 80, 160, 320}

Z4'= {9, 18, 36, 72, 144, 288}

Z5'= {2, 4, 8, 16, 32, 64, 128, 256}

Z6'= {15, 30, 60, 120, 240}

Z7'= {7, 14, 28, 56, 112, 224}

Z8'= {13, 26, 52, 104, 208}

Examples of the exponential matrix corresponding to the parity check matrix of the QC LDPC code designed based on Equations 15 to 17 or 23 are sequentially shown in FIGS. 26 to 33 . The exponential matrices of the LDPC code shown in FIGS. 26 to 33 all have the same basic matrix, and the basic matrix is that of FIG. 25 .

25A to 25I are enlarged views of the basic matrix of FIG. 25 by dividing each part. 25 corresponds to the matrix of the drawing corresponding to the reference number described in each part. Accordingly, FIGS. 25A to 25I may be combined to form one basic matrix.

26A to 26I are enlarged views of each part by dividing the exponential matrix of FIG. 26 . 26 corresponds to the matrix of the drawing corresponding to the reference number described in each part. Accordingly, FIGS. 26A to 26I may be combined to form one exponential matrix. 27 to 33 show only parts A, D and G of FIG. 26 . Parts B, C, E, F, H and I of FIGS. 27 to 33 are the same as parts B, C, E, F, H and I of FIG. 26 . That is, it is the same as shown in parts 26b, 26c, 26e, 26f, 26h and 26i. Using FIGS. 27 to 33 as parts A, D, and G, FIGS. 26b, 26c, 26e, 26f, 26h and 26i may be combined to form an exponential matrix.

The basic and exponential matrices of FIGS. 25 to 33 are basic and exponential matrices generated under the condition of a partial matrix of 22x32 size consisting of 22 rows from the top and 32 columns from the top in each basic matrix and exponential matrix. That is, it can be seen that the extended basic matrix or exponential matrix can be designed through the method proposed in the present invention even when a part of the basic matrix or the exponential matrix is fixed to a specific matrix or sequence in advance.

The basic matrix and the exponential matrix shown in FIGS. 25 to 33 can be expressed in various forms. For example, they can be expressed using a sequence as shown in Equation 24 below. Equation 24 represents the position of element 1 in the basic matrix of FIG. 25 for each row.

[Equation 24]

0 1 2 3 6 9 10 11

0 3 4 5 6 7 8 9 11 12

0 1 3 4 8 10 12 13

1 2 4 5 6 7 8 9 10 13

0 1 11 14

0 1 5 7 11 15

0 5 7 9 11 16

1 5 7 11 13 17

0 1 12 18

1 8 10 11 19

0 1 6 7 20

0 7 9 13 21

1 3 11 22

0 1 8 13 23

1 6 11 13 24

0 10 11 25

1 9 11 12 26

1 5 11 12 27

0 6 7 28

0 1 10 29

1 4 11 30

0 8 13 31

1 2 32

0 3 5 33

1 2 9 34

0 5 35

2 7 12 13 36

0 6 37

1 2 5 38

0 4 39

2 5 7 9 40

1 13 41

2 5 7 8 42

1 12 43

0 3 44

2 5 7 45

1 10 46

2 5 7 47

0 8 12 48

2 5 7 49

0 4 50

2 12 13 51

Equation 25 represents the position of element 1 in the basic matrix of FIG. 25 for each column.

[Equation 25]

0 1 2 4 5 6 8 10 11 13 15 18 19 21 23 25 27 29 34 38 40

0 2 3 4 5 7 8 9 10 12 13 14 16 17 19 20 22 24 28 31 33 36

0 3 22 24 26 28 30 32 35 37 39 41

0 1 2 12 23 34

1 2 3 20 29 40

1 3 5 6 7 17 23 25 28 30 32 35 37 39

0 1 3 10 14 18 27

1 3 5 6 7 10 11 18 26 30 32 35 37 39

1 2 3 9 13 21 32 38

0 1 3 6 11 16 24 30

0 2 3 9 15 19 36

0 1 4 5 6 7 9 12 14 15 16 17 20

1 2 8 16 17 26 33 38 41

2 3 7 11 13 14 21 26 31 41

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

If a certain rule can be found for a part of the base matrix, the base matrix may be expressed more simply. For example, in the case of having a diagonal structure from the 15th column to the last column as in the basic matrix of FIG. 25, assuming that the transceiver knows the corresponding rule, the position of the element or the element values may be omitted. .

For reference, with respect to the LDPC code that can be generated based on the basic matrix or the exponential matrix of FIGS. 25 to 33, a part of the information word bit is shortened appropriately and a part of the codeword bit is punctured to provide various code rates and various codes. LDPC encoding and decoding of length can be supported. For example, in the basic matrix and exponential matrix of FIGS. 25 to 33, after applying a shortening to some information word bits, the information word bits corresponding to the first two columns are always punctured, and when a part of the parity is punctured, various information word lengths are (or code block length) and various code rates can be supported.

In addition, when a variable information word length or a variable code rate is supported using shortening or zero padding of the LDPC code, it is possible to improve the performance of the code according to the shortening order or the shortening method. If the shortening order is preset, encoding performance may be improved by appropriately rearranging some or all of the basic matrix as described above. In addition, performance may be improved by appropriately determining the block size or the size of the column block to which the shortening is applied for a specific information word length (or code block length).

For example, 10 columns from the front correspond to information word bits (or code blocks) in FIGS. 25 to 33. When the number of columns required for LDPC encoding is Kb, an appropriate rule is applied as follows for shortening. Therefore, better performance can be obtained by determining the Kb and block size (Z) values.

if(CBS>640)

Kb=10;

elseif(CBS>=576)

Kb=9;

elseif(CBS>=200)

Kb=8;

else

if(CBS is member of [48,96,176,184,192])

Kb=7;

else

Kb=6;

end

end

In the above, CBS means information word bit length or code block length. When the Kb value is determined above, the block size (Z) value may be determined as a minimum value satisfying Z×Kb >= CBS. For example, Kb and the block size are determined as in Equation 26 below.

[Equation 26]

CBS=40 => Kb=6 => Z=7

CBS=48 => Kb=7 => Z=7

CBS=56 => Kb=6 => Z=10

CBS=64 => Kb=6 => Z=11

CBS=72 => Kb=6 => Z=12

CBS=80 => Kb=6 => Z=14

CBS=200 => Kb=8 => Z=26

CBS=640 => Kb=9 => Z=72

CBS=1024=> Kb=10 => Z=104

Depending on the system, the basic matrix or exponential matrix shown in FIGS. 25 to 33 may be used as it is, or only a part thereof may be used. For example, an LDPC basic matrix having a size of 22x32 different from the partial matrix except for a partial matrix of a size of 22x32 consisting of 22 rows and 32 columns from the front of the basic matrix of FIGS. 25 to 33 or each exponential matrix Alternatively, it may be used in a new basic matrix or an LDPC encoding and decoding method and apparatus based on an exponential matrix by concatenating the exponential matrix. For example, as shown in Equation (24) to Equation (27), a new basic matrix may be generated by concatenating it with another basic matrix using the following 20 numerical sequences.

[Equation 27]

1 2 32

0 3 5 33

1 2 9 34

0 5 35

2 7 12 13 36

0 6 37

1 2 5 38

0 4 39

2 5 7 9 40

1 13 41

2 5 7 8 42

1 12 43

0 3 44

2 5 7 45

1 10 46

2 5 7 47

0 8 12 48

2 5 7 49

0 4 50

2 12 13 51

As another example, a new basic matrix may be generated by concatenating the above 32 sequences and 10 other LDPC basic matrices or LDPC sequences as shown in Equation 28 in Equation 24 below, and LDPC encoding and decoding based on the basic matrix Applicable to the method and apparatus. For reference, as shown in Equation 28, it is noted that the sub-matrix of the basic matrix defined by selecting the above 32 sequences in Equation 24 is the same as the sub-matrix of the basic matrix defined by selecting the upper 32 rows in FIG. 25 .

When a new basic matrix is defined using a sequence corresponding to a partial matrix (or part of a sequence) of the LDPC basic matrix (or sequence) corresponding to FIG. 25 or Formula 24 as shown in Equations 27 and 28 above, In the LDPC exponential matrix corresponding to FIGS. 26 to 33, a new exponential matrix can also be generated by using only a part corresponding to the partial matrix (or a part of a sequence).

[Equation 28]

0 1 2 3 6 9 10 11

0 3 4 5 6 7 8 9 11 12

0 1 3 4 8 10 12 13

1 2 4 5 6 7 8 9 10 13

0 1 11 14

0 1 5 7 11 15

0 5 7 9 11 16

1 5 7 11 13 17

0 1 12 18

1 8 10 11 19

0 1 6 7 20

0 7 9 13 21

1 3 11 22

0 1 8 13 23

1 6 11 13 24

0 10 11 25

1 9 11 12 26

1 5 11 12 27

0 6 7 28

0 1 10 29

1 4 11 30

0 8 13 31

1 2 32

0 3 5 33

1 2 9 34

0 5 35

2 7 12 13 36

0 6 37

1 2 5 38

0 4 39

2 5 7 9 40

1 13 41

In general, a partial matrix formed by appropriately selecting rows and columns from the basic matrix and exponential matrix of FIGS. 25 to 33 may be applied as a new basic matrix and exponential matrix to be used in the LDPC encoding and decoding method and apparatus.

Although the present invention has been described in terms of a preferred embodiment, various changes and modifications may occur to those skilled in the art. Such changes and modifications are intended to be covered by the appended claims.

Claims (24)

In a method performed by a transmitter of a communication system or a broadcast system,
checking, by at least one processing unit, a block size;
identifying, by the at least one processing unit, a first matrix corresponding to the block size based on a base matrix;
Comprising the step of the at least one processing unit performing an encoding process based on the first matrix,
a column index of the base matrix corresponds to a non-zero element in a row of the base matrix;
A method, characterized in that a plurality of rows of the basic matrix have the following values as the column indices:
0, 1, 2, 3, 6, 9, 10, and 11 for one of the plurality of rows;
0, 3, 4, 5, 6, 7, 8, 9, 11, and 12 for one of said plurality of rows;
0, 1, 3, 4, 8, 10, 12, and 13 for one of the plurality of rows;
1, 2, 4, 5, 6, 7, 8, 9, 10, and 13 for one of said plurality of rows;
0, 1, 11, and 14 for one of the plurality of rows;
0, 1, 5, 7, 11, and 15 for one of the plurality of rows;
0, 5, 7, 9, 11, and 16 for one of the plurality of rows;
1, 5, 7, 11, 13, and 17 for one of the plurality of rows;
0, 1, 12, and 18 for one of the plurality of rows;
1, 8, 10, 11, and 19 for one of the plurality of rows;
0, 1, 6, 7, and 20 for one of the plurality of rows;
0, 7, 9, 13, and 21 for one of the plurality of rows;
1, 3, 11, and 22 for one of the plurality of rows;
0, 1, 8, 13, and 23 for one of the plurality of rows;
1, 6, 11, 13, and 24 for one of the plurality of rows;
0, 10, 11, and 25 for one of the plurality of rows;
1, 9, 11, 12, and 26 for one of the plurality of rows;
1, 5, 11, 12, and 27 for one of the plurality of rows;
0, 6, 7, and 28 for one of the plurality of rows;
0, 1, 10, and 29 for one of the plurality of rows;
1, 4, 11, and 30 for one of the plurality of rows;
0, 8, 13, and 31 for one of the plurality of rows;
1, 2, and 32 for one of the plurality of rows;
0, 3, 5, and 33 for one of the plurality of rows;
1, 2, 9, and 34 for one of the plurality of rows;
0, 5, and 35 for one of the plurality of rows;
2, 7, 12, 13, and 36 for one of the plurality of rows;
0, 6, and 37 for one of the plurality of rows;
1, 2, 5, and 38 for one of the plurality of rows;
0, 4, and 39 for one of the plurality of rows;
2, 5, 7, 9, and 40 for one of the plurality of rows, and
1, 13, and 41 for one of the plurality of rows. The method of claim 1, wherein the block size is ascertained based on a size of a bit sequence to be encoded. The method of claim 1, wherein the block size Z is selected from the following block size group:
Z1'= {3, 6, 12, 24, 48, 96, 192, 384}
Z2'= {11, 22, 44, 88, 176, 352}
Z3'= {5, 10, 20, 40, 80, 160, 320}
Z4'= {9, 18, 36, 72, 144, 288}
Z5'= {2, 4, 8, 16, 32, 64, 128, 256}
Z6'= {15, 30, 60, 120, 240}
Z7'= {7, 14, 28, 56, 112, 224}
Z8' = {13, 26, 52, 104, 208}. The method of claim 1, wherein the first matrix is identified by replacing a value of 1 in the base matrix with a second matrix. 5. The method of claim 4, wherein the second matrix is identified by cyclically moving an identity matrix based on a value determined by applying a modulo operation of a predetermined matrix element and the block size. A method characterized by being. 2. The method of claim 1, wherein the base matrix has 42 rows and 52 columns. In a method performed by a receiver of a communication system or a broadcast system,
checking, by at least one processing unit, a block size;
identifying, by the at least one processing unit, a first matrix corresponding to the block size based on a base matrix;
Comprising the step of the at least one processing unit performing a decoding process based on the first matrix,
a column index of the base matrix corresponds to a non-zero element in a row of the base matrix;
A method, characterized in that a plurality of rows of the basic matrix have the following values as the column indices:
0, 1, 2, 3, 6, 9, 10, and 11 for one of the plurality of rows;
0, 3, 4, 5, 6, 7, 8, 9, 11, and 12 for one of said plurality of rows;
0, 1, 3, 4, 8, 10, 12, and 13 for one of the plurality of rows;
1, 2, 4, 5, 6, 7, 8, 9, 10, and 13 for one of said plurality of rows;
0, 1, 11, and 14 for one of the plurality of rows;
0, 1, 5, 7, 11, and 15 for one of the plurality of rows;
0, 5, 7, 9, 11, and 16 for one of the plurality of rows;
1, 5, 7, 11, 13, and 17 for one of the plurality of rows;
0, 1, 12, and 18 for one of the plurality of rows;
1, 8, 10, 11, and 19 for one of the plurality of rows;
0, 1, 6, 7, and 20 for one of the plurality of rows;
0, 7, 9, 13, and 21 for one of the plurality of rows;
1, 3, 11, and 22 for one of the plurality of rows;
0, 1, 8, 13, and 23 for one of the plurality of rows;
1, 6, 11, 13, and 24 for one of the plurality of rows;
0, 10, 11, and 25 for one of the plurality of rows;
1, 9, 11, 12, and 26 for one of the plurality of rows;
1, 5, 11, 12, and 27 for one of the plurality of rows;
0, 6, 7, and 28 for one of the plurality of rows;
0, 1, 10, and 29 for one of the plurality of rows;
1, 4, 11, and 30 for one of the plurality of rows;
0, 8, 13, and 31 for one of the plurality of rows;
1, 2, and 32 for one of the plurality of rows;
0, 3, 5, and 33 for one of the plurality of rows;
1, 2, 9, and 34 for one of the plurality of rows;
0, 5, and 35 for one of the plurality of rows;
2, 7, 12, 13, and 36 for one of the plurality of rows;
0, 6, and 37 for one of the plurality of rows;
1, 2, 5, and 38 for one of the plurality of rows;
0, 4, and 39 for one of the plurality of rows;
2, 5, 7, 9, and 40 for one of the plurality of rows, and
1, 13, and 41 for one of the plurality of rows. 8. The method of claim 7, wherein the block size is determined based on a size of an encoded bit sequence. 8. The method of claim 7, wherein the block size Z is selected from the following block size group:
Z1'= {3, 6, 12, 24, 48, 96, 192, 384}
Z2'= {11, 22, 44, 88, 176, 352}
Z3'= {5, 10, 20, 40, 80, 160, 320}
Z4'= {9, 18, 36, 72, 144, 288}
Z5'= {2, 4, 8, 16, 32, 64, 128, 256}
Z6'= {15, 30, 60, 120, 240}
Z7'= {7, 14, 28, 56, 112, 224}
Z8' = {13, 26, 52, 104, 208}. 8. The method of claim 7, wherein the first matrix is identified by replacing a value of 1 in the base matrix with a second matrix. 11. The method of claim 10, wherein the second matrix is identified by cyclically moving an identity matrix based on a value determined by applying a modulo operation of a predetermined matrix element and the block size. A method characterized by being. 8. The method of claim 7, wherein the base matrix has 42 rows and 52 columns. In the transmitter of a communication system or a broadcasting system,
transceiver; and
At least one processing unit that checks the block size, identifies a first matrix corresponding to the block size based on a base matrix, and controls to perform an encoding process based on the first matrix including,
a column index of the base matrix corresponds to a non-zero element in a row of the base matrix;
A transmitter, characterized in that a plurality of rows of the base matrix have the following values as the column indices:
0, 1, 2, 3, 6, 9, 10, and 11 for one of the plurality of rows;
0, 3, 4, 5, 6, 7, 8, 9, 11, and 12 for one of said plurality of rows;
0, 1, 3, 4, 8, 10, 12, and 13 for one of the plurality of rows;
1, 2, 4, 5, 6, 7, 8, 9, 10, and 13 for one of said plurality of rows;
0, 1, 11, and 14 for one of the plurality of rows;
0, 1, 5, 7, 11, and 15 for one of the plurality of rows;
0, 5, 7, 9, 11, and 16 for one of the plurality of rows;
1, 5, 7, 11, 13, and 17 for one of the plurality of rows;
0, 1, 12, and 18 for one of the plurality of rows;
1, 8, 10, 11, and 19 for one of the plurality of rows;
0, 1, 6, 7, and 20 for one of the plurality of rows;
0, 7, 9, 13, and 21 for one of the plurality of rows;
1, 3, 11, and 22 for one of the plurality of rows;
0, 1, 8, 13, and 23 for one of the plurality of rows;
1, 6, 11, 13, and 24 for one of the plurality of rows;
0, 10, 11, and 25 for one of the plurality of rows;
1, 9, 11, 12, and 26 for one of the plurality of rows;
1, 5, 11, 12, and 27 for one of the plurality of rows;
0, 6, 7, and 28 for one of the plurality of rows;
0, 1, 10, and 29 for one of the plurality of rows;
1, 4, 11, and 30 for one of the plurality of rows;
0, 8, 13, and 31 for one of the plurality of rows;
1, 2, and 32 for one of the plurality of rows;
0, 3, 5, and 33 for one of the plurality of rows;
1, 2, 9, and 34 for one of the plurality of rows;
0, 5, and 35 for one of the plurality of rows;
2, 7, 12, 13, and 36 for one of the plurality of rows;
0, 6, and 37 for one of the plurality of rows;
1, 2, 5, and 38 for one of the plurality of rows;
0, 4, and 39 for one of the plurality of rows;
2, 5, 7, 9, and 40 for one of the plurality of rows, and
1, 13, and 41 for one of the plurality of rows. 14. The transmitter of claim 13, wherein the block size is ascertained based on a size of a bit sequence to be encoded. 14. The transmitter of claim 13, wherein the block size Z is selected from the following block size group:
Z1'= {3, 6, 12, 24, 48, 96, 192, 384}
Z2'= {11, 22, 44, 88, 176, 352}
Z3'= {5, 10, 20, 40, 80, 160, 320}
Z4'= {9, 18, 36, 72, 144, 288}
Z5'= {2, 4, 8, 16, 32, 64, 128, 256}
Z6'= {15, 30, 60, 120, 240}
Z7'= {7, 14, 28, 56, 112, 224}
Z8' = {13, 26, 52, 104, 208}. 14. The transmitter of claim 13, wherein the first matrix is identified by replacing a value of 1 in the base matrix with a second matrix. The method of claim 16, wherein the second matrix is identified by cyclically moving an identity matrix based on a value determined by applying a modulo operation of a predetermined matrix element and the block size. Transmitter characterized in that it becomes. 14. The transmitter of claim 13, wherein the base matrix has 42 rows and 52 columns. A receiver of a communication system or broadcast system, comprising:
transceiver; and
at least one processing unit that checks the block size, identifies a first matrix corresponding to the block size based on a base matrix, and controls to perform a decoding process based on the first matrix do,
a column index of the base matrix corresponds to a non-zero element in a row of the base matrix;
A receiver, characterized in that the plurality of rows of the base matrix have the following values as the column indexes:
0, 1, 2, 3, 6, 9, 10, and 11 for one of the plurality of rows;
0, 3, 4, 5, 6, 7, 8, 9, 11, and 12 for one of said plurality of rows;
0, 1, 3, 4, 8, 10, 12, and 13 for one of the plurality of rows;
1, 2, 4, 5, 6, 7, 8, 9, 10, and 13 for one of said plurality of rows;
0, 1, 11, and 14 for one of the plurality of rows;
0, 1, 5, 7, 11, and 15 for one of the plurality of rows;
0, 5, 7, 9, 11, and 16 for one of the plurality of rows;
1, 5, 7, 11, 13, and 17 for one of the plurality of rows;
0, 1, 12, and 18 for one of the plurality of rows;
1, 8, 10, 11, and 19 for one of the plurality of rows;
0, 1, 6, 7, and 20 for one of the plurality of rows;
0, 7, 9, 13, and 21 for one of the plurality of rows;
1, 3, 11, and 22 for one of the plurality of rows;
0, 1, 8, 13, and 23 for one of the plurality of rows;
1, 6, 11, 13, and 24 for one of the plurality of rows;
0, 10, 11, and 25 for one of the plurality of rows;
1, 9, 11, 12, and 26 for one of the plurality of rows;
1, 5, 11, 12, and 27 for one of the plurality of rows;
0, 6, 7, and 28 for one of the plurality of rows;
0, 1, 10, and 29 for one of the plurality of rows;
1, 4, 11, and 30 for one of the plurality of rows;
0, 8, 13, and 31 for one of the plurality of rows;
1, 2, and 32 for one of the plurality of rows;
0, 3, 5, and 33 for one of the plurality of rows;
1, 2, 9, and 34 for one of the plurality of rows;
0, 5, and 35 for one of the plurality of rows;
2, 7, 12, 13, and 36 for one of the plurality of rows;
0, 6, and 37 for one of the plurality of rows;
1, 2, 5, and 38 for one of the plurality of rows;
0, 4, and 39 for one of the plurality of rows;
2, 5, 7, 9, and 40 for one of the plurality of rows, and
1, 13, and 41 for one of the plurality of rows. 20. The receiver of claim 19, wherein the block size is ascertained based on a size of an encoded bit sequence. 20. The receiver of claim 19, wherein the block size Z is selected from the following block size group:
Z1'= {3, 6, 12, 24, 48, 96, 192, 384}
Z2'= {11, 22, 44, 88, 176, 352}
Z3'= {5, 10, 20, 40, 80, 160, 320}
Z4'= {9, 18, 36, 72, 144, 288}
Z5'= {2, 4, 8, 16, 32, 64, 128, 256}
Z6'= {15, 30, 60, 120, 240}
Z7'= {7, 14, 28, 56, 112, 224}
Z8' = {13, 26, 52, 104, 208}. 20. The receiver of claim 19, wherein the first matrix is identified by replacing a value of 1 in the base matrix with a second matrix. 23. The method of claim 22, wherein the second matrix is identified by cyclically moving an identity matrix based on a value determined by applying a modulo operation of a predetermined matrix element and the block size. A receiver, characterized in that it becomes. 20. The receiver of claim 19, wherein the base matrix has 42 rows and 52 columns.

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