KR102296062B1 - Semiconductor integrated circuit and method of manufacturing the same - Google Patents

Abstract

The semiconductor integrated circuit includes first and second active regions, first through fourth gate structures, and first through fourth contacts. The first and second active regions are defined by a device isolation layer formed on the substrate, respectively extend in a first direction and spaced apart from each other in a second direction substantially perpendicular to the first direction, and are formed of impurities of different conductivity types. each doped. The first and third gate structures are spaced apart from each other in the first direction to extend in the second direction, respectively, and are respectively formed on the first active region and the first portion of the isolation layer between the first and second active regions . The second and fourth gate structures are spaced apart from each other in the first direction to extend in the second direction, respectively, are respectively formed on the second active region and the first portion of the isolation layer, and the first and third gate structures along the second direction The gate structures face each other and are spaced apart from each other. The first to fourth contacts are respectively formed on portions of the first to fourth gate structures formed on the first portion of the isolation layer. The first and fourth contacts are electrically connected to each other, and the second and third contacts are electrically connected to each other. The first and third contacts are spaced apart from the first active region by a substantially equal distance along the second direction, and the second and fourth contacts are spaced apart from the second active region by a substantially equal distance along the second direction.

Description

Semiconductor integrated circuit and manufacturing method thereof

The present invention relates to a semiconductor integrated circuit and a method for manufacturing the same. More particularly, the present invention relates to a semiconductor integrated circuit including a clock latch circuit and a method of manufacturing the same.

To implement a clock latch circuit, a PMOS gate and an NMOS gate must be cross-connected to each other. For this, a dummy gate can be used, but in this case Since the area increases, it is not preferable. Accordingly, there is a need for a method of implementing a clock latch circuit without increasing an area.

SUMMARY OF THE INVENTION One object of the present invention is to provide a semiconductor integrated circuit including a clock latch circuit implemented in a small area.

Another object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit including the clock latch circuit.

A semiconductor integrated circuit according to example embodiments may include first and second active regions, first to fourth gate structures, and first to fourth contacts. The first and second active regions are defined by a device isolation layer formed on the substrate, respectively extend in a first direction and spaced apart from each other in a second direction substantially perpendicular to the first direction, and have impurities of different conductivity types. are each doped with The first and third gate structures are spaced apart from each other in the first direction and extend in the second direction, respectively, in the first active region and in the isolation layer between the first and second active regions. formed on each part. The second and fourth gate structures are spaced apart from each other in the first direction to extend in the second direction, respectively, are formed on the second active region and the first portion of the isolation layer, respectively, in the second direction Accordingly, the first and third gate structures face each other and are spaced apart from each other. The first to fourth contacts are respectively formed on portions of the first to fourth gate structures formed on the first portion of the isolation layer. The first and fourth contacts are electrically connected to each other, and the second and third contacts are electrically connected to each other. The first and third contacts are spaced apart from the first active region by a substantially equal distance along the second direction, and the second and fourth contacts are spaced apart from the first active region by substantially the same distance along the second direction. separated by the same distance.

In example embodiments, the first active region may be doped with a p-type impurity, and the second active region may be doped with an n-type impurity.

In example embodiments, the first and fourth contacts may be electrically connected to each other by a first lower wiring commonly formed thereon.

In example embodiments, the semiconductor integrated circuit includes a second lower interconnection formed on the second contact, a third lower interconnection formed on the third contact, a first via formed on the second lower interconnection, and the It may further include a second via formed on the third lower interconnection, and a first upper interconnection commonly connected to the first and second vias. In this case, the second and third contacts may be electrically connected to each other by the second and third lower wirings, the first and second vias, and the first upper wiring.

In example embodiments, the semiconductor integrated circuit may include first and third impurity regions formed on both sides of the first gate structure on both sides of the first active region and doped with impurities of a first conductivity type, and The second and fourth impurity regions respectively formed on both sides of the second gate structure and doped with impurities of the second conductivity type may be further included.

In example embodiments, the semiconductor integrated circuit may further include fifth and sixth contacts respectively formed on the first and second impurity regions and electrically connected to each other.

In example embodiments, the semiconductor integrated circuit includes a fourth lower interconnection formed on the fifth contact, a fifth lower interconnection formed on the sixth contact, a third via formed on the fourth lower interconnection, and the A fourth via formed on the fifth lower interconnection and a second upper interconnection commonly connected to the third and fourth vias may be further included. In this case, the fifth and sixth contacts may be electrically connected to each other by the fourth and fifth lower interconnections, the third and fourth vias, and the second upper interconnection.

In example embodiments, the semiconductor integrated circuit may further include seventh and eighth contacts respectively formed on the third and fourth impurity regions and electrically connected to each other.

In example embodiments, the semiconductor integrated circuit includes a sixth lower interconnection formed on the seventh contact, a seventh lower interconnection formed on the eighth contact, a fifth via formed on the sixth lower interconnection, and the A sixth via formed on the seventh lower interconnection and a third upper interconnection commonly connected to the fifth and sixth vias may be further included. In this case, the seventh and eighth contacts may be electrically connected to each other by the sixth and seventh lower interconnections, the fifth and sixth vias, and the third upper interconnection.

In example embodiments, the semiconductor integrated circuit is spaced apart from the third gate structure in the first direction and extends in the second direction, and is formed on the first active region and the first portion of the isolation layer. A fifth gate structure and a sixth gate structure spaced apart from the fourth gate structure in the first direction and extending in the second direction, the sixth gate structure formed on the second active region and the first portion of the isolation layer can In this case, the fifth and sixth gate structures may be connected to each other on the first portion of the isolation layer to extend in the second direction as a whole.

In example embodiments, the semiconductor integrated circuit may include fifth and seventh impurity regions formed on both sides of the fifth gate structure on both sides of the first active region and doped with impurities of a first conductivity type; and sixth and eighth impurity regions formed on both sides of the sixth gate structure, respectively, on the second active region and doped with impurities of the second conductivity type.

In example embodiments, the semiconductor integrated circuit may further include a ninth contact formed on the seventh impurity region to which a power voltage is applied, and a tenth contact formed on the eighth impurity region to be grounded. can

In example embodiments, the semiconductor integrated circuit further includes an eighth lower wiring formed on the ninth contact to apply the power supply voltage, and a ninth lower wiring formed on the tenth contact to be grounded. may include

In example embodiments, the semiconductor integrated circuit is spaced apart from the fifth gate structure in the first direction and extends in the second direction, and is formed on the first active region and the first portion of the isolation layer. a seventh gate structure, and an eighth gate structure spaced apart from the sixth gate structure in the first direction and extending in the second direction, the eighth gate structure formed on the second active region and the first portion of the isolation layer can In this case, the seventh and eighth gate structures may be connected to each other on the first portion of the isolation layer to extend in the second direction as a whole.

In example embodiments, the semiconductor integrated circuit may include first and third impurity regions formed on both sides of the first gate structure on both sides of the first active region and doped with impurities of a first conductivity type; on second and fourth impurity regions respectively formed on the second active region on both sides of the second gate structure and doped with impurities of a second conductivity type, and on the seventh gate structure or the eighth gate structure It may further include an eleventh contact formed. In this case, the eleventh contact may be electrically connected to the third and fourth impurity regions.

In example embodiments, the semiconductor integrated circuit may further include a ninth impurity region formed on the second active region adjacent to the eighth gate structure and doped with an impurity of the second conductivity type. have. In this case, the ninth impurity region may be electrically connected to the fifth gate structure or the sixth gate structure.

In example embodiments, a clock signal may be applied to each of the first to fourth gate structures.

In example embodiments, a first clock signal may be applied to the second and third gate structures, and a second clock signal may be applied to the first and fourth gate structures.

In example embodiments, the second gate structure may also extend on a second portion of the device isolation layer opposite to the first portion of the device isolation layer in the second direction with respect to the second active region. can In this case, the semiconductor integrated circuit includes a twelfth contact formed on the second gate structure portion formed on the second portion of the isolation layer, a tenth lower wiring formed on the twelfth contact, and a tenth lower wiring formed on the tenth lower wiring The display device may further include a seventh via and a fourth upper interconnection formed on the seventh via and extending in the first direction, to which the first clock signal is applied.

In example embodiments, the first gate structure may also extend on a third portion of the device isolation layer opposite to the first portion of the device isolation layer in the second direction with respect to the first active region. can In this case, the semiconductor integrated circuit includes a thirteenth contact formed on the first gate structure portion formed on the third portion of the isolation layer, an eleventh lower wiring formed on the thirteenth contact, and an eleventh lower wiring formed on the eleventh lower wiring. The apparatus may further include an eighth via and a fifth upper interconnection formed on the eighth via and extending in the first direction, to which the second clock signal is applied.

A semiconductor integrated circuit according to other embodiments of the present invention may include first and second active regions, first to fourth gate structures, and first to fourth contacts. The first and second active regions are defined by a device isolation layer formed on the substrate, respectively extend in a first direction and spaced apart from each other in a second direction substantially perpendicular to the first direction, and have impurities of different conductivity types. are each doped with The first and third gate structures are spaced apart from each other in the first direction to extend in the second direction, respectively, and are respectively formed on the first active region and a portion of the device isolation layer adjacent thereto. The second and fourth gate structures are spaced apart from each other in the first direction to extend in the second direction, respectively, and are respectively formed on the second active region and a portion of the device isolation layer adjacent thereto, along the second direction. The first and third gate structures face each other and are spaced apart from each other. The first to fourth contacts are respectively formed on portions of the first to fourth gate structures formed on the isolation layer. The first and fourth contacts are electrically connected to each other, and the second and third contacts are electrically connected to each other. The first and third contacts are spaced apart from one boundary of the first active region by substantially the same distance in the second direction, and the second and fourth contacts are spaced apart from one boundary of the second active region by the second active region. are spaced apart by substantially equal distances along the two directions.

In example embodiments, the first active region may include first and second boundaries along the second direction, and the second active region includes third and fourth boundaries along the second direction. may include, and the first and third boundaries may face each other.

In example embodiments, each of the first and third contacts may be formed closer to the second boundary than the first boundary of the first active region, and each of the second and fourth contacts may be formed to be adjacent to the first boundary. The second active region may be formed closer to the fourth boundary than to the third boundary.

In example embodiments, each of the first and third contacts may be formed closer to the first boundary than the second boundary of the first active region, and each of the second and fourth contacts may be formed to be adjacent to the first boundary. The second active region may be formed closer to the fourth boundary than to the third boundary.

In example embodiments, each of the first and third contacts may be formed closer to the second boundary than the first boundary of the first active region, and each of the second and fourth contacts may be formed to be adjacent to the first boundary. The second active region may be formed closer to the third boundary than the fourth boundary.

In example embodiments, each of the first and third contacts may be formed closer to the first boundary than the second boundary of the first active region, and each of the second and fourth contacts may be formed to be adjacent to the first boundary. The second active region may be formed closer to the third boundary than the fourth boundary.

In example embodiments, the first and fourth contacts may be electrically connected to each other by a first lower wiring commonly formed thereon.

In example embodiments, the semiconductor integrated circuit includes a second lower interconnection formed on the second contact, a third lower interconnection formed on the third contact, a first via formed on the second lower interconnection, and the It may further include a second via formed on the third lower interconnection, and a first upper interconnection commonly connected to the first and second vias. In this case, the second and third contacts may be electrically connected to each other by the second and third lower wirings, the first and second vias, and the first upper wiring.

In example embodiments, the semiconductor integrated circuit may include first and third impurity regions formed on both sides of the first gate structure on both sides of the first active region and doped with impurities of a first conductivity type; and second and fourth impurity regions respectively formed on both sides of the second gate structure on both sides of the second active region and doped with impurities of a second conductivity type.

In example embodiments, the first and second impurity regions may be electrically connected to each other, and the third and fourth impurity regions may be electrically connected to each other.

In example embodiments, the semiconductor integrated circuit is spaced apart from the third gate structure in the first direction and extends in the second direction, and a fifth gate is formed on the first active region and the isolation layer. and a sixth gate structure spaced apart from the fourth gate structure in the first direction and extending in the second direction, the sixth gate structure being formed on the second active region and the device isolation layer. In this case, the fifth and sixth gate structures may be connected to each other on a portion of the isolation layer between the first and second active regions to extend in the second direction as a whole.

In example embodiments, the semiconductor integrated circuit may include fifth and seventh impurity regions formed on both sides of the fifth gate structure on both sides of the first active region and doped with impurities of a first conductivity type; and sixth and eighth impurity regions respectively formed on the second active regions on both sides of the sixth gate structure and doped with impurities of the second conductivity type.

In example embodiments, a power voltage may be applied to the seventh impurity region, and the eighth impurity region may be grounded.

In example embodiments, the semiconductor integrated circuit is spaced apart from the fifth gate structure in the first direction and extends in the second direction, and a seventh gate is formed on the first active region and the device isolation layer. and an eighth gate structure spaced apart from the sixth gate structure in the first direction and extending in the second direction, the eighth gate structure being formed on the second active region and the device isolation layer. In this case, the seventh and eighth gate structures may be formed to be connected to each other on a portion of the isolation layer between the first and second active regions, and may extend in the second direction as a whole.

In example embodiments, the semiconductor integrated circuit may include first and third impurity regions formed on both sides of the first gate structure on both sides of the first active region and doped with impurities of a first conductivity type; and second and fourth impurity regions respectively formed on both sides of the second gate structure on both sides of the second active region and doped with impurities of a second conductivity type. In this case, the seventh and eighth gate structures may be electrically connected to the third and fourth impurity regions.

In example embodiments, the semiconductor integrated circuit may further include a ninth impurity region formed on the second active region adjacent to the eighth gate structure and doped with an impurity of the second conductivity type. have. In this case, the ninth impurity region may be electrically connected to the fifth and sixth gate structures.

In example embodiments, a first clock signal may be applied to the second and third gate structures, and a second clock signal may be applied to the first and fourth gate structures.

A semiconductor integrated circuit according to other embodiments of the present invention may include first and second active regions, first to eighth gate structures, and first to fourth contacts. The first and second active regions are defined by a device isolation layer formed on the substrate, respectively extend in a first direction and spaced apart from each other in a second direction substantially perpendicular to the first direction, and have impurities of different conductivity types. are each doped with The first and third gate structures are spaced apart from each other in the first direction to extend in the second direction, respectively, and are respectively formed on the first active region and a portion of the device isolation layer adjacent thereto. The second and fourth gate structures are spaced apart from each other in the first direction to extend in the second direction, respectively, and are respectively formed on the second active region and a portion of the device isolation layer adjacent thereto, along the second direction. The first and third gate structures face each other and are spaced apart from each other. The fifth gate structure is spaced apart from the third gate structure in the first direction and extends in the second direction, and is formed on the first active region and the isolation layer. The sixth gate structure is spaced apart from the fourth gate structure in the first direction and extends in the second direction, and is formed on the second active region and the device isolation layer. The seventh gate structure is spaced apart from the fifth gate structure in the first direction and extends in the second direction, and is formed on the first active region and the isolation layer. The eighth gate structure is spaced apart from the sixth gate structure in the first direction and extends in the second direction, and is formed on the second active region and the device isolation layer. The first to fourth contacts are respectively formed on portions of the first to fourth gate structures formed on the isolation layer. The fifth and sixth gate structures are connected to each other on a portion of the isolation layer between the first and second active regions to extend in the second direction as a whole, and the seventh and eighth gate structures are formed between the first and second active regions. The second active regions are connected to each other on a portion of the isolation layer between the second active regions and extend in the second direction as a whole. The first and fourth contacts are electrically connected to each other, and the second and third contacts are electrically connected to each other, and the first and third contacts extend in the second direction from one boundary of the first active region. are spaced apart from each other by a substantially equal distance, and the second and fourth contacts are spaced apart from one boundary of the second active region by a substantially equal distance along the second direction.

In example embodiments, the semiconductor integrated circuit may include first and third impurity regions formed on both sides of the first gate structure on both sides of the first active region and doped with impurities of a first conductivity type; and second and fourth impurity regions respectively formed on both sides of the second gate structure on both sides of the second active region and doped with impurities of a second conductivity type. In this case, the first and second impurity regions may be electrically connected to each other, and the third and fourth impurity regions may be electrically connected to each other.

In example embodiments, the seventh and eighth gate structures may be electrically connected to the third and fourth impurity regions.

In example embodiments, the semiconductor integrated circuit may include fifth and seventh impurity regions formed on both sides of the fifth gate structure on both sides of the first active region and doped with impurities of a first conductivity type; and sixth and eighth impurity regions formed on both sides of the sixth gate structure, respectively, on the second active region and doped with impurities of the second conductivity type. In this case, a power voltage may be applied to the seventh impurity region, and the eighth impurity region may be grounded.

In example embodiments, the semiconductor integrated circuit may further include a ninth impurity region formed on the second active region adjacent to the eighth gate structure and doped with an impurity of the second conductivity type. have. In this case, the ninth impurity region may be electrically connected to the fifth and sixth gate structures.

In example embodiments, a first clock signal may be applied to the second and third gate structures, and a second clock signal may be applied to the first and fourth gate structures.

In the method of manufacturing a semiconductor integrated circuit according to exemplary embodiments for achieving another object of the present invention, a device isolation layer is formed on a substrate, each extending in a first direction and substantially perpendicular to the first direction First and second active regions spaced apart from each other in the second direction are defined. First and third gate structures spaced apart from each other in the first direction and extending in the second direction are formed on the first active region and a portion of the isolation layer adjacent thereto, and spaced apart from each other in the first direction. The second and fourth gate structures respectively extending in the second direction face the first and third gate structures in the second direction on the second active region and the portion of the isolation layer adjacent thereto, respectively. formed to be spaced apart from each other. First to fourth contacts are respectively formed on portions of the first to fourth gate structures formed on the isolation layer. The first and fourth contacts are electrically connected to each other, and the second and third contacts are electrically connected to each other. The first and third contacts are formed to be spaced apart from the first active region by a substantially equal distance in the second direction, and the second and fourth contacts are formed to be spaced apart from the first active region by a substantially equal distance in the second direction. They are formed to be spaced apart by substantially the same distance.

In example embodiments, after forming the first to fourth gate structures, a p-type impurity is doped over the first active region adjacent to the first and third gate structures, and the first to fourth gate structures are doped. An n-type impurity may be doped over the second active region adjacent to the second and fourth gate structures.

In example embodiments, when the first and fourth contacts are electrically connected to each other, a first lower interconnection may be formed on the first and fourth contacts.

In example embodiments, when the second and third contacts are electrically connected to each other, second and third lower interconnections are respectively formed on the second and third contacts, and the second and third contacts are respectively formed. First and second vias may be respectively formed on the lower interconnections, and a first upper interconnection may be formed on the first and second vias.

In example embodiments, after the first to fourth gate structures are formed, first and third impurities of a first conductivity type are doped over the first active region on both sides of the first gate structure. Impurity regions may be respectively formed, and second and fourth impurity regions may be respectively formed by doping an impurity of a second conductivity type on the second active region on both sides of the second gate structure.

In example embodiments, after forming the first to fourth impurity regions, fifth and sixth contacts are respectively formed on the first and second impurity regions, and the fifth and sixth contacts are respectively formed. Fourth and fifth lower interconnections are respectively formed on the contacts, third and fourth vias are respectively formed on the fourth and fifth lower interconnections, and second and second vias are formed on the third and fourth vias, respectively. An upper wiring may be formed.

In example embodiments, after forming the first to fourth impurity regions, seventh and eighth contacts are respectively formed on the third and fourth impurity regions, and the seventh and eighth contacts are respectively formed. Sixth and seventh lower interconnections are formed on the contacts, respectively, fifth and sixth vias are formed on the sixth and seventh lower interconnections, respectively, and third and third vias are formed on the fifth and sixth vias, respectively. An upper wiring may be formed.

A semiconductor integrated circuit according to example embodiments may include a PMOS gate and an NMOS gate that are alternately connected to each other through a contact, a lower interconnection, a via, and/or an upper interconnection. Accordingly, a circuit including a PMOS gate and an NMOS gate that are alternately connected to each other, for example, a clock latch circuit, may be easily implemented without increasing the area thereof.

However, the effects of the present invention are not limited to the above-mentioned effects, and may be variously expanded without departing from the spirit and scope of the present invention.

1 is an equivalent circuit diagram of a semiconductor integrated circuit according to exemplary embodiments, and FIGS. 2A, 2B, 2C and 3 are plan views according to exemplary embodiments for explaining the layout of region X shown in FIG. 1 . .
4 to 6 are plan views according to other embodiments for explaining the layout of the X region shown in FIG. 1 .
7 to 38 are plan views and cross-sectional views for explaining steps of a method of manufacturing a semiconductor integrated circuit according to example embodiments.

With respect to the embodiments of the present invention disclosed in the text, specific structural or functional descriptions are only exemplified for the purpose of describing the embodiments of the present invention, and the embodiments of the present invention may be embodied in various forms. It should not be construed as being limited to the embodiments described in .

Since the present invention can have various changes and can have various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention.

Terms such as first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The above terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component.

When a component is referred to as being “connected” or “connected” to another component, it is understood that the other component may be directly connected or connected to the other component, but other components may exist in between. it should be On the other hand, when it is mentioned that a certain element is "directly connected" or "directly connected" to another element, it should be understood that the other element does not exist in the middle. Other expressions describing the relationship between elements, such as "between" and "immediately between" or "neighboring to" and "directly adjacent to", should be interpreted similarly.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present application, terms such as “comprise” or “have” are intended to designate that the described feature, number, step, operation, component, part, or combination thereof exists, and includes one or more other features or numbers. , it is to be understood that it does not preclude the possibility of the presence or addition of steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as meanings consistent with the context of the related art, and unless explicitly defined in the present application, they are not to be interpreted in an ideal or excessively formal meaning. .

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and repeated descriptions of the same components are omitted.

1 is an equivalent circuit diagram of a semiconductor integrated circuit according to exemplary embodiments, and FIGS. 2A, 2B, 2C, and 3 are plan views according to exemplary embodiments for explaining the layout of region X shown in FIG. 1 . .

In example embodiments, the semiconductor integrated circuit may be a clock latch circuit, and accordingly, two circuits included in the X region may be serially connected to each other. Hereinafter, for convenience of explanation, only the layout of the structure in which the circuit in the X region is implemented will be described. Also, some components of the semiconductor integrated circuit, for example, spacers, are not shown in FIGS. 2 to 6 for convenience of description.

Referring first to FIGS. 1 and 2A , the semiconductor integrated circuit includes first and second active regions 102 and 104 , an isolation layer 110 , and first to fourth gate structures formed on a substrate 100 . 151 , 152 , 153 , 154 , and first to fourth contacts 281 , 282 , 283 , 284 .

In addition, the semiconductor integrated circuit includes fifth to eighth gate structures 155 , 156 , 157 , 158 , and first to tenth impurity regions 221 , 222 , 223 , 224 , 225 , 226 , 227 , 228 , 229 . , 230), fifth to fifteenth contacts 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, first to twelfth lower interconnections 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312), first through eighth vias (341, 342, 343, 344, 345, 346, 347, 348), first through It may further include fifth upper wirings 351 , 352 , 353 , 354 , and 355 .

Further, the semiconductor integrated circuit includes ninth and tenth gate structures 190 and 195 , eleventh to fourteenth impurity regions 241 , 242 , 245 , and 246 , and a first interlayer insulating layer 250 ( FIGS. 15 to FIG. 15 ). 17), the second interlayer insulating layer 320 (refer to FIGS. 25 to 28), and the first to tenth spacers 201, 202, 203, 204, 205, 206, 207, 208, 210, 215, and 12 to FIG. 14) may be further included.

The substrate 100 may include a semiconductor material such as silicon, germanium, silicon-germanium, or the like, or a group III-V compound such as GaP, GaAs, or GaSb. According to some embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

According to the device isolation layer 110 formed on the substrate 100 , the substrate 100 has a field region whose upper surface is covered by the device isolation layer 110 , and first and second fields whose upper surface is not covered by the device isolation layer 110 . Two active regions 102 and 104 may be defined. The device isolation layer 110 may include, for example, an oxide such as silicon oxide.

The first and second active regions 102 and 104 may each extend in a first direction parallel to the top surface of the substrate 100 , and may be parallel to the top surface of the substrate 100 and substantially perpendicular to the first direction. They may be spaced apart from each other in two directions.

At this time, at least a portion of each of the first and second active regions 102 and 104 may be doped with impurities, and the first and second active regions 102 and 104 are each made of impurities of different conductivity types. may be doped. In example embodiments, the first, third, fifth, seventh, ninth, eleventh, and thirteenth impurity regions 221 , 223 , 225 , 227 , 229 , 241 , and 245 may be formed by doping with p-type impurities such as boron and aluminum, for example, and second, fourth, sixth, eighth, The tenth, twelfth, and fourteenth impurity regions 222 , 224 , 226 , 228 , 230 , 242 , and 246 may be formed by doping with, for example, n-type impurities such as phosphorus and arsenic. Accordingly, the first active region 102 may be a positive-channel metal oxide semiconductor (PMOS) region in which p-type transistors are formed, and the second active region 104 is an NMOS region in which n-type transistors are formed. (Negative-channel Metal Oxide Semiconductor: NMOS) region.

The first and third gate structures 151 and 153 may be spaced apart from each other in the first direction to extend in the second direction, respectively, and include the first active region 102 and the first and second active regions. They may be respectively formed on the first portion of the device isolation layer 110 formed between 102 and 104 . However, each of the first and third gate structures 151 and 153 further extends in the second direction, so that the first and second gate structures of the device isolation layer 110 are formed along the second direction with respect to the first active region 102 . It may also be formed on a third portion of the device isolation layer 110 formed opposite to the first portion.

The second and fourth gate structures 152 and 154 may be spaced apart from each other in the first direction to extend in the second direction, respectively, and include a second active region 104 and the first and second active regions. They may be respectively formed on the first portion of the device isolation layer 110 formed between 102 and 104 . However, each of the second and fourth gate structures 152 and 154 further extends in the second direction, so that the second gate structure of the isolation layer 110 is formed along the second direction with respect to the second active region 104 . It may also be formed on the second portion of the device isolation layer 110 formed opposite to the first portion.

In example embodiments, the second and fourth gate structures 152 and 154 may face the first and third gate structures 151 and 153 along the second direction, respectively, and may be spaced apart from each other. .

The fifth gate structure 155 may be spaced apart from the third gate structure 153 in the first direction and extend in the second direction, and may include the first active region 102 and the first isolation layer 110 . may be formed on the part. In this case, the fifth gate structure 155 also extends further in the second direction, and is formed on the opposite side of the first portion of the device isolation layer 110 in the second direction with respect to the first active region 102 . It may also be formed on the third portion of the separation membrane 110 .

The sixth gate structure 156 may be spaced apart from the fourth gate structure 154 in the first direction to extend in the second direction, and may include the second active region 104 and the first isolation layer 110 . may be formed on the part. In this case, the sixth gate structure 156 also extends further in the second direction, so that the device formed on the opposite side of the first portion of the device isolation layer 110 in the second direction with respect to the second active region 104 . It may also be formed on the second portion of the separation membrane 110 .

In example embodiments, the fifth and sixth gate structures 155 and 156 may be connected to each other on the first portion of the isolation layer 110 to extend in the second direction as a whole.

The seventh gate structure 157 may be spaced apart from the fifth gate structure 155 in the first direction to extend in the second direction, and may include the first active region 102 and the first isolation layer 110 . may be formed on the part. In this case, the seventh gate structure 157 also extends further in the second direction, and is formed on the opposite side of the first portion of the device isolation layer 110 in the second direction with respect to the first active region 102 . It may also be formed on the third portion of the separation membrane 110 .

The eighth gate structure 158 may be spaced apart from the sixth gate structure 156 in the first direction to extend in the second direction, and may include the second active region 104 and the first isolation layer 110 . may be formed on the part. In this case, the eighth gate structure 158 also extends further in the second direction, and is formed on the opposite side of the first portion of the device isolation layer 110 in the second direction with respect to the second active region 104 . It may also be formed on the second portion of the separation membrane 110 .

In example embodiments, the seventh and eighth gate structures 157 and 158 may be connected to each other on the first portion of the isolation layer 110 to extend in the second direction as a whole.

Meanwhile, the ninth gate structure 190 may extend in the second direction to be formed on the first and second active regions 102 and 104 and the device isolation layer 110 . In this case, the ninth gate structure 190 is a first gate structure opposite to the third and fourth gate structures 153 and 154 in the first direction with respect to the first and second gate structures 151 and 152 . and the second gate structures 151 and 152 may be formed to be spaced apart from each other. In addition, the tenth gate structure 195 may extend in the second direction to be formed on the first and second active regions 102 and 104 and the device isolation layer 110 . In this case, the tenth gate structure 195 is a seventh gate structure opposite to the fifth and sixth gate structures 155 and 156 in the first direction with respect to the seventh and eighth gate structures 157 and 158 . and the eighth gate structures 157 and 158 may be formed to be spaced apart.

As described above, the ninth, first, third, fifth, seventh, and tenth gate structures 190 , 151 , 153 , 155 , 157 , and 195 are formed in the first active region 102 and adjacent thereto. The device isolation layer 110 may be disposed along the first direction, and in this case, the distance between them may be constant or different from each other. Similarly, the ninth, second, fourth, sixth, eighth, and tenth gate structures 190 , 152 , 154 , 156 , 158 , and 195 form the second active region 104 and the device isolation layer adjacent thereto. 110) may be disposed along the first direction on the portion, and an interval therebetween may be constant or different.

Although the first to eighth gate structures 151 , 152 , 153 , 154 , 155 , 156 , 157 , and 158 directly correspond to devices included in the equivalent circuit diagram of FIG. 1 , the ninth and tenth gate structures (190, 195) may not. That is, the ninth and tenth gate structures 190 and 195 may not necessarily correspond to respective devices included in the clock latch circuit, or may correspond to devices included in other circuits connected to the clock latch circuit. have.

Meanwhile, each of the gate structures 151 , 152 , 153 , 154 , 155 , 156 , 157 , 158 , 190 , and 195 has a gate insulating layer pattern, a gate electrode, and a gate mask formed on the substrate 100 and the device isolation layer 110 . may include. In this case, the gate insulating layer pattern may be formed only on the active regions 102 and 104 of the substrate 100 , or may be formed on the device isolation layer 110 as well as the active regions 102 and 104 . The drawing illustrates that the gate insulating layer pattern is formed only on the active regions 102 and 104 of the substrate 100 .

Referring to FIGS. 10, 11, 13, and 14 along with FIGS. 1 and 2A , the first gate structure 151 includes a first gate insulating layer pattern 121 , a first gate electrode 131 , and a first sequentially stacked first gate structure 151 . The gate mask 141 may be included, and the second gate structure 152 may include the sequentially stacked second gate insulating layer pattern 122 , the second gate electrode 132 , and the second gate mask 142 . can The third gate structure 153 may include a third gate insulating layer pattern 123 , a third gate electrode 133 , and a third gate mask 143 that are sequentially stacked, and the fourth gate structure 154 is A fourth gate insulating layer pattern 124 , a fourth gate electrode 134 , and a fourth gate mask 144 may be sequentially stacked. The fifth gate structure 155 may include a fifth gate insulating layer pattern 125 , a fifth gate electrode 135 , and a fifth gate mask 145 that are sequentially stacked, and the sixth gate structure 156 is A sixth gate insulating layer pattern 126 , a sixth gate electrode 136 , and a sixth gate mask 146 may be sequentially stacked. The seventh gate structure 157 may include a seventh gate insulating layer pattern 127, a seventh gate electrode 137, and a seventh gate mask 147 sequentially stacked, and the eighth gate structure 158 is An eighth gate insulating layer pattern 128 , an eighth gate electrode 138 , and an eighth gate mask 148 may be sequentially stacked. The ninth gate structure 190 may include a ninth gate insulating layer pattern 160 , a ninth gate electrode 170 , and a ninth gate mask 180 sequentially stacked, and the tenth gate structure 195 is A tenth gate insulating layer pattern 165 , a tenth gate electrode 175 , and a tenth gate mask 185 may be sequentially stacked.

The first to tenth gate insulating layer patterns 121 , 122 , 123 , 124 , 125 , 126 , 127 , 128 , 160 , and 165 may include, for example, an oxide such as silicon oxide, and the first to tenth gate insulating layer patterns 10 The gate electrodes 131 , 132 , 133 , 134 , 135 , 136 , 137 , 138 , 170 , and 175 may include a conductive material such as polysilicon doped with impurities, a metal, or a metal nitride, and first to The tenth gate masks 141 , 142 , 143 , 144 , 145 , 146 , 147 , 148 , 180 , and 185 may include a nitride such as silicon nitride.

Meanwhile, referring to FIGS. 12 to 14 along with FIGS. 1 and 2A , both sidewalls of the first to tenth gate structures 151 , 152 , 153 , 154 , 155 , 156 , 157 , 158 , 190 and 195 . First to tenth spacers 201 , 202 , 203 , 204 , 205 , 206 , 207 , 208 , 210 , and 215 may be respectively formed there. The first to tenth spacers 201 , 202 , 203 , 204 , 205 , 206 , 207 , 208 , 210 , and 215 may include, for example, a nitride such as silicon nitride.

In example embodiments, a portion in which the first gate structure 151 is formed has a greater width in the second direction than a portion in which the third gate structure 153 is formed. can Accordingly, in FIG. 2A , for example, third, fifth, seventh, and tenth gate structures 153 , 155 , 157 , and 195 having a width in the second direction of the first active region 102 are formed. It is shown that the portion in which the first and ninth gate structures 153 and 190 are formed is larger than the portion. Also, the width of the second active region 104 in the second direction may be greater in the portion where the second gate structure 152 is formed than in the portion in which the fourth gate structure 154 is formed. Accordingly, in FIG. 2A , for example, fourth, sixth, eighth, and tenth gate structures 154 , 156 , 158 , and 195 are formed with the width of the second active region 104 in the second direction. It is shown that the portion where the second and ninth gate structures 152 and 190 are formed is larger than the portion.

However, the concept of the present invention is not necessarily limited thereto. Accordingly, referring to FIG. 3 , the widths of the third and fourth active regions 103 and 105 in the second direction are the gate structures 151 , 152 , 153 , 154 , 155 , 156 , 157 , and 158 . , 190, 195) is shown to be constant along the first direction irrespective of its relative position, and this can also be included in the concept of the present invention. Hereinafter, for convenience of description, only the first and second active regions 102 and 104 having the shape shown in FIG. 2A will be described.

The first active region 102 may have a first boundary adjacent to the first portion of the isolation layer 110 and a second boundary facing the first boundary in the second direction. In example embodiments, the first boundary may have a linear shape that is not bent in the first direction. Also, the second active region 104 may have a third boundary adjacent to the first portion of the isolation layer 110 and a fourth boundary facing the third boundary in the second direction. In example embodiments, the third boundary may have a linear shape that is not bent in the first direction.

The first, third, fifth, seventh, and ninth impurity regions 221 , 223 , 225 , 227 , and 229 are formed in the ninth, first, third, fifth, seventh and tenth gate structures ( 190 , 151 , 153 , 155 , 157 , and 195 may be respectively formed over the first active region 102 . In example embodiments, the first, third, fifth, seventh, and ninth impurity regions 221 , 223 , 225 , 227 and 229 may be doped with p-type impurities. In addition, the second, fourth, sixth, eighth, and tenth impurity regions 222 , 224 , 226 , 228 , and 230 are formed in the ninth, second, fourth, sixth, eighth and tenth gate structures. They may be respectively formed on the second active region 104 between the 190 , 152 , 154 , 156 , 158 and 195 . In example embodiments, the second, fourth, sixth, eighth, and tenth impurity regions 222 , 224 , 226 , 228 and 230 may be doped with n-type impurities.

Meanwhile, the eleventh and twelfth impurity regions 241 and 242 may be respectively formed on the first and second active regions 102 and 104 adjacent to the ninth gate structure 190 , respectively, and may be p-type and p-type and twelfth impurity regions 242 , respectively. It may be doped with an n-type impurity. In addition, the thirteenth and fourteenth impurity regions 245 and 246 may be respectively formed on the first and second active regions 102 and 104 adjacent to the tenth gate structure 195 , respectively, and may be p-type and p-type regions, respectively. It may be doped with an n-type impurity.

Each of the first to tenth gate structures 151 , 152 , 153 , 154 , 155 , 156 , 157 , 158 , 190 and 195 has first to fourteenth impurity regions 221 , 222 , 223 and 224 adjacent thereto. , 225 , 226 , 227 , 228 , 229 , 230 , 241 , 242 , 245 , 246 may form a PMOS transistor or an NMOS transistor together with the first to fourteenth impurity regions 221 , respectively. , 222, 223, 224, 225, 226, 227, 228, 229, 230, 241, 242, 245, 246) may serve as source/drain regions of each of the PMOS transistors or NMOS transistors.

18 to 20 together with FIGS. 1 and 2A , the first interlayer insulating layer 250 may be formed on the substrate 100 and the device isolation layer 110 to cover the transistors, and 15 The contacts 281 , 282 , 283 , 284 , 285 , 286 , 287 , 288 , 289 , 290 , 291 , 292 , 293 , 294 , and 295 penetrate through the first interlayer insulating layer 250 to form the gate structures 151 . , 152, 153, 154, 155, 156, 157, 158, 190, 195) or impurity regions 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 241, 242, 245, 246) and may be electrically connected to them. Accordingly, each of the first to fifteenth contacts 281 , 282 , 283 , 284 , 285 , 286 , 287 , 288 , 289 , 290 , 291 , 292 , 293 , 294 and 295 is formed by the gate structures 151 and 152 . , 153, 154, 155, 156, 157, 158, 190, 195, specifically, when formed on the gate structures 151, 152, 153, 154, 155, 156, 157, 158, 190, 195 ) of each of the gate electrodes 131 , 132 , 133 , 134 , 135 , 136 , 137 , 138 , 170 , and 175 may be in contact with the top surface.

The first interlayer insulating layer 250 may include, for example, an oxide such as silicon oxide, and the first to fifteenth contacts 281 , 282 , 283 , 284 , 285 , 286 , 287 , 288 , 289 and 290 . , 291, 292, 293, 294, and 295) may include polysilicon doped with impurities, metal, metal nitride, metal silicide, and the like.

The first to fourth contacts 281 , 282 , 283 , and 284 are formed on portions of the first to fourth gate structures 151 , 152 , 153 and 154 formed on the first portion of the isolation layer 110 . can be formed.

In example embodiments, the first and third contacts 281 and 283 may be spaced apart from each other by a first distance D1 at the first boundary of the first active region 102 in the second direction. can That is, the first and third contacts 281 and 283 may be spaced apart from each other by substantially the same distance in the first active region 102 along the second direction. Also, the second and fourth contacts 282 and 284 may be spaced apart from each other by a second distance D2 at the third boundary of the second active region 104 in the second direction. That is, the second and fourth contacts 282 and 284 may be spaced apart from each other by substantially the same distance in the second active region 104 in the second direction. In this case, the first and second distances D1 and D2 may be the same as or different from each other.

In example embodiments, as the first and third boundaries of the first and second active regions 102 and 104 have a linear shape that is not curved in the first direction, the first and second active regions The three contacts 281 and 283 may be aligned with each other in the first direction, and the second and fourth contacts 282 and 284 may also be aligned with each other in the first direction.

The fifth and sixth contacts 285 and 286 may be formed on the third and fourth impurity regions 223 and 224 , and the seventh contact 287 is the seventh gate structure 157 or the eighth gate structure 157 . It may be formed on the gate structure 158 , and the eighth contact 288 may be formed on the fifth gate structure 155 or the sixth gate structure 156 . The ninth to eleventh contacts 289 , 290 , and 291 may be formed on the tenth, seventh, and eighth impurity regions 230 , 227 , and 228 , respectively, and the twelfth and thirteenth contacts 292 , respectively. , 293 may be formed on the first and second impurity regions 221 and 222 , respectively.

The fourteenth and fifteenth contacts 294 and 295 are to be formed on portions of the second and first gate structures 152 and 151 respectively formed on the second and third portions of the isolation layer 110 , respectively. can However, the inventive concept is not necessarily limited thereto, and the fourteenth and fifteenth contacts 294 and 295 may be formed on different portions of the second and first gate structures 152 and 151 , respectively. .

21 to 24 along with FIGS. 1 and 2A , the first to twelfth lower wirings 301 , 302 , 303 , 304 , 305 , 306 , 307 , 308 , 309 , 310 , 311 and 312 are The first to fifteenth contacts 281 , 282 , 283 , 284 , 285 , 286 , 287 , 288 , 289 , 290 , 291 , 292 , 293 , 294 and 295 are formed on the first interlayer insulating layer 250 . It may come into contact with the upper surface of a portion of the rib and may be electrically connected thereto.

The first to twelfth lower interconnections 301 , 302 , 303 , 304 , 305 , 306 , 307 , 308 , 309 , 310 , 311 , and 312 may include a metal, a metal nitride, a metal silicide, or the like, and may include a single layer. Alternatively, it may include a plurality of layers. In an embodiment, each of the first to twelfth lower wirings 301 , 302 , 303 , 304 , 305 , 306 , 307 , 308 , 309 , 310 , 311 , and 312 may include a metal pattern and a bottom surface and a sidewall thereof. A barrier layer pattern may be included.

The first lower wiring 301 may contact upper surfaces of the first and fourth contacts 281 and 284 . Since the first and fourth contacts 281 and 284 are formed on the first and fourth gate structures 151 and 154 formed on the first portion of the isolation layer 110, respectively, in the first direction or They do not face each other in the second direction. Accordingly, in an embodiment, the first lower wiring 301 may include a portion extending in the first direction and a portion extending in the second direction.

The second and third lower wirings 302 and 303 may contact upper surfaces of the second and third contacts 282 and 283 , respectively. In an embodiment, the second lower wiring 302 may extend in the first direction, and the third lower wiring 303 may extend in the second direction.

The fourth lower interconnection 304 may commonly contact upper surfaces of the fifth and seventh contacts 285 and 287 . In an embodiment, the fourth lower wiring 304 may include a portion extending in the first direction and a portion extending in the second direction.

The fifth lower interconnection 305 may contact upper surfaces of the sixth contacts 286 . In an embodiment, the fifth lower wiring 305 may include a portion extending in the first direction and a portion extending in the second direction.

The sixth lower interconnection 306 may commonly contact upper surfaces of the eighth and ninth contacts 288 and 289 . In an embodiment, the sixth lower wiring 306 may include a portion extending in the first direction and a portion extending in the second direction.

The seventh and eighth lower interconnections 307 and 308 may contact upper surfaces of the tenth and eleventh contacts 290 and 291 , respectively. In an embodiment, each of the seventh and eighth lower interconnections 307 and 308 may extend in the first direction, and a portion thereof may extend in the second direction to the tenth and eleventh contacts 290 . , 291) may be in contact with the upper surfaces, respectively.

The ninth and tenth lower wirings 309 and 310 may contact upper surfaces of the twelfth and thirteenth contacts 292 and 293, respectively. In an embodiment, each of the ninth and tenth lower wirings 309 and 310 may extend in the first direction.

The eleventh and twelfth lower interconnections 311 and 312 may contact upper surfaces of the fourteenth and fifteenth contacts 294 and 295, respectively. In an embodiment, each of the eleventh and twelfth lower wirings 311 and 312 may extend in the first direction.

29 to 32 together with FIGS. 1 and 2A , the second interlayer insulating layer 320 is formed on the first interlayer insulating layer 250 to form the first to twelfth lower wirings 301 , 302 , 303 , and 304 . , 305 , 306 , 307 , 308 , 309 , 310 , 311 , 312 , and each of the first to eighth vias 341 , 342 , 343 , 344 , 345 , 346 , 347 and 348 is the first Formed on some of the first to twelfth lower wirings 301 , 302 , 303 , 304 , 305 , 306 , 307 , 308 , 309 , 310 , 311 , and 312 through the second interlayer insulating film 320 , can be electrically connected.

The second interlayer insulating layer 320 may include, for example, an oxide such as silicon oxide, and the first to eighth vias 341 , 342 , 343 , 344 , 345 , 346 , 347 , and 348 may contain impurities. doped polysilicon, metal, metal nitride, metal silicide, and the like.

The first and second vias 341 and 342 may contact the upper surfaces of the second and third lower interconnections 302 and 303 , respectively, and the third and fourth vias 343 and 344 are respectively a fourth and upper surfaces of the fifth lower wirings 304 and 305 . The fifth and sixth vias 345 and 346 may contact upper surfaces of the ninth and tenth lower interconnections 309 and 310 , respectively, and the seventh and eighth vias 347 and 348 are respectively eleventh vias 347 and 348 , respectively. and upper surfaces of the twelfth lower wirings 311 and 312 .

Referring to FIGS. 33 to 38 together with FIGS. 1 and 2A , the first to fifth upper wirings 351 , 352 , 353 , 254 , and 355 are formed on the second interlayer insulating layer 320 to form the first The to eighth vias 341 , 342 , 343 , 344 , 345 , 346 , 347 , and 348 may come into contact with and be electrically connected to the top surface of some of them.

The first to fifth upper wirings 351 , 352 , 353 , 254 , and 355 may include metal, metal nitride, metal silicide, or the like, and may include a single layer or a plurality of layers. In an embodiment, each of the first to fifth upper wirings 351 , 352 , 353 , 254 , and 355 may include a metal pattern and a barrier layer pattern surrounding the bottom and sidewalls thereof.

The first upper interconnection 351 may commonly contact upper surfaces of the first and second vias 341 and 342 . In an embodiment, the first upper wiring 351 may include a portion extending in the first direction and a portion extending in the second direction.

The second upper interconnection 352 may commonly contact upper surfaces of the third and fourth vias 343 and 344 . In an embodiment, the second upper wiring 352 may extend in the second direction.

The third upper interconnection 353 may commonly contact upper surfaces of the fifth and sixth vias 345 and 346 . In an embodiment, the third upper wiring 353 may extend in the second direction.

The fourth and fifth upper interconnections 354 and 355 may contact upper surfaces of the seventh and eighth vias 347 and 348 , respectively. In an embodiment, each of the fourth and fifth upper wirings 354 and 355 may extend in the first direction.

As described above, the semiconductor integrated circuit includes gate structures 151 , 152 , 153 , 154 , 155 , 156 , 157 , 158 , 190 , 195 , impurity regions 221 , 222 , 223 , 224 , 225 , 226, 227, 228, 229, 230, 241, 242, 245, 246, contacts 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295), lower wirings 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, vias 341, 342, 343, 344, 345, 346, 347, 348 ), and upper wirings 351 , 352 , 353 , 354 , and 355 , which may be partially electrically connected to each other to implement the equivalent circuit shown in FIG. 1 .

That is, the semiconductor integrated circuit may include a PMOS gate and an NMOS gate that are staggeredly connected to each other through a contact, a lower interconnection, a via, and/or an upper interconnection, and thus the PMOS gates are staggeredly connected without increasing the area. and a circuit including an NMOS gate, for example, a clock latch circuit may be easily implemented.

In example embodiments, the first gate structure 151 and the first and third impurity regions 221 and 223 may form a PMOS transistor of a transmission gate, and the second gate structure 152 and the second and fourth impurity regions 222 and 224 may form an NMOS transistor of the transmission gate.

Accordingly, the first and second impurity regions 221 and 222 serving as one source/drain region in the transmission gate are formed by the twelfth and thirteenth contacts 292 and 293 and the ninth and tenth lower regions. The interconnections 309 and 310 may be electrically connected to each other through the fifth and sixth vias 345 and 346 , and the third upper interconnection 353 . In addition, the third and fourth impurity regions 223 and 224 serving as the other source/drain region in the transmission gate are the fifth and sixth contacts 285 and 286 and the fourth and fifth lower interconnections. They may be electrically connected to each other through the 304 and 305 , the third and fourth vias 343 and 344 , and the second upper interconnection 352 .

Meanwhile, the second and third gate structures 152 and 153 to which the first signal, that is, the nclock signal, are commonly applied are the second and third contacts 282 and 283 and the second and third lower wirings ( 302 and 303 , the first and second vias 341 and 342 , and the first upper wiring 351 may be electrically connected to each other, and may be separated from the fourth upper wiring 354 to which the nclock signal is applied. They may be electrically connected through the fourteenth contact 294 , the eleventh lower interconnection 311 , and the seventh via 347 .

In addition, the first and fourth gate structures 151 and 154 to which the second signal, ie, the bclock signal, are commonly applied are connected through the first and fourth contacts 281 and 284 and the first lower wiring 301 . They may be electrically connected to each other, and may be electrically connected to the fifth upper wiring 355 applying the bclock signal through the fifteenth contact 295 , the twelfth lower wiring 312 , and the eighth via 348 . .

In the PMOS transistor including the third gate structure 153 and the fifth gate structure 155 sharing the source/drain region of the fifth impurity region 225 , the seventh impurity region 227 is connected to the other source/drain region. It may be included as a drain region, and a drain power supply voltage VDD may be applied thereto. That is, the seventh lower wiring 307 applying the drain power supply voltage VDD may be electrically connected to the seventh impurity region 227 through the tenth contact 290 .

In addition, in the NMOS transistor including the fourth gate structure 154 and the sixth gate structure 156 sharing the source/drain region of the sixth impurity region 226 , the eighth impurity region 228 is formed with the other one. It may be included as a source/drain region, which may be grounded. That is, the eighth lower interconnection 308 for grounding the device by applying the source voltage VSS may be electrically connected to the eighth impurity region 228 through the eleventh contact 291 .

Meanwhile, the seventh gate structure 157 and the seventh and ninth impurity regions 227 and 229 may form a PMOS transistor of an inverter circuit, and the eighth gate structure 158 and the eighth and ninth impurity regions 227 and 229 may be formed. The tenth impurity regions 228 and 230 may form the inverter NMOS transistor. In this case, an input terminal of the inverter circuit may be electrically connected to the third and fourth impurity regions 223 and 224 , and an output terminal of the inverter circuit may be electrically connected to the fifth and sixth gate structures 155 and 156 . can be connected

Specifically, the input terminals of the inverter circuit, that is, the seventh and eighth gate structures 157 and 158 are connected to fifth to seventh contacts 285 , 286 , 287 , fourth and fifth lower interconnections 304 , 305 , and may be electrically connected to the third and fourth impurity regions 223 and 224 through the second upper interconnection 352 . In addition, the output terminal of the inverter circuit, that is, the tenth impurity region 230 is formed by the fifth and sixth gate structures 155 and 155 through the eighth and ninth contacts 288 and 289 and the sixth lower wiring 306 . 156) may be electrically connected.

Meanwhile, the layout of elements for implementing the equivalent circuit shown in FIG. 1 is not necessarily limited to that shown in FIG. 2A . That is, for example, although each element is illustrated as being electrically connected to each other through a contact and a lower wiring, in addition, they may be electrically connected to each other through a via and an upper wiring. Also, although illustrated as being electrically connected to each other through a contact, a lower interconnection, a via, and an upper interconnection, only the contact and the lower interconnection among them may be electrically connected to each other.

Referring, for example, to FIG. 2B under this concept, the second and third lower wirings 302 and 303 contact upper surfaces of the second and third contacts 282 and 283, respectively, but the first and second direction may not extend. That is, the second and third lower wirings may be formed to have only an area sufficient to contact the second and third contacts 282 and 283, respectively, and first and second vias ( 341 and 342) may be formed. Meanwhile, since the first upper wiring 351 is not formed on the same layer as the first lower wiring 301 , unlike in FIG. 2A , when viewed from the top, the first upper wiring 351 may be formed to overlap the first lower wiring 301 . In an embodiment, the first upper wiring 351 may include a portion extending in the first direction and a portion extending in the second direction, and upper surfaces of the first and second vias 341 and 342 . can be commonly contacted.

Also, referring to FIG. 2C , the second lower interconnection 302 may be formed so as not to contact the first lower interconnection 301 while in common contact with upper surfaces of the second and third contacts 282 and 283 . That is, unlike in FIG. 2A , in order to electrically connect the second and third contacts 282 and 283 to each other, the lower wiring, the via, and the upper wiring are not formed, but only the lower wiring may be formed. Accordingly, in an embodiment, the second lower interconnection 302 may include a portion extending in the first direction and a portion extending in the second direction, and the second and third contacts 282 , 283) can be in common contact with the upper surface. However, since the second and third contacts 282 and 283 may be electrically connected to each other only by the second lower interconnection 302 , the third lower interconnection 303 and the first and second vias 341 and 342 . , and the first upper wiring 351 may not be separately formed.

So far, the layout for implementing the clock latch circuit as a cross-coupled circuit in which the gate structure of the PMOS transistor and the gate structure of the NMOS transistor are cross-coupled to each other has been described. not limited That is, even if it is not a clock latch circuit, the concept of the present invention may be applied if the gate structure of the PMOS transistor and the gate structure of the NMOS transistor are cross-coupled to each other for circuit implementation.

4 to 6 are plan views according to other embodiments for explaining the layout of the X region shown in FIG. 1 . The layouts of the semiconductor integrated circuit shown in FIGS. 4 to 6 are for implementing the equivalent circuit shown in FIG. 1 , except for positions of some contacts, shapes of active regions, and shapes of lower and upper wirings. , which is substantially the same as or similar to the layout of the semiconductor integrated circuit shown in FIG. 2A . Accordingly, the same reference numerals are assigned to the same components, and a detailed description thereof will be omitted.

Referring first to FIG. 4 , the semiconductor integrated circuit includes fifth and sixth active regions 106 and 108 , first to tenth gate structures 151 , 152 , 153 , 154 formed on a substrate 100 , 155, 156, 157, 158, 190, 195), 16th to 19th contacts 401, 402, 403, 404, 5th to 15th contacts 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295), thirteenth to twenty-fourth lower interconnections 411, 412, 413, 414, 415, 416, 417, 418, 419, 420, 421, 422, ninth to sixteenth It may include vias 431 , 432 , 433 , 434 , 435 , 436 , 437 , and 438 , and sixth to tenth upper interconnections 441 , 442 , 443 , 444 , and 445 .

The fifth and sixth active regions 106 and 108 may each extend in the first direction and may be spaced apart from each other in the second direction. At least a portion of each of the fifth and sixth active regions 106 and 108 may be doped with p-type and n-type impurities, respectively.

In example embodiments, a portion in which the first gate structure 151 is formed has a greater width in the second direction than a portion in which the third gate structure 153 is formed. can Accordingly, in FIG. 4 , the third, fifth, seventh, and tenth gate structures 153 , 155 , 157 , and 195 are formed in the width of the fifth active region 106 in the second direction. It is shown that the portion in which the first and ninth gate structures 153 and 190 are formed is larger than the portion. In addition, the width of the sixth active region 108 in the second direction may be greater in the portion where the second gate structure 152 is formed than in the portion in which the fourth gate structure 154 is formed. Accordingly, in FIG. 4 , for example, fourth, sixth, eighth, and tenth gate structures 154 , 156 , 158 , and 195 having a width in the second direction of the sixth active region 108 are formed. It is shown that the portion where the second and ninth gate structures 152 and 190 are formed is larger than the portion.

The fifth active region 106 may have a first boundary adjacent to the first portion of the isolation layer 110 and a second boundary facing the first boundary in the second direction. In example embodiments, the second boundary may have a straight shape that is not bent in the first direction. Also, the sixth active region 108 may have a third boundary adjacent to the first portion of the isolation layer 110 and a fourth boundary facing the third boundary in the second direction. In example embodiments, the fourth boundary may have a linear shape that is not bent in the first direction.

The sixteenth and eighteenth contacts 401 and 403 may be formed on portions of the first and third gate structures 151 and 153 formed on the third portion of the isolation layer 110 . In example embodiments, the sixteenth and eighteenth contacts 401 and 403 may be spaced apart from each other by a third distance D3 at the second boundary of the fifth active region 106 in the second direction. can That is, the sixteenth and eighteenth contacts 401 and 403 may be spaced apart from each other by substantially the same distance in the fifth active region 106 along the second direction. In addition, the seventeenth and nineteenth contacts 402 and 404 may be spaced apart from each other by a fourth distance D4 at the fourth boundary of the sixth active region 108 in the second direction. That is, the seventeenth and nineteenth contacts 402 and 404 may be spaced apart from each other by substantially the same distance in the sixth active region 108 along the second direction. In this case, the third and fourth distances D3 and D4 may be the same as or different from each other.

In example embodiments, as the second and fourth boundaries of the fifth and sixth active regions 106 and 108 have a linear shape that is not curved in the first direction, the sixteenth and sixth active regions 106 and 108 are The 18 contacts 401 and 403 may be aligned with each other in the first direction, and the 17th and 19th contacts 402 and 404 may also be aligned with each other in the first direction.

Meanwhile, the thirteenth to twenty-fourth lower interconnections 411 , 412 , 413 , 414 , 415 , 416 , 417 , 418 , 419 , 420 , 421 , and 422 are the first to twelfth lower interconnections illustrated in FIG. 2 , respectively. (301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312), and the ninth to sixteenth vias 431, 432, 433, 434, 435, 436, 437 and 438 may correspond to the first to eighth vias 341 , 342 , 343 , 344 , 345 , 346 , 347 , and 348 illustrated in FIG. 2 , and the sixth to tenth upper interconnections 441 , 442 , 443 , 444 , and 445 may correspond to the first to fifth upper wirings 351 , 352 , 353 , 354 , and 355 illustrated in FIG. 2 . That is, the thirteenth to twenty-fourth lower interconnections 411 , 412 , 413 , 414 , 411 , 412 , 413 , and 414 formed on the first to fourth contacts 281 , 282 , 283 , and 284 of FIG. 415, 416, 417, 418, 419, 420, 421, 422), ninth to sixteenth vias 431, 432, 433, 434, 435, 436, 437, 438, and sixth to tenth upper wiring The shapes of the fields 441 , 442 , 443 , 444 , and 445 may partially vary.

Referring to FIG. 5 , the semiconductor integrated circuit includes first and sixth active regions 102 and 108 and first to tenth gate structures 151 , 152 , 153 , 154 and 155 formed on a substrate 100 . , 156, 157, 158, 190, 195), 20th to 23rd contacts 451, 452, 453, 454, and 5th to 15th contacts 285, 286, 287, 288, 289, 290, 291 , 292, 293, 294, 295), 25th to 36th lower wirings 461, 462, 463, 464, 465, 466, 467, 468, 469, 470, 471, 472), 17th to 24th vias 481 , 482 , 483 , 484 , 485 , 486 , 487 , 488 , and eleventh to fifteenth upper wirings 491 , 492 , 493 , 494 , and 495 may be included.

The twentieth and twenty-second contacts 451 and 453 may be formed on portions of the first and third gate structures 151 and 153 formed on the first portion of the isolation layer 110 . In example embodiments, the twentieth and twenty-second contacts 451 and 453 may be spaced apart from each other by a first distance D1 at the first boundary of the first active region 102 in the second direction. can Meanwhile, the twenty-first and twenty-third contacts 452 and 454 may be formed on portions of the second and fourth gate structures 152 and 154 formed on the second portion of the isolation layer 110 . In example embodiments, the twenty-first and twenty-third contacts 452 and 454 may be spaced apart from each other by a fourth distance D4 at the fourth boundary of the sixth active region 108 in the second direction. can

In example embodiments, as the first and fourth boundaries of the first and sixth active regions 102 and 108 have a linear shape that is not curved in the first direction, the twentieth and sixth active regions The 22 contacts 451 and 453 may be aligned with each other in the first direction, and the 21st and 23rd contacts 452 and 454 may also be aligned with each other in the first direction.

Meanwhile, the 25th to 36th lower wirings 461 , 462 , 463 , 464 , 465 , 466 , 467 , 468 , 469 , 470 , 471 and 472 are the first to twelfth lower wirings illustrated in FIG. 2 , respectively. (301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312), and 17 to 24 vias 481, 482, 483, 484, 485, 486, 487 and 488 may correspond to the first to eighth vias 341 , 342 , 343 , 344 , 345 , 346 , 347 , and 348 illustrated in FIG. 2 , and the eleventh to fifteenth upper interconnections 491 , 492 , 493 , 494 , and 495 may correspond to the first to fifth upper wirings 351 , 352 , 353 , 354 , and 355 illustrated in FIG. 2 .

Referring to FIG. 6 , the semiconductor integrated circuit includes fifth and second active regions 106 and 104 and first to tenth gate structures 151 , 152 , 153 , 154 and 155 formed on a substrate 100 . , 156, 157, 158, 190, 195), 24-27th contacts 501, 502, 503, 504, 5th-15th contacts 285, 286, 287, 288, 289, 290, 291 , 292, 293, 294, 295), 37th to 48th lower wirings 511, 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522, 25th to 32nd vias 531 , 532 , 533 , 534 , 535 , 536 , 537 , and 538 , and sixteenth to twentieth upper interconnections 541 , 542 , 543 , 544 , and 545 may be included.

The twenty-fourth and twenty-sixth contacts 501 and 503 may be formed on portions of the first and third gate structures 151 and 153 formed on the third portion of the isolation layer 110 . In example embodiments, the twenty-fourth and twenty-sixth contacts 501 and 503 may be spaced apart from each other by a third distance D3 at the second boundary of the fifth active region 106 in the second direction. can Meanwhile, the 25th and 27th contacts 502 and 504 may be formed on portions of the second and fourth gate structures 152 and 154 formed on the first portion of the isolation layer 110 . In example embodiments, the twenty-fifth and twenty-seventh contacts 502 and 504 may be spaced apart from each other by a second distance D2 at the third boundary of the second active region 104 in the second direction. can

In example embodiments, as the second and third boundaries of the fifth and second active regions 106 and 104 have a linear shape that is not curved in the first direction, the twenty-fourth and second The 26 contacts 501 and 503 may be aligned with each other in the first direction, and the 25th and 27th contacts 502 and 504 may also be aligned with each other in the first direction.

Meanwhile, the 37th to 48th lower wirings 511 , 512 , 513 , 514 , 515 , 516 , 517 , 518 , 519 , 520 , 521 and 522 are the first to twelfth lower wirings illustrated in FIG. 2 , respectively. (301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312), and the 25th to 32nd vias 531, 532, 533, 534, 535, 536, 537 and 538 may correspond to the first to eighth vias 341 , 342 , 343 , 344 , 345 , 346 , 347 , and 348 illustrated in FIG. 2 , and the sixteenth to twentieth upper wirings 541 , 542 , 543 , 544 , and 545 may correspond to the first to fifth upper interconnections 351 , 352 , 353 , 354 , and 355 illustrated in FIG. 2 .

7 to 38 are plan views and cross-sectional views for explaining steps of a method of manufacturing a semiconductor integrated circuit according to example embodiments. Specifically, FIGS. 7, 9, 12, 15, 18, 21, 25, 29 and 33 are plan views, and FIGS. 8, 10-11, 13-14, 16-17, 19-20, 22-24, 26- 28, 30-32 and 34-38 are cross-sectional views. At this time, FIGS. 8, 10, 16, 19, 22 and 34 are cross-sectional views taken along line A-A' of the corresponding respective plan views, and FIGS. 11, 13, 17, 20, 23, 26, 30 and 35 are Figs. 14, 27, 31 and 36 are cross-sectional views taken along line B-B' of the corresponding respective plan views, and Figs. 24, 28, 32 and 37 are cross-sectional views taken along line D-D' of the corresponding respective plan views, and FIG. 38 is a cross-sectional view taken along line E-E' of the corresponding plan views.

7 and 8 , the upper portion of the substrate 100 is partially etched to form a trench (not shown), and an isolation layer 110 filling the trench is formed.

In example embodiments, the device isolation layer 110 may be formed by forming an insulating layer sufficiently filling the trench on the substrate 100 and planarizing the insulating layer until the top surface of the substrate 100 is exposed. The insulating layer may be formed to include, for example, an oxide such as silicon oxide.

As the device isolation layer 110 is formed, the substrate 100 has a field region whose upper surface is covered by the device isolation layer 110 and first and second active regions ( 102, 104) can be defined.

The first and second active regions 102 and 104 may each extend in a first direction parallel to the top surface of the substrate 100 , and may be parallel to the top surface of the substrate 100 and substantially perpendicular to the first direction. It may be formed to be spaced apart from each other in two directions.

In example embodiments, each of the first and second active regions 102 and 104 may be formed to have different widths in the second direction along the first direction. However, the concept of the present invention is not necessarily limited thereto, and the width of each of the first and second active regions 102 and 104 in the second direction may be uniformly formed along the first direction.

The device isolation layer 110 includes the first portion of the device isolation layer 110 along the second direction with respect to the first portion and the second active region 104 formed between the first and second active regions 102 and 104 . It may include a second portion formed opposite to the first portion, and a third portion formed opposite to the first portion of the device isolation layer 110 in the second direction with respect to the first active region 102 .

The first active region 102 may have a first boundary adjacent to the first portion of the device isolation layer 110 and a second boundary adjacent to the third portion of the device isolation layer 110 . In example embodiments, the first boundary may have a linear shape that is not bent in the first direction. Also, the second active region 104 may have a third boundary adjacent to the first portion of the device isolation layer 110 and a fourth boundary adjacent to the second portion of the device isolation layer 110 . In example embodiments, the third boundary may have a linear shape that is not bent in the first direction.

9 to 11 , after sequentially forming a gate insulating layer, a gate electrode layer, and a gate mask layer on the first and second active regions 102 and 104 and the device isolation layer 110 of the substrate 100 , , are patterned to form gate structures 151 , 152 , 153 , 154 , 155 , 156 , 157 , 158 , 190 , and 195 .

The gate insulating layer may be formed to include, for example, an oxide such as silicon oxide, and the gate electrode layer may be formed to include, for example, doped polysilicon, metal, metal nitride, etc., and the gate mask may be formed to include, for example, a nitride such as silicon nitride.

In an embodiment, the gate insulating layer may be formed through a thermal oxidation process on the upper portion of the substrate 100 , and in this case, may be formed only on the first and second active regions 102 and 104 . . Alternatively, the gate insulating layer may be formed through a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or the like. In this case, the first and second active regions It may be formed on the device isolation layer 110 as well as (102, 104).

The first, third, fifth, and seventh gate structures 151 , 153 , 155 , and 157 may extend in the second direction on the first active region 102 and the device isolation layer 110 adjacent thereto, respectively. and may be formed to be spaced apart from each other along the first direction. In addition, the second, fourth, sixth, and eighth gate structures 152 , 154 , 156 , and 158 are formed on the second active region 104 and the device isolation layer 110 adjacent thereto in the second direction, respectively. It may extend, and may be formed to be spaced apart from each other in the first direction.

In this case, the first and second gate structures 151 and 152 may be spaced apart from each other while facing each other in the second direction, and the third and fourth gate structures 153 and 154 may also face each other in the second direction. can be seen and separated. Meanwhile, the fifth and sixth gate structures 155 and 156 may face each other in the second direction and contact each other in the first portion of the device isolation layer 110 , and the seventh and eighth gate structures ( 157 and 158 may also face each other in the second direction and contact each other at the first portion of the device isolation layer 110 .

Meanwhile, the ninth gate structure 190 may extend in the second direction on the first and second active regions 102 and 104 and the device isolation layer 110 , and the first and second gate structures 151 . , 152) may be spaced apart from the first direction. Also, the tenth gate structure 195 may extend in the second direction on the first and second active regions 102 and 104 and the isolation layer 110 , and the seventh and eighth gate structures 157 . , 158) may be spaced apart from the first direction.

The first gate structure 151 may include a first gate insulating layer pattern 121 , a first gate electrode 131 , and a first gate mask 141 that are sequentially stacked, and the second gate structure 152 is A second gate insulating layer pattern 122 , a second gate electrode 132 , and a second gate mask 142 may be sequentially stacked. The third gate structure 153 may include a third gate insulating layer pattern 123 , a third gate electrode 133 , and a third gate mask 143 that are sequentially stacked, and the fourth gate structure 154 is A fourth gate insulating layer pattern 124 , a fourth gate electrode 134 , and a fourth gate mask 144 may be sequentially stacked. The fifth gate structure 155 may include a fifth gate insulating layer pattern 125 , a fifth gate electrode 135 , and a fifth gate mask 145 that are sequentially stacked, and the sixth gate structure 156 is A sixth gate insulating layer pattern 126 , a sixth gate electrode 136 , and a sixth gate mask 146 may be sequentially stacked. The seventh gate structure 157 may include a seventh gate insulating layer pattern 127, a seventh gate electrode 137, and a seventh gate mask 147 sequentially stacked, and the eighth gate structure 158 is An eighth gate insulating layer pattern 128 , an eighth gate electrode 138 , and an eighth gate mask 148 may be sequentially stacked. The ninth gate structure 190 may include a ninth gate insulating layer pattern 160 , a ninth gate electrode 170 , and a ninth gate mask 180 sequentially stacked, and the tenth gate structure 195 is A tenth gate insulating layer pattern 165 , a tenth gate electrode 175 , and a tenth gate mask 185 may be sequentially stacked.

12 to 14 , a spacer layer covering the gate structures 151 , 152 , 153 , 154 , 155 , 156 , 157 , 158 , 190 , and 195 is disposed on the substrate 100 and the device isolation layer 110 . Formed and then anisotropically etched on both sidewalls of each of the first to tenth gate structures 151 , 152 , 153 , 154 , 155 , 156 , 157 , 158 , 190 and 195 in the first direction First to tenth spacers 201 , 202 , 203 , 204 , 205 , 206 , 207 , 208 , 210 and 215 may be formed, respectively.

The spacer layer may be formed to include, for example, a nitride such as silicon nitride (SiN) or silicon oxycarbonitride (SiOCN).

Hereinafter, for convenience of description, the spacers 201 , 202 , 203 , 204 , 205 , 206 , 207 , 208 , 210 , and 215 are not shown in each plan view.

Thereafter, the upper portions of the first and second active regions 102 and 104 that are not covered by the first to tenth gate structures 151 , 152 , 153 , 154 , 155 , 156 , 157 , 158 , 190 and 195 . First to fourteenth impurity regions 221 , 222 , 223 , 224 , 225 , 226 , 227 , 228 , 229 , 230 , 241 , 242 , 245 and 246 may be formed by implanting impurities into the .

In example embodiments, after forming a first mask (not shown) covering the second active region 104 , the first mask and the first to tenth gate structures 151 , 152 , and 153 are , 154 , 155 , 156 , 157 , 158 , 190 , and 195 through an ion implantation process using as an ion implantation mask, the ninth, first, third, fifth, seventh and tenth gate structures 190 , 151 , 153 , 155 , 157 , and 195 , first, third, fifth, seventh, and ninth impurity regions 221 , 223 , doped with p-type impurities on the first active region 102 , 11th and thirteenth impurity regions 225 , 227 , and 229 are formed, respectively, and p-type impurities are doped over the first active region 102 outside the ninth and tenth gate structures 190 and 195 , respectively The ones 241 and 245 may be formed, respectively.

After removing the first mask, a second mask (not shown) covering the first active region 102 is formed, and then the second mask and the first to tenth gate structures 151 , 152 and 153 are formed. , 154 , 155 , 156 , 157 , 158 , 190 , and 195 , through an ion implantation process using ion implantation masks, the ninth, second, fourth, sixth, eighth and tenth gate structures 190 , 152 , 154 , 156 , 158 , and 195 , second, fourth, sixth, eighth, and tenth impurity regions 222 , 224 , doped with n-type impurities on the second active region 104 , 226 , 228 , and 230 are formed, respectively, and twelfth and fourteenth impurity regions doped with n-type impurities on the second active region 104 outside the ninth and tenth gate structures 190 and 195 , respectively. The fields 242 and 246 may be formed, respectively.

Each of the first to tenth gate structures 151 , 152 , 153 , 154 , 155 , 156 , 157 , 158 , 190 and 195 includes first to fourteenth impurity regions 221 , 222 , 223 , 224 , 225 , 226 , 227 , 228 , 229 , 230 , 241 , 242 , 245 , 246 may form a PMOS transistor or an NMOS transistor together with a portion formed adjacent thereto.

15 to 17 , a first interlayer insulating layer 250 sufficiently covering the transistors is formed on the substrate 100 and the device isolation layer 110 and partially etched to form the first to tenth gate structures Each of the first to tenth gate electrodes 131, 132, 133, 134, 135, 136, 137, 138, 170 of the ones 151, 152, 153, 154, 155, 156, 157, 158, 190, and 195 , 175) or some of the first to fourteenth impurity regions 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 241, 242, 245, and 246 are exposed. The first to fifteenth openings 261 , 262 , 263 , 264 , 265 , 266 , 267 , 268 , 269 , 270 , 271 , 272 , 273 , 274 and 275 are formed.

The first interlayer insulating layer 250 may be formed to include, for example, an oxide such as silicon oxide.

Specifically, the first to fourth openings 261 , 262 , 263 , and 264 are the first to fourth gate electrodes 131 , 132 , 133 , and 134 formed on the first portion of the isolation layer 110 . The upper surface of each can be exposed. In example embodiments, each of the first and third openings 261 and 263 may be spaced apart from the first boundary of the first active region 102 by a first distance D1, and each second and the fourth openings 262 and 264 may be spaced apart from the third boundary of the second active region 104 by a second distance D2.

The fifth and sixth openings 265 and 266 may expose top surfaces of the third and fourth impurity regions 223 and 224 , respectively, and the seventh opening 267 may be connected to the seventh gate electrode 137 or A top surface of the eighth gate electrode 138 may be exposed, and the eighth opening 268 may expose a top surface of the fifth gate electrode 135 or the sixth gate electrode 136 .

The ninth to thirteenth openings 269 , 270 , 271 , 272 , and 273 are the top surfaces of the tenth, seventh, eighth, first and second impurity regions 230 , 227 , 228 , 221 and 222 , respectively. may be exposed, and the fourteenth and fifteenth openings 274 and 275 may expose upper surfaces of the second and first gate electrodes 132 and 131 , respectively.

18 to 20 , first to fifteenth openings 261 , 262 , 263 , 264 , 265 , 266 , 267 , 268 , 269 , 270 , 271 , 272 are formed on the first interlayer insulating layer 250 . After forming the first conductive film filling the 273 , 274 , and 275 , the first to fifteenth openings 261 , 262 , 263 , 264 and the first to fifteenth openings 261 , 262 , 263 and 264 are formed by planarizing the first interlayer insulating film 250 until the top surface is exposed. 265 , 266 , 267 , 268 , 269 , 270 , 271 , 272 , 273 , 274 and 275 respectively fill the first to fifteenth contacts 281 , 282 , 283 , 284 , 285 , 286 , 287 , 288 , 289 . , 290, 291, 292, 293, 294, 295) can be formed.

The first conductive layer may be formed to include, for example, polysilicon doped with impurities, metal, metal nitride, and/or metal silicide.

21 to 24 , the first interlayer insulating layer 250 and the first to fifteenth contacts 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293 , 294 and 295) by forming a second conductive film and patterning the first to twelfth lower interconnections (301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312) can form. The second conductive layer may be formed to include, for example, a metal, a metal nitride, and/or a metal silicide.

Alternatively, the first to twelfth lower interconnections 301 , 302 , 303 , 304 , 305 , 306 , 307 , 308 , 309 , 310 , 311 , and 312 may be formed by a damascene process.

That is, on the first interlayer insulating layer 250 and the first to fifteenth contacts 281 , 282 , 283 , 284 , 285 , 286 , 287 , 288 , 289, 290 , 291 , 292 , 293 , 294 and 295 . After forming an interlayer insulating film (not shown) and partially etching it to form a trench (not shown), the second conductive film sufficiently filling the trench is formed on the interlayer insulating film, the upper surface of the interlayer insulating film is It can be formed by planarizing the second conductive film until exposed. In this case, a barrier film may be first formed before forming the second conductive film, and the second conductive film may be formed on the barrier film, and accordingly, the lower portion including the barrier film pattern and the conductive pattern sequentially stacked. A wiring may be formed.

The upper wiring to be formed thereafter may also be formed by the damascene process, but only a method of forming them through the patterning process will be described below for convenience of description.

The first lower wiring 301 may contact upper surfaces of the first and fourth contacts 281 and 284 , and may include a portion extending in the first direction and a portion extending in the second direction. The second and third lower wirings 302 and 303 may contact upper surfaces of the second and third contacts 282 and 283, respectively, and the second lower wiring 302 may extend in the first direction. and the third lower wiring 303 may extend in the second direction.

The fourth lower interconnection 304 may contact the upper surfaces of the fifth and seventh contacts 285 and 287 in common, and may include a portion extending in the first direction and a portion extending in the second direction. can The fifth lower wiring 305 may contact upper surfaces of the sixth contacts 286 and may include a portion extending in the first direction and a portion extending in the second direction. The sixth lower interconnection 306 may contact the upper surfaces of the eighth and ninth contacts 288 and 289 in common, and may include a portion extending in the first direction and a portion extending in the second direction. can

The seventh and eighth lower interconnections 307 and 308 may contact upper surfaces of the tenth and eleventh contacts 290 and 291, respectively, and extend in the first direction and in the second direction. It may include an extended portion. The ninth and tenth lower wirings 309 and 310 may contact upper surfaces of the twelfth and thirteenth contacts 292 and 293, respectively, and may each extend in the first direction. The eleventh and twelfth lower interconnections 311 and 312 may contact upper surfaces of the fourteenth and fifteenth contacts 294 and 295, respectively, and may each extend in the first direction.

If each of the lower wirings 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312 is formed only to contact the corresponding contacts, their shape is necessarily shown in the drawing. It is not limited to what has been done, and may be implemented in various ways.

25 to 28 , the first interlayer insulating layer 250 and the first interlayer insulating layer 250 and the lower wirings 301 , 302 , 303 , 304 , 305 , 306 , 307 , 308 , 309 , 310 , 311 , and 312 are sufficiently covered. A portion of the first to twelfth lower wirings 301 , 302 , 303 , 304 , 305 , 306 , 307 , 308 , 309 , 310 , 311 and 312 is formed by forming the second interlayer insulating layer 320 and partially etching it. Sixteenth to twenty-third openings 331 , 332 , 333 , 334 , 335 , 336 , 337 and 338 exposing the upper surface are formed.

The second interlayer insulating layer 320 may be formed to include, for example, an oxide such as silicon oxide.

Specifically, the sixteenth and seventeenth openings 331 and 332 may expose upper surfaces of the second and third lower interconnections 302 and 303, respectively, and the eighteenth and nineteenth openings 333 and 334 may Top surfaces of the fourth and fifth lower wirings 304 and 305 may be exposed, respectively. The twentieth and twenty-first openings 335 and 336 may expose upper surfaces of the ninth and tenth lower interconnections 309 and 310, respectively, and the twenty-second and twenty-third openings 337 and 338 are respectively eleventh openings. and upper surfaces of the twelfth lower wirings 311 and 312 may be exposed.

29 to 32 , a third conductive layer filling the 16th to 23rd openings 331 , 332 , 333 , 334 , 335 , 336 , 337 and 338 is formed on the second interlayer insulating layer 320 . Thereafter, the first to 23rd openings 331 , 332 , 333 , 334 , 335 , 336 , 337 and 338 are respectively filled by planarizing the second interlayer insulating layer 320 until the top surface is exposed. Eighth vias 341 , 342 , 343 , 344 , 345 , 346 , 347 and 348 may be formed. The third conductive layer may be formed to include, for example, polysilicon doped with impurities, metal, metal nitride, and/or metal silicide.

33 to 38 , a fourth conductive film is formed on the second interlayer insulating film 320 and the first to eighth vias 341 , 342 , 343 , 344 , 345 , 346 , 347 and 348 , and the By patterning, first to fifth upper interconnections 351 , 352 , 353 , 354 , and 355 may be formed. The fourth conductive layer may be formed to include, for example, a metal, a metal nitride, and/or a metal silicide.

The first upper wiring 351 may commonly contact upper surfaces of the first and second vias 341 and 342 , and may include a portion extending in the first direction and a portion extending in the second direction. have. The second upper interconnection 352 may commonly contact upper surfaces of the third and fourth vias 343 and 344 and may extend in the second direction. The third upper interconnection 353 may commonly contact upper surfaces of the fifth and sixth vias 345 and 346 and may extend in the second direction. The fourth and fifth upper interconnections 354 and 355 may contact the upper surfaces of the seventh and eighth vias 347 and 348, respectively, and the fourth and fifth upper interconnections 354 and 355, respectively, are It may extend in the first direction.

If each of the upper wirings 351 , 352 , 353 , 354 , and 355 is formed only to contact the vias corresponding thereto, their shapes are not necessarily limited to those shown in the drawings and may be implemented in various ways.

Thereafter, a passivation layer may be formed on the second interlayer insulating layer 320 to cover and protect the upper wirings 351 , 352 , 353 , 354 , and 355 to complete the semiconductor integrated circuit. Alternatively, other vias and upper wirings electrically connected to the upper wirings 351 , 352 , 353 , 354 and 355 may be further formed.

The above-described semiconductor integrated circuit and manufacturing method thereof may be applied to a structure in which a PMOS gate and an NMOS gate are cross-coupled to each other, for example, a clock latch circuit. Accordingly, the present invention can be applied to various devices including the clock latch circuit or other circuits including a cross-coupled structure. For example, the semiconductor integrated circuit and the manufacturing method thereof include a logic device such as a central processing unit (CPU, MPU), an application processor (AP), etc., a volatile memory device such as an SRAM device, a DRAM device, etc.; and a nonvolatile memory device such as a flash memory device, a PRAM device, an MRAM device, and an RRAM device, and a method for manufacturing the same.

Although the above has been described with reference to the embodiments of the present invention, those skilled in the art can variously modify and change the present invention within the scope without departing from the spirit and scope of the present invention described in the claims below. You will understand that you can.

100: substrate
102, 104, 103, 105, 106, 108: first to sixth active regions
110: element isolation film
121, 122, 123, 124, 125, 126, 127, 128, 160, 165: first to tenth gate insulating layer patterns
131, 132, 133, 134, 135, 136, 137, 138, 170, 175: first to tenth gate electrodes
141, 142, 143, 144, 145, 146, 147, 148, 180, 185: first to tenth gate masks
151, 152, 153, 154, 155, 156, 157, 158, 190, 195: first to tenth gate structures
201, 202, 203, 204, 205, 206, 207, 208, 210, 215: first to tenth spacers
221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 241, 242, 245, 246: first to fourteenth impurity regions
250, 320: first and second interlayer insulating films
281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295: first to fifteenth contacts
301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312: first to twelfth lower wirings
341, 342, 343, 344, 345, 346, 347, 348: first to eighth vias
351, 352, 353, 354, 355: first to fifth upper wirings
401, 402, 403, 404: 16th to 19th contacts
411, 412, 413, 414, 415, 416, 417, 418, 419, 420, 421, 422: 13th to 24th lower wiring
431, 432, 433, 434, 435, 436, 437, 438: 9th to 16th vias
441, 442, 443, 444, 445: sixth to tenth upper wirings
451, 452, 453, 454: 20th to 23rd contacts
461, 462, 463, 464, 465, 466, 467, 468, 469, 470, 471, 472: 25th to 36th lower wiring
481, 482, 483, 484, 485, 486, 487, 488: 17th to 24th via
491, 492, 493, 494, 495: 11th to 15th upper wiring
501, 502, 503, 504: 24-27th contacts
511, 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522: 37th to 48th lower wirings
531, 532, 533, 534, 535, 536, 537, 538: vias 25 to 32
541, 542, 543, 544, 545: 16th to 20th upper wiring

Claims (10)

First and second actives defined by a device isolation layer formed on the substrate, respectively extending in a first direction, spaced apart from each other in a second direction perpendicular to the first direction, and doped with impurities of different conductivity types, respectively areas;
first and third gate structures spaced apart from each other in the first direction, respectively extending in the second direction, and passing through the first active region;
second and fourth gate structures spaced apart from each other in the first direction, respectively extending in the second direction, and passing through the second active region; and
and first to fourth contacts respectively formed on portions of the first to fourth gate structures,
The first active region includes a first portion having a first width in the second direction, and a second portion having a second width different from the first width in the second direction,
the first gate structure is formed on the first portion of the first active region and on a first portion of the isolation layer between the first and second active regions;
the third gate structure is formed on the second portion of the first active region and on the first portion of the isolation layer;
the second and fourth gate structures are formed on the second active region and the first portion of the isolation layer;
the first and fourth contacts are electrically connected to each other, and the second and third contacts are electrically connected to each other;
all of the first to fourth contacts are formed between the first and second active regions when viewed from above;
The first and third contacts are spaced apart from the first active region by the same distance along the second direction, and the second and fourth contacts are spaced apart from the second active region by the same distance along the second direction. semiconductor integrated circuit. The semiconductor integrated circuit of claim 1 , wherein the first active region is doped with a p-type impurity and the second active region is doped with an n-type impurity. The semiconductor integrated circuit of claim 1 , wherein the first and fourth contacts are electrically connected to each other by a first lower wiring formed in common thereon. The method of claim 1,
a second lower wiring formed on the second contact;
a third lower interconnection formed on the third contact;
a first via formed on the second lower wiring;
a second via formed on the third lower interconnection; and
Further comprising a first upper wiring commonly connected to the first and second vias,
The second and third contacts are electrically connected to each other by the second and third lower interconnections, the first and second vias, and the first upper interconnection. The method of claim 1,
first and third impurity regions formed over the first active region on both sides of the first gate structure and doped with impurities of a first conductivity type; and
The semiconductor integrated circuit further includes second and fourth impurity regions formed on both sides of the second gate structure, respectively, on the second active region and doped with impurities of a second conductivity type. The semiconductor integrated circuit of claim 5 , further comprising fifth and sixth contacts respectively formed on the first and second impurity regions and electrically connected to each other. 7. The method of claim 6,
a fourth lower interconnection formed on the fifth contact;
a fifth lower interconnection formed on the sixth contact;
a third via formed on the fourth lower interconnection;
a fourth via formed on the fifth lower interconnection; and
Further comprising a second upper wiring commonly connected to the third and fourth vias,
The fifth and sixth contacts are electrically connected to each other by the fourth and fifth lower interconnections, the third and fourth vias, and the second upper interconnection. The semiconductor integrated circuit of claim 5 , further comprising seventh and eighth contacts respectively formed on the third and fourth impurity regions and electrically connected to each other. 9. The method of claim 8,
a sixth lower interconnection formed on the seventh contact;
a seventh lower interconnection formed on the eighth contact;
a fifth via formed on the sixth lower interconnection;
a sixth via formed on the seventh lower interconnection; and
Further comprising a third upper wiring commonly connected to the fifth and sixth vias,
The seventh and eighth contacts are electrically connected to each other by the sixth and seventh lower interconnections, the fifth and sixth vias, and the third upper interconnection. The method of claim 1,
A fifth gate structure spaced apart from the third gate structure in the first direction and extending in the second direction is formed on the first active region and a portion of the isolation layer between the first and second active regions ; and
A sixth gate structure spaced apart from the fourth gate structure in the first direction and extending in the second direction is formed on the second active region and a portion of the isolation layer between the first and second active regions further comprising,
The fifth and sixth gate structures are connected to each other on a portion of the isolation layer between the first and second active regions and extend in the second direction as a whole.

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