KR102284467B1 - Techniques for power management associated with processing received packets at a network device - Google Patents

Abstract

Examples may include power management techniques associated with processing a received packet at the NW device. Receive queues for network input/output (NW I/O) devices or network interface cards (NICs) may be monitored to determine activity levels of data plane development kit (DPDK) polling threads. Various power or performance management actions may be taken based on information obtained from monitoring the receive queues.

Description

TECHNIQUES FOR POWER MANAGEMENT ASSOCIATED WITH PROCESSING RECEIVED PACKETS AT A NETWORK DEVICE

The examples described herein relate generally to network packet processing.

A data plane development kit (DPDK) is a set of software libraries and drivers that can be used to accelerate user space packet processing for network computing platforms based on a processor architecture, such as the Intel® processor architecture. DPDK has been deployed in data center networks throughout the world to support high performance network packet processing applications. These network packet processing applications may include, but are not limited to, firewall, virtual private network (VPN), network address translation (NAT), deep packet inspection (DPI) or load balancer applications. For example, these firewall, VPN, NAT, DPI, or load balancer applications may include, but are not limited to, Intel Xeon® processors coupled to Intel 10 Gigabit/40 Gigabit (10G/40G) network interface cards (NICs). It can be implemented on a standard x86 server platform that can include Using a DPDK to support high performance network packet processing applications may replace at least some expensive and less flexible physical components of a network device.

1 shows an exemplary system;
Fig. 2 illustrates an exemplary first logic flow;
3 shows an exemplary first process;
4 illustrates an exemplary second process;
5 illustrates an exemplary third process.
6 is an exemplary block diagram of an apparatus;
7 illustrates an exemplary second logic flow;
Fig. 8 shows an exemplary third logic flow;
9 is a diagram illustrating an example of a storage medium;
10 depicts an exemplary computing platform.

In some examples, implementation of the DPDK for high performance packet processing applications includes deploying poll mode drivers (PMDs) to configure and/or operate NW I/O devices, such as Intel 1G/10G/40G NICs. can do. For these examples, deploying the PMD allows DPDK-based network applications to receive, process and transmit packets in a high performance and low latency manner to receive, process and transmit NW I/NW I/C at the highest or maximum processor/core frequency without triggering interrupts. O device resources (eg, receive (Rx) and transmit (Tx) queues) will be accessible. However, in data center networks, a well-known phenomenon called the "tidal effect" may occur. The tidal effect may be due to significant changes in network traffic patterns occurring in different geographic areas over time periods. Thus, during periods of processing low network traffic or no network traffic at all, a thread of a DPDK-based application running on x86 processing cores ("DPDK polling thread") may still be busy waiting (e.g., continuously , but does not process network packets). Waiting for network packets can waste a significant amount of power as well as computational resources.

Operating system (OS) power management subsystems or modules employ a number of techniques (mainly P-states, C-states and control in OS kernel space) to regulate processor power during periods of peak or low network traffic. ) can be provided. In standard OSs (eg, Linux or Windows®), OS power management modules, by periodically sampling CPU usage, allow the processor or cores to enter, respectively, the appropriate processor voltage and/or frequency, operating point ( P-state) and processor idle state (C-state). However, this approach is not suitable for PMD-based packet processing applications with DPDK polling threads, as the OS power management module cannot determine whether the DPDK polling threads are actually processing packets or waiting busy. The inability of the OS power management module to determine the operating state of the DPDK polling threads means that the processors or cores supporting these DPDK polling threads will enter the appropriate state to save power in data center networks affected by the "tidal effect". Determining power states can be problematic. The examples described herein in connection with these challenges are needed.

According to some first examples, power management techniques associated with processing packets received at the NW I/O device are receive maintained in a receive queue for the NW I/O device over multiple polling iterations for the DPDK polling thread. This may include monitoring old and available packet descriptors. These first examples also include determining a level of fullness for a receive queue based on available packet descriptors maintained in the receive queue after each polling iteration and determining the level of fullness for the receive queue. incrementing a trend count based on it. These first examples may also include sending a performance indication to the OS power management module based on whether the trend count exceeds a trend count threshold. The performance indication may cause the OS power management module to increase the performance state of the processing element executing the DPDK polling thread.

According to some second examples, power management techniques associated with processing received packets at the NW device are also maintained in a receive queue for the NW I/O device over multiple polling iterations for the DPDK polling thread. It may include monitoring available packet descriptors. These second examples also include determining the number of packets received in the receive queue for each polling iteration based on available packet descriptors maintained in the receive queue after each polling iteration, and a consecutive threshold ), incrementing an idle count by a count of 1 if the number of packets received for a number of consecutive polling iterations greater than . These second examples may also include causing the DPDK polling thread to sleep during one of a first period or a second period based on whether the idle count is above or below the first idle count threshold. . The second period of time may be longer than the first period.

1 illustrates an exemplary system 100 . 1 , in some examples, system 100 includes a NW I/O device 110 configured to receive or transmit packets included in NW traffic 105 . A pre-flow load balancer 120 may distribute packets to receive (Rx) queues 130-1 through 130-n, where “n” is any amount greater than one. is an integer For these examples, Rx queues 130-1 through 130-n may be configured to at least temporarily hold received packets for processing by respective DPDK polling threads 140-1 through 140-n. . Each DPDK polling thread 140-1 through 140-n may execute at least portions of a network packet processing application, including but not limited to firewall, VPN, NAT, DPI or load balancer applications. Each DPDK polling thread 140-1 to 140-n has Rx queues 130-1 to 130- in the polling mode of operation, without interrupts, to receive, process or transmit packets received with the NW traffic 105 . n) may include respective poll mode drivers 142-1 to 142-n to enable access.

1 , system 100 also includes DPDK power management components 150 configured to operate in user space 101 and an OS power management module configured to operate in kernel space 102 , according to some examples. (160). As described in more detail below, DPDK power management components 150 are maintained in Rx queues 130-1 through 130-n for processing by DPDK polling threads 140-1 through 140-n. It may include logic and/or features capable of monitoring received and available packet descriptors. Logic and/or features in DPDK power management components 150 may also monitor sleep or idle times for DPDK polling threads 140-1 through 140-n.

In some examples, state algorithms 154 of DPDK power management components 150 use the monitored information to put DPDK polling threads 140-1 through 140-n into temporary sleep states ( Sending an interrupt turn on hint or message to the NW I/O device 110 (via one-shot Rx interrupt on hint 180 ) to cause a change from polling mode to interrupt operating mode or , may enable library 152 to send C-state (sleep) or P-state (performance) hints or indications. For these examples, as shown in FIG. 1 , C-state or P-state hints may be transmitted on a processor element (PE) idle 162 or PE frequency 164 in the OS power management module 160 . there is. Elements of OS power management module 160 are then configured to one or more PEs 172-1 through 172-n included in one or more processor(s) 170 based on the received C-state or P-state hints. may cause changes to either the C-state(s) or P-state(s) of C-states or P-states, such as Advanced Configuration and Power Interface Specification (ACPI), Revision 5.1 (“ACPI Specification”), published July 2014 by the Unified Extensible Firmware Interface Forum (UEFI), It may be modified or controlled according to one or more processor power management standards or specifications.

According to some examples, processor(s) 170 may include a multicore processor, and each of PEs 172-1 through 172-n may be a core of a multicore processor and/or may be of a multicore processor. It may be a virtual machine (VM) supported by one or more cores. Also, for these examples, DPDK polling threads 140-1 through 140-n may be executed by PEs 172-1 through 172-n. Processor(s) 170 include: AMD® Athlon®, Duron®, Phenom®, and Opteron® processors; Various types of commercially available processors including, but not limited to, Intel Atom®, Celeron®, Core (2) Duo®, Core i3, Core i5, Core i7, Pentium®, Xeon or Xeon Phi® processors. It may include x86 processors.

According to some examples, a new API (NAPI) interrupt for use in kernel space 102 (eg, for a Linux kernel) to support packet processing by DPDK polling threads 140-1 through 140-n. It may be an interrupt mitigation technique. NAPI is typically designed to improve the performance of high-speed networking by introducing a polling mode capability to the OS and NIC or NW I/O drivers. With NAPI, the NW I/O driver operates in interrupt-driven mode by default, and can switch to polling mode only when the flow of incoming packets exceeds a certain threshold. . NAPI enables frequent mode switching, which can be widely accepted for network endpoints (e.g., servers or personal computers) because these endpoints may not have stringent low latency and jitter requirements. because there is However, certain types of network devices (eg switches, routers and L4 to L7 network appliances) may operate within stringent latency, jitter and packet loss requirements. For these types of network devices, frequent mode switches, servicing interrupts, and waking up suspended, suspended or sleeping threads can be costly in terms of processor resources and latency hits. there is. This processor resource and latency hit may be unacceptable for network devices in deployments such as in a data center network.

According to some examples, the poll mode drivers 142-1 to 142-n of the DPDK polling threads 140-1 to 140-n may be designed or configured to operate in polling mode by default. As will be described further below, when DPDK power management components 150 detect a network traffic that is trending lower and lower, DPDK power management components 150 send DPDK polling threads 140-1 through 140 - n ) to sleep for one or more periods, and may also send hints to OS power management module 160 . Based on the hints, OS power management module 160 may cause PEs 172-1 through 172-n to lower processor frequencies or transition to an idle or sleep state to save power. Also, when the DPDK power management components 150 do not detect any traffic for a certain duration threshold, the poll mode drivers 142-1 through 142-n may switch from a default polling mode to an interrupt mode. . In this way, the DPDK polling threads 140-1 can mainly operate in a polling mode environment to better meet performance requirements when processing packets and thus avoid frequent mode switches.

2 shows an exemplary first logic flow. As shown in FIG. 2 , a first exemplary logic flow includes logic flow 200 . According to some examples, logic flow 200 may be for power management associated with processing received packets for a NW device (eg, located in a data center). For such examples, at least some components of system 100 shown in FIG. 1 may implement portions of logic flow 200 . However, the example logic flow 200 is not limited to using the components of the system 100 shown or described in FIG. 1 .

In some examples, as shown in FIG. 2 , the DPDK power management components may be initialized ( 202 ). For these examples, the DPDK polling thread (eg, DPDK polling thread 140-1) runs a continuous loop of polling packets from Rx queues (eg, Rx queue 130-1) for the NW I/O device. can start As further described below, the loop may be continuous as long as it is not in sleep or an interrupt has not been issued. For each polling iteration (eg, for every 1-2 microseconds (μs)), the number of used and free packet descriptors maintained in the Rx queue may be obtained 204 by the DPDK power management components. If zero packets are received for a given polling iteration ( 206 ), the number of iterations for which zero packets have been received may be compared to a consecutive number threshold (eg, 5 iterations) ( 208 ). In some examples, if the consecutive count threshold is not exceeded, the logic flow moves back to 204 .

According to some examples, the 'idle' count may be incremented by one at 210 based on the number of iterations for which zero packet was received. At 212 a determination is made whether the 'idle' count is less than or less than THRESHOLD_1. At 214 , if the 'idle' count is less than THRESHOLD_1, the DPDK polling thread may be put to sleep by the DPDK power management components for a short period of time (eg, several μs). At 216 , if the 'idle' count is less than THRESHOLD_2, the DPDK polling thread may sleep for a relatively long period (eg, tens of μs).

In some examples, the short sleep period may be a short, several μs sleep period to reduce power consumption as compared to a continuous spin loop. As such, the DPDK polling thread avoids costly context switching during times of traffic trends that are not yet discernible. Relatively long sleep periods may allow lower traffic trends to be identified. In this case, the DPDK power management components may sleep the DPDK polling thread for a longer period, and may also send a long sleep indication or C-state hint to the OS power management module. The OS power management module may then cause the PE supporting the DPDK polling thread to enter the ACPI C1 power state. This C1 power state will still allow the PE to quickly power up and enter the C0 power state when new NW traffic arrives. Also, when new NW traffic arrives, the 'idle' count is reset to a count of zero.

According to some examples, THRESHOLD_1 may be several times lower compared to THRESHOLD_2 to sleep the DPDK polling thread after relatively short periods of time when 0 packets are in the Rx queue. However, if the 'idle' count exceeds THRESHOLD_2, a one-shot Rx interrupt may be enabled (220). If there is an incoming packet being received by the NW I/O, a one-shot Rx interrupt is triggered which may cause the paused DPDK polling thread to switch back from interrupt mode back to polling mode (222). An idle count exceeding THRESHOLD_2 may indicate a period of slow network traffic or no network traffic. Also, suspending the DPDK polling thread may allow the OS power management module to put the PE executing the DPDK polling thread in deeper C-states of lower power usage than the C1 state. In effect, the DPDK polling thread can now operate in interrupt mode and switch back to polling mode in response to receiving network traffic again.

In some examples, once packets are received in the Rx queue, the fullness levels of the Rx queue may be determined. For example, if the Rx queue is nearly empty (eg, 25% to 50% full) 224 , the 'trend' count may be incremented 226 by a small number. If the RX queue is half full (eg, 51% to 75%) 234 , the 'trend' count may be incremented 236 by a large number. Also, at 228 if the 'trend' count exceeds the trend count threshold, the DPDK power management components may send a performance indication or P-status hint to the OS power management module. The performance indication may cause the OS power management module to increase operating frequencies (230) or elevate the ACPI P-state for the PE executing the DPDP polling thread. The 'trend' count indicates that the P-states for the PEs will be incrementally increased so that incremental increases in network traffic can be detected, and to balance power savings with performance while processing (232) received packets. can be set to be

According to some examples, if the Rx queue is near full (eg, over 76% full) 238 , then at 240 the number of consecutive polling iterations at which the Rx queue is nearly full is equal to a consecutive threshold (eg, 5 polling iterations) and can be compared. For these examples, if the continuity threshold is exceeded, the DPDK power management components may send a high performance indication or high P-state hint to the OS power management module. The high performance indication may cause the OS power management module to raise the operating frequencies to the highest frequency ( 242 ) or to raise the ACPI P-state for the PE executing the DPDK polling thread to the highest performing P-state. Raising to the highest performance P-state allows the PE running the DPDK polling thread to save power and performance while the OS power management module responds quickly to high network traffic loads and thus processes received packets (232). It will allow us to transition from the balance of

In some examples, the DPDK power management components periodically monitor the amount of time the DPDK polling thread has been sleeping. For these examples, the DPDK power management components may initialize, at 244 , a periodic timer, which may start a timer interval during which monitoring of sleep for the DPDK polling thread may take place. After expiration of the timer at 246 , the DPDK power management components may determine whether the DPDK polling thread is sleeping for more than 25% of polling iterations. As previously mentioned, the DPDK polling thread may sleep for various times based on whether the 'idle' count is less than THRESHOLD_1 or THRESHOLD_2. If the DPDK poll is found to be sleeping for more than 25%, then at 252 the DPDK power management components may send a performance indication or P-status hint to the OS power management module. As a result of the performance indication, the OS power management module may cause the PE executing the DPDK polling thread to have a degraded or reduced operating frequency. In other words, the ACPI P-state for the PE may be degraded to a lower performance P-state.

According to some examples, if the DPDK polling thread is not sleeping for more than 25% of the polling iterations, then at 250 the DPDK power management components determine that the average packet per iteration for packets received during the time interval is a threshold of expected average packet per iteration. It can be determined whether or not If below the threshold, at 252 the DPDK power management components may send a performance indication or P-state hint to the OS power management module. Causes a PE to degrade its P-state in response to more than 25% sleep or fewer than expected packets being received, indicating that monitored information indicative of network traffic or at least processing of packets from network traffic is decreasing. may be a way to degrade performance states to save power based on

3 shows an exemplary first process 300 . As shown in FIG. 3 , the first process includes a process 300 . According to some examples, process 300 may represent how different elements of system 100 may implement portions of logic flow 200 described above with respect to FIG. 2 . Specifically, the parts relate to sleep, idle or interrupt operations taken by the DPDK power management components (PMCs). For these examples, at least some components of the system 100 shown in FIG. 1 may be involved in the process 300 . However, the example process 300 is not limited to implementations using the components of the system 100 shown or described in FIG. 1 .

Starting at process 3.1 (receiving packets), packets may be received by NW I/O device 110 and placed at least temporarily in Rx queues 130 .

Moving on to process 3.2 (Polling and Processing), the DPDK polling threads 140 may poll the Rx queues 130 and process the packets as they are received in the Rx queues 130 .

Moving on to process 3.3 (monitoring received and available packet descriptors), DPDK power management components 150 maintain in Rx queues 130 over multiple polling iterations for DPDK polling threads 140 . logic and/or features to monitor received and available packet descriptors.

Proceeding to process 3.4 (0 packets for successive threshold exceeded), DPDK power management components 150 return 0 for a number of successive polling iterations exceeding a successive threshold (eg, 5 polling iterations). It may include logic and/or features that determine whether a packet has been received.

Moving on to process 3.5 (incrementing the idle count), the DPDK power management components 150 may include logic and/or features to increment the idle count by a count of one when a successive threshold is exceeded.

Moving to process 3.6A (short duration sleep), the DPDK power management components 150 send the DPDK polling threads 140 if the incremental idle count is found to be less than a first idle count threshold (eg, THRESHOLD_1). may include logic and/or features that put them to sleep for short periods of time (eg, 2 μs). The process can then be terminated.

Moving to the first alternative in process 3.6B (long duration sleep), the DPDK power management components 150 are configured such that the incremental idle count is greater than the first idle count threshold but a second idle count threshold (eg, THRESHOLD_2) If found to be less than, it may include logic and/or features that put the DPDK polling threads 140 to sleep for a relatively long sleep period (eg, tens of μs).

Moving to process 3.7B (long sleep indication), the DPDK power management components 150 display a long sleep indication to the OS power management module to indicate that the DPDK polling threads 140 have been in sleep for the long sleep period. It may include logic and/or features that transmit to (PMM) 160 .

Moving to process 3.8B (sleep mode for long duration), OS power management module 160 may cause PE(s) 172 to be in sleep mode for maximum long sleep duration. In some examples, the sleep mode may include an ACPI C1 power state. The process may then end for this first alternative.

Moving on to the second alternative in process 3.6C (turning on the one-shot Rx interrupt), the DPDK power management components 150 based on the idle count exceeding a second idle count threshold (eg, THRESHOLD_2). Thus, it may include logic and/or features to transmit an interrupt turn on hint or message to the NW I/O device 110 .

Moving to process 3.7C (switching to interrupt mode), poll mode driver 142 may switch from operating with NW I/O device 110 in poll mode to interrupt mode. This mode switch may also pause the DPDK polling threads 140 .

Moving on to process 3.8C (receiving packets), network traffic 105 may now include packets for processing by DPDK threads 140 .

Moving on to process 3.9C (switching to poll mode), the poll mode driver 142 can switch back from the poll mode to operating with the NW I/O device 110 , the process then proceeding to this second alternative can be terminated for

4 illustrates an exemplary second process 400 . As shown in FIG. 4 , the second process includes process 400 . Similar to process 300 , process 400 may represent how different elements of system 100 may implement portions of logic flow 200 described above with respect to FIG. 2 . Specifically, the portions relate to monitoring the sleep percentages or average packet per iteration for the DPDK polling threads to determine if it will degrade the performance state for the PE(s) 172 . For these examples, at least some components of system 100 shown in FIG. 1 may be involved in process 400 . However, the example process 400 is not limited to implementations using the components of the system 100 shown or described in FIG. 1 .

Beginning at process 4.1 (Initializing Timer), DPDK power management components 150 may include logic and/or features to initialize or initiate a timer having a timer interval. In some examples, the timer interval may be approximately 100 milliseconds (ms).

Moving on to process 4.2 (monitoring activity to determine sleep %), DPDK power management components 150 implement logic and/or features to monitor how often DPDK polling threads 140 are in sleep. may include

Go to process 4.3 (Timer expires), the timer expires after the timer interval.

Moving on to process 4.4A (Performance Indication (Sleep %)), the DPDK power management components 150 determine if the DPDK polling threads 140 are sleeping for a percentage of the time above the percent threshold during the timer interval. logic and/or features. In some examples, when the sleep percentage for DPDK polling threads 140 exceeds or exceeds a percentage threshold (eg, greater than 25%), DPDK power management components 150 send a performance indication to the OS power management module ( 160) can be sent.

Moving to process 4.5A (degrading performance state), OS power management module 160 may cause PE(s) 172 to degrade its performance state or P-state. The process can then be terminated.

Moving on to the first alternative in process 4.4B (Performance Indication (Packet Average)), the DPDK power management components 150 provide logic and/or a feature for determining whether an average packet per iteration is above or below a packet average threshold. may include parts. In some examples, if the average packet per iteration is below a packet average threshold, the DPDK power management components 150 can send a performance indication to the OS power management module 160 .

Moving to process 4.5B (degrading performance state), OS power management module 160 may cause PE(s) 172 to degrade its performance state or P-state. The process may then end for this first alternative.

5 illustrates an exemplary third process 500 . As shown in FIG. 5 , the third process includes process 500 . According to some examples, process 500 may represent how different elements of system 100 may implement portions of logic flow 200 described above with respect to FIG. 2 . Specifically, those parts relate to monitoring Rx queue fullness to determine if or when to boost performance for the PE(s). For these examples, at least some components of the system 100 shown in FIG. 1 may be involved in the process 500 . However, the example process 500 is not limited to implementations using the components of the system 100 shown or described in FIG. 1 .

Starting at process 5.1 (receiving packets), packets may be received by NW I/O device 110 and placed at least temporarily in Rx queues 130 .

Moving on to process 5.2 (Polling and Processing), the DPDK polling threads 140 may poll the Rx queues 130 and process the packets as they are received in the Rx queues 130 .

Moving on to process 5.3 (monitoring received and available packet descriptors), DPDK power management components 150 maintain in Rx queues 130 over multiple polling iterations for DPDK polling threads 140 . logic and/or features to monitor received and available packet descriptors.

Moving on to process 5.4 (determining Rx queue fullness), DPDK power management components 150 determine Rx queues 130 based on available packet descriptors maintained in Rx queues 130 after each polling iteration. ) and/or features that determine the fullness of

Moving on to process 5.5 (incrementing the trend count), the DPDK power management components 150 reach the determined fullness level of the Rx queues 130 as described above with respect to the logic flow 200 shown in FIG. 2 . may include logic and/or features to increment the trend count by a single count or a large count based on it.

Moving to process 5.6A (performance indication), the DPDK power management components 150 include logic to send a performance indication to the OS power management module 160 based on the incremented trend count exceeding a trend count threshold and / or features.

Moving to process 5.7A (increasing the operating frequency one step up), the OS power management module 160 may increase the performance state or P-state of the PE(s) 172 . In some examples, the performance state for the PE(s) 172 may be raised one level up or to a single P-state, which is the level of the PE(s) 172 when executing the DPDK polling threads 140 . The operating frequency can be increased. The process can then be terminated.

Moving on to the first alternative in process 5.6B (high performance indication), the DPDK power management components 150 determine that the Rx queues 130 are near full (eg, greater than 75%) at the number of consecutive polling iterations. logic and/or features to responsively transmit a high performance indication to the OS power management module 160 .

Moving to process 5.7B (maximum increase in operating frequency), OS power management module 160 may increase the performance state or P-state of PE(s) 172 to the highest or maximum P-state. . In some examples, as a result of raising the PE(s) 172 to the highest or maximum P-state, the PE(s) 172 are raised to their highest or maximum operating frequency when executing the DPDK polling threads 140 . . The process may then end for this first alternative.

6 shows an exemplary block diagram of an apparatus 600 . It should be noted that while the apparatus 600 shown in FIG. 6 has a limited number of elements in a particular topology, the apparatus 600 may include more or fewer elements in alternative topologies as desired for a given implementation. well know

According to some examples, apparatus 600 may be supported by circuitry 620 maintained on a computing platform or network device that may be deployed in a data center. Circuitry 620 may be configured to execute one or more software or firmware implemented modules or components 622-a. Notably, "a" and "b" and "c" and similar directives, as used herein, are intended to be variables representing any positive integer. As such, for example, if one implementation sets the value for a to 6, then the entire set of software or firmware for components 622-a is 3, 622-4, 622-5 or 622-6). The examples presented are not limiting in this regard, and different variables used throughout may represent the same or different integer values. Also, these “components” may be software/firmware stored on a computer readable medium, and although components are shown as separate boxes in FIG. 6 , this may separate these components into different computer readable media components (eg, separate It is not limited to storage in memory, etc.).

According to some examples, circuitry 620 may include a processor, processor circuitry, or processor circuitry. Circuitry 620 includes AMD® Athlon®, Duron®, Phenom®, and Opteron® processors; Various commercially available processors including, but not limited to, Intel Atom®, Celeron®, Core (2) Duo®, Core i3, Core i5, Core i7, Pentium®, Xeon or Xeon Phi® processors may be any of According to some examples, circuitry 620 may also include an application specific integrated circuit (ASIC), and at least some components 622-a may be implemented as hardware elements of the ASIC.

In some examples, device 600 may include a queue component 622-1. Queue component 622-1 is to be executed by circuitry 620 to monitor received and available packet descriptors maintained in a receive queue for the NW I/O device over a number of polling iterations for the DPDK polling thread. can Received and available packet descriptors may be included in received and available packet descriptors 610 , in Rx queue information 623-a (eg, lookup table (LUT)) by queue component 622-1. may be maintained in a data structure such as The queue module 622-1 may determine a fullness level for the receive queue based on available packet descriptors maintained in the receive queue after each polling iteration. A fullness level may also be maintained in the Rx queue information 623-a.

In some examples, queue component 622-1 may also determine the number of packets received in the receive queue for each polling iteration based on information included in Rx queue information 623-a.

According to some examples, apparatus 600 may include an increment component 622 - 2 . Increment component 622 - 2 may be executed by circuitry 620 to increment the trend count based on the fullness level for the receive queue after each polling iteration. For these examples, the trend count may be maintained in the trend count 624 - b (eg, in the LUT) by the increment component 622 - 2 . Increment component 622-2 also increments the idle count by a count of at least one when the queue module 622-1 determines that zero packets have been received for a number of successive polling iterations exceeding a successive threshold. can do it The idle count may be maintained in the idle count 625 - c (eg, in the LUT) by the increment component 622 - 2 .

In some examples, apparatus 600 may also include a performance component 622 - 3 . Performance component 622 - 3 may be executed by circuitry 620 to send a performance indication 640 to the OS power management module based on whether the trend count exceeds a trend count threshold. The performance indication 640 may cause the OS power management module to increase the performance state of the processing element executing the DPDK polling thread. For these examples, the trend count threshold may be maintained by the performance component 622-3 at the trend count threshold 626-d (eg, in the LUT).

According to some examples, the performance component 622-3 responds to a number of successive polling iterations determined by the queue component 622-1 as being nearly full of the receive queue exceeds a successive threshold, An indication 645 may be sent to the OS power management module. The high performance indication 645 may cause the OS power management module to increase the performance state of the processing element to the highest performance state by causing the operating frequency of the processing element to be increased to the highest operating frequency. For these examples, the continuous threshold may be maintained by the performance component 622-3 at the continuous threshold 627 - e (eg, in the LUT).

In some examples, device 600 may also include a sleep component 622 - 4 . Sleep component 622-4 determines that an idle count incremented by the incrementing component and maintained at idle count 625-c is passed by sleep component 622-4 to idle count thresholds 630-h (e.g., , LUT) may be executed by circuitry 620 to sleep the DPDK polling thread for one of a first period or a second period based on whether it exceeds or is below a first idle count threshold maintained. For these examples, the second period of time may be longer than the first period of time. Sleep 615 may include indications or instructions to sleep the DPDK polling thread.

According to some examples, the sleep component 622 - 4 may sleep the DPDK polling thread for a second period based on the idle count exceeding the first idle count threshold and display a long sleep indication 650 , according to some examples. It can be sent to the OS power management module. The long sleep indication 650 may cause the OS power management module to cause the processing element executing the DPDK polling thread to be in a sleep mode for up to a second period of time.

According to some examples, apparatus 600 may also include an interrupt control component 622 - 5 . Interrupt control component 622 - 4 is configured to configure a second idle count at which the idle count incremented by increment component 622 - 2 is maintained at idle count thresholds 630 - h by sleep component 622 - 5 . Based on whether the threshold is exceeded, it may be executed by circuitry 620 to transmit a message to the NW I/O device to enable the one-shot Rx interrupt. For these examples, the message may be included in the one-shot Rx interrupt 635 .

According to some examples, apparatus 600 may also include a timer component 622 - 6 . Timer component 622-6 may be executed by circuitry 620 to start a timer having a timer interval maintained by timer component 622-6 at timer interval 632-j (eg, in a LUT). there is.

In some examples, sleep component 622 - 4 can determine the percentage of repetitions in which the DPKK polling thread was sleeping during the timer interval in response to the timer initiated by timer component 622 - 6 having expired. The percentage may be maintained in the sleep information 631 - i by the sleep component 622 - 4 . For these examples, the performance component 622 - 3 can send the performance indication 640 to the OS power management module based on whether the percentage is above a percentage threshold. The performance indication 640 may cause the OS power management module to degrade the performance state of the processing element, including reducing the operating frequency or reducing the operating voltage of the processing element. The percentage threshold used for this determination may be maintained by the performance component 622 - 3 at the percentage threshold 628 - f (eg, in the LUT).

According to some examples, the queue component 622-1 determines, in response to the timer initiated by the timer component 622-6 expiring, an average packet per iteration for packets received in the receive queue during the timer interval. can The average packet per iteration determined by the queue component 622-1 may be maintained in the Rx queue information 623-a. For these examples, the performance component 622 - 3 can send the performance indication 640 to the OS power management module based on whether the average packets per iteration is above a packet average threshold. The performance indication 640 may cause the OS power management module to degrade the performance state of the processing element, including reducing the operating frequency of the processing element. The packet average threshold may be maintained by the performance component 622 - 3 at the average threshold 629 - g (eg, in the LUT).

The various components of apparatus 600 and a device, node, or logical server implementing apparatus 600 may be communicatively coupled to one another by various types of communication media to coordinate operations. Coordination may involve one-way or two-way information exchange. For example, components may communicate information in the form of signals carried over a communication medium. The information may be implemented as signals assigned to various signal lines. In these assignments, each message is a signal. However, further embodiments may alternatively use data messages. These data messages may be transmitted over various connections. Exemplary connections include parallel interfaces, serial interfaces, and bus interfaces.

Included herein is a set of logic flows that represent example methods of performing novel aspects of the disclosed architecture. For simplicity of description, one or more methods shown herein are shown and described as a series of acts; however, those skilled in the art will understand and appreciate that the methods are not limited by the order of the acts. Some operations may, therefore, be performed in an order different from that shown and described herein and/or concurrently with other operations. For example, those skilled in the art will understand and appreciate that a method may alternatively be represented as a series of interrelated states or events, such as in a state diagram. Moreover, not all of the acts illustrated in a method may be required for a novel implementation.

The logic flow may be implemented in software, firmware, and/or hardware. In software and firmware embodiments, the logic flow may be implemented by computer-executable instructions stored in at least one non-transitory computer-readable medium or machine-readable medium, such as optical, magnetic or semiconductor storage. The embodiments are not limited in this regard.

7 illustrates an exemplary second logic flow. As shown in FIG. 7 , an exemplary second logic flow includes a logic flow 700 . Logic flow 700 may represent some or all of the operations performed by one or more logic, features, or devices described herein, such as apparatus 600 . More particularly, logic flow 700 may be implemented by at least a queue component 622-1, an increment component 622-2, or a performance component 622-3.

According to some examples, logic flow 700 , at block 702 , retrieves received and available packet descriptors maintained in a receive queue for the NW I/O device across multiple polling iterations for the DPDK polling thread. can be monitored. For these examples, queue component 622-1 may monitor the receive queue.

In some examples, logic flow 700 may determine, at block 704 , a fullness level for the receive queue based on available packet descriptors maintained in the receive queue after each polling iteration. For these examples, the queue component 622-1 may determine the fullness level.

According to some examples, logic flow 700 may, at block 706 , increment a trend count based on a fullness level for the receive queue. For these examples, increment component 622 - 2 can increment the trend count.

In some examples, logic flow 700 can send, at block 708 , a performance indication to the OS power management module based on whether the trend count exceeds a trend count threshold, wherein the performance indication is sent to the OS power management module. to increase the performance state of the processing element executing the DPDK polling thread. For these examples, performance component 622 - 3 may transmit a performance indication.

8 shows an exemplary third logic flow. As shown in FIG. 8 , an exemplary third logic flow includes logic flow 800 . Logic flow 800 may represent some or all of the operations performed by one or more logic, features, or devices described herein, such as apparatus 600 . More specifically, logic flow 800 may be implemented by at least a queue component 622-1, an increment component 622-2, or a sleep component 622-4.

According to some examples, logic flow 800 , at block 802 , lists the received and available packet descriptors maintained in a receive queue for the NW I/O device across multiple polling iterations for the DPDK polling thread. can be monitored. For these examples, queue component 622-1 may monitor the receive queue.

In some examples, logic flow 800 determines, at block 804 , the number of packets received in the receive queue for each polling iteration based on available packet descriptors maintained in the receive queue after each polling iteration. can be decided For these examples, the queue component 622-1 may determine the number of packets received in the receive queue.

According to some examples, logic flow 800 may increment the idle count by a count of one if the number of packets received for a number of successive polling iterations exceeding a successive threshold is zero, at block 806 , according to some examples. there is. For these examples, increment component 622 - 2 can increment the trend count.

In some examples, logic flow 800 , at block 808 , polls the DPDK polling thread for one of a first period or a second period based on whether the idle count is above or below the first idle count threshold. and the second period of time is longer than the first period of time. For these examples, sleep component 622-4 may sleep the DPDK polling thread.

9 illustrates an exemplary storage medium 900 . As shown in FIG. 9 , the first storage medium includes a storage medium 900 . The storage medium 900 may include an article of manufacture. In some examples, storage medium 900 may include any non-transitory computer-readable medium or machine-readable medium, such as optical, magnetic, or semiconductor storage. Storage medium 900 may store various types of computer-executable instructions, such as instructions that implement logic flow 700 or logic flow 800 . Examples of computer-readable or machine-readable media are capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, and the like. It may include any tangible medium. Examples of computer-executable instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, visual code, and the like. . Examples are not limited in this regard.

10 illustrates an example computing platform 1000 . In some examples, as shown in FIG. 10 , computing platform 1000 may include processing component 1040 , other platform components 1050 , or communication interface 1060 . According to some examples, computing platform 1000 may include power and/or performance management elements (eg, DPDK power management) that provide power/performance management functionality for a system having DPDK polling threads, such as system 100 of FIG. 1 . components and OS power management module). The computing platform 1000 may be a single physical network device, or it may be a configured logical network device comprising disaggregated physical components or combinations of elements constructed from a shared pool of configurable computing resources located in a data center.

According to some examples, processing component 1040 may execute processing operations or logic for device 600 and/or storage medium 900 . Processing component 1040 may include various hardware elements, software elements, or a combination of both. Examples of hardware elements are devices, logic devices, components, processors, microprocessors, circuits, processor circuits, circuit elements (eg, transistors, resistors, capacitors, inductors, etc.), integrated circuits, application specific integrated circuits (ASICs), PLDs (PLDs). It may include a programmable logic device), a digital signal processor (DSP), a field programmable gate array (FPGA), a memory unit, a logic gate, a register, a semiconductor device, a chip, a microchip, a chipset, and the like. Examples of software elements are software components, programs, applications, computer programs, application programs, device drivers, system programs, software development programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods , procedure, software interface, application program interface (API), instruction set, computing code, computer code, code segment, computer code segment, word, value, symbol, or any combination thereof. Determining whether an example is implemented using hardware elements and/or software elements determines a desired computational speed, power level, thermal tolerance, processing cycle budget, and input data, as desired for a given example. may depend on any number of factors, such as rate, output data rate, memory resources, data bus speed, and other design or performance constraints.

In some examples, other platform components 1050 may include one or more processors, multi-core processors, coprocessors, memory units, chipsets, controllers, peripherals, interfaces, oscillators, timing devices, common computing elements, such as video cards, audio cards, multimedia input/output (I/O) components (eg, digital displays), power supplies, and the like. Examples of memory units include read-only memory (ROM), random-access memory (RAM), dynamic RAM (DRAM), double-data-rate DRAM (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), Polymer memory such as programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, ferroelectric polymer memory, ovonic memory, phase change or ferroelectric memory, silicon- Arrays of devices such as oxide-nitride-oxide-silicon memory, magnetic or optical cards, RAID (Redundant Array of Independent Disks) drives, solid state memory devices (eg USB memory), solid state (SSD) drives), and various types of computer-readable and machine-readable storage media in the form of one or more high-speed memory units, such as any other tangible storage medium suitable for storing information. can

In some examples, communication interface 1060 may include logic and/or features to support the communication interface. For these examples, communication interface 1060 may include one or more communication interfaces that operate according to various communication protocols or standards to communicate either directly or over network communication links. Direct communication may be done using communication protocols or standards described in one or more industry standards (including descendants and variants), such as those associated with the PCIe specification. Network communication may be done using communication protocols or standards, such as those described in one or more Ethernet standards promulgated by the IEEE. For example, one such Ethernet standard may include IEEE 802.3. Network communication may also be done according to one or more OpenFlow specifications, such as the OpenFlow Hardware Abstraction API Specification. Network communication may also be done according to Infiniband Architecture specification or TCP/IP protocol.

As noted above, computing platform 1000 may be implemented in a single network device or a logical network device made up of disaggregated physical components or elements that are constructed from a shared pool of configurable computing resources. Accordingly, functions and/or specific configurations of computing platform 1000 described herein may be included or omitted in various embodiments of computing platform 1000 as suitably desired for a physical or logical network device. there is.

The components and features of computing platform 1000 may be implemented using any combination of discrete circuitry, application specific integrated circuits (ASICs), logic gates, and/or single chip architectures. Moreover, features of the computing platform 1000 may be implemented using a microcontroller, programmable logic array and/or microprocessor, or any combination of the foregoing, where appropriate and appropriate. It should be noted that hardware, firmware and/or software elements may be referred to herein as “logic” or “circuitry”, either individually or in whole.

It will be appreciated that the example computing platform 1000 shown in the block diagram of FIG. 10 may represent one functionally descriptive example of many potential implementations. Accordingly, division, omission or inclusion of block functions shown in the accompanying drawings implies that hardware components, circuits, software and/or elements for implementing these functions are necessarily divided, omitted or included in the embodiments. don't

One or more aspects of at least one example represent various logic within a processor that, when read by a machine, computing device, or system, causes the machine, computing device, or system to manufacture logic that performs the techniques described herein. It may be implemented in representative instructions stored on at least one machine readable medium. These representations, known as “IP cores,” may be stored on a tangible machine-readable medium and supplied to various customers or manufacturing facilities for loading into a manufacturing machine that actually manufactures the logic or processor.

Various examples may be implemented using hardware elements, software elements, or a combination of the two. In some examples, hardware elements are devices, components, processors, microprocessors, circuits, circuit elements (eg, transistors, resistors, capacitors, inductors, etc.), integrated circuits, application specific integrated circuits (ASICs), programmable logic devices (PLDs). , a digital signal processor (DSP), a field programmable gate array (FPGA), a memory unit, a logic gate, a register, a semiconductor device, a chip, a microchip, a chipset, and the like. In some examples, software elements are software component, program, application, computer program, application program, system program, machine program, operating system software, middleware, firmware, software module, routine, subroutine, function, method, procedure, software may comprise an interface, application program interface (API), instruction set, computing code, computer code, code segment, computer code segment, word, value, symbol, or any combination thereof. Determining whether an example is implemented using hardware elements and/or software elements determines a desired computational speed, power level, thermal tolerance, processing cycle budget, input data rate, output data rate, as desired for a given implementation. , memory resources, data bus speed, and other design or performance constraints.

Some examples may include an article of manufacture or at least one computer-readable medium. Computer-readable media can include non-transitory storage media that store logic. In some examples, the non-transitory storage medium is one or more tangible types of storage media capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, and the like. computer-readable storage media of In some examples, logic is a software component, program, application, computer program, application program, system program, machine program, operating system software, middleware, firmware, software module, routine, subroutine, function, method, procedure, software interface , API, instruction set, computing code, computer code, code segment, computer code segment, word, value, symbol, or any combination thereof.

According to some examples, a computer readable medium stores or maintains instructions that, when executed by a machine, computing device or system, cause the machine, computing device or system to perform methods and/or operations according to the described examples. It may include a non-transitory storage medium. Instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. The instructions may be implemented according to a predefined computer language, manner, or syntax that instructs a machine, computing device, or system to perform a particular function. The instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled, and/or interpreted programming language.

Some examples may be described using the expression “in an example” or “an example” along with its derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one example. The phrases "in one example" in various places in the specification are not necessarily all referring to the same example.

Some examples may be described using the expressions “coupled” and “connected” along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, those described using the terms “connected” and/or “coupled” may indicate that two or more elements are in direct physical or electrical contact with each other. However, the term “coupled” can also mean that two or more elements are not in direct contact with each other but still cooperate or interact with each other.

The following examples relate to additional examples of the techniques disclosed herein.

Example 1. An example apparatus maintains received and available packet descriptors in a receive queue for a NW I/O device across multiple polling iterations for a DPDK polling thread and circuitry in a host computing platform. It may include a queue component for execution by circuitry to monitor. The queue module may determine a level of fullness for the receive queue based on available packet descriptors maintained in the receive queue after each polling iteration. The apparatus may also include an increment component for execution by the circuitry that may increment a trend count based on a fullness level for the receive queue after each polling iteration. The apparatus may also include a performance component for execution by the circuitry to transmit a performance indication to the OS power management module based on whether the trend count exceeds a trend count threshold. The performance indication may cause the OS power management module to increase the performance state of the processing element executing the DPDK polling thread.

Example 2. The apparatus of example 1, wherein the OS power management module capable of increasing a performance state of the processing element includes an OS power management module capable of causing an operating frequency of the processing element to be increased.

Example 3. The apparatus of example 1, wherein the fullness level determined by the queue component may include one of nearly empty, half full, or near full.

Example 4. The apparatus of example 3, wherein the increment component is a small number if the fullness level is determined by the queue component to be nearly empty or large if the fullness level is determined by the queue component to be half full By a number - a large number is approximately 100 times the small number - the trend count can be incremented.

Example 5. The apparatus of example 3 is further configured to send a high performance indication to the OS power management module in response to a number of successive polling repetitions determined by the queue component as being near full to the receive queue exceeds a successive threshold. It may include performance components. The high performance indication may cause the OS power management module to increase the performance state of the processing element to the highest performance state by causing the operating frequency of the processing element to be increased to the highest operating frequency.

Example 5-1. The device of Example 3, near empty may be 25% to 50% full, half full may be 51% to 75% full, and near full may be greater than 75% full.

Example 6. The device of example 1, wherein the OS power management module may be capable of increasing the performance state of the processing element in accordance with one or more industry standards, including the ACPI specification, revision 5.0. For these examples, the OS power management module may increase the performance state of the processing element to enter a Pn-1 performance state, where "n" represents the lowest performance state that results in the lowest operating frequency of the processing element.

Example 7. The apparatus of example 1 may also include a queue component that determines a number of packets received in the receive queue for each polling iteration based on available packet descriptors maintained in the receive queue after each polling iteration. can The increment component may increment an idle count by a count of one if the number of packets received for a number of consecutive polling iterations exceeding a consecutive threshold is zero. The apparatus may also include a sleep component for execution by the circuitry to sleep the DPDK polling thread for one of a first period or a second period based on whether the idle count exceeds or is below the first idle count threshold. can For these examples, the second period of time may be longer than the first period of time.

Example 8. The apparatus of example 7 may also include an interrupt turn on message capable of enabling a one-shot Rx interrupt based on whether the idle count exceeds a second idle count threshold. may include an interrupt control component for execution by the circuitry to transmit to the NW I/O device.

Example 9. The apparatus of example 7, wherein the sleep component is further configured to: based on the idle count exceeding the first idle count threshold, sleep the DPDK polling thread for a second period of time, and provide a long sleep indication to the OS power management module can be sent to The long sleep indication may cause the OS power management module to cause the processing element executing the DPDK polling thread to be in the sleep mode for up to a second period of time.

Example 10. The apparatus of example 9 may also include a timer component for execution by circuitry to initiate a timer having a timer interval. The sleep component may, in response to the timer expire, determine the percentage of iterations in which the DPDK polling thread was sleeping during the timer interval. The performance component may send a performance indication to the OS power management module based on whether the percentage is above a percentage threshold. The performance indication may cause the OS power management module to degrade the performance state of the processing element, including reducing the operating frequency or reducing the operating voltage of the processing element.

Example 11. The apparatus of example 9 may also include a timer component for execution by the circuitry to initiate a timer having a timer interval. The queue component may, in response to the timer expire, determine an average packet per repetition for packets received in the receive queue during the timer interval. The performance component may send a performance indication to the OS power management module based on whether the average packets per iteration is below a packet average threshold. The performance indication may cause the OS power management module to degrade the performance state of the processing element, including reducing the operating frequency of the processing element.

Example 12. The apparatus of example 9, wherein the OS power management module may be capable of placing the processing element in a sleep mode in accordance with one or more industry standards, including the ACPI specification, revision 5.0. For these examples, the OS power management module may cause the processing element to enter at least a C1 processor power state to put the processing element in a sleep mode in response to the sleep indication.

Example 13 The apparatus of example 7, wherein the successive threshold may be 5 iterations, and each polling iteration may be approximately every 1 microsecond.

Example 14. The apparatus of example 13, wherein the sleep indication indicating that the idle count is less than the first idle count threshold may sleep the DPDK polling thread for a first period of time. For these examples, the first period may last approximately 5 polling iterations.

Example 15. The apparatus of example 13, wherein the sleep indication indicating that the idle count exceeds the first idle count threshold may sleep the DPDK polling thread for a second period of time. For these examples, the second period may last approximately 50 polling iterations.

Example 16 The apparatus of example 1, wherein the processing element can include one of a core of a multicore processor or a virtual machine supported by one or more cores of the multicore processor.

Example 17 The apparatus of example 1, wherein the DPDK polling thread may execute a network packet processing application to process packets received by the NW I/O device. The network packet processing application may include one of a firewall application, a VPN application, a NAT application, a DPI application, or a load balancer application.

Example 18. The apparatus of example 1 may also include a digital display coupled to the circuitry to present a user interface view.

Example 19. An example method may include monitoring received and available packet descriptors maintained in a receive queue for a NW I/O device across multiple polling iterations for a DPDK polling thread. The method may also include determining a fullness level for the receive queue based on available packet descriptors maintained in the receive queue after each polling iteration. The method may also include incrementing the trend count based on the fullness level for the receive queue. The method may also include sending a performance indication to the OS power management module based on whether the trend count exceeds a trend count threshold. The performance indication may cause the OS power management module to increase the performance state of the processing element executing the DPDK polling thread.

Example 20 The method of example 19, wherein the OS power management module to increase a performance state of the processing element includes an OS power management module capable of causing an operating frequency of the processing element to be increased.

Example 21. The method of example 19, wherein the fullness level can include one of nearly empty, half full, or nearly full.

Example 22 The method of example 21, comprising incrementing the trend count by a small number if the fullness level is nearly empty or by a large number if the fullness level is half full. For these examples, the large number may be approximately 100 times the small number.

Example 23. The method of example 21 also includes sending a high performance indication to the OS power management module in response to a number of consecutive polling iterations in which it is determined that the receive queue is near full exceeds a consecutive threshold. can The high performance indication may cause the OS power management module to increase the performance state of the processing element to the highest performance state, including increasing the operating frequency of the processing element to the highest operating frequency.

Example 24. The method of example 21, wherein nearly empty may be 25% to 50% full, half full may be 51% to 75% full, and near full may be greater than 75% full can

Example 25 The method of example 19, wherein the OS power management module may increase the performance state of the processing element according to one or more industry standards, including the ACPI specification, revision 5.0. For these examples, the OS power management module may increase the performance state of the processing element to enter a Pn-1 performance state, where "n" represents the lowest performance state that results in the lowest operating frequency of the processing element.

Example 26 The method of example 17, wherein the processing element can include one of a core of a multicore processor or a virtual machine supported by one or more cores of the multicore processor.

Example 27 The method of example 19, wherein the DPDK polling thread may execute a network packet processing application to process packets received by the NW I/O device. The network packet processing application may include one of a firewall application, a VPN application, a NAT application, a DPI application, or a load balancer application.

Example 28. The exemplary at least one machine readable medium may include a plurality of instructions that, in response to being executed by the system, may cause the system to perform a method according to any of examples 19-27. can

Example 29. An apparatus may include means for performing the method of any of examples 19-27.

Example 30. The example at least one machine readable medium, in response to being executed on a system at a host computing platform, causes the system to receive for a NW I/O device over multiple polling iterations for a DPDK polling thread. It may include a plurality of instructions to monitor received and available packet descriptors maintained in a queue. The instructions may also cause the system to determine a fullness level for the receive queue based on available packet descriptors maintained in the receive queue after each polling iteration. The instructions may also cause the system to increment the trend count based on the fullness level for the receive queue and send a performance indication to the OS power management module based on whether the trend count exceeds a trend count threshold. The performance indication may cause the OS power management module to increase the performance state of the processing element executing the DPDK polling thread.

Example 31. The at least one machine readable medium of example 30, wherein the OS power management module for increasing a performance state of a processing element may include an OS power management module capable of causing an operating frequency of the processing element to be increased.

Example 32. The at least one machine readable medium of example 30, wherein the fullness level can include one of nearly empty, half full, or near full.

Example 33. The at least one machine readable medium of example 32, the instructions to cause the system to increment the trend count by a small number if the fullness level is nearly empty or by a large number if the fullness level is half full. can make it For these examples, the large number may be approximately 100 times the small number.

Example 34. The at least one machine readable medium of example 32, the instructions further causing the system to further cause the system to: in response to a number of consecutive polling iterations in which it is determined that the receive queue is near full exceeds a consecutive threshold, the high performance An indication may be sent to the OS power management module. For these examples, the high performance indication may cause the OS power management module to increase the performance state of the processing element to the highest performance state, including increasing the operating frequency of the processing element to the highest operating frequency.

Example 35. The at least one machine readable medium of example 32, wherein substantially empty may be 25% to 50% full, half full may be 51% to 75% full, and wherein It may be more than 75% full.

Example 36 The at least one machine readable medium of example 30, wherein the OS power management module may be capable of increasing the performance state of the processing element according to one or more industry standards, including the ACPI specification, revision 5.0. The OS power management module may increase the performance state of the processing element to enter a Pn-1 performance state, where "n" represents the lowest performance state that results in the lowest operating frequency of the processing element.

Example 37 The at least one machine readable medium of example 30, wherein the processing element can include one of a core of a multicore processor or a virtual machine supported by one or more cores of a multicore processor.

Example 38. The at least one machine readable medium of example 30, wherein the DPDK polling thread is capable of executing a network packet processing application to process packets received by the NW I/O device. The network packet processing application may include one of a firewall application, a VPN application, a NAT application, a DPI application, or a load balancer application.

Example 39. An example method may include monitoring received and available packet descriptors maintained in a receive queue for a NW I/O device across multiple polling iterations for a DPDK polling thread. The method may also include determining a number of packets received in the receive queue for each polling iteration based on available packet descriptors maintained in the receive queue after each polling iteration. The method may also include incrementing the idle count by a count of one if the number of packets received for a number of successive polling iterations exceeding the successive threshold is zero. The method may also include sleeping the DPDK polling thread for one of the first period or the second period based on whether the idle count is above or below the first idle count threshold. The second period of time may be longer than the first period.

Example 40. The method of example 39 further includes sending an interrupt turn on hint to the NW I/O device and suspending the DPDK polling thread based on the idle count exceeding a second idle count threshold. can

Example 41. The method of example 39 further, based on the idle count exceeding the first idle count threshold, the DPDK polling thread sleeps for a second period of time. The method may also include sending a long sleep indication to the OS power management module. The long sleep indication may cause the OS power management module to cause the processing element executing the DPDK polling thread to be in the sleep mode for up to a second period of time.

Example 42. The method of example 41 can also include starting a timer having a timer interval. The method may also include, in response to the timer expiring, determining a percentage of iterations in which the DPDK polling thread was sleeping during the timer interval. The method may also include sending a performance indication to the OS power management module based on whether the percentage is above a percentage threshold. The performance indication may cause the OS power management module to degrade the performance state of the processing element, including reducing the operating frequency or reducing the operating voltage of the processing element.

Example 43. The method of example 41 can also include starting a timer having a timer interval. The method may also include determining, in response to the timer expiring, an average packet per repetition for packets received in the receive queue during the timer interval. The method may also include sending a performance indication to the OS power management module based on whether the average packets per iteration is below a packet average threshold. The performance indication may cause the OS power management module to degrade the performance state of the processing element, including reducing the operating frequency of the processing element.

Example 44 The method of example 41, wherein the OS power management module may be capable of placing the processing element in a sleep mode in accordance with one or more industry standards, including the ACPI specification, revision 5.0. For these examples, the OS power management module may cause the processing element to enter at least a C1 processor power state to put the processing element in a sleep mode in response to the sleep indication.

Example 45 The method of example 41, wherein the processing element can be one of a core of a multicore processor or a virtual machine supported by one or more cores of the multicore processor.

Example 46 The method of example 39, wherein the successive threshold may be 5 iterations, and each polling iteration may be approximately every 1 microsecond.

Example 47 The method of example 46, wherein the sleep indication may indicate that the idle count is less than a first idle count threshold, and may sleep the DPDK polling thread for a first period of time. The first period may last approximately 5 polling iterations.

Example 48 The method of example 46, wherein the sleep indication may indicate that the idle count exceeds a first idle count threshold, and may sleep the DPDK polling thread for a second period of time. The second period may last approximately 50 polling iterations.

Example 49 The method of example 39, wherein the DPDK polling thread may execute a network packet processing application to process packets received by the NW I/O device. The network packet processing application may include one of a firewall application, a VPN application, a NAT application, a DPI application, or a load balancer application.

Example 50. Illustrative at least one machine readable medium includes a plurality of, in response to being executed by a system at a host computing platform, capable of causing a system to perform a method according to any one of examples 39-49. may contain commands.

Example 51. An exemplary apparatus can include means for performing the method of any one of examples 39-49.

Example 52. The example at least one machine-readable medium, in response to being executed on a system at a host computing platform, causes the system to receive for a NW I/O device over multiple polling iterations for a DPDK polling thread. It may include a plurality of instructions that may allow monitoring of received and available packet descriptors maintained in a queue. The instructions may also cause the system to determine the number of packets received in the receive queue for each polling iteration based on available packet descriptors maintained in the receive queue after each polling iteration. The instructions may also cause the system to increment the idle count by a count of one if the number of packets received is zero for a number of successive polling iterations exceeding the successive threshold. The instructions may also cause the DPDK polling thread to sleep for one of the first period or the second period based on whether the idle count is above or below the first idle count threshold. The second period of time may be longer than the first period.

Example 53. The at least one machine readable medium of example 52, the instructions further causing the system to cause the system to send an interrupt turn on hint to the NW I/O device based on the idle count exceeding a second idle count threshold. Send and pause the DPDK polling thread.

Example 54. The at least one machine readable medium of example 52, wherein based on the idle count exceeding the first idle count threshold, the DPDK polling thread sleeps for a second period of time. The instructions may further cause the system to send a long sleep indication to the OS power management module. The long sleep indication may cause the OS power management module to cause the processing element executing the DPDK polling thread to be in the sleep mode for up to a second period of time.

Example 55. The at least one machine readable medium of example 54, the instructions further to cause the system to start a timer having a timer interval, and in response to the timer expiring, the DPDK polling thread was sleeping during the timer interval. Lets you determine the percentage of iterations. The instructions may also cause the system to send a performance indication to the OS power management module based on whether the percentage is above a percentage threshold. The performance indication may cause the OS power management module to degrade the performance state of the processing element, including reducing the operating frequency or reducing the operating voltage of the processing element.

Example 56. The at least one machine readable medium of example 54, the instructions further to cause the system to start a timer having a timer interval, and in response to the timer expiring, packets received in the receive queue during the timer interval Determine the average packet per iteration for . The instructions may also cause the system to send a performance indication to the OS power management module based on whether the average packets per iteration is below a packet average threshold. The performance indication may cause the OS power management module to degrade the performance state of the processing element, including reducing the operating frequency of the processing element.

Example 57. The at least one machine readable medium of example 54, wherein the OS power management module is capable of putting the processing element in a sleep mode in accordance with one or more industry standards, including the ACPI specification, revision 5.0. The OS power management module may cause the processing element to enter at least a C1 processor power state to put the processing element in a sleep mode in response to the sleep indication.

Example 58 The at least one machine readable medium of example 54, wherein the processing element can include one of a core of a multicore processor or a virtual machine supported by one or more cores of a multicore processor.

Example 59. The at least one machine readable medium of example 51, wherein the successive threshold may include 5 iterations, and each polling iteration may be approximately every 1 microsecond.

Example 60 The at least one machine readable medium of example 59, wherein the sleep indication can indicate that the idle count is less than a first idle count threshold, and can sleep the DPDK polling thread for a first period of time. The first period may last approximately 5 polling iterations.

Example 61 The at least one machine readable medium of example 59, wherein the sleep indication can indicate that the idle count exceeds a first idle count threshold, and can put the DPDK polling thread to sleep for a second period of time. The second period may last approximately 50 polling iterations.

Example 62. The at least one machine readable medium of example 52, wherein the DPDK polling thread is capable of executing a network packet processing application to process packets received by the NW I/O device. The network packet processing application may include one of a firewall application, a VPN application, a NAT application, a DPI application, or a load balancer application.

It should be emphasized that 37 C.F.R. that an abstract of the present disclosure is provided to comply with Section 1.72(b). The abstract is provided with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing detailed description, it can be seen that various features are grouped together in a single embodiment in order to streamline the present disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed examples require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in some, but not all, features of a single disclosed example. Accordingly, the following claims are hereby incorporated into the detailed description for carrying out the invention, with each claim standing on its own as a separate example. In the appended claims, the terms "including" and "in which" are used as plain English equivalents of the respective terms "comprising" and "wherein". . Moreover, the terms "first," "second," and "third," etc. are used merely as modifiers and are not intended to impose numerical requirements on their objects.

Although the subject matter has been described in terms of structural features and/or method acts, it will be appreciated that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims (30)

As a device,
circuitry in the host computing platform;
Monitoring received and available packet descriptors maintained in a receive queue for a NW network input/output (NW I/O) device across multiple polling iterations for a data plane development kit (DPDK) polling thread. a queue component for execution by the circuitry to: the queue component provides a level of fullness for the receive queue based on available packet descriptors maintained in the receive queue after each polling iteration. fullness), and the queue component determines the number of packets received in the receive queue for each polling iteration based on available packet descriptors maintained in the receive queue after each polling iteration; ;
an increment component for execution by the circuitry to increment a trend count based on the fullness level for the receive queue after each polling iteration, wherein the increment component sets a successive threshold increment the idle count by a count of 1 if the number of packets received for an exceeding number of consecutive polling iterations is 0;
a performance component for executing by the circuitry to transmit a performance indication to an operating system (OS) power management module based on whether the trend count exceeds a trend count threshold - the performance the indication may cause the OS power management module to increase the performance state of a processing element executing the DPDK polling thread;
a sleep component for execution by the circuitry to sleep the DPDK polling thread for one of a first period or a second period based on whether the idle count is above or below a first idle count threshold component), wherein the second period is longer than the first period; and
based on whether the idle count exceeds a second idle count threshold, to send an interrupt turn on message capable of enabling a one-shot receive (Rx) interrupt to the NW I/O device. an interrupt control component for execution by the circuitry;
A device comprising a. The apparatus of claim 1 , wherein the OS power management module for increasing the performance state of the processing element comprises the OS power management module capable of causing an operating frequency of the processing element to be increased. 2. The method of claim 1, wherein the fullness level determined by the queue component comprises one of near empty, half full, or near full; wherein is 25% to 50% full, half full is 51% to 75% full, and near full is more than 75% full. 4. The method of claim 3, wherein the increment component is determined by the queue component to be half full or by a small number if the fullness level is determined by the queue component to be nearly empty. increment the trend count by a larger number if the larger number is 100 times the smaller number. 4. The method of claim 3,
In response to a consecutive number of polling interations determined by the queue component as substantially full of the receive queue exceeding a consecutive threshold, a performance indication is displayed to the OS power management module the performance component transmitting to - the performance indication causes the OS power management module to increase the performance state of the processing element to a highest performance state by causing the operating frequency of the processing element to be increased to a highest operating frequency. may - a device comprising delete The OS power management module of claim 1 , wherein the OS power management module is capable of increasing the performance state of the processing element according to one or more industry standards, including an Advanced Configuration and Power Interface (ACPI) specification, revision 5.0. a module may increase the performance state of the processing element to enter a Pn-1 performance state, wherein "n" represents the lowest performance state that results in the lowest operating frequency of the processing element. , Device. delete delete The sleep of claim 1, wherein based on the idle count exceeding the first idle count threshold, to sleep a DPDK polling thread for the second period and to send a long sleep indication to the OS power management module a component, wherein the long sleep indication may cause the OS power management module to cause the processing element executing the DPDK polling thread to be in a sleep mode for up to the second period of time. As a device,
circuitry in the host computing platform;
circuitry to monitor received and available packet descriptors maintained in a receive queue for a NW network input/output (NW I/O) device over multiple polling iterations for a data plane development kit (DPDK) polling thread. a queue component for executing by - the queue component determines a fullness level for the receive queue based on available packet descriptors maintained in the receive queue after each polling iteration, the queue component determining the fullness level for the receive queue after each polling iteration determining the number of packets received in the receive queue for each polling iteration based on available packet descriptors maintained in the receive queue after iteration;
an incrementing component for execution by the circuitry to increment a trend count based on the fullness level for the receive queue after each polling iteration, wherein the incrementing component exceeds a successive threshold number of successive polling iterations increment the idle count by a count of 1 if the number of packets received for ;
a performance component for executing by the circuitry to transmit a performance indication to an operating system (OS) power management module based on whether the trend count exceeds a trend count threshold, the performance indication to the OS power management module increase the performance state of a processing element executing the DPDK polling thread;
a sleep component for execution by the circuitry to sleep the DPDK polling thread for one of a first period or a second period based on whether the idle count is above or below a first idle count threshold; a second period of time is longer than the first period of time, and the sleep component causes a DPDK polling thread to sleep for the second period based on the idle count exceeding the first idle count threshold, and to issue a long sleep indication. send to the OS power management module, wherein the long sleep indication may cause the OS power management module to cause the processing element executing the DPDK polling thread to be in a sleep mode for at most the second period;
A timer component for execution by the circuitry to initiate a timer having a timer interval.
including,
the sleep component determines, in response to the timer expiring, the percentage of iterations in which the DPDK polling thread was sleeping during the timer interval;
The performance component is configured to: based on whether the percentage is above a percentage threshold, a performance indication, wherein the performance indication causes the OS power management module to: reduce an operating frequency or reduce an operating voltage of the processing element; capable of degrading the performance state of the processing element to the OS power management module. As a device,
circuitry in the host computing platform;
circuitry to monitor received and available packet descriptors maintained in a receive queue for a NW network input/output (NW I/O) device over multiple polling iterations for a data plane development kit (DPDK) polling thread. a queue component for executing by - the queue component determines a fullness level for the receive queue based on available packet descriptors maintained in the receive queue after each polling iteration, the queue component determining the fullness level for the receive queue after each polling iteration determining the number of packets received in the receive queue for each polling iteration based on available packet descriptors maintained in the receive queue after iteration;
an incrementing component for execution by the circuitry to increment a trend count based on the fullness level for the receive queue after each polling iteration, wherein the incrementing component exceeds a successive threshold number of successive polling iterations increment the idle count by a count of 1 if the number of packets received for ;
a performance component for executing by the circuitry to transmit a performance indication to an operating system (OS) power management module based on whether the trend count exceeds a trend count threshold, the performance indication to the OS power management module increase the performance state of a processing element executing the DPDK polling thread;
a sleep component for execution by the circuitry to sleep the DPDK polling thread for one of a first period or a second period based on whether the idle count is above or below a first idle count threshold; a second period of time is longer than the first period of time, and the sleep component causes a DPDK polling thread to sleep for the second period based on the idle count exceeding the first idle count threshold, and to issue a long sleep indication. send to the OS power management module, wherein the long sleep indication may cause the OS power management module to cause the processing element executing the DPDK polling thread to be in a sleep mode for at most the second period;
A timer component for execution by the circuitry to initiate a timer having a timer interval.
including,
the queue component determines, in response to the timer expiring, an average packet per iteration for packets received in the receive queue during the timer interval;
wherein the performance component is based on whether the average packets per iteration is less than a packet average threshold, wherein the performance indication causes the OS power management module to reduce an operating frequency of the processing element. to the OS power management module. 11. The OS power management module of claim 10, wherein the OS power management module is capable of placing the processing element in a sleep mode according to one or more industry standards, including Advanced Configuration and Power Interface (ACPI) specification, revision 5.0; , causing the processing element to enter at least a C1 processor power state to place the processing element in the sleep mode in response to the sleep indication. The apparatus of claim 1 , wherein the successive threshold comprises 5 iterations, each polling iteration being done every 1 microsecond. As a device,
circuitry in the host computing platform;
circuitry to monitor received and available packet descriptors maintained in a receive queue for a NW network input/output (NW I/O) device over multiple polling iterations for a data plane development kit (DPDK) polling thread. a queue component for executing by - the queue component determines a fullness level for the receive queue based on available packet descriptors maintained in the receive queue after each polling iteration, the queue component determining the fullness level for the receive queue after each polling iteration determining the number of packets received in the receive queue for each polling iteration based on available packet descriptors maintained in the receive queue after iteration;
an incrementing component for execution by the circuitry to increment a trend count based on the fullness level for the receive queue after each polling iteration, wherein the incrementing component exceeds a successive threshold number of successive polling iterations increment the idle count by a count of 1 if the number of packets received for ;
a performance component for executing by the circuitry to transmit a performance indication to an operating system (OS) power management module based on whether the trend count exceeds a trend count threshold, the performance indication to the OS power management module increase the performance state of a processing element executing the DPDK polling thread;
a sleep component for execution by the circuitry to sleep the DPDK polling thread for one of a first period or a second period based on whether the idle count is above or below a first idle count threshold; the second period is longer than the first period;
including,
the successive threshold includes 5 iterations, each polling iteration being done every 1 microsecond, a sleep indication indicating that the idle count is less than the first idle count threshold, and sending the DPDK polling thread to the first sleep for a period of time, wherein the first period lasts for 5 polling iterations. As a device,
circuitry in the host computing platform;
circuitry to monitor received and available packet descriptors maintained in a receive queue for a NW network input/output (NW I/O) device over multiple polling iterations for a data plane development kit (DPDK) polling thread. a queue component for executing by - the queue component determines a fullness level for the receive queue based on available packet descriptors maintained in the receive queue after each polling iteration, the queue component determining the fullness level for the receive queue after each polling iteration determining the number of packets received in the receive queue for each polling iteration based on available packet descriptors maintained in the receive queue after iteration;
an incrementing component for execution by the circuitry to increment a trend count based on the fullness level for the receive queue after each polling iteration, wherein the incrementing component exceeds a successive threshold number of successive polling iterations increment the idle count by a count of 1 if the number of packets received for ;
a performance component for executing by the circuitry to transmit a performance indication to an operating system (OS) power management module based on whether the trend count exceeds a trend count threshold, the performance indication to the OS power management module increase the performance state of a processing element executing the DPDK polling thread;
a sleep component for execution by the circuitry to sleep the DPDK polling thread for one of a first period or a second period based on whether the idle count is above or below a first idle count threshold; the second period is longer than the first period;
including,
The successive threshold includes 5 iterations, each polling iteration being done every 1 microsecond, a sleep indication indicating that the idle count exceeds the first idle count threshold, and sending the DPDK polling thread to the second sleep for two periods, the second period lasting 50 polling iterations. The apparatus of claim 1 , wherein the processing element comprises one of a core of a multicore processor or a virtual machine supported by one or more cores of the multicore processor. 2. The DPDK polling thread capable of executing a network packet processing application to process packets received by the NW I/O device - the network packet processing application is a firewall application, a virtual private network (VPN) application , including one of a network address translation (NAT) application, a deep packet inspection (DPI) application, or a load balancer application. In response to being executed on a system at a host computing platform, the system causes
monitor received and available packet descriptors maintained in a receive queue for a NW network input/output (NW I/O) device across multiple polling iterations for a data plane development kit (DPDK) polling thread;
determine a fullness level for the receive queue based on available packet descriptors maintained in the receive queue after each polling iteration;
increment a trend count based on the fullness level for the receive queue;
determine a number of packets received in the receive queue for each polling iteration based on available packet descriptors maintained in the receive queue after each polling iteration;
increment the idle count by a count of 1 if the number of packets received for the number of consecutive polling iterations exceeding the consecutive threshold is 0;
send a performance indication to an operating system (OS) power management module based on whether the trend count exceeds a trend count threshold, wherein the performance indication causes the OS power management module to execute the DPDK polling thread. - May increase the performance state of ;
make the DPDK polling thread sleep for one of a first period or a second period based on whether the idle count exceeds or falls below a first idle count threshold, wherein the second period is greater than the first period. More Kim - ;
send an interrupt turn on message capable of enabling a one-shot receive (Rx) interrupt to the NW I/O device based on whether the idle count exceeds a second idle count threshold;
At least one machine-readable medium comprising a plurality of instructions. 20. The method of claim 19, wherein the fullness level comprises one of near empty, half full or near full, wherein the near empty is 25% to 50%. at least one machine-readable medium, wherein said half-full is 51% to 75% full, and wherein said nearly full is more than 75% full. 21. The method of claim 20, wherein the instructions further cause the system to:
transmit a performance indication to the OS power management module in response to a number of consecutive polling iterations in which the receive queue is determined to be near full exceeds a consecutive threshold, the performance indication causing the OS power management module to , capable of increasing the performance state of the processing element to the highest performance state, including increasing the operating frequency of the processing element to the highest operating frequency; at least one machine readable medium. delete 20. The system of claim 19, wherein the OS power management module is capable of increasing the performance state of the processing element according to one or more industry standards, including an Advanced Configuration and Power Interface (ACPI) specification, revision 5.0, and wherein the OS power the management module may increase the performance state of the processing element to enter a Pn-1 performance state, where "n" represents the lowest performance state that results in the lowest operating frequency of the processing element, at least one machine-readable possible medium. 20. The method of claim 19, wherein the DPDK polling thread is capable of executing a network packet processing application to process packets received by the NW I/O device, the network packet processing application being a firewall application, virtual private network (VPN) At least one machine readable medium comprising one of an application, a network address translation (NAT) application, a deep packet inspection (DPI) application, or a load balancer application. delete delete delete delete delete delete

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