KR102204954B1 - Can controller and method for transmission of data using the same - Google Patents

Abstract

The present invention relates to a CAN controller and a data transmission method using the same. A CAN controller according to an embodiment of the present invention includes a receiver, a receive first-in, first-out memory, a transmit first-in, first-out memory, and a transmitter. The receiver analyzes the received information received from the CAN bus according to the set protocol. The reception first-in, first-out memory stores reception information so as to overwrite previously stored reception information based on the identification data and bus load of the reception information. The transmission first-in, first-out memory stores transmission information so that it is overwritten with previously stored transmission information based on the identification data of the transmission information and the processor load. The transmitter sets the protocol and transmits the transmission information stored in the transmission first-in, first-out memory to the CAN bus according to the set protocol. According to the present invention, various CAN protocols are supported, and speed of CAN communication is ensured.

Description

CAN controller and data transmission method using it {CAN CONTROLLER AND METHOD FOR TRANSMISSION OF DATA USING THE SAME}

The present invention relates to an architecture supporting a vehicle network standard CAN (Controller Area Network), and more particularly, to a CAN controller and a data transmission method using the same.

In a vehicle system, a controller area network (CAN) is used as a standard communication standard as a vehicle network protocol for communication between an ECU (Electronic Control Unit) or peripheral electronic equipment. Since the number of electronic control devices included in a conventional vehicle system is limited, each of the electronic control devices is connected by a point-to-point connection method. However, such a point-to-point connection method can rapidly increase the complexity, cost, and weight of connection as the number of electronic control devices increases. Since CAN communication uses a serial bus network method, communication between various electronic control devices is easy.

CAN communication is designed to allow electronic control devices to communicate with each other via a CAN bus without a host. To this end, the electronic control device may include a CAN controller connected to the CAN bus. The CAN controller controls the communication between the electronic control unit and the CAN bus. The vehicle system requires rapid data communication in order to ensure the safety of the occupant. Accordingly, there is a demand for a CAN controller capable of minimizing the delay in data communication and securing the speed of CAN communication.

CAN 2.0 A and CAN 2.0 B are used as protocols for CAN communication. In addition, CAN 2.0 A FD and CAN 2.0 B FD have been additionally developed recently. Each data frame structure of CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, and CAN 2.0 B FD is different. Therefore, there is a demand for a CAN controller that can be easily configured to fit this type of protocol.

The present invention provides a CAN controller capable of supporting all of CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, and CAN 2.0 B FD and securing the speed of CAN communication, and a data transmission method using the same.

The CAN controller according to an embodiment of the present invention includes an interface, a transmitter, a receiver, a receive first-in, first-out memory, and a transmit first-in, first-out memory. The interface provides reception information stored in a reception first-in, first-out memory to the processor, or receives transmission information from the processor.

The transmitter sets the protocol and transmits the transmission information stored in the transmission first-in, first-out memory to the CAN bus according to the protocol. The transmitter includes a protocol generator. The protocol generator may set a protocol by selecting target bit states of a data frame corresponding to the protocol from among a plurality of bit states. The protocol generator may sequentially transition each of the target bit states to determine a data frame of transmission information. The protocol generator may select one of CAN 2.0 A protocol, CAN 2.0 B protocol, CAN 2.0 A FD protocol, and CAN 2.0 B FD protocol, and select target bit states based on the selected protocol.

The receiver analyzes the received information received from the CAN bus according to the set protocol. The receiver may include a protocol analyzer, a masking filter register, a baud-rate adjuster, and an error detector. The protocol analyzer may analyze received information by sequentially transitioning target bit states. The masking filter register may filter reception information based on identification data of the reception information. The baud-rate adjuster may adjust the baud rate of a data frame of received information according to a set protocol. The error detector may detect an error in the received information and determine whether to provide the received information to the receive first-in, first-out memory.

The reception first-in, first-out memory stores reception information so that it is overwritten with previously stored reception information based on the identification data of the reception information and the bus load of the CAN bus. The transmission first-in, first-out memory stores transmission information so that it is overwritten with previously stored transmission information based on the identification data of the transmission information and the processor load.

The CAN controller further includes an identification data scanner, a bus load detector, and a processor load detector. For example, when the bus load is higher than the processor load, the identification data scanner may overwrite the reception information in a memory block of the reception first-in, first-out memory in which information having the same identification data as the identification data of the reception information is stored. For example, when the processor load is higher than the bus load, the identification data scanner may overwrite the transmission information in a memory block of a transmission first-in, first-out memory in which information having the same identification data as the identification data of the transmission information is stored. The bus load detector can detect the bus load, and the processor load detector can detect the processor load.

The data transmission method of the CAN controller according to an embodiment of the present invention includes the steps of receiving data information, detecting the amount of data information to be received, and storing information having the same identification data as the identification data of the data information. Retrieving the memory block of the memory, and overwriting the data information on the memory block based on the amount of data information to be received.

For example, the data information may be transmission information provided from a processor. In this case, detecting the amount of data information may include detecting a processor load and comparing the processor load and the bus load. In the step of overwriting data information, if the processor load is greater than the bus load or a set reference load value, the transmission information may be overwritten. The data transmission method of the CAN controller may further include sequentially outputting information stored in the first-in, first-out memory to the CAN bus.

For example, the data information may be reception information provided from a CAN bus. In this case, detecting the amount of data information may include detecting a bus load of the CAN bus and comparing the processor load with the bus load. In the step of overwriting data information, if the bus load is greater than the processor load or the set reference load value, the received information may be overwritten. The data transmission method of the CAN controller may further include sequentially outputting information stored in the first-in, first-out memory to the processor.

The CAN controller and the data transmission method using the same according to an embodiment of the present invention can support various CAN protocols by setting the order of state transitions, and data communication by overwriting data in a first-in-first-out memory according to a bus load and a processor load. Can ensure the speed of the

1 is a block diagram of a CAN system according to an embodiment of the present invention.
2 is a block diagram of a CAN controller included in FIG. 1.
3 is a block diagram of a concrete protocol engine of FIG. 2.
4 is a diagram showing the structure of a data frame for the CAN 2.0 A protocol.
5 is a diagram showing the structure of a data frame for the CAN 2.0 B protocol.
6 is a diagram showing the structure of a data frame for CAN 2.0 A FD protocol.
7 is a diagram showing the structure of a data frame for the CAN 2.0 B FD protocol.
8 is a block diagram in which the data buffer unit of FIG. 2 or 3 is embodied.
9 is a flowchart for a method of transmitting received information according to an embodiment of the present invention.
10 is a flowchart of a method of transmitting transmission information according to an embodiment of the present invention.

In the following, embodiments of the present invention are described clearly and in detail to the extent that a person having ordinary knowledge in the technical field of the present invention can easily implement the present invention. Below, a CAN controller for CAN (Controller Area Network) communication delivers transmission information or reception information. Transmission information and reception information may be partially changed in form due to various reasons such as protocol setting of the CAN controller, baud rate adjustment, bit stuffing, or clock synchronization. If the meaning of the data included in each of the transmission information and the reception information is maintained, even if the format of the transmission information and the reception information changes in terms of efficiency of data communication or minimization of errors, it will be referred to as transmission information and reception information without changing the terms. will be.

1 is a block diagram of a CAN system according to an embodiment of the present invention. The CAN system 100 may be a system that performs communication by any one of CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, and CAN 2.0 B FD protocols to be described later. Referring to FIG. 1, the CAN system 100 may include first to third electronic control devices 110 to 130 and a CAN bus 140. Although three electronic control devices are illustrated as an example, there is no limit to the number of electronic control devices. The CAN system 100 can be applied to various fields using the CAN protocol. For example, the CAN system 100 may be a vehicle system.

The first electronic control device 110 includes a first processor 112 and a first CAN controller 114. The second electronic control device 120 includes a second processor 122 and a second CAN controller 124. The third electronic control device 130 includes a third processor 132 and a third CAN controller 134. Each of the first to third electronic control devices 110 to 130 is connected to the CAN bus 140 to perform communication. For example, when the CAN system 100 is a vehicle system, each of the first to third electronic control devices 110 to 130 may be a device for electronically controlling various vehicle devices such as an engine, a steering wheel, and a brake. .

The first to third processors 112 to 132 may perform a function of a central processing unit (CPU) for a corresponding electronic control device. For example, when the first electronic control device 110 is an ECU for controlling an engine, the first processor 112 may perform a control operation and a calculation operation required to control the engine. The first processor 112 may provide information generated by such a control operation and an operation operation as a transmission signal to the first CAN controller 114. In addition, the first processor 112 may receive information generated by the second processor 122 or the third processor 132 from the first CAN controller 114. Accordingly, the electronic control device can interact with other electronic control devices, and through such interaction, complex functions such as autonomous driving can be performed.

The first to third CAN controllers 114 to 134 control transmission and reception of information to a corresponding electronic control device. Each of the first to third CAN controllers 114 to 134 provides information including identification data to the CAN bus 140. Each of the first to third CAN controllers 114 to 134 analyzes identification data of information provided on the CAN bus 140 to determine whether to receive the information. The identification data represents a property of the corresponding information, and each of the first to third CAN controllers 114 to 134 may determine whether information is necessary for driving the corresponding electronic control device through the identification data.

Each of the first to third CAN controllers 114 to 134 may integrally support various CAN protocols. In addition, each of the first to third CAN controllers 114 to 134 detects the load of the corresponding processor or the load of the CAN bus 140 among the first to third processors 112 to 132 and transmits the latest transmission. Information or received information can be overwritten. Accordingly, the efficiency of the CAN system 100 can be ensured, and a delay in transmission of information due to a load can be prevented, thereby ensuring stability. Details of overwriting the transmission information or the reception information will be described later.

The CAN bus 140 may provide a communication path between the first to third electronic control devices 110 to 130 of the CAN system 100. The first to third electronic control devices 110 to 130 may exchange information with each other through the CAN bus 140. In the case of using the CAN bus 140, since information is exchanged without directly connecting each of the electronic control devices, efficiency in terms of complexity, cost, and weight of the connection between the electronic control devices can be secured.

2 is a block diagram of a CAN controller included in FIG. 1. For the convenience of description, with reference to the reference numerals in FIG. 1, the configurations of FIG. The CAN controller 200 may be viewed as first to third CAN controllers 114 to 134 of FIG. 1. Hereinafter, the CAN bus will be described with reference to the reference numerals of the CAN bus 140 of FIG. 1, and the processor to be described later will be described with reference to the reference numerals of the first processor 112 of FIG. 1.

Referring to FIG. 2, the CAN controller 200 includes a synchronizer 210 and a protocol engine 220. The protocol engine 220 includes an interface 221, a data buffer unit 222, and a transceiver 223. The CAN controller 200 may be included in the first to third electronic control devices 110 to 130. The CAN controller 200 may receive data information from the processor 112 and output the data information to the CAN bus 140. Alternatively, the CAN controller 200 may receive data information from the CAN bus 140 and output the data information to the processor 112.

The synchronizer 210 may be connected to the processor 112 to perform data communication. The synchronizer 210 may be connected to the processor 112 through a peripheral bus. For example, the peripheral device bus may be an Advanced Peripheral Bus (APB). The clock frequency and phase of the peripheral bus may be different from the clock frequency and phase of the CAN controller 200. In this case, clock domain crossing (CDC) may occur. The synchronizer 210 may synchronize the clock of the peripheral device bus and the clock of the CAN controller 200.

The protocol engine 220 controls data communication between the processor 112 and the CAN bus 140. To this end, the protocol engine 220 may generate a protocol for data communication with the CAN bus 140. The protocol engine 220 may receive transmission information of the processor 112 provided through the synchronizer 210. The protocol engine 220 may transmit transmission information to the CAN bus 140. Transmission information provided on the CAN bus 140 may be provided to a CAN controller included in another electronic control device. The protocol engine 220 may receive reception information provided through the CAN bus 140. The protocol engine 220 may transmit the received information to the synchronizer 210. The synchronizer 210 may provide the received information to the processor 112.

The interface 221 may be implemented as a circuit for performing data communication between the protocol engine 220 and the processor 112. The interface 221 may provide transmission information received from the synchronizer 210 to the data buffer unit 222. The interface 221 may receive a received signal from the data buffer unit 222 and provide it to the synchronizer 210. The received signal may be provided to the peripheral device bus through the synchronizer 210 and may be provided to the processor 112.

The data buffer unit 222 may store transmission information provided from the transceiver 223. The data buffer unit 222 may sequentially store transmission information according to the passage of time, and may provide the transmission information to the interface 221 in the stored order. To this end, the data buffer unit 222 may include a First In First Out (FIFO) memory. Also, the data buffer unit 222 may store reception information provided from the interface 221. The data buffer unit 222 may sequentially store the reception information according to the passage of time, and provide the reception information to the transceiver 223 in the stored order. To this end, the data buffer unit 222 may include a first-in, first-out memory.

The data buffer unit 222 may output data in an order in which data is inputted in a normal state. However, when the amount of data processing of the processor 112 is large or the amount of data provided to the CAN bus 140 is large, it may take time for the data buffer unit 222 to output all data. In particular, in a vehicle system in which the CAN communication method is frequently used, the delay in data output can be directly related to the safety of the occupant. In addition, due to the characteristics of a vehicle system where the surrounding situation changes rapidly in real time, and the most recent data is more important than the previous data, delaying data output to output all data may be inefficient. Accordingly, when the amount of data information to be provided to the data buffer unit 222 is large, new data information may be overwritten on previously stored data information. Details about this will be described later.

The transceiver 223 receives transmission information from the data buffer unit 222 and transmits it to the CAN bus 140. The transceiver 223 receives reception information from the CAN bus 140 and transmits it to the data buffer unit 222. The transceiver 223 may preset a protocol. The transceiver 223 may transmit transmission information to the CAN bus 140 and receive reception information from the CAN bus 140 according to a set protocol. The protocol may be any one of CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, and CAN 2.0 B FD. The transceiver 223 may support all of CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, and CAN 2.0 B FD, and may select a protocol determined according to the vehicle system. Details about this will be described later.

3 is a block diagram of a concrete protocol engine of FIG. 2. Referring to FIG. 3, the protocol engine 300 includes an interface 310, a data buffer unit 320, a receiver 330, and a transmitter 340. The interface 310 of FIG. 3 is substantially the same as the interface 221 of FIG. 2, and thus a detailed description thereof is omitted. The data buffer unit 320 of FIG. 3 corresponds to the data buffer unit 222 of FIG. 2. The receiver 330 and the transmitter 340 of FIG. 3 may be viewed as a configuration included in the transceiver 223 of FIG. 2.

The data buffer unit 320 includes a receive first in first out (FIFO) memory 322 and a transmit first in first out memory 324. In principle, the reception first-in, first-out memory 322 and the transmission first-in, first-out memory 324 store data information in the order of reception, and output data information in the stored order. The reception first-in, first-out memory 322 stores reception information in the order received from the receiver 330. The reception first-in, first-out memory 322 outputs reception information to the interface 310 in the stored order. The transmission first-in, first-out memory 324 stores transmission information in the order received from the interface 310. The transmission first-in, first-out memory 324 outputs transmission information to the transmitter 340 in the stored order. The reception first-in, first-out memory 322 and the transmission first-in, first-out memory 324 may be implemented with the same type of memo.

The reception first-in-first-out memory 322 may store reception information instead of previously stored information according to the bus load of the CAN bus 140. The bus load is determined by the amount of data provided to the CAN bus 140. If the amount of data provided on the CAN bus is large, the bus load increases. When the bus load is large, reception information to be stored in the reception first-in, first-out memory 322 may increase. In this case, newly received reception information may be overwritten on reception information having the same attribute. In this case, the reception information stored in the reception first-in, first-out memory 322 may be output to the interface 310 in the order of outputting received information deleted by overwriting.

The transmission first-in, first-out memory 324 may store transmission information instead of previously stored information according to the processor load of the processor 112. The processor load is determined by the amount of data processed by the processor 112. When the amount of data processed by the processor 112 is large, the processor load increases. When the processor load is large, transmission information to be stored in the transmission first-in, first-out memory 324 may increase. In this case, newly received transmission information may be overwritten on transmission information having the same attribute. In this case, the transmission information stored in the transmission first-in-first-out memory 324 may be output to the transmitter 340 in an output order of transmission information deleted by overwriting.

The receiver 330 may receive reception information from the CAN bus 140. The receiver 330 may provide the received information to the data buffer unit 320. The reception information provided to the data buffer unit 320 may be stored in the reception first-in, first-out memory 322. The receiver 330 includes an error detector 331, a receive baud rate adjuster 333, a masking filter register 334, and a protocol analyzer 335. The error detector 331 includes a counter 332.

The error detector 331 detects an error in the received information. For example, the error detector 331 may detect a bit error, a stuff error, a form error, a cyclic redundancy check (CRC) error, and an acknowledgment bit error. A bit error occurs when information transmitted from one node is not represented on the CAN bus. Stuff error occurs when 6 consecutive bit values appear in the CAN protocol even though they cannot appear in principle. A format error occurs when a bit value specified as 0 or 1 appears differently. The CRC error occurs when it is confirmed that some bits have changed through the CRC calculation for the CRC area of the received information. The confirmation bit error occurs when the confirmation bit having a bit value of 0 has a different value when the receiver 330 receives the reception information without an error. The counter 332 may count the number of errors detected by the error detector 331. When the number of detected errors is greater than or equal to a specific number, the error detector 331 may control the receiver 330 not to receive the received information and provide it to the reception first-in, first-out memory 322.

The received baud rate adjuster 333 adjusts the baud rate of the received information. The reception baud rate adjuster 333 adjusts the baud rate of the data area included in the reception information according to the set protocol. For example, when the protocol is set to CAN 2.0 A or CAN 2.0 B, the reception baud rate controller 333 may adjust the clock so that the data area is transmitted at a maximum of 1 Mbps. When the protocol is set to CAN 2.0 A FD or CAN 2.0 B FD, the reception baud rate controller 333 may adjust the clock so that the data area is transmitted at a maximum of 8 Mbps. The reception baud rate adjuster 333 may not adjust the baud rate of a region other than the data region regardless of the set protocol. For example, the reception baud rate adjuster 333 may maintain the baud rate of the arbitration region, the control region, the CRC region, and the confirmation region to be described later at 1 Mbps. In addition, the reception baud rate adjuster 333 may additionally change the sampling position of the reception information.

The masking filter register 334 may filter reception information based on identification data of the reception information. The identification data may be provided to an arbitration area included in the data frame of the received information. The masking filter register 334 may set identification data of reception information to be received by the receiver 330 and provided to the reception first-in, first-out memory 322. For example, when the identification data of the reception information matches the set identification data value, the receiver 330 may provide the reception information to the reception first-in, first-out memory 322. When the identification data of the reception information is different from the set identification data value, the receiver 330 may not provide the reception information to the reception first-in, first-out memory 322. Conversely, the masking filter register 334 may set identification data of reception information not to be provided to the reception first-in, first-out memory 322.

The protocol analyzer 335 is connected to the CAN bus 140 to receive reception information. The protocol analyzer 335 analyzes the received information according to the set protocol. The protocol analyzer 335 may sequentially analyze data frames of received information according to a structure of a data frame according to a set protocol. The structures of bits included in each data frame of the CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, and CAN 2.0 B FD protocols are different. Accordingly, state transitions for analysis of received information may be different according to a set protocol. A specific example of this state transition will be described later.

Based on the received information analyzed by the protocol analyzer 335, the error detector 331 may recognize the position of a bit required for error detection and may detect an error. Based on the analyzed received information, the reception baud-rate adjuster 333 may recognize the location of the data region and adjust the baud rate of the data region according to a set protocol. Based on the analyzed received information, the masking filter register 334 may recognize the location of the arbitration area and the identification data, and may determine whether to provide the received information.

The protocol analyzer 335 may remove the stuff bits of the data frame of the received information. As mentioned above, 6 consecutive bit values cannot appear in the CAN protocol. To this end, when five consecutive bit values appear in the received information provided to the receiver 330, stuff bits having a bit value opposite to the consecutive bit values are added to the sixth bit. The protocol analyzer 335 may remove these stuff bits. In addition, the protocol analyzer 335 may adjust the reception information so that the confirmation bit has a value of 0 to 1 when reception information is received without an error.

The transmitter 340 may receive transmission information from the data buffer unit 320. The transmitter 340 may provide transmission information to the CAN bus 140. The transmitter 340 includes a transmit baud-rate adjuster 343 and a protocol generator 345. The transmit baud rate adjuster 343 adjusts the baud rate of the data area included in the transmit information, similar to the receive baud rate adjuster 333 included in the receiver 330. That is, when the protocol is set to CAN 2.0 A or CAN 2.0 B, the transmission baud rate controller 343 may adjust the clock so that the data area is transmitted at a maximum of 1 Mbps. When the protocol is set to CAN 2.0 A FD or CAN 2.0 B FD, the transmit baud rate controller 343 may adjust the clock so that the data area is transmitted at a maximum of 8 Mbps.

The protocol generator 345 is connected to the CAN bus 140 to transmit transmission information. The protocol generator 345 sets the protocol. The protocol generator 345 may support integrated CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, and CAN 2.0 B FD protocols. The protocol generator 345 may select a protocol to match the type of protocol for the vehicle system in question. For example, if the system including the corresponding CAN controller supports the CAN 2.0 A protocol, the protocol generator 345 may set the protocol to have a data frame corresponding to CAN 2.0 A.

The protocol generator 345 may determine each bit of transmission information according to a set protocol. In order to determine the bits of the transmission information, the protocol generator 345 may determine all bit states of a data frame included in the CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, and CAN 2.0 B FD protocols. The protocol generator 345 may select target bit states according to a set protocol among all bit states. The protocol generator 345 may determine a data frame of transmission information by sequentially transitioning the selected target bit states. Table 1 shows the state transition of the data frame.

domain Bit state CAN 2.0 A CAN 2.0 B CAN 2.0 A FD CAN 2.0 B FD SOF SOF O O O O Arbitration area




ID1 O O O O SRR X O X O IDE X O X O ID2 X O X O RTR O O X X R1 X X O O Control area





IDE O X O X R1 X O X X EDL X X O O R0 O O O O BRS X X O O ESI X X O O DLC O O O O Data area DATA O O O O CRC area

SC X X O O CRC O O O O CRC_D O O O O Confirmation area
ACK O O O O ACK_D O O O O EOF EOF O O O O

Referring to Table 1, the data frame is a start of frame, an arbitration field, a control field, a data field, a CRC field, and an acknowledgment field. ), and End of frame. The arbitration region includes a first identification data (ID1), a Substitute Remote Request (SRR) bit, an identifier extension (IDE) bit, a second identification data (ID2), a remote transmission request (RTR) bit, and an arbitration region spare bit (R1). It may include at least one of. The control region is an IDE bit, a first control region reserved bit (R1), an extended data length (EDL) bit, a second control region reserved bit (R0), a bit rate switch (BRS) bit, an error state indicator (ESI) bit, And at least one of DLC (Data Length Code) bits. The CRC region may include at least one of an SC bit, a CRC bit, and a CRC delimiter bit (CRC_D). The acknowledgment area may include an acknowledgment bit (ACK) and an acknowledgment partition bit (ACK_D).

The data frame of each of the CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, and CAN 2.0 B FD protocols contains a bit corresponding to the bit state indicated by'O' and corresponds to the bit state indicated by'X'. Does not contain bits. The protocol generator 245 determines a data frame of transmission information by sequentially transitioning target bit states, which are bit states indicated by'O' in the set protocol. For example, when the CAN 2.0 A protocol is set, the protocol generator 245 includes a start frame (SOF), a first identification data (ID1), an RTR bit, an IDE bit, a second control area reserved bit (R0), and a DLC bit. The data frame is determined by sequentially making state transitions. At this time, the protocol generator 245 may determine the data frame by selecting the first identification data ID1, skipping the SRR bit, the IDE bit of the arbitration area, and the second identification data, and making a state transition to the RTR bit. A description of the bits corresponding to each bit state will be described later.

The protocol generator 345 may use a dedicated circuit such as an Application Specific Integrated Circuit (ASIC) to implement the state transition of Table 1. For example, a plurality of determination circuits for determining each bit state may be connected in series, and a determination circuit corresponding to the bit state indicated by'O' according to the set protocol is passed, and the bit state indicated by'X' is passed through. The corresponding determination circuit may be implemented to be bypassed. In addition, the protocol generator 345 may be implemented as software or firmware, and may be programmed to determine and analyze a data frame by sequentially transitioning target bit states indicated by'O'. Similarly, the protocol analyzer 335 may be implemented as a dedicated circuit, software, or firmware to analyze the data frame.

When the protocol generator 345 transmits the transmission information to the CAN bus 140, another transmitter may simultaneously transmit the transmission information to the CAN bus 140. In this case, the protocol generator 345 may intervene to first transmit transmission information to the CAN bus from a transmitter having a high priority. The priority may be determined based on identification data of transmission information. The protocol generator 345 may additionally add stuff bits. In the CAN protocol, when five consecutive bit values appear, the protocol generator 345 may add a stuff bit having a bit value opposite to the consecutive bit value to the sixth bit.

Reception information or transmission information according to the CAN protocol may include a remote frame, an error frame, and an overload frame as well as the data frame described above. The remote frame may be used by the receiver 330 to request transmission of information to a transmitter of another node. The error frame may be used to inform other nodes of the detected error when an error is detected in the received information. The overload frame may be used when the receiver 330 is not ready to receive information. Each data frame of the CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, and CAN 2.0 B FD protocols may have a different bit structure, but the remote frame, error frame, and overload frame have the same bit structure. Have. Accordingly, the protocol generator 345 may determine the data frame by selecting target bit states for only the data frame.

4 is a diagram showing the structure of a data frame for the CAN 2.0 A protocol. Referring to FIG. 4, the data frame for the CAN 2.0 A protocol is divided into a start frame (Start), an arbitration area, a control area, a data area, a CRC area, a confirmation area, and an end frame (End). The data frame may have a length of 52 bits or more and 108 bits or less.

The arbitration area may include 11 bits of identification data (ID) and 1 bit of RTR bits. The identification data (ID) may indicate a property of a data frame. The priority of the data frame may be determined based on the identification data ID. The RTR bit is used to determine the data frame and the remote frame, and may have a bit value of 0 in the data frame.

The control area may include an IDE bit of 1 bit, a reserved bit of 1 bit, and a DLC bit of 4 bits. The IDE bit can be used to indicate that it is a CAN 2.0 A protocol with 11 bits of identification data (ID), and can have a bit value of 0. The DLC bit can be used to indicate the length of the data area. In the CAN 2.0 A protocol, the data area can have a length of 8 bits or more and 64 bits or less. In addition, as described above, in the CAN 2.0 A protocol, the data area can be transmitted at a maximum of 1 Mbps.

The CRC area may include 15 bits of CRC bits and 1 bit of CRC partition bits. The CRC bit can be used to detect an error through a cyclic redundancy check. The CRC partition bit may be provided to distinguish between the CRC area and the check area, and may have a bit value of 1. The confirmation area may include a 1-bit confirmation bit and a 1-bit confirmation partition bit. The confirmation bit is set to have a bit value of 1 in the transmission information, and may be provided to the CAN bus 140. The confirmation bit may be set to have a bit value of 0 when received information is received without an error. The confirmation partition bit may be provided to distinguish between the confirmation region and the end frame, and may have a bit value of 1.

5 is a diagram showing the structure of a data frame for the CAN 2.0 B protocol. Referring to FIG. 5, the data frame for the CAN 2.0 B protocol is divided into a start frame (Start), an arbitration area, a control area, a data area, a CRC area, a confirmation area, and an end frame (End). The data frame may have a length of 72 bits or more and 128 bits or less.

The arbitration area may include 11 bits of first identification data ID1, 1 bit of SRR bit, 1 bit of IDE bit, 18 bits of second identification data ID2, and 1 bit of RTR bit. The first identification data ID1 and RTR bits perform the same functions as the identification data ID and RTR bits of FIG. 3. The SRR bit and the IDE bit may be provided for distinguishing from the CAN 2.0 A protocol, and may have a bit value of 1. The protocol generator 345 or the protocol analyzer 335 of FIG. 2 may recognize the existence of the second identification data ID2 by analyzing the SRR bit and the IDE bit. In the CAN 2.0 B protocol, since the second identification data (ID2) is provided, more various attributes and priorities of the data frame can be expressed.

The control region may include 2 bits of reserved bits and 4 bits of DCL bits. The DLC bit can be used to indicate the length of the data area. In the CAN 2.0 B protocol, the data area can have a length of 8 bits or more and 64 bits or less. In addition, as described above, in the CAN 2.0 B protocol, the data area can be transmitted at a maximum of 1 Mbps. The CRC area may include a 15-bit CRC bit and a 1-bit CRC partition bit like the CAN 2.0 A protocol of FIG. 4. The confirmation area may include a 1-bit confirmation bit and a 1-bit confirmation partition bit as in the CAN 2.0 A protocol of FIG. 4.

6 is a diagram showing the structure of a data frame for CAN 2.0 A FD protocol. Referring to FIG. 6, a data frame for the CAN 2.0 A FD protocol is divided into a start frame (Start), an arbitration area, a control area, a data area, a CRC area, a confirmation area, and an end frame (End). The arbitration area may include 11 bits of identification data (ID) and 1 bit of RTR, as in the CAN 2.0 A protocol of FIG. 4.

The control region may include 1 bit of IDE bit, 1 bit of EDL bit, 1 bit of reserved bit, 1 bit of BRS bit, 1 bit of ESI bit, and 4 bit of DLC bit. The IDE bit can be used to indicate that it is a CAN 2.0 A series protocol with 11 bits of identification data (ID), and can have a bit value of 0. The EDL bit may be used to indicate that the FD protocol has the length of the extended data area, and may have a bit value of 1 when the data area has a length of 8 bytes or more. The BRS bit may be used to switch to a fast baud rate when transmitting the data region, and may have a bit value of 1. The ESI bit can be used to identify errors when transmitting information in the CAN 2.0 A FD protocol. The DLC area may be used to indicate the length of the data area in bytes. In the CAN 2.0 A FD protocol, the data area can have a length of 8 bytes or more and 64 bytes or less. As described above, in the CAN 2.0 A FD protocol, the data area can be transmitted at a maximum of 8 Mbps.

The CRC area may include 17 or 21 bits of CRC bits and 1 bit of CRC partition bits. Compared to the CAN 2.0 A protocol, the length of the CRC bit for calculating the cyclic redundancy check (CRC) increases as the length of the data area increases. The CRC partition bit may be provided to distinguish between the CRC area and the check area, and may have a bit value of 1. Although not shown, the CRC area may further include a stuff count (SC) bit for reflecting the stuff bit when calculating the cyclic redundancy check (CRC). The confirmation area may include a 1-bit confirmation bit and a 1-bit confirmation partition bit as in the CAN 2.0 A protocol of FIG. 3.

7 is a diagram showing the structure of a data frame for the CAN 2.0 B FD protocol. Referring to FIG. 7, a data frame for the CAN 2.0 B FD protocol is divided into a start frame (Start), an arbitration area, a control area, a data area, a CRC area, a confirmation area, and an end frame (End). The arbitration area is 11 bits of first identification data (ID1), 1 bit of SRR bit, 1 bit of IDE bit, 18 bits of second identification data (ID2), and 1 bit, as in the CAN 2.0 B protocol of FIG. May include the RTR bit of.

The control region may include 1 bit of EDL bit, 1 bit of reserved bit, 1 bit of BRS bit, 1 bit of ESI bit, and 4 bit of DLC bit. The functions of the EDL bit, spare bit, BRS bit, ESI bit, and DLC bit are the same as the EDL bit, spare bit, BRS bit, ESI bit, and DLC bit in the CAN 2.0 A FD protocol of FIG. 6. In the CAN 2.0 B FD protocol, the data area can have a length of 8 bytes or more and 64 bytes or less. As described above, in the CAN 2.0 B FD protocol, the data area can be transmitted at a maximum of 8 Mbps. Like the CAN 2.0 A FD protocol of FIG. 6, the CRC area may include a CRC bit of 17 or 21 bits and a CRC partition bit of 1 bit. The confirmation area may include a 1-bit confirmation bit and a 1-bit confirmation partition bit as in the protocol of FIGS. 4 to 6.

4 to 7, each of the CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, and CAN 2.0 B FD protocols may have different data frame structures. The bit states selected in each protocol may be different. However, as shown in Table 1, target bit states selected from the CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, and CAN 2.0 B FD protocols exist among a total of 21 bit states.

The protocol generator 345 of FIG. 2 may set one of CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, and CAN 2.0 B FD protocols. In this case, the protocol generator 345 and the protocol analyzer 335 may determine and analyze a data frame by sequentially transitioning target bit states selected from a corresponding protocol. Therefore, the CAN controller of the present invention can support integrated CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, and CAN 2.0 B FD protocols. That is, in order to support different protocols, the use of different CAN controllers is not required, and modules as many as the number of protocols supported inside the CAN controller are not required.

8 is a block diagram in which the data buffer unit of FIG. 2 or 3 is embodied. Referring to FIG. 8, the data buffer unit 400 includes an identification data scanner 410, a bus load detector 420, a processor load detector 430, and a first-in, first-out memory 440. The first-in, first-out memory 440 includes a plurality of memory blocks 441 to 44n. The first-in, first-out memory 440 can be viewed as the receive first-in, first-out memory 322 of FIG. 3. Alternatively, the first-in, first-out memory 440 may be viewed as the transmission first-in, first-out memory 324 of FIG. 3. For the convenience of explanation, with reference to the reference numerals in FIG. 3, the configurations of FIG. 8 will be described. Further, the CAN bus is described with reference to the reference numerals of the CAN bus 140 of FIG. 1, and the processor to be described later is described with reference to the reference numerals of the first processor 112 of FIG. 1.

The data buffer unit 400 may receive transmission information Td from the interface 310 or receive reception information Rd from the receiver 330. That is, the identification data scanner 410, the bus load detector 420, the processor load detector 430, and the first-in, first-out memory 440 are shown as one configuration, but the actual data buffer unit 400 is transmitted information (Td ) Can be separated into a configuration that processes the received information (Rd). That is, the identification data scanner 410, the bus load detector 420, the processor load detector 430, and the first-in, first-out memory 440 may each be composed of two. Alternatively, only two first-in, first-out memories 440 are configured, and the identification data scanner 410, the bus load detector 420, and the processor load detector 430 may be configured as one to process both transmission information and reception information. .

The identification data scanner 410 receives transmission information (Td) or reception information (Rd). The identification data scanner 410 scans identification data of transmission information (Td) or reception information (Rd). As described above, the identification data exists in the arbitration area in the data frame of transmission information (Td) or reception information (Rd). The identification data scanner 410 may search a memory block in which information having the same identification data as the scanned identification data is stored. The identification data scanner 410 may overwrite the transmission information Td or the reception information Rd on the retrieved memory block when an output delay of the received transmission information Td or the reception information Rd is expected.

The identification data scanner 410 may overwrite the transmission information Td on the memory block based on the processor load. When the processor load is greater than the reference load, the identification data scanner 410 may overwrite the transmission information Td in the memory block. The reference load may be a preset value. In this case, the value of the reference load may not change, and the value of the reference load may be determined in consideration of stability and speed of the system. Alternatively, the reference load may be a processor load. When the processor load is larger than the bus load, transmission of the transmission information Td to the CAN bus may be delayed. Accordingly, the identification data scanner 410 may overwrite the transmission information Td on the memory block for rapid transmission of the transmission information Td.

The identification data scanner 410 may overwrite the received information Rd on the memory block based on the bus load. When the bus load is larger than the reference load, the identification data scanner 410 may overwrite the received information Rd on the memory block. The reference load may be a preset value. In this case, the value of the reference load may not change, and the value of the reference load may be determined in consideration of stability and speed of the vehicle system. Alternatively, the reference load may be a processor load. When the bus load is larger than the processor load, transmission of the reception information Rd to the processor may be delayed. Accordingly, the identification data scanner 410 may overwrite the received information Rd on the memory block for rapid transmission of the received information Rd.

The bus load detector 420 detects the bus load of the CAN bus 140. The bus load detector 420 may detect the amount of data provided to the CAN bus 140. The bus load detector 420 may generate bus load information based on the detected bus load. The bus load detector 420 may provide bus load information to the identification data scanner 410. The identification data scanner 410 may determine whether to overwrite the reception information Rd or the transmission information Td based on the bus load information.

The processor load detector 430 detects the processor load. The processor load detector 430 may detect the amount of data processed by the processor 112. The processor load detector 430 may generate processor load information based on the detected processor load. The processor load detector 430 may provide processor load information to the identification data scanner 410. The identification data scanner 410 may determine whether to overwrite the transmission information Td or the reception information Rd based on the processor load information.

The first-in, first-out memory 440 may store transmission information Td or reception information Rd provided according to the passage of time in the order in which they are received. In addition, the first-in, first-out memory 440 may output transmission information Td or reception information Rd in the stored order. For example, the first transmission information T1d provided first in the first memory block 441 may be stored, and the second transmission information T2d provided next may be stored in the second memory block 442. I can. Thereafter, the transmission information may be sequentially stored in the n-th first-in, first-out memory 44n. In this case, in principle, the first transmission information T1d, the second transmission information T2d, and the n-th transmission information Tnd may be sequentially output to the transmitter 340.

Third transmission information provided next to the second transmission information T2d may be stored in the third memory block 443. However, the identification data scanner 410 may determine that the processor load is greater than the reference load (bus load) and may overwrite the transmission information Td in the first-in, first-out memory 440. In this case, the identification data of the third transmission information and the transmission information Td may be the same. The identification data represents an attribute of transmission information. Since the latest information among the information having the same attribute in the vehicle system will be the most important, the transmission information Td is stored in the third memory block 443. That is, the third transmission information is deleted.

The transmission information Td' is output to the transmitter 340 after the second transmission information T2d is output. That is, information input later may be output faster by overwriting the transmission information Td. In this case, the output order of transmission information to be received next can be pulled one by one. Therefore, even when the processor load is large, the latest transmission information can be quickly output to the CAN bus. Similarly, even when the bus load is large, the latest received information can be quickly output to the processor. The transmission process of the transmission information Td described above is applied to the process in which the reception information Rd is overwritten in the first-in, first-out memory 440 and outputs the same.

9 is a flowchart for a method of transmitting received information according to an embodiment of the present invention. The steps of FIG. 9 may be performed in the data buffer unit 400 of FIG. 8. For the convenience of explanation, with reference to the reference numerals in FIG. 8, the steps in FIG. 8 are described.

In step S110, the data buffer unit 400 detects a bus load and a processor load. The bus load may be detected by the bus load detector 420. The processor load may be detected by the processor load detector 430.

In step S120, the data buffer unit 400 compares the sensed bus load and the processor load. The identification data scanner 410 may receive bus load information from the bus load detector 420 and may receive processor load information from the processor load detector 430. The identification data scanner 410 may determine load information having a larger value by comparing the bus load information and the processor load information. If the bus load is larger than the processor load, step S130 proceeds. If the bus load is not larger than the processor load, step S150 proceeds. Alternatively, as mentioned in FIG. 8, the identification data scanner 410 may compare a bus load and a preset reference load.

In step S130, the data buffer unit 400 determines whether reception information having the same identification data is already stored. The identification data scanner 410 may extract identification data by analyzing a data frame of the received information Rd. The identification data scanner 410 may search for reception information having the same identification data as the reception information Rd among memory blocks of the first-in, first-out memory 440. If reception information having the same identification data as the reception information Rd is stored in a specific memory block, step S140 is performed. If the reception information having the same identification data as the reception information Rd is not stored in all memory blocks of the first-in, first-out memory 440, step S150 proceeds.

In step S140, the data buffer unit 400 overwrites the reception information Rd on a memory block in which reception information having the same identification data is stored. Accordingly, previously stored reception information is deleted, and newly provided reception information Rd is stored in the memory block. In step S150, the first-in, first-out memory 440 stores the reception information Rd. In step S150, since the bus load is sufficient, all received information may be sufficiently transmitted to the processor in a first-in, first-out manner. Accordingly, the received information Rd is stored in an empty memory block. After step S140 or step S150 proceeds, step S160 proceeds.

In step S160, the data buffer unit 400 provides the stored reception information Rd to the interface 310. The first-in, first-out memory 440 outputs the received information Rd to the interface 310 according to an output order of stored information. In step S140, when the reception information Rd is overwritten, the reception information Rd is output to the interface 310 according to the output order of the deleted reception information. In step S150, when the reception information Rd is stored in an empty memory block, the reception information Rd may be output to the interface 310 after all previously stored reception information is output. However, when the reception information provided to the data buffer unit 400 is overwritten on the reception information of the previous priority, the reception information overwritten afterwards may be output to the interface 310 before the reception information Rd.

10 is a flowchart of a method of transmitting transmission information according to an embodiment of the present invention. The steps of FIG. 10 may be performed in the data buffer unit 400 of FIG. 8. For the convenience of explanation, with reference to the reference numerals in FIG. 8, the steps in FIG. 10 are described. In step S210, the data buffer unit 400 detects a bus load and a processor load. The bus load may be detected by the bus load detector 420. The processor load may be detected by the processor load detector 430.

In step S220, the data buffer unit 400 compares the sensed bus load and the processor load. The identification data scanner 410 may receive bus load information from the bus load detector 420 and may receive processor load information from the processor load detector 430. The identification data scanner 410 may determine load information having a larger value by comparing the bus load information and the processor load information. If the bus load is smaller than the processor load, step S230 proceeds. If the bus load is not smaller than the processor load, step S250 proceeds. Alternatively, as mentioned in FIG. 8, the identification data scanner 410 may compare processor load information and a preset reference load.

In step S230, the data buffer unit 400 determines whether transmission information having the same identification data is already stored. The identification data scanner 410 may extract identification data by analyzing a data frame of the received information Td. The identification data scanner 410 may search for transmission information having the same identification data as the transmission information Td among memory blocks of the first-in, first-out memory 440. When transmission information having the same identification data as the transmission information Td is stored in a specific memory block, step S240 proceeds. If the transmission information having the same identification data as the transmission information Td is not stored in all memory blocks of the first-in, first-out memory 440, step S250 proceeds.

In step S240, the data buffer unit 400 overwrites the transmission information Td on a memory block in which transmission information having the same identification data is stored. Accordingly, previously stored transmission information is deleted, and newly provided transmission information Td is stored in the memory block. In step S250, the first-in, first-out memory 440 stores transmission information Td. In step S250, since the processor load is sufficient, all transmission information may be sufficiently transmitted to the CAN bus 140 in a first-in, first-out manner. Accordingly, the transmission information Td is stored in an empty memory block. After step S240 or step S250 is performed, step S260 is performed.

In step S260, the data buffer unit 400 provides the stored transmission information Td to the transmitter 340. The first-in, first-out memory 440 outputs the transmission information Td to the transmitter 340 according to the output order of the stored information. In step S240, when the transmission information Td is overwritten, the transmission information Td is output to the transmitter 340 according to the output order of the deleted transmission information. In step S250, when the transmission information Td is stored in an empty memory block, the transmission information Td may be output to the transmitter 340 after all previously stored transmission information is output. However, when the transmission information provided to the data buffer unit 400 is overwritten on the transmission information of the previous priority, the transmission information overwritten afterwards may be output to the transmitter 340 before the transmission information Td.

The contents described above are specific examples for carrying out the present invention. The present invention will include not only the embodiments described above, but also embodiments that can be changed in design or easily changed. In addition, the present invention will also include techniques that can be easily modified and implemented in the future using the above-described embodiments.

100: CAN system 200: CAN controller
220, 300: protocol engine 221, 310: interface
222, 320, 400: data buffer unit 330: receiver
335: protocol analyzer 340: transmitter
345: protocol generator 410: identification data scanner
440: first in, first out memory

Claims (18)

A receiver for analyzing received information received from the CAN bus according to the set protocol;
A reception first-in, first-out memory for storing the reception information to be overwritten with previously stored reception information based on the identification data of the reception information and a bus load of the CAN bus before outputting the previously stored reception information;
An interface for providing reception information stored in the reception first-in, first-out memory to a processor or for receiving transmission information from the processor;
A transmission first-in, first-out memory for storing the transmission information so as to overwrite previously stored transmission information based on identification data of the transmission information and a processor load of the processor before outputting previously stored reception information; And
And a transmitter configured to set the protocol and transmit transmission information stored in the transmission first-in, first-out memory to the CAN bus according to the protocol. The method of claim 1,
The transmitter,
A CAN controller comprising a protocol generator configured to set the protocol by selecting target bit states of a data frame corresponding to the protocol from among a plurality of bit states. The method of claim 2,
The protocol generator,
A CAN controller that sequentially transitions each of the target bit states to determine a data frame of the transmission information. The method of claim 2,
The protocol generator,
A CAN controller that selects one of a CAN 2.0 A protocol, a CAN 2.0 B protocol, a CAN 2.0 A FD protocol, and a CAN 2.0 B FD protocol, and selects the target bit states based on the selected protocol. The method of claim 2,
The receiver,
CAN controller including a protocol analyzer for sequentially transitioning the target bit states to analyze the received information. The method of claim 1,
The receiver,
A masking filter register that determines whether to provide the reception information to the reception first-in, first-out memory based on the identification data of the reception information;
A baud rate adjuster for adjusting a baud rate of the data frame of the received information according to the set protocol; And
A CAN controller comprising an error detector configured to detect an error in the received information and determine whether to provide the received information to the received first-in, first-out memory. The method of claim 1,
When the bus load is higher than the processor load, the CAN controller further comprises an identification data scanner that overwrites the reception information on a memory block of the reception first-in, first-out memory in which information having the same identification data as the identification data of the reception information is stored. . The method of claim 7,
A bus load detector that detects the bus load and provides bus load information to the identification data scanner; And
CAN controller further comprising a processor load detector for detecting the processor load and providing processor load information to the identification data scanner. The method of claim 1,
When the processor load is higher than the bus load, the CAN controller further comprises an identification data scanner that overwrites the transmission information on a memory block of the transmission first-in, first-out memory in which information having the same identification data as the identification data of the transmission information is stored. . Receiving, by the CAN controller, data information;
Sensing, by the CAN controller, an amount of data information to be received;
Searching, by the CAN controller, a memory block of a first-in, first-out memory storing information having the same identification data as the identification data of the data information; And
And overwriting, by the CAN controller, the data information on the memory block based on the amount of data information to be received, before outputting previously stored reception information or transmission information. The method of claim 10,
The data information is transmission information provided from a processor,
The step of detecting the amount of data information,
The CAN controller data transmission method comprising the step of detecting the processor load of the processor. The method of claim 11,
The CAN controller data transmission method further comprising the step of sequentially outputting the information stored in the first-in, first-out memory to the CAN bus. The method of claim 11,
The step of detecting the amount of data information,
The CAN controller further comprises comparing the processor load and the bus load of the CAN bus,
In the step of overwriting the data information, when the processor load is larger than the bus load, the transmission information is overwritten by a CAN controller. The method of claim 11,
In the step of overwriting the data information, when the load of the processor is greater than a set reference load value, the data transmission method of the CAN controller overwrites the transmission information. The method of claim 10,
The data information is reception information provided from the CAN bus,
The step of detecting the amount of data information,
The CAN controller data transmission method comprising the step of detecting the bus load of the CAN bus. The method of claim 15,
The CAN controller data transmission method further comprising the step of sequentially outputting the information stored in the first-in, first-out memory to the processor. The method of claim 15,
The step of detecting the amount of data information,
The CAN controller further comprises comparing the load of the processor and the load of the bus,
In the step of overwriting the data information, when the bus load is larger than the processor load, the data transmission method of the CAN controller overwrites the received information. The method of claim 15,
In the step of overwriting the data information, when the bus load is greater than a set reference load value, the data transmission method of the CAN controller overwrites the received information.

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