KR102194914B1 - Memory with error correction circuit - Google Patents

Abstract

An object of the present invention is to provide a memory having an error correction circuit. In the memory having an error correction circuit, the first error correction circuit performs error correction of the first partial data to generate first partial write data or first partial read data, and the second error correction circuit generates the second partial data. To generate the second partial write data or the second partial read data, and in the write mode, the plurality of detection driving circuits each have a plurality of first partial write bits and the first partial write data of the first partial write data. 2 Receiving a plurality of second partial write bits of the partial write data, each detection driving circuit combines the first partial write bit and the second partial write bit to write a corresponding memory cell column. In the read mode, the plurality of detection driving circuits respectively detect stored data in a plurality of memory cell columns and generate a plurality of first partial read data and a plurality of second partial read data.

Description

Memory with error correction circuit {MEMORY WITH ERROR CORRECTION CIRCUIT}

The present invention relates to a memory circuit, and more particularly, to a memory having an error correction circuit.

An error-correcting code (?ECC) circuit is integrated on a dynamic RAM (Dynamic?Random?Access?Memory, DRAM) chip. An error correction code circuit having a 2-bit error error correction capability requires a large circuit area and a long error correction time, and thus an error correction code circuit having an error correction capability of a 1-bit error is mainly used.

Referring to FIG. 1, the memory 100 includes a first error correction circuit ECC1, a second error correction circuit ECC2, a plurality of memory cell columns MCC, and a plurality of detection driving circuits SD. Includes. Here, both the first error correction circuit ECC1 and the second error correction circuit ECC2 have an error correction capability of a 1-bit error. Each memory cell column MCC includes a plurality of mutually serial memory cell blocks MC, and each memory cell block MC also includes a plurality of memory cells (not shown). The plurality of detection drive circuits SD are each coupled to a plurality of memory cell rows MCC, and each detection drive circuit SD is a first error correction circuit ECC1 or a second error correction circuit ( ECC2). Referring to FIG. 1 as an example, a plurality of detection driving circuits SD located on the left half of the memory 100 are coupled to the first error correction circuit ECC1, and the right half of the memory 100 The plurality of detection drive circuits SD located on the division side are coupled to the second error correction circuit ECC2.

When adjacent memory cells fail together, the adjacent memory cells in which the failure has occurred are coupled to the same error correction circuit, and the error correction circuit (e.g., the first error correction circuit (ECC1)) can It cannot be corrected exactly. In order to avoid the above-described problem, in a known technique, a person skilled in the art uses a memory of an alternative error correction circuit, the circuit area is increased, and the manufacturing cost is increased.

In view of the above-described problem, the present invention provides a memory having an error correction circuit corresponding to a situation of a 2-bit error due to a failure of an adjacent memory cell.

The present invention provides a memory having a first error correction circuit, a second error correction circuit, a plurality of memory cell columns, and an error correction circuit including a plurality of detection driving circuits. Here, the first error correction circuit performs error correction of the first partial data to generate first partial write data or first partial read data. The second error correction circuit performs error correction of the second partial data to generate second partial write data or second partial read data. The plurality of detection drive circuits are each coupled to a plurality of memory cell columns, and are coupled to a first error correction circuit and a second error correction circuit. In the write mode, the plurality of detection driving circuits each receive a plurality of first partial write bits of the first partial write data, and each receive a plurality of second partial write bits of the second partial write data. Each of the detection driving circuits combines a corresponding first partial write bit and a second partial write bit to write a corresponding memory cell column. In the read mode, the plurality of detection driving circuits respectively detect stored data of a plurality of memory cell columns to generate a plurality of first partial read data and a plurality of second partial read data.

Based on the above, two adjacent memory cells are connected to the first error correction circuit and the second error correction circuit, respectively. When the two adjacent memory cells have failed and are read errors, the first error correction circuit has only one read error, and similarly, the second error correction circuit also has only one read error, so the first error The correction circuit and the second error correction circuit perform error correction in response to a 1-bit error.

In order to further clarify the above-described features and advantages of the present invention, detailed descriptions will be given below with reference to the drawings by way of example.

1 is a memory having a known error correction circuit.
2 is a memory having an error correction circuit shown in the embodiment of the present invention.
3 is a schematic diagram of a memory cell block in a first column of each memory cell row.

Referring to FIG. 2, the memory 200 includes a first error correction circuit ECC1, a second error correction circuit ECC2, a plurality of detection driving circuits SD, an address decoder ADD, and a memory. Including a cell display, the memory cell display is composed of a plurality of memory cell columns (MCC) and a plurality of memory cell rows (MCR), each memory cell column (MCC) is a plurality of memory cells in series A block MC is included, and each memory cell block MC includes a plurality of memory cells M (as shown in FIG. 3 ). The plurality of memory cell columns MCC are coupled to a plurality of detection driving circuits SD, respectively, through an address decoder ADD, and each detection driving circuit SD includes a first error correction circuit ECC1 and a second It is simultaneously coupled to the error correction circuit ECC2. Here, the first error correction circuit ECC1 and the second error correction circuit ECC2 may correct an error for one bit error. The address decoder ADD may include a column decoder (not shown) and a row decoder (not shown).

The memory 200 allows data D of a specific size to be read or written. In the memory write mode, the data D is divided into a first partial data D1 and a second partial data D2. The first error correction circuit ECC1 generates first partial write data ECCD1 including a first error correction code based on the first partial data D1. Similarly, the second error correction circuit ECC2 generates the second partial write data ECCD2 including the second error correction code based on the second partial data D2. In this embodiment, the size of the data D may be 256 bits, for example, the size of the first partial data D1 and the second partial data D2 is 128 bits, and the first partial write data ECCD1 ) And the second partial write data ECCD2 are 136 bits, including an 8-bit first error correction code and an 8-bit second error correction code.

Next, the first partial write data ECCD1 may be divided into a plurality of first partial write bits DB1 (the size is, for example, 4 bits), and the second partial write data ECCD2 is a plurality of It may be divided into the second partial write bit DB2. Each detection driving circuit SD receives the first partial write bit DB1 and the second partial write bit DB2 at the same time, and combines the first partial write bit DB1 and the second partial write bit DB2. Thereafter, the address is designated through the address decoder ADD, and the designated address of the corresponding memory cell column MCC is written.

Taking the detection driving circuit SD(1) as an example, the detection driving circuit SD(1) receives the first partial write bit DB1 and the second partial write bit DB2, and the first partial write bit After (DB1) and the second partial write bit (DB2) are combined, the designated address of the corresponding MCC (1) is written, and this address is designated by the address decoder (ADD), for example, as shown in FIG. This is the first column memory cell block MC of the memory cell column MCC(1).

With continued reference to Fig. 2, in the present embodiment, the first error correction code (e.g., 8 bits) generated by the first error correction circuit ECC1 and included in the first partial write data ECCD1 is Likewise, it is divided into two first partial write bits DB1 (e.g., 4 bits) and is received by the detection driving circuit SD(P) and the detection driving circuit SD(P+1), respectively. . Similarly, the second error correction code (for example, 8 bits) generated by the second error correction circuit ECC2 and included in the second partial write data ECCD2 is two second partial write bits DB2 It is divided into (for example, 4 bits), and is received by the detection driving circuit SD(P) and the detection driving circuit SD(P+1), respectively. That is, the detection drive circuit SD(P) (referred to as a first error correction code memory cell row) receives a part of the first error correction code and a part of the second error correction code, respectively, and the detection drive circuit SD (P+1)) (referred to as a second error correction code memory cell row) is also the same. Next, similarly, the detection drive circuit SD(P) combines some of the first error correction codes and some of the second error correction codes, and then the designated address in the corresponding memory cell row MCC(P). Is written, and the detection driving circuit SD(P+1) is also the same.

In this embodiment, the plurality of memory cell columns MCC has a total of N columns, and the first error correction code memory cell column and the second error correction code memory cell column are in the Pth row and the P+1 row, respectively. They are located and arranged adjacent to each other (as shown in Fig. 2), and P and N are both natural numbers and 1<P<N. In another embodiment, the first error correction code memory cell row and the second error correction code memory cell row are located at a central position of the plurality of memory cell rows MCC. For convenience of explanation, a plurality of memory cell columns on the left side of the first error correction code memory cell column in the drawing are referred to as a first data code memory cell column, and a plurality of memories on the right side of the second error correction code memory cell column in the drawing The cell row is referred to as a second data code memory cell row.

In the read mode of the memory 200, each detection driving circuit SD detects from a designated position (designated by the address decoder ADD) of the corresponding memory cell column MCC, and reads out a data bit group, It is divided into a first partial read bit and a second partial read bit. For convenience of explanation, the first partial read bit and the second partial read bit are similarly recorded in DB1 and DB2. Next, the detection driving circuit SD sends the first partial read bit DB1 and the second partial read bit DB2 to the first error correction circuit ECC1 and the second error correction circuit ECC2, respectively, to generate an error. Correct. Referring to FIG. 2, a plurality of first partial read bits DB1 are coupled to first partial read data (including a first error correction code) and received by a first error correction circuit ECC1. Similarly, the plurality of second partial read bits DB2 are coupled to the second partial read data (including the second error correction code) and received by the second error correction circuit ECC2.

For convenience of explanation, the first partial read data and the second partial read data are similarly recorded as ECCD1 and ECCD2. Next, the first error correction circuit ECC1 corrects the first partial read data ECCD1 based on the first error correction code in the first partial read data ECCD1, and corrects the first partial data ( D1) is created. Similarly, the second error correction circuit ECC2 corrects the second partial read data ECCD2 based on the second error correction code in the second partial read data ECCD2, and corrects the second partial read data D2. ). Finally, the first partial data D1 and the second partial data D2 are combined and output as data D. In the present embodiment, the sizes of the plurality of first partial read bits DB1 and the plurality of second partial read bits DB2 are all 4 bits, and the sizes of the first partial read data and the second partial read data are all 136. The size of the first error correction code and the second error correction code may be 8 bits, and finally, the size of the data D is 256 bits.

In the following, as shown in Fig. 3, each detection driving circuit SD writes the specified address of the memory cell column MCC corresponding to the writing of the data bit group and the specified address of the corresponding memory cell column MCC Details of reading out a data bit group from Each memory cell block MC includes a plurality of first memory cells M1, a second memory cell M2, a sub word line driver SWD, a first bit line sensor BLSA1, and a second A bit line sensor BLSA2, a first selection switch SW1, and a second selection switch SW2 are included. Here, in FIG. 2, only the bit line sensor BLSA is generally referred to as a first bit line sensor BLSA1 and a second bit line sensor BLSA2. 3, each of the first memory cell M1 and each of the second memory cells M2 includes a transistor T and a capacitor C, and the capacitor C includes a transistor T and a reference potential terminal. Are combined between. The control terminal of the transistor T is coupled to the sub word line driver SWD through the word line WL and is controlled by the sub word line driver SWD. The transistor T is coupled between the capacitor C and the corresponding bit line. The transistor T (transistor in the first memory cell M1) is coupled to the first bit line sensor BLSA1, or the transistor T (transistor in the second memory cell M2) is 2 It is coupled to the bit line sensor BLSA2. The first bit line sensor BLSA1 detects the data stored in the first memory cell M1 through the first bit line BL1, and the second bit line sensor BLSA2 is configured with the second bit line BL2. ) To detect data stored in the second memory cell M2. The first bit line sensor BLSA1 is coupled to the main input/output line MIO through the low switch RSW, and similarly, the second bit line sensor BLSA2 is connected to the main input/output line through the low switch RSW. MIO). For convenience of explanation, the bit line BL connected to the first memory cell M1 is referred to as a first bit line BL1, and the bit line BL connected to the second memory cell M2 is referred to as a second. It is referred to as bit line BL2. In the present embodiment, the transistor T may be a metal oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), and the memory cell M located in the same memory cell row MCR is , May be controlled by the same word line WL.

Referring to FIGS. 2 and 3 simultaneously, in the write mode of the memory 200, the write address designated by the address decoder ADD is the first column memory cell block MC11 of the memory cell column MCC(1). ), the detection driving circuit SD(1) is the transistor of all the memory cells M of the memory cell block (MC11) by the sub word line driver SWD. (T) is started. Further, the detection drive circuit SD(1) controls the start of the row switch RSW, controls the column selection line CSL0 to transmit the selection signal S, and The first selection switch SW1 and the second selection switch SW2 of the memory cell block MC11 are activated to connect the main input/output line MIO and the memory cell block MC11. Here, the plurality of first bit line sensors BLSA1 are connected to the plurality of first memory cells M1 through the plurality of first bit lines BL1, and the plurality of second bit line sensors BLSA2 are , The plurality of second memory cells M2 are connected through the plurality of second bit lines BL2. Next, the detection driving circuit SD(1) is coupled to the first partial write bit DB1 The second partial write bit DB2 is transmitted through the main input/output line MIO, respectively, of the memory cell block MC11 by the first bit line sensor BLSA1 and the second bit line sensor BLSA2. Writes to a plurality of memory cells (M).

For convenience of explanation, the first bit line BL1 coupled to the activated first selection switch SW1 is referred to as a bit line among the first lines. Similarly, the second bit line BL2 coupled to the activated second selection switch SW2 is referred to as a bit line among the second lines.

In the read mode of the memory 200, assuming that the read address designated by the address decoder ADD corresponds to the memory cell block (MC(11)), similarly, the detection driving circuit SD(1) is It controls the start of the switch RSW, controls the transmission of the selection signal S by the column selection line CSL0, and controls the first selection switch SW1 and the second of the memory cell block MC11. The selection switch SW2 is activated to connect the main input/output line MIO and the first bit line sensor BLSA1 and the second bit line sensor BLSA2 of the memory cell block MC11. Here, The plurality of first bit line sensors BLSA1 are connected to the plurality of first memory cells M1 through the plurality of first bit lines BL1, and the plurality of second bit line sensors BLSA2 are It is connected to the plurality of second memory cells M2 through the second bit line BL2. Next, the detection driving circuit SD(1) is a first memory of the memory cell block MC(11). The data saved from the cell M1 is detected, and the saved data is transferred to the first error correction circuit ECC1 through the first bit line sensor BLSA1 and the main input/output line MIO. (1)) detects the data saved from the second memory cell M2 of the memory cell block (MC11), and transfers the saved data to the second bit line sensor BLSA2 and the main input/output line MIO. ) To the second error correction circuit ECC2, that is, the two adjacent memory cells M of the memory cell block MC, respectively, a first error correction circuit ECC1 and a second error correction circuit. Corresponds to (ECC2).

Because two adjacent memory cells fail (for example, the first memory cell M1 and the second memory cell M2 of the memory cell block (MC 11) in FIG. 3), Under the circumstances, two adjacent memory cells M1 and M2 are coupled to the first error correction circuit ECC1 and the second error correction circuit ECC2, respectively, so that the first error correction circuit ECC1 is one There is only a read error of (e.g., read data of the first memory cell M1), and similarly, the second error correction circuit ECC2 also has only one read error (e.g., the second The read data of the memory cell M2), the first error correction circuit ECC1 and the second error correction circuit ECC2 make error correction corresponding to one bit address. By using a memory having an error correction circuit, it is possible to obtain a desirable error correction effect, thereby reducing the use of a replacement memory. In addition, the first memory cells M1 and the second memory cells M2 are alternately arranged. The installation method can reduce mutual electrical interference.

Although the text has been shown as in the above examples, it is not intended to limit the present invention, and since it is possible to change or modify a person skilled in the art without departing from the scope of the spirit of the present invention, the scope of protection of the present invention follows Based on what is defined in the claims of

The present invention couples two adjacent memory cells to a first error correction circuit and a second error correction circuit, respectively. Under a situation in which two adjacent memory cells have failed, the first error correction circuit and the second error correction circuit need to handle only one error. Therefore, under the same cost, by the memory having the error correction circuit of the present invention, a desirable error correction effect can be obtained, and the use of the replacement memory can be reduced.

100: memory
200: memory
ADD: Address decoder
BL: bit line
BL1: first bit line
BL2: second bit line
BLSA: Bitline sensor
BLSA1: first bit line sensor
BLSA2: second bit line sensor
C: condenser
CSL0, CSL1, CSLN: column selection line
D: data
D1: first partial data
D2: second partial data
DB1: first partial write bit or first partial read bit
DB2: second partial write bit or second partial read bit
ECC1: first error correction circuit
ECC2: second error correction circuit
ECCD1: first partial write data or first partial read data
ECCD2: second partial write data or second partial read data
M: memory cell
M1: first memory cell
M2: second memory cell
MC/MC(11): memory cell block
MCC, MCC(1), MCC(P-1), MCC(P), MCC(P+1), MCC(P+2), MCC(N): memory cell row
MCR: memory cell row
MIO: Main input/output line
RSW: Low switch
SD, SD(1), SD(P-1), SD(P), SD(P+1), SD(P+2), SD(N): detection drive circuit
S: selection signal
SW1: first selection switch
SW2: second selection switch
SWD: Sub word line driver
T: transistor

Claims (10)

In a memory having an error correction circuit,
A first error correction circuit for performing error correction of the first partial data to generate first partial write data or first partial read data,
A second error correction circuit for performing error correction of the second partial data to generate second partial write data or second partial read data,
A plurality of rows of memory cells, and
A plurality of detection driving circuits each coupled to the plurality of memory cell columns and coupled to the first error correction circuit and the second error correction circuit
Including,
In the write mode, the plurality of detection driving circuits each receive a plurality of first partial write bits of the first partial write data, each receiving a plurality of second partial write bits of the second partial write data, , Each of the detection driving circuits combines a corresponding first partial write bit and a second partial write bit, writes a corresponding memory cell column,
In the read mode, the plurality of detection driving circuits detect stored data of the plurality of memory cell rows, respectively, to generate a plurality of first partial read data and a plurality of second partial read data,
The plurality of memory cell rows,
A first error correction code memory cell row, and
Second error correction code memory cell row
Including,
Both the first error correction code memory cell row and the second error correction code memory cell row
A part of the first error correction code in the first partial write data, and
Part of the second error correction code in the second partial write data
To preserve,
The number of bits of the first partial write data and the second partial write data are the same,
The number of bits of the first partial read data and the second partial read data are the same,
Memory. The method of claim 1,
The first error correction code memory cell row and the second error correction code memory cell row are disposed adjacent to each other,
The plurality of memory cell rows further include a plurality of first data code memory cell rows and a plurality of second data code memory cell rows,
The plurality of first data code memory cell rows are disposed adjacent to each other, and are disposed on a first side of the first error correction code memory cell row,
The plurality of second data code memory cell rows are disposed adjacent to each other, and are disposed on a second side of the second error correction code memory cell row,
The first side and the second side are opposite to each other. The method of claim 1,
Each of the memory cell rows,
Multiple memory cell blocks connected in series with each other
Including,
Each of the memory cell blocks,
A plurality of memory cells controlled by word lines,
A first bit line sensor coupled to a plurality of first bit lines of a plurality of first memory cells in the plurality of memory cells,
A plurality of first selection switches for coupling a bit line of a plurality of first lines in the plurality of first bit lines to a corresponding detection driving circuit based on a selection signal;
A second bit line sensor coupled to a plurality of second bit lines in a plurality of second memory cells of the plurality of memory cells,
A plurality of second selection switches for coupling a bit line among a plurality of second lines in the plurality of second bit lines to a corresponding detection driving circuit based on the selection signal
Including,
The plurality of first memory cells and the plurality of second memory cells are alternately arranged. The method of claim 3,
Each of the memory cell blocks,
A word line driver coupled to the word line to generate a word line signal
The memory further comprising. delete The method according to any one of claims 1 to 4,
The memory,
Coupled to the plurality of memory cell columns and the plurality of detection driving circuits, and in the write mode, the plurality of first partial write bits and the plurality of second partial write bits designate an address of a corresponding memory cell column, and the In the read mode, an address decoding circuit for designating an address of a memory cell column corresponding to a plurality of first partial read data and a plurality of second partial read data
The memory further comprising. The method of claim 3,
Each of the memory cells,
A transistor coupled to the first bit line sensor,
A capacitor coupled between the transistor and the reference potential terminal
A memory containing. The method according to any one of claims 1 to 4,
In the read mode, each of the detection driving circuits,
A memory for detecting at least 2 bits of reserved data from a corresponding memory cell column. The method of claim 8,
Each of the detection driving circuits,
A memory for dividing the stored data of at least two bits into first partial read data of at least one bit and second partial read data of at least one bit. The method of claim 2,
And each of the first error correction code and each of the second error correction codes are at least 2 bits.

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