KR102167136B1 - Display device having thin film transistor array substrate and method for fabricating the same - Google Patents

Abstract

The present invention relates to a display device including a thin film transistor array substrate and a method of manufacturing the same. The disclosed invention includes an active layer formed on the substrate; A gate insulating film formed on the entire surface of the substrate including the active layer; A gate electrode formed on the gate insulating layer over the active layer; An interlayer insulating film formed on the entire surface of the substrate including the gate electrode and exposing the source region and the drain region of the active layer; A source electrode and a drain electrode formed on the interlayer insulating layer and contacting the source region and the drain region, respectively; A first passivation film formed on an interlayer insulating film including the source electrode and the drain electrode and exposing the drain electrode; A metal layer pattern formed on the first passivation layer and in contact with the drain electrode; A common electrode formed on the first passivation layer; A second passivation layer formed on the first passivation layer including the common electrode and the metal layer pattern and exposing the metal layer pattern; And a plurality of pixel electrodes formed on the second passivation layer and in contact with the metal layer pattern to be electrically connected to the drain electrode.

Description

A display device including a thin film transistor array substrate, and a manufacturing method thereof {DISPLAY DEVICE HAVING THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a display device including a thin film transistor array substrate, and more particularly, a contact resistance of a pixel electrode portion is changed by changing a source electrode and a drain electrode metal to Ti/Al/Ti for improved reliability and a narrow bezel. The present invention relates to a display device including an improved thin film transistor array substrate and a method of manufacturing the same.

TV (Television) products are the biggest application target in the rapidly growing flat panel display market. Currently, a liquid crystal display (LCD) is the main focus of TV panels, and a lot of research is being conducted for an organic light emitting display to be applied to a TV.

The direction of the current TV display technology is focused on the main items required by the market. The requirements in the market include large-sized TV or DID (Digital Information Display), low price, high quality (video expression, high resolution, brightness, contrast ratio). , Color reproduction).

Meanwhile, Mo/Al/Mo materials have been widely used as metal materials for source and drain electrodes of thin film transistors used as driving elements of display devices.

However, recently, in the case of a display device such as a liquid crystal panel, the necessity of a narrow bezel has emerged a lot, so when a Mo/Al/Mo material is used as a metal material for the source electrode and the drain electrode, the display device There was a limit to realizing the narrow bezel of

In particular, in in-cell touch panels and general display panels, when Mo/Al/Mo materials are used, a narrow bezel is used to implement a touch electrode. It is difficult to implement and has a disadvantage in that the driving reliability of the panel is poor.

However, in recent years, the use of Ti/Al/Ti materials has increased in order to improve the narrow bezel and driving reliability by supplementing the disadvantages of the existing Mo/Al/Mo materials.

In this respect, a thin film transistor array substrate according to the prior art using a Ti/Al/Ti material will be described with reference to FIG. 1.

1 is a schematic cross-sectional view of a thin film transistor array substrate according to the prior art.

Referring to FIG. 1, in a thin film transistor array substrate 10 according to the prior art, a light shielding layer 13 is formed on a substrate 11.

In addition, a buffer insulating layer 15 is formed on the light blocking layer 13, and an active layer 17 made of polysilicon is formed on the buffer insulating layer 15.

In addition, a gate insulating layer 19 and a gate electrode 21 are formed on the active layer 17.

Further, on the buffer insulating layer 15 including the gate electrode 21 and the active layer 17, a contact hole (not shown) exposing the source region 17a and the drain region 17b of the active layer 17, respectively; 25a, 25b), and an interlayer insulating film 23 is formed.

Further, a source electrode 27 and a drain electrode 29 contacting the source region 17a and the drain region 17b are formed on the interlayer insulating layer 23. At this time, the source electrode 27 and the drain electrode 29 in contact with the source region 17a and the drain region 17b are made of a Ti/Al/Ti metal material instead of Mo/Al/Mo.

Further, a first passivation layer 33 having a drain contact hole (not shown; see 35) exposing the drain electrode 29 on the interlayer insulating layer 23 including the source electrode 27 and the drain electrode 29. ) Is formed. In this case, the first passivation layer 33 is made of a photoacryl material, which is an organic insulating material, and is used as a planarization layer.

Moreover, on the first passivation layer 33, together with the common electrode 37a, a drain connection pattern 37b electrically connected to the drain electrode 29 through the drain contact hole 35 and an in-cell touch panel ( A transparent electrode pattern 37c for an In-Cell Touch Panel) is formed.

In addition, a first metal layer pattern 41a and a second metal layer pattern 41b are formed on the drain connection pattern 37b and the transparent electrode pattern 37c, respectively, and a first metal layer pattern including the first passivation layer 33 A second passivation layer 43 exposing the first metal layer pattern 41a is formed on the metal layer pattern 41a, the second metal layer pattern 41b for the lower electrode, and the common electrode 37a. In this case, the transparent electrode pattern 37c and the second metal layer pattern 41b are used as lower electrodes of the in-cell touch panel.

In addition, the second metal layer pattern 41b is formed on the second passivation layer 43 along with a plurality of pixel electrodes 47a which are in contact with the first metal layer pattern 41a and electrically connected to the drain electrode 29. ) And the upper electrode 47b for an in-cell touch panel are formed. At this time, the lower electrode and the upper electrode 47b composed of the transparent electrode pattern 37c and the second metal layer pattern 41b, and the second passivation layer 43 interposed therebetween constitute the in-cell touch panel 50. do.

A process of manufacturing a thin film transistor array substrate according to the prior art having the above configuration will be schematically described below with reference to FIG. 2.

2 is a flowchart illustrating a process of manufacturing an oxide semiconductor thin film transistor array substrate according to the prior art.

Referring to FIG. 2, in the manufacturing process of an oxide semiconductor thin film transistor array substrate according to the prior art, a process of first forming a light shielding layer 13 on the substrate 11 (S11), and the light shielding layer ( 13) forming an active layer 17 made of an oxide semiconductor on the buffer insulating layer 15 formed on the entire surface of the substrate (S12), and the gate insulating layer 19 and the gate electrode 21 on the active layer 17 A step of forming (S13) and a contact hole (not shown) exposing each of the source region 17a and the drain region 17b in the active layer 17 on the entire surface of the substrate including the gate electrode 21 The step of forming the interlayer insulating film 23 (S14), the step of forming the source electrode 27 and the drain electrode 29 on the interlayer insulating film 23 (S15), and the source electrode 27 and the drain A step of forming a drain contact hole 35 in the first passivation layer 33 formed on the interlayer insulating layer 23 including the electrode 29 (S16), and the drain electrode 29 under the drain contact hole 35 ) A process of removing the metal oxide layer 31 formed on the surface (S17), and a drain connection pattern electrically connected to the drain electrode 29 together with the common electrode 37a on the first passivation layer 33 ( 37b) and forming the transparent electrode pattern 37c for the lower electrode of the in-cell touch panel (S18), and the first metal layer pattern 41a and the lower portion on the drain connection pattern 37b and the transparent electrode pattern 37c. A process of forming a second metal layer pattern 41b for an electrode (S19), and a drain connection pattern exposing the drain connection pattern 41 to the second passivation layer 43 formed on the first passivation layer 33 It consists of a process of forming the contact hole 45 (S20), and a process of forming a plurality of pixel electrodes 47a and an upper electrode 47b for an in-cell touch panel on the second passivation layer 43 (S21). .

Meanwhile, a method of manufacturing an oxide semiconductor thin film transistor array substrate according to the prior art in the order of the above processes will be described with reference to FIGS. 3A to 3H.

3A to 3H are cross-sectional views illustrating a process of manufacturing an oxide semiconductor thin film transistor array substrate according to the prior art.

Referring to FIG. 3A, first, a material layer having a light-blocking property is formed on a substrate 11, and then a light shielding layer 13 is formed by selectively patterning it through a mask process.

Next, after forming the buffer insulating layer 15 on the entire surface of the substrate including the light blocking layer 13, an oxide semiconductor layer (not shown) is formed thereon.

Subsequently, an oxide semiconductor layer (not shown) is selectively patterned through a mask process to form an active layer 17 made of an oxide semiconductor.

Then, a gate insulating film 19 is formed on the entire surface of the substrate including the active layer 17.

Subsequently, a metal layer (not shown) is deposited on the gate insulating layer 19 and then selectively patterned through a mask process to form a gate electrode 21 on the gate insulating layer 19 on the active layer 17. To form.

Then, impurities are implanted into the active layer 17 under the gate electrode 21 to define a source region 17a and a drain region 17b, respectively, and a channel region 17c between these regions.

Subsequently, after forming an interlayer insulating layer 23 on the entire surface of the substrate including the gate electrode 21, the interlayer insulating layer 23 and the gate insulating layer 19 below the interlayer insulating layer 23 are selectively patterned through a mask process, and the source region 17a ) And contact holes 25a and 25b exposing the drain regions 17b, respectively.

Then, after depositing a metal layer (not shown) composed of Ti/Al/Ti on the interlayer insulating layer 23, it is selectively patterned through a mask process to form the source region 17a and the drain region 17b, respectively. The source electrode 27 and the drain electrode 29 are formed in contact with each other.

Subsequently, referring to FIG. 3B, a first passivation layer 33 made of photoacryl as an organic insulating material is formed on the interlayer insulating layer 23 including the source electrode 27 and the drain electrode 29. Then heat cured. At this time, when the first passivation film 33 is thermally cured, a Ti oxide film, that is, a metal oxide film 31 is formed on the surface of the source electrode 27 and drain electrode 29 made of Ti/Al/Ti.

Next, referring to FIG. 3C, a drain contact hole 35 is formed by selectively patterning the first passivation layer 33 through a mask process. At this time, when the drain contact hole 35 is formed, the metal oxide film 31 on the surface of the drain electrode 29 is exposed to the outside.

Subsequently, referring to FIG. 3D, a pretreatment process for removing the metal oxide film 31 formed on the surface of the drain electrode 29 under the drain contact hole 35 is performed. At this time, since the metal oxide layer 31 is removed, the surface of the drain electrode 29 is exposed to the outside.

Next, referring to FIG. 3E, a transparent conductive material layer 37 is deposited on the first passivation layer 33 including the exposed drain electrode 29, and a photosensitive layer (not shown) is applied thereon. .

Subsequently, the photosensitive film (not shown) is selectively patterned through exposure and development processes using photolithography process technology to form the photosensitive film pattern 39.

Next, referring to FIG. 3F, a drain contacting the drain electrode 29 with the common electrode 37a by selectively etching the photosensitive layer pattern 39 as an etching mask and the transparent conductive material layer 37 The connection pattern 37b and the transparent electrode pattern 37c for the lower electrode of the in-cell touch panel are formed.

Next, referring to FIG. 3G, the photoresist pattern 39 is removed, the common electrode 37a, the drain connection pattern 37b, the transparent electrode pattern 37c for the lower electrode of the in-cell touch panel, and the first passivation layer. (33) After forming a metal layer (not shown) on the first metal layer pattern (41a) and the in-cell touch panel on the drain connection pattern (37b) by selectively etching the metal layer (not shown) through a mask process. A second metal layer pattern 41b for the lower electrode is formed.

Next, referring to FIG. 3H, a second passivation layer 43 is deposited on the first metal layer pattern 41a, the common electrode 37a, and the first passivation layer 33 including, and through a mask process. This is selectively patterned to form a drain connection pattern contact hole 45 exposing the first metal layer pattern 41a.

Subsequently, after depositing a transparent conductive material layer (not shown) on the second passivation layer 43 including the drain connection pattern contact hole 45, it is selectively patterned through a mask process, and the first metal layer pattern ( 41a) and electrically connected to the drain electrode 29, and an upper electrode 47b corresponding to the second metal layer pattern 41b along with a plurality of pixel electrodes 47a corresponding to the common electrode 37a By forming the oxide semiconductor thin film transistor array substrate manufacturing process according to the prior art is completed.

As described above, according to the conventional thin film transistor array substrate and its manufacturing method, Ti/Al/Ti metal material is used instead of Mo/Al/Mo as the metal material for forming the source electrode and the drain electrode. When the passivation film is formed before the transparent conductive material layer for the common electrode to be formed, a metal (Ti) oxide film is formed on the surface of the metal layer for the source electrode and the drain electrode made of the Ti/Al/Ti metal material. Contact resistance increases between the metal layers for the source and drain electrodes and the transparent conductive material layer for the common electrode.

In addition, since a separate pretreatment process for removing the metal oxide film, which acts as a cause of the increase in contact resistance, must be added, the number of manufacturing processes increases accordingly.

In addition, since a part of the thermally cured surface of the passivation layer is etched during dry etching for a separate pretreatment process for removing the metal oxide layer, the resistivity of the metal layer pattern formed thereafter increases, The touch characteristics of the touch panel may be deteriorated, and the yield of the thin film transistor array substrate may decrease.

The present invention is to solve the problems of the prior art, and an object of the present invention is to improve the contact resistance without a pretreatment process of removing the metal oxide film formed on the surface of the metal layer for forming the source electrode and the drain electrode, and An object of the present invention is to provide a display device including a thin film transistor array substrate and a method of manufacturing the same, which can simplify the manufacturing process by omitting the pretreatment process to be removed.

A display device having a thin film transistor array substrate according to the present invention for achieving the above object comprises: an active layer formed on the substrate; A gate insulating film formed on the entire surface of the substrate including the active layer; A gate electrode formed on the gate insulating layer over the active layer; An interlayer insulating film formed on the entire surface of the substrate including the gate electrode and exposing the source region and the drain region of the active layer; A source electrode and a drain electrode formed on the interlayer insulating layer and contacting the source region and the drain region, respectively; A first passivation film formed on an interlayer insulating film including the source electrode and the drain electrode and exposing the drain electrode; A metal layer pattern formed on the first passivation layer and in contact with the drain electrode; A common electrode formed on the first passivation layer; A second passivation layer formed on the first passivation layer including the common electrode and the metal layer pattern and exposing the metal layer pattern; And a plurality of pixel electrodes formed on the second passivation layer and in contact with the metal layer pattern to be electrically connected to the drain electrode.

A method for manufacturing a display device having a thin film transistor array substrate according to the present invention for achieving the above object comprises: forming an active layer on the substrate; Forming a gate insulating film on the entire surface of the substrate including the active layer; Forming a gate electrode on the gate insulating layer over the active layer; Forming an interlayer insulating film exposing the source region and the drain region of the active layer on the entire surface of the substrate including the gate electrode; Forming a source electrode and a drain electrode on the interlayer insulating layer to contact the source region and the drain region, respectively; Forming a first passivation layer exposing the drain electrode on the interlayer insulating layer including the source electrode and the drain electrode; Forming a transparent conductive material layer on the first passivation layer in contact with the drain electrode; Removing the transparent conductive material layer in contact with the drain electrode to expose the drain electrode, and forming a common electrode on the first passivation layer; Forming a metal layer pattern formed on the first passivation layer and in contact with the drain electrode; Forming a second passivation layer exposing the metal layer pattern on the first passivation layer including the common electrode and the metal layer pattern; And forming a plurality of pixel electrodes electrically connected to the drain electrode by contacting the metal layer pattern on the second passivation layer.

The display device including the thin film transistor array substrate according to the present invention and a method of manufacturing the same can improve contact resistance without a pretreatment process of removing a metal oxide film formed on the surface of a metal layer for forming a source electrode and a drain electrode.

In particular, the metal oxide film (Ti oxide) formed on the surface of the metal layer during wet etching of the transparent conductive material layer in a state in which the transparent conductive material layer for common electrode is formed on the metal layer without a pretreatment process to remove the metal oxide film is also Since they are etched together, there is no need to perform a pretreatment process to remove the metal oxide layer.

In addition, the display device including the thin film transistor array substrate according to the present invention and the manufacturing method thereof eliminate the pretreatment process of removing the metal oxide film, so that a part of the heat-cured surface of the passivation film made of an organic material is prevented from being etched. Thus, it is possible to suppress an increase in the specific resistance of the metal layer pattern formed on the surface of the passivation film.

In addition, in the display device including the thin film transistor array substrate and the method of manufacturing the same according to the present invention, the pretreatment process of removing the metal oxide layer can be omitted, thereby simplifying the manufacturing process.

1 is a schematic cross-sectional view of a thin film transistor array substrate according to the prior art.
2 is a flowchart of a manufacturing process of a thin film transistor array substrate according to the prior art.
3A to 3H are cross-sectional views illustrating a manufacturing process of a thin film transistor array substrate.
4 is a schematic cross-sectional view of a display device including a thin film transistor array substrate according to the present invention.
5 is a flowchart of a manufacturing process of a display device including a thin film transistor array substrate according to the present invention.
6A to 6R are cross-sectional views illustrating a manufacturing process of a display device including a thin film transistor array substrate according to the present invention.

Hereinafter, a display device including a thin film transistor array substrate according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

Here, the thin film transistor array substrate 100 according to the present invention includes all of a driveable thin film transistor structure including a top gate and a bottom gate method. In addition, the thin film transistor 100 may be applied to a thin film transistor using an etch stop layer and a thin film transistor having a BCE structure.

The thin film transistor array substrate 100 according to the present invention is a driving element or a switching element of a flat panel display such as a liquid crystal display (LCD), an organic light emitting diode (OLED), etc. B. It can be applied to various electronic devices such as devices for configuring peripheral circuits of memory devices.

4 is a schematic cross-sectional view of a thin film transistor array substrate according to the present invention.

4, a light shielding layer 103 made of a light blocking material is formed on a substrate 101 for a thin film transistor array substrate 100 according to the present invention. In this case, the substrate 101 may be made of silicon, glass, plastic, or other suitable material. Here, a case where a glass substrate is applied as a substrate will be described as an example.

The light blocking layer 103 is a layer used to block light from being transmitted through the oxide semiconductor layer 107, and a material for forming the light blocking layer 103 is selected from semiconductor materials including amorphous silicon (a-Si).

In addition, the buffer insulating film 105 is formed on the entire surface of the substrate 101 including the light blocking film 103. In this case, as a material for forming the buffer insulating layer 105, any one of inorganic insulating materials including an oxide layer and a nitride layer is used.

In addition, an active layer 107 made of polysilicon (Poly-Si) is formed on the buffer insulating layer 105 on the light blocking layer 103.

At this time, the active layer 107 includes a source region 107a and a drain region 107b contacting the source electrode 117a and the drain electrode 117b, respectively, and the source electrode 117a and the drain electrode 117b. It includes a channel region 107c for forming a channel through which electrons move.

The active layer 107 is a layer for forming a channel through which electrons move between the source electrode 117a and the drain electrode 117b, and includes low temperature polysilicon (LTPS) or amorphous silicon ( a-Si) material, in addition to these, silicon (Si)-based semiconductor films, IGZO-based oxide semiconductor films, compound semiconductors, carbon nanotubes, graphene, and organic semiconductors are used. .

At this time, as the oxide semiconductor, at least one material selected from the group consisting of germanium (Ge), tin (Sn), lead (Pb), indium (In), titanium (Ti), gallium (Ga), and aluminum (Al) And a material in which silicon (Si) is added to an oxide semiconductor including zinc (Zn). For example, the active layer 107 may be formed of indium zinc oxide (Si-InZnO: SIZO) in which silicon ions are added to an indium zinc composite oxide (InZnO). In addition, the active layer 107 is used by selecting any one of oxide semiconductor materials including a-IGZO, a-IZO, a-ITZO, and IGO.

And, when the active layer 107 is made of SIZO, the composition ratio of the content of silicon (Si) atoms to the total content of zinc (Zn), indium (In) and silicon (Si) atoms is about 0.001% by weight (wt%) to It may be about 30 wt%. As the content of silicon (Si) atoms increases, the role of controlling electron generation becomes stronger, and the mobility may decrease, but the stability of the device may be improved.

Meanwhile, as the active layer 107, in addition to the above-described materials, a group I element such as lithium (Li) or potassium (K), a group II element such as magnet?? (Mg), calcium (Ca), or strontium (Sr) , Group III elements such as gallium (Ga), aluminum (Al), indium (In) or yttrium (Y), titanium (Ti), zirconium (Zr), silicon (Si), tin (Sn) or germanium (Ge) Group IV elements such as, tantalum (Ta), vanadium (V), niobium (Nb), or group V elements such as antimony (Sb), or lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium ( Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolithium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ether A lanthanum (Ln)-based element such as bium (Yb) or rutedium (Lu) may be further included.

Furthermore, a gate insulating film 109 is formed on the entire surface of the substrate including the active layer 107. In this case, as the gate insulating layer 109, a silicon (Si)-based oxide layer, a nitride layer, or a compound including the same, a metal oxide layer including Al ₂ O ₃ , an organic insulating layer, and a low dielectric constant (low- Includes materials with k) values. For example, as the gate insulating layer 113a, silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide ( Ta ₂ O ₅ ), any one selected from the group consisting of barium-strontium-titanium-oxygen compounds (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compounds (Bi-Zn-Nb-O) Or a combination of two or more thereof or other suitable materials may be included.

Also, a gate electrode 111 is formed on the gate insulating layer 109 on the active layer 107. At this time, as the gate electrode 111, aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), Molytungsten (MoW), Molytitanium (MoTi), copper/molitanium (Cu /MoTi) may include at least one selected from the group of conductive metals, a combination of two or more thereof, or other suitable materials.

In addition, an interlayer insulating film 113 is formed on the entire surface of the substrate including the gate electrode 111, and the source region 107a and the drain region 107b of the active layer 107 are exposed in the interlayer insulating film 113. A source region contact hole 115a and a drain region contact hole 115b are formed. In this case, as the interlayer insulating layer 113, a silicon (Si)-based oxide layer, a nitride layer, or a compound including the same, a metal oxide layer including Al ₂ O ₃ , an organic insulating layer, and a low dielectric constant (low- Includes materials with k) values. For example, as the gate insulating layer 107, silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide ( Ta ₂ O ₅ ), any one selected from the group consisting of barium-strontium-titanium-oxygen compounds (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compounds (Bi-Zn-Nb-O) Or a combination of two or more thereof or other suitable materials may be included.

Further, on the interlayer insulating layer 113, a source electrode 117a and a drain electrode in contact with the source region 107a and the drain region 107b through the source region contact hole 115a and the drain region contact hole 115b. (117b) is formed. At this time, the source electrode 117a and the drain electrode 1117b include aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), and silver (Ag). , Silver alloy, gold (Au), gold alloy, chromium (Cr), titanium (Ti), titanium alloy, molybdenum (MoW), molitanium (MoTi), copper It may include at least one selected from the group of conductive metals containing / molitanium (Cu/MoTi), a combination of two or more thereof, or another suitable material. Here, a case of using a Ti/Al/Ti metal material as a material of the source electrode 117a and the drain electrode 117b will be described as an example.

In addition, a first passivation layer 121 is formed on the interlayer insulating layer 113 including the source electrode 117a and the drain electrode 117b, and the drain electrode 121 is formed in the first passivation layer 121. A drain contact hole 123 exposing the 117b is formed. In this case, the first passivation layer 121 is used for planarization, and may be formed of photoacryl, which is an organic insulating material, or other organic material. Here, a case where the first passivation layer 121 is made of photoacrylic will be described as an example.

In particular, a thermal curing process is required when the organic material layer for the first passivation layer 121 is formed. In this case, a metal oxide layer is formed on the surfaces of the source electrode 117a and drain electrode 117b composed of Ti/Al/Ti. (Ti oxide) 119 is generated.

Meanwhile, a transparent electrode pattern 125b for a lower electrode of an in-cell touch panel is formed on the first passivation layer 121 together with a common electrode 125a. At this time, the material constituting the common electrode 125a and the transparent electrode pattern 125b is selected from transparent conductive materials including Indium-Tin-Oxide (ITO) and Indium-Zinc-Oxide (IZO).

In addition, a second metal layer pattern 129a connected to the drain electrode 117b on the first passivation layer 121 including the drain contact hole 123 and the transparent electrode pattern 125b A metal layer pattern 129b is formed. At this time, the first metal layer pattern 129a is in direct contact with the drain electrode 117b, which means that the metal oxide layer 119 formed on the surface of the drain electrode 117b is used to form the common electrode 125a. This is because they are removed together during wet wet etching of the transparent conductive material layer. The transparent electrode pattern 125b and the second metal layer pattern 129b are used as lower electrodes of the in-cell touch panel.

In addition, a second passivation layer 133 is formed on the first passivation layer 121 including the common electrode 125a, the first metal layer pattern 129a, and the second metal layer pattern 129b. 2 A metal layer pattern contact hole 135 exposing the first metal layer pattern 129a is formed in the passivation layer 133. In this case, as the passivation layer 133, a silicon (Si)-based oxide layer, a nitride layer, or a compound including the same, and a metal oxide layer including Al ₂ O ₃ , an organic insulating layer, and a low dielectric constant (low- Includes materials with k) values. For example, as the gate insulating layer 107, silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide ( Ta ₂ O ₅ ), any one selected from the group consisting of barium-strontium-titanium-oxygen compounds (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compounds (Bi-Zn-Nb-O) Or a combination of two or more thereof or other suitable materials may be included.

Further, on the second passivation layer 133, a plurality of pixel electrodes 137a are in contact with the first metal layer pattern 135 to be electrically connected to the drain electrode 117b and corresponding to the common electrode 125a. In addition, an upper electrode 137b corresponding to the second metal layer pattern 129b is formed. At this time, the pixel electrode 137a is used by selecting from transparent conductive materials including Indium-Tin-Oxide (ITO) and Indium-Zinc-Oxide (IZO). In addition, the upper electrode 137b, the second metal layer pattern 129b, and the second passivation layer 133 therebetween constitute the in-cell touch panel 150.

A manufacturing process of a display device having a thin film transistor array substrate according to the present invention having the above configuration will be described with reference to FIG. 5.

5 is a flowchart of a manufacturing process of a display device including a thin film transistor array substrate according to the present invention.

Referring to FIG. 5, in the manufacturing process of a display device having a thin film transistor array substrate according to the present invention, a first process of forming a light blocking film 103 using a light blocking material on the substrate 101 (S101). Conduct.

Then, after forming the buffer insulating layer 105 on the entire surface of the substrate including the light blocking layer 103, a second process of forming the active layer 107 on the buffer insulating layer 105 on the light blocking layer 103 ( S102) is carried out.

Subsequently, after forming the gate insulating layer 109 on the entire surface of the substrate including the active layer 107, a third step of forming a gate electrode 111 on the gate insulating layer 107 on the active layer 107 (S103) ).

Then, a fourth process (S104) of forming an interlayer insulating layer 113 exposing the source region 107a and the drain region 107b of the active layer 107 on the entire substrate including the gate electrode 111 is performed. do.

Subsequently, a fifth step (S105) of forming a source electrode 117a and a drain electrode 117b contacting the source region 107a and the drain region 107b on the interlayer insulating layer 113, respectively, is performed.

Then, after the first passivation layer 121 is formed on the interlayer insulating layer 113 including the source electrode 117a and the drain electrode 117b, the drain electrode 117b is formed in the first passivation layer 121. A sixth process (S106) of forming the drain contact hole 123 exposing) is performed.

Subsequently, after forming a transparent conductive material layer in contact with the drain electrode 117b on the first passivation layer 121, the transparent conductive material layer in contact with the drain electrode is removed to form the drain electrode 117b. A seventh step (S107) of forming the common electrode 125a and the transparent electrode pattern 125b for the lower electrode of the in-cell touch panel on the first passivation layer 121 is performed.

Then, a second metal layer pattern 129b is formed on the first passivation layer 121 and on the first metal layer pattern 129a and the transparent electrode pattern 125b in contact with the drain electrode 117b. The eighth process (S108) of forming is performed.

Subsequently, a second passivation exposing the first metal layer pattern 129a on the first passivation layer 121 including the common electrode 125a and the first metal layer pattern 129a and the second metal layer pattern 129b. After the layer 133 is formed, a ninth step (S109) of forming the first metal layer pattern contact hole 135 in the second passivation layer 133 is performed.

Then, an upper electrode for an in-cell touch panel along with a plurality of pixel electrodes 137a that are in contact with the first metal layer pattern 129a on the second passivation layer 13 and electrically connected to the drain electrode 117b. By performing the tenth step (S110) of forming (137b), the manufacturing process of the thin film transistor array substrate for a display device according to the present invention is completed.

A method of manufacturing a display device including a thin film transistor array substrate according to the present invention in the order of manufacturing processes as described above will be described with reference to FIGS. 6A to 6R.

6A to 6R are cross-sectional views illustrating a manufacturing process of a display device including a thin film transistor array substrate according to the present invention.

Referring to FIG. 6A, a light shielding layer is formed by first forming a light blocking material layer (not shown) on the substrate 101 and then selectively patterning the light blocking material layer (not shown) through a mask process. Form 103. In this case, the substrate 101 may be made of silicon, glass, plastic, or other suitable material. Here, a case where a glass substrate is applied as a substrate will be described as an example.

In addition, the light-blocking layer 103 is a layer used to block light from being transmitted to the active layer (not shown, see 107 in FIG. 6C), and the forming material is a semiconductor material including amorphous silicon (a-Si). Select and use it.

Next, referring to FIG. 6B, a buffer insulating layer 105 is formed on the entire surface of the substrate 101 including the light blocking layer 103. In this case, as a material for forming the buffer insulating layer 105, any one of inorganic insulating materials including an oxide layer and a nitride layer is used.

Subsequently, after forming a semiconductor layer (not shown) on the buffer insulating layer 105, the oxide semiconductor layer (not shown) is selectively patterned through a mask process, and the buffer insulating layer 105 on the light blocking layer 103 is formed. ) To form an active layer 107 on it. At this time, the acid active layer 107 is a layer for forming a channel through which electrons move between the source electrode 117a and the drain electrode 117b to be formed in a subsequent process, and is a low temperature polysilicon (LTPS) layer. ) Or amorphous silicon (a-Si) material.In addition to these, silicon (Si)-based semiconductor films, IGZO-based oxide semiconductor films, compound semiconductors, carbon nano tubes, graphene ) And organic semiconductors.

At this time, as the oxide semiconductor, at least one material selected from the group consisting of germanium (Ge), tin (Sn), lead (Pb), indium (In), titanium (Ti), gallium (Ga), and aluminum (Al) And a material in which silicon (Si) is added to an oxide semiconductor including zinc (Zn). For example, the active layer 107 may be formed of indium zinc oxide (Si-InZnO: SIZO) in which silicon ions are added to an indium zinc composite oxide (InZnO). In addition, the active layer 107 is used by selecting any one of oxide semiconductor materials including a-IGZO, a-IZO, a-ITZO, and IGO.

And, when the active layer 107 is made of SIZO, the composition ratio of the content of silicon (Si) atoms to the total content of zinc (Zn), indium (In) and silicon (Si) atoms is about 0.001% by weight (wt%) to It may be about 30 wt%. As the content of silicon (Si) atoms increases, the role of controlling electron generation becomes stronger, and the mobility may decrease, but the stability of the device may be improved.

Meanwhile, as the active layer 107, in addition to the above-described materials, a group I element such as lithium (Li) or potassium (K), a group II element such as magnet?? (Mg), calcium (Ca), or strontium (Sr) , Group III elements such as gallium (Ga), aluminum (Al), indium (In) or yttrium (Y), titanium (Ti), zirconium (Zr), silicon (Si), tin (Sn) or germanium (Ge) Group IV elements such as, tantalum (Ta), vanadium (V), niobium (Nb), or group V elements such as antimony (Sb), or lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium ( Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolithium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ether A lanthanum (Ln)-based element such as bium (Yb) or rutedium (Lu) may be further included.

Next, referring to FIG. 6D, a gate insulating layer 109 is formed on the entire surface of the substrate including the active layer 107. In this case, as the gate insulating layer 109, a silicon (Si)-based oxide layer, a nitride layer, or a compound including the same, a metal oxide layer including Al ₂ O ₃ , an organic insulating layer, and a low dielectric constant (low- Includes materials with k) values. For example, as the gate insulating layer 113a, silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide ( Ta ₂ O ₅ ), any one selected from the group consisting of barium-strontium-titanium-oxygen compounds (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compounds (Bi-Zn-Nb-O) Or a combination of two or more thereof or other suitable materials may be included.

Subsequently, a first metal layer (not shown) for a gate electrode is formed on the gate insulating layer 109 on the active layer 107 and then the first metal layer (not shown) is selectively etched through a mask process to form the active layer. (107) A gate electrode 111 is formed on the gate insulating layer 109 above. At this time, as the gate electrode 111, aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), Molytungsten (MoW), Molytitanium (MoTi), copper/molitanium (Cu /MoTi) may include at least one selected from the group of conductive metals, a combination of two or more thereof, or other suitable materials.

Then, by implanting impurities into the active layer 107 under both sides of the gate electrode 111, the source region 107a and the drain region respectively contact the source electrode 117a and the drain electrode 117b to be formed in a subsequent process. Together with 107b, a channel region 107c for forming a channel through which electrons move between the source electrode 117a and the drain electrode 117b is defined.

Next, referring to FIG. 6E, after forming the interlayer insulating layer 113 on the entire surface of the substrate including the gate electrode 111, the source region 107a of the active layer 107 in the interlayer insulating layer 113 through a mask process. And a source region contact hole 115a and a drain region contact hole 115b exposing the drain region 107b, respectively. In this case, the interlayer insulating layer 113 includes a silicon (Si)-based oxide layer, a nitride layer, or a compound containing the same, and a metal oxide layer including Al ₂ O ₃ , an organic insulating layer, and a low dielectric constant (low- Includes materials with k) values. For example, as the gate insulating layer 107, silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide ( Ta ₂ O ₅ ), any one selected from the group consisting of barium-strontium-titanium-oxygen compounds (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compounds (Bi-Zn-Nb-O) Or a combination of two or more thereof or other suitable materials may be included.

Next, referring to FIG. 6F, contact with the source region 107a and the drain region 107b through the source region contact hole 115a and the drain region contact hole 115b on the interlayer insulating layer 113. A second metal layer 117 is deposited.

Subsequently, referring to FIG. 6G, a source electrode 117a and a drain electrode 117b are formed by selectively etching the second metal layer 117 through a mask process. In this case, the source electrode 117a and the drain electrode 1117b include aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), and silver (Ag). , Silver alloy, gold (Au), gold alloy, chromium (Cr), titanium (Ti), titanium alloy, molybdenum (MoW), molitanium (MoTi), copper It may include at least one selected from the group of conductive metals containing / molitanium (Cu/MoTi), a combination of two or more thereof, or another suitable material. Here, a case of using a Ti/Al/Ti metal material as a material of the source electrode 117a and the drain electrode 117b will be described as an example.

Next, referring to FIG. 6H, a first passivation layer 121 is coated on the interlayer insulating layer 113 including the source electrode 117a and the drain electrode 117b and then thermally cured. In this case, the first passivation layer 121 may be formed of photo acryl, which is an organic insulating material, or other organic material. Here, a case where the first passivation film 121 is made of photoacrylic will be described as an example. In addition, the first passivation layer 121 is used as a planarization layer.

In particular, in the process of performing a thermal curing process after applying the organic material layer for the first passivation layer 121, the surface of the source electrode 117a and drain electrode 117b composed of Ti/Al/Ti A metal oxide film (Ti oxide) 119 is formed.

Subsequently, referring to FIG. 6I, by selectively patterning the first passivation layer 121 through a mask process, a drain contact hole 123 exposing the metal oxide layer 119 on the surface of the drain electrode 117b is formed. do.

Next, referring to FIG. 6J, a transparent conductive material layer 125 is deposited on the first passivation layer 121 including the drain contact hole 123 to make contact with the metal oxide layer 119.

Subsequently, after applying a first photoresist layer (not shown) on the transparent conductive material layer 125, the first photoresist layer (not shown) is selectively removed through exposure and development processes using photolithography process technology. A first photoresist pattern 127 is formed to expose a portion of the transparent conductive material layer 125 over the contact hole 123.

Next, referring to FIG. 6K, the first photoresist layer pattern 127 is used as an etching mask, and the transparent conductive material layer 125 in contact with the metal oxide layer 119 is selectively etched to form a common electrode 125a and A transparent electrode pattern 125b for an in-cell touch panel is formed. At this time, when the transparent conductive material layer 125 is etched, a portion of the metal oxide layer 119 in contact with the transparent conductive material layer 125 is also etched, thereby exposing the surface of the drain electrode 117b to the outside. do. In addition, as a material constituting the common electrode 125a, transparent conductive materials including ITO (Indium-Tin-Oxide) and IZO (Indium-Zinc-Oxide) are selected and used.

Next, referring to FIG. 6L, the first photoresist pattern 127 is removed, and a metal layer 129 is formed on the entire surface of the substrate including the common electrode 125a and the transparent electrode pattern 125b. At this time, the metal layer 129 includes aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), and silver alloy. , Gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), Molytungsten (MoW), Molytitanium (MoTi), Copper/Moleitanium (Cu/MoTi) ), or a combination of two or more of them or other suitable materials.

Next, referring to FIG. 6M, after applying a second photosensitive film (not shown) on the metal layer 129, the second photosensitive film (not shown) is selectively subjected to exposure and development processes using photolithography process technology. Removed to form a second photoresist pattern 131 on the metal layer 129 above the drain contact hole 123.

Subsequently, referring to FIG. 6N, the metal layer 129 is etched using the second photoresist pattern 131 as an etching mask to form a first metal layer pattern 129a and a second metal layer pattern 129b for a lower electrode of the in-cell touch panel. To form. At this time, the first metal layer pattern 129a is in direct contact with the drain electrode 117b, which means that the metal oxide layer 119 formed on the surface of the drain electrode 117b is used to form the common electrode 125a. This is because they are removed together during wet etching of the transparent conductive material layer.

Next, referring to FIG. 6O, the second photoresist pattern 131 is removed, and the first passivation layer including the common electrode 125a, the first metal layer pattern 129a, and the second metal layer pattern 129b A second passivation film 133 is formed on 121. At this time, as the passivation layer 133, a silicon (Si)-based oxide layer, a nitride layer, or a compound including the same, a metal oxide layer including Al ₂ O ₃ , an organic insulating layer, and a low dielectric constant (low- Includes materials with k) values. For example, as the gate insulating layer 107, silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide ( Ta ₂ O ₅ ), any one selected from the group consisting of barium-strontium-titanium-oxygen compounds (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compounds (Bi-Zn-Nb-O) Or a combination of two or more thereof or other suitable materials may be included.

Subsequently, although not shown in the drawing, after applying a third photosensitive film (not shown) on the second passivation film 133, the third photosensitive film (not shown) is subjected to exposure and development processes using photolithography process technology. Is selectively removed to form a third photoresist pattern (not shown).

Next, referring to FIG. 6P, a metal layer pattern contact hole 135 exposing the first metal layer pattern 129a by etching the second passivation layer 133 using the third photoresist pattern (not shown) as an etching mask. ) To form.

Subsequently, referring to FIG. 6q, a transparent conductive material layer 137 is deposited on the second passivation layer 133 including the metal layer pattern contact hole 135.

Then, referring to FIG. 6R, although not shown in the drawing, after applying a fourth photosensitive film (not shown) on the transparent conductive material layer (not shown), exposure and development processes using photolithography process technology are performed. The fourth photoresist layer (not shown) is selectively removed to form a fourth photoresist layer pattern (not shown).

Subsequently, the transparent conductive material layer 137 is selectively etched using the fourth photoresist pattern (not shown) as an etching mask to be electrically connected to the drain electrode 117b through contact with the first metal layer pattern 129a. Manufacturing a thin film transistor array substrate using the oxide semiconductor thin film transistor according to the present invention by forming a plurality of connected pixel electrodes 137a and an upper electrode 137b for an in-cell touch panel, and removing the fourth photoresist pattern (not shown) Complete the process. At this time, the pixel electrode 137a is used by selecting from transparent conductive materials including Indium-Tin-Oxide (ITO) and Indium-Zinc-Oxide (IZO).

In addition, the upper electrode 137b, the second metal layer pattern 129b below the upper electrode 137b, and the second passivation layer 133 therebetween constitute the in-cell touch panel 150.

As described above, the display device including the thin film transistor array substrate and the method of manufacturing the same according to the present invention can improve contact resistance without a pretreatment process of removing the metal oxide film formed on the surface of the metal layer for forming the source and drain electrodes.

In particular, the metal oxide film (Ti oxide) formed on the surface of the metal layer during wet etching of the transparent conductive material layer in a state in which the transparent conductive material layer for common electrode is formed on the metal layer without a pretreatment process to remove the metal oxide film is also Since they are etched together, there is no need to perform a pretreatment process to remove the metal oxide layer.

In addition, the display device including the thin film transistor array substrate according to the present invention and the manufacturing method thereof eliminate the pretreatment process of removing the metal oxide film, so that a part of the heat-cured surface of the passivation film made of an organic material is prevented from being etched. Thus, it is possible to suppress an increase in the specific resistance of the metal layer pattern formed on the surface of the passivation film.

In addition, in the display device including the thin film transistor array substrate and the method of manufacturing the same according to the present invention, the pretreatment process of removing the metal oxide layer can be omitted, thereby simplifying the manufacturing process.

Although many items are specifically described in the above description, they should be interpreted as examples of preferred embodiments rather than limiting the scope of the invention. For example, those of ordinary skill in the art to which the present invention pertains will be able to diversify the components of the thin film transistor of the present invention, and also to change the structure into various forms.

It will be appreciated that the thin film transistor array substrate of the present invention can be applied not only to a liquid crystal display device or an organic light emitting display device, but also to a memory device and a logic device field. Therefore, the scope of the present invention should not be determined by the described embodiments, but should be determined by the technical idea described in the claims.

100: thin film transistor array substrate 103: light blocking film
105: buffer insulating film 107: active layer
109: gate insulating film 111: gate electrode
113: interlayer insulating film 117a: source electrode
117b: drain electrode 119: metal oxide film
121: first passivation film 125a: common electrode
125b: transparent electrode pattern 129a: first metal layer pattern
129b: second metal layer pattern 133: second passivation layer
137a: pixel electrode 137b: upper electrode

Claims (14)

An active layer disposed on the substrate;
A gate insulating film disposed on the entire surface of the substrate including the active layer;
A gate electrode disposed on the gate insulating layer over the active layer;
An interlayer insulating film disposed on the entire surface of the substrate including the gate electrode and exposing the source region and the drain region of the active layer;
A source electrode and a drain electrode disposed on the interlayer insulating layer and contacting the source region and the drain region, respectively;
A first passivation layer disposed on an interlayer insulating layer including the source electrode and the drain electrode and exposing the drain electrode;
A first metal layer pattern disposed on the first passivation layer and in contact with the drain electrode;
A common electrode disposed on the first passivation layer;
A second passivation layer disposed on the first passivation layer including the common electrode and the metal layer pattern, and exposing the metal layer pattern;
A plurality of pixel electrodes disposed on the second passivation layer, contacting the first metal layer pattern, and electrically connected to the drain electrode;
A transparent electrode pattern disposed on the first passivation layer and overlapping the pixel electrode;
And a second metal layer pattern disposed on the transparent electrode pattern,
The first metal layer pattern includes a thin film transistor array substrate made of the same material as the second metal layer pattern and a different material from the transparent electrode pattern. The display device of claim 1, wherein the first passivation layer is a thin film transistor array substrate selected from organic insulating materials including photoacrylic. The display device of claim 1, further comprising a thin film transistor array substrate on which a light blocking film is disposed under the active layer. The display device of claim 1, wherein the drain electrode includes a thin film transistor array substrate in direct contact with the first metal layer pattern. The display device of claim 1, wherein the source electrode and the drain electrode are formed of Ti/Al/Ti. The method of claim 1,
Further comprising an upper electrode disposed on the second passivation layer,
A display device having a thin film transistor array substrate including an in-cell touch panel including the transparent electrode pattern, the second metal layer pattern, and the upper electrode. Forming an active layer on the substrate;
Forming a gate insulating film on the entire surface of the substrate including the active layer;
Forming a gate electrode on the gate insulating layer over the active layer;
Forming an interlayer insulating film exposing the source region and the drain region of the active layer on the entire surface of the substrate including the gate electrode;
Forming a source electrode and a drain electrode on the interlayer insulating layer to contact the source region and the drain region, respectively;
Forming a first passivation layer exposing the drain electrode on the interlayer insulating layer including the source electrode and the drain electrode;
Forming a transparent conductive material layer on the first passivation layer in contact with the drain electrode;
Removing the transparent conductive material layer in contact with the drain electrode to expose the drain electrode, and forming a common electrode and a transparent electrode pattern on the first passivation layer;
Forming a first metal layer pattern on the first passivation layer in contact with the drain electrode and a second metal layer pattern on the transparent electrode pattern;
Forming a second passivation layer exposing the metal layer pattern on the first passivation layer including the common electrode and the metal layer pattern; And
And forming a plurality of pixel electrodes on the second passivation layer in contact with the metal layer pattern, electrically connected to the drain electrode, and overlapping the transparent electrode pattern, on the second passivation layer, and
A method of manufacturing a display device including a thin film transistor array substrate, wherein the first metal layer pattern is made of the same material as the second metal layer pattern and made of a material different from the transparent electrode pattern. The method of claim 7,
A method of manufacturing a display device including a thin film transistor array substrate using any one of organic insulating materials including photoacrylic as the first passivation layer. The method of claim 7,
A method of manufacturing a display device having a thin film transistor array substrate, further comprising forming a light blocking layer under the active layer. The method of claim 7,
A method of manufacturing a display device including a thin film transistor array substrate in which the drain electrode is in direct contact with the metal layer pattern. The method of claim 7,
The source electrode and the drain electrode are a method of manufacturing a display device including a thin film transistor array substrate composed of Ti/Al/Ti. The method of claim 7,
Further comprising forming an upper electrode on the second passivation layer,
A method of manufacturing a display device including a thin film transistor array substrate including an in-cell touch panel composed of the transparent electrode pattern, the second metal layer pattern, and the upper electrode. The method of claim 1,
Further comprising a metal oxide layer disposed between the drain electrode and the first passivation layer,
The first metal layer pattern includes a thin film transistor array substrate in contact with a side surface of the metal oxide layer. The method of claim 7,
Further comprising forming a metal oxide layer disposed between the drain electrode and the first passivation layer,
A method of manufacturing a display device including a thin film transistor array substrate in which the first metal layer pattern contacts a side surface of the metal oxide layer.

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